TWI457782B - Information generating apparatus and operation method thereof - Google Patents

Description

Information generating device and operating method thereof

The present invention relates to an integrated circuit, and more particularly to an information generating apparatus and method of operating the same.

As the design requirements change, the layout and functions inside the integrated circuit need to be modified accordingly. Different modifications will result in multiple different versions of the integrated circuit. In order to manage/confirm the version of the integrated circuit, the integrated circuit must have a mechanism to provide relevant information to the system. For example, a version information generating device can be configured in the timing controller (TCON) of the display to generate corresponding version information. The system can read back the version information of the timing controller via an I ² C bus (Inter-Integrated Circuit Bus).

However, in practice, in addition to modifying the corresponding mask of the timing controller according to the design requirements, the conventional technology often additionally modifies the corresponding mask of the version information generating device. It takes an extra cost to modify the corresponding mask of the version information generating device.

The invention provides an information generating device and an operating method thereof. In the modification process of the integrated circuit, no matter which metal layer mask is modified, the logic information output by the information generating device can be correspondingly changed without changing the additional mask.

An embodiment of the present invention provides an information generating apparatus, including a first logical contact, a second logical contact, an information output contact, and a plurality of switching elements SW _{(i, j)} , wherein SW _{(i, j)} represents an ith layer Jth switching element, 1 i L,1 j 2 ^(i-1) , L is an integer. The switching element SW _{(i, j)} has a first input, a second input and an output. An output terminal for selectively switching element SW _{(i, j)} is connected to the first input terminal of the switch element SW _{(i, j)} or the second input of the switching element SW _{(i, j)} of. The first input end and the second input end of the _L-th layer switching element SW _{(L, j)} are respectively connected to the first logical contact and the second logical contact, and the switching elements SW _{(i, j) of the} other layers The first input end and the second input end are respectively connected to the output end of the switching element SW _{(i+ 1, 2j-1) and} the output end of the switching element SW _{(i+1, 2j)} . The output of the layer 1 switching element SW _{(1, 1)} is connected to the information output contact.

The embodiment of the invention provides an operation method of the information generating device, and the information generating device is as described above. The switching elements are arranged in different metal layers of the integrated circuit. One of the metal layer reticle of the integrated circuit is modified according to design requirements. Wherein, the metal layer mask corresponds to the i-th layer switching element SW _{(i, j)} . According to design requirements, the output ends of the odd-numbered switching elements of the i-th layer are connected to the first input end, and the output ends of the even-numbered switching elements of the i-th layer are connected to the second input end. Or, according to design requirements, the output ends of the odd-numbered switching elements of the i-th layer are connected to the second input end, and the output ends of the even-numbered switching elements of the i-th layer are connected to the first input end.

The embodiment of the invention provides an operation method of the information generating device, and the information generating device is as described above. The switching elements are arranged in different metal layers of the integrated circuit. One of the metal layer reticle of the integrated circuit is modified according to design requirements. Wherein, the metal layer mask corresponds to the i-th layer switching element SW _{(i, j)} . According to design requirements, the output end of the i-th layer switching element SW _{(i, j)} is connected to the first input end, or the output end of the i-th layer switching element SW _{(i, j)} is connected to the second input end.

The above described features and advantages of the present invention will be more apparent from the following description.

1 is a functional block diagram showing an integrated circuit in accordance with an embodiment of the present invention. The integrated circuit packs a core circuit 10 and a chip information module 11. The chip information module 11 can generate logical information I[0:N-1] of N bits according to the configuration, where N is an integer. This logic information I[0:N-1] can be used as the operational parameters of the core circuit 10, customized setpoints, version information, or other applications. Taking the application of the version information as an example, the logic information I[0:N-1] may be the version value of the core circuit 10. Corresponding to the modification of the core circuit 10, the configuration of the wafer information module 11 must be correspondingly adjusted to generate corresponding logical information I[0:N-1] to the core circuit 10. When the external system makes a "version query" request to the core circuit 10, the core circuit 10 outputs the version value VV to the external system according to the logical information I[0:N-1]. Therefore, the external system can confirm the modified version of the core circuit 10 by the setting of the logical information I[0:N-1].

Referring to FIG. 1, the chip information module 11 includes N information generating devices 11-1, 11-2, ..., 11-N. Each information generating device is responsible for providing one of the logical information I[0:N-1]. For example, the first information generating device 11-1 provides the bit I[0] of the logical information, the second information generating device 11-2 provides the bit I[1] of the logical information, and the Nth information generating device 11 -N provides the bit I[N-1] of the logical information.

During the modification of the core circuit 10, it may be desirable to modify one or more metal layer reticle of the integrated circuit. Regardless of which metal layer mask is modified, the present embodiment can provide a group of wafer designer change information generating devices 11-1, 11-2, ..., 11-N without changing the additional mask. State mechanism. For example, if the chip designer needs to modify the layout of the first metal layer M1 during the modification of the core circuit 10, the chip designer can change the information generating devices 11-1, 11-2, ..., 11-N. The configuration of the first metal layer M1 corresponds to the adjustment logic information I[0:N-1]. That is to say, in addition to the mask of the first metal layer M1, the wafer designer does not need to modify the mask of the other metal layer, and the logic information I[0:N-1] can be changed correspondingly.

An embodiment of the information generating apparatus 11-1 will be described below, and the embodiments of the other information generating apparatuses 11-2, ..., 11-N in Fig. 1 can refer to the related description of the information generating apparatus 11-1. FIG. 2 is a functional block diagram showing the information generating apparatus 11-1 of FIG. 1 according to an embodiment of the present invention. This embodiment will assume that the integrated circuit has at least L metal layers, and L is a positive integer. The information generating device 11-1 includes a first logical contact IN1, a second logical contact IN2, an information output contact OUT, and a plurality of switching elements SW _(i,j) , wherein SW _(i,j) represents the i-th layer j switching elements, 1 i L,1 j 2 ^(i-1) . All of the switching elements belonging to the same layer (for example, the i-th layer switching element SW _{(i, j)} ) are disposed in the same metal layer (any one of the metal layers) in the integrated circuit. For example, the first layer switching element SW _{(1, 1)} may be disposed in the first metal layer M1, the second metal layer M2, or other metal layers in the integrated circuit. Switching elements (e.g., the i-th layer of the switching element SW _{(i, j)} i + 1 of the first layer of the switching element _{SW (i + 1, j)} ) belonging to different layers in the integrated circuit disposed in different metal layers. For example, the i-th layer switching element SW _{(i, j)} is disposed on the L-i+1-th metal layer.

In this embodiment, the first logic contact IN1 is connected to a first logic value source (eg, system voltage source VDD). The second logic contact IN2 is connected to a second logic value source (eg, ground voltage source GND). In other embodiments, the first logic contact IN1 can be connected to the ground voltage source GND and the second logic contact IN2 can be connected to the system voltage source VDD.

Each of the switching elements SW _{(i, j)} (eg, switching elements SW _{(1, 1)} ) has a first input A, a second input B, and an output C, respectively. An output terminal C of selectively switching element SW _{(i, j)} is connected to a first input terminal A of the switching elements SW _{(i, j)} or the second input of the switching element SW _{(i, j)} of B.

Switching element SW _{(L, j) of} the Lth layer (ie, switching elements SW _{(L, 1)} , SW _{(L, 2)} , ..., SW _{(L, 2^(L-1)-1)} , SW The first input terminal A and the second input terminal B of _{(L, 2^(L-1))} ) are respectively connected to the first logical contact IN1 and the second logical contact IN2, and the switching elements SW _{(i of} other layers ₎ The first input A and the second input B of _j) are respectively connected to the output C of the switching element SW _{(i+ 1, 2j-1) and} the output C of the switching element SW _{(i+1, 2j)} . For example, the switching element SW _(L-1,1) a first input terminal A and the second input terminal B are respectively connected to the output terminal C of the switching element SW _{(L, 2)} to the switching element SW _{(L, 1)} the End C. The first input terminal A and the second input terminal B of the switching element SW _{(L-1, 2^(L-2))} are respectively connected to the output ends of the switching elements SW _{(L, 2^(L-1)-1)} C and the output C of the switching element SW _{(L, 2^(L-1))} . A first input terminal and the second input terminal B of the switching elements SW _(1,1) are connected to the switching element SW _(2,1) of the output terminal C of the switching element SW _(2,2) to the output terminal C. The output terminal C of the switching element SW _{(1, 1)} of the first layer is connected to the information output contact OUT. The information output contact OUT outputs the logical information I[0] to the core circuit 10.

The above switching element SW _{(i, j)} may be a switch or a multiplexer. 3A and 3B are schematic diagrams showing the layout of the switching element SW _{(1, 1)} of FIG. 2 according to an embodiment of the present invention. The implementation of the other switching elements SW _{(i, j)} in Fig. 2 can be referred to the relevant description of the switching elements SW _{(1, 1)} . The switching element SW _{(1, 1)} shown in FIGS. 3A and 3B can be disposed in any one of the metal layers of the integrated circuit, for example, in the L-th metal layer. The switching element SW _{(1, 1)} includes a first connection end, a second connection end, a third connection end, and a wire 310. In this embodiment, the first connection end, the second connection end, the third connection end, and the wires 310 are all disposed on the Lth metal layer of the integrated circuit. The first connection end, the second connection end and the third connection end respectively serve as a first input end A, a second input end B and an output end C of the switching element SW _{(1, 1)} . FIG. 3A illustrates a layout structure in which the wire 310 is connected between the second input terminal B and the output terminal C. FIG. 3B illustrates a layout structure in which the wire 310 is connected between the first input terminal A and the output terminal C.

Hereinafter, an implementation example of the information generating apparatus 11-1 shown in Fig. 2 will be described by taking four layers (i.e., L = 4) as an example. FIG. 4A is a functional block diagram showing the information generating apparatus 11-1 of FIG. 2 according to an embodiment of the present invention. The first layer switching element SW _{(1, 1)} is disposed on the fourth metal layer M4 of the integrated circuit. Layer 2 switching element SW _(2,1) to SW _(2,2) is arranged on the integrated circuit a metal layer M3 third layer. The third layer switching elements SW ₍₃ , ₁₎ , SW ₍₃ , ₂₎ , SW _{(3, 3),} and SW _{(3, 4)} are disposed in the second metal layer M2 of the integrated circuit. Layer 4 switching elements SW _(4,1) , SW _(4,2) , SW _(4,3) , SW _(4,4) , SW _(4,5) , SW _(4,6) , SW _{(4 7)} and SW _{(4, 8)} are arranged in the first metal layer M1 of the integrated circuit.

According to the design requirements of the chip designer, the output terminal C of the odd-numbered switching elements of the i-th layer is connected to the first input terminal A, and the output terminal C of the even-numbered switching elements of the i-th layer is connected to the second input terminal B. . Or, according to the design requirements of the chip designer, the output terminal C of the odd-numbered switching elements of the i-th layer and the second input terminal B are connected to each other, and the output terminal C and the first input end of the even-numbered switching elements of the i-th layer A is connected to each other.

Referring to FIG. 4A, the output C and the second input B of the fourth layer of odd-numbered switching elements SW _{(4, 1)} , SW ₍₄ , ₃₎ , SW _{(4, 5),} and SW _{(4, 7)} connected to each other, and even-numbered layer 4 switching elements _{SW (4,2), SW (4,4} ), SW (4,6) to SW _(4,8) to the output terminal C of the first input terminal a to each other connection. The output terminals C and the second input terminals B of the third-layer odd-numbered switching elements SW _{(3, 1)} and SW _{(3, 3)} are connected to each other, and the third-order even-numbered switching elements SW _{(3, 2)} and The output C of the SW _{(3, 4)} is connected to the first input A. The output terminal C of the second layer of the odd-numbered switching elements SW _{(2, 1)} and the second input terminal B are connected to each other, and the output terminal C of the second-layer even-numbered switching elements SW _{(2, 2)} and the first input End A is connected to each other. The output terminal C of the odd-numbered switching elements SW _{(1, 1)} of the first layer and the second input terminal B are connected to each other. At this time, the logic information I[0] supplied from the information generating device 11-1 through the information output contact OUT is the system voltage VDD (ie, the logical value "1").

Assuming that the chip designer modifies the mask of one or more of the metal layers of the integrated circuit according to the design requirements, regardless of which metal layer the modified mask is, the chip designer can modify the same metal layer by the way. Corresponding switching element SW _{(i, j)} . FIG. 4B to FIG. 4D are schematic diagrams showing the process of the information generating apparatus 11-1 shown in FIG. 4A being modified multiple times according to design requirements according to an embodiment of the present invention. For example, if the chip designer modifies the mask of the second metal layer M2 of the integrated circuit according to the design requirements, the logic information I[0] provided by the information generating device 11-1 through the information output contact OUT must be changed to ground. Voltage GND (ie, logic value "0"), the chip designer can connect the third layer of odd-numbered switching elements SW _(3,1) and SW _(3,3) output C to the first according to design requirements. The input terminal A, and the output terminal C of the third-layer even-numbered switching elements SW _{(3, 2)} and SW _{(3, 4)} are reconnected to the second input terminal B, as shown in FIG. 4B. Thus, in the case where it is not necessary to change the mask of the additional metal layer, the chip designer can correspondingly change the logic information I[0] output from the information generating device 11-1 from the system voltage VDD to the ground voltage GND.

Referring to FIG. 4B, it is assumed that the chip designer modifies the photomask of the fourth metal layer M4 of the integrated circuit according to the design requirements, and the logic information I[0] provided by the information generating device 11-1 through the information output contact OUT must be Then change to the system voltage VDD. At this time, the chip designer can reconnect the output terminal C corresponding to the odd-numbered switching elements SW _{(1, 1)} of the first layer of the fourth metal layer M4 to the first input terminal A according to design requirements, as shown in FIG. 4C. Show. Thus, in the case where it is not necessary to change the mask of the additional metal layer, the chip designer can correspondingly change the logic information I[0] output from the information generating device 11-1 from the ground voltage GND to the system voltage VDD.

Referring to FIG. 4C, it is assumed that the chip designer modifies the mask of the first metal layer M1 of the integrated circuit according to the design requirements, and the logic information I[0] provided by the information generating device 11-1 through the information output contact OUT must be Then change to the ground voltage GND. At this time, the wafer in accordance with the designer can design requirements corresponding to the first metal layer M1 Layer 4 switching elements of odd-numbered _{SW (4,1), SW (4,3} ), SW (4,5) to SW _{( 4,7)} The output C is reconnected to the first input A, and the 4th even-numbered switching elements SW ₍₄ , ₂₎ , SW ₍₄ , ₄₎ , SW _{(4, 6)} and SW ₍ The output C of _{4, 8)} is reconnected to the second input B as shown in Figure 4D. Thus, in the case where it is not necessary to change the mask of the additional metal layer, the chip designer can correspondingly change the logic information I[0] output from the information generating device 11-1 from the system voltage VDD to the ground voltage GND.

FIG. 5A is a functional block diagram showing the information generating apparatus 11-1 of FIG. 2 according to another embodiment of the present invention. In the embodiment shown in FIGS. 4A to 4D, the i-th layer switching element SW _{(i, j)} is disposed on the L-i+1-th metal layer. In the embodiment shown in FIGS. 5A to 5D, the i-th layer switching element SW _{(i, j)} is disposed on the i-th metal layer. The first layer switching element SW _{(1, 1)} is disposed on the first metal layer M1 of the integrated circuit. Layer 2 switching element SW _(2,1) to SW _(2,2) is arranged on the metal layer M2 integrated circuit of the second layer. The third layer switching elements SW ₍₃ , ₁₎ , SW ₍₃ , ₂₎ , SW _{(3, 3),} and SW _{(3, 4)} are disposed on the third metal layer M3 of the integrated circuit. Layer 4 switching elements SW _(4,1) , SW _(4,2) , SW _(4,3) , SW _(4,4) , SW _(4,5) , SW _(4,6) , SW _{(4 7)} and SW _{(4, 8)} are arranged in the fourth metal layer M4 of the integrated circuit.

The output terminal C of the i-th layer switching element SW _{(i, j)} is connected to the first input terminal A in accordance with the design requirements of the chip designer. Alternatively, the output terminal C of the i-th layer switching element SW _{(i, j)} and the second input terminal are connected to each other B in accordance with the design requirements of the chip designer.

Referring to FIG. 5A, the fourth layer switching elements SW _{(4, 1)} , SW ₍₄ , ₂₎ , SW ₍₄ , ₃₎ , SW ₍₄ , ₄₎ , SW ₍₄ , ₅₎ , SW _{(4, 6 ),} SW _(4,7) to SW _(4,8) to the output terminal C of the first input terminal a connected to each other. The output terminals C of the third layer switching elements SW ₍₃ , ₁₎ , SW ₍₃ , ₂₎ , SW _{(3, 3)} and SW _{(3, 4)} are connected to the first input terminal A. The output terminals C of the second layer switching elements SW _{(2, 1)} and SW _{(2, 2)} are connected to the first input terminal A. The output terminal C of the first layer switching element SW _{(1, 1)} is connected to the first input terminal A. At this time, the logic information I[0] supplied from the information generating device 11-1 through the information output contact OUT is the system voltage VDD (ie, the logical value "1").

Assuming that the chip designer modifies the mask of one or more of the metal layers of the integrated circuit according to the design requirements, regardless of which metal layer the modified mask is, the chip designer can modify the same metal layer by the way. Corresponding switching element SW _{(i, j)} . FIG. 5B to FIG. 5D are schematic diagrams showing the process of the information generating apparatus 11-1 shown in FIG. 5A being modified multiple times according to design requirements according to another embodiment of the present invention. For example, if the chip designer modifies the mask of the third metal layer M3 of the integrated circuit according to the design requirements, the logic information I[0] provided by the information generating device 11-1 through the information output contact OUT must be changed to ground. The voltage GND (ie, logic value "0") allows the chip designer to switch the Layer 3 switching elements SW _(3,1) , SW _(3,2) , SW _(3,3) and SW _(3, according to design requirements _{) .} The output C of ₄₎ is reconnected to the second input B as shown in FIG. 5B. Thus, in the case where it is not necessary to change the mask of the additional metal layer, the chip designer can correspondingly change the logic information I[0] output from the information generating device 11-1 from the system voltage VDD to the ground voltage GND.

Referring to FIG. 5B, it is assumed that the chip designer modifies the mask of the first metal layer M1 of the integrated circuit according to the design requirements, and the logic information I[0] provided by the information generating device 11-1 through the information output contact OUT must be Then change to the system voltage VDD. At this time, the chip designer can reconnect the output terminal C of the first layer switching element SW _{(1, 1)} corresponding to the first metal layer M1 to the second input terminal B according to design requirements, as shown in FIG. 5C. Thus, in the case where it is not necessary to change the mask of the additional metal layer, the chip designer can correspondingly change the logic information I[0] output from the information generating device 11-1 from the ground voltage GND to the system voltage VDD.

Referring to FIG. 5C, it is assumed that the chip designer modifies the photomask of the fourth metal layer M4 of the integrated circuit according to the design requirements, and the logic information I[0] provided by the information generating device 11-1 through the information output contact OUT must be Then change to the ground voltage GND. At this time, the chip designer can design the fourth layer switching elements SW _{(4, 1)} , SW ₍₄ , ₂₎ , SW ₍₄ , ₃₎ , SW ₍₄ , ₄₎ corresponding to the fourth metal layer M4 according to design requirements. ₎ , the output terminals C of SW ₍₄ , ₅₎ , SW ₍₄ , ₆₎ , SW _{(4, 7),} and SW _{(4, 8)} are reconnected to the second input terminal B, as shown in FIG. 5D. Thus, in the case where it is not necessary to change the mask of the additional metal layer, the chip designer can correspondingly change the logic information I[0] output from the information generating device 11-1 from the system voltage VDD to the ground voltage GND.

In summary, regardless of which metal layer is modified, the embodiments of the present invention can provide the chip designer to modify the corresponding switching element SW _{(i, j)} in the same metal layer to adjust accordingly. The logical information provided by the information generating devices 11-1 to 11-N.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10. . . Core circuit

11. . . Chip information module

11-1, 11-2, 11-N. . . Information generating device

310. . . wire

A, B. . . Input

C. . . Output

GND. . . Ground voltage source

I[0], I[1], I[N-1]. . . Logic information

IN1, IN2. . . Logical contact

M1~M4. . . Metal layer

OUT. . . Information output contact

SW _(1,1) , SW _(2,1) , SW _(2,2) , SW _(3,1) ~SW _(3,4) , SW _(4,1) ~SW _(4,8) , SW _{(L, 1)} , SW _{(L, 2)} , SW _{(L, 2^(L-1)-1)} , SW _{(L, 2^(L 1))} , SW _(L-1 , ₁₎ , SW _{(L-1, 2^(L-2))} . . . Switching element

VDD. . . System voltage source

VV. . . Version value

1 is a functional block diagram showing an integrated circuit in accordance with an embodiment of the present invention.

FIG. 2 is a functional block diagram showing the information generating apparatus 11-1 of FIG. 1 according to an embodiment of the present invention.

3A and 3B are schematic diagrams showing the layout of the switching element of FIG. 2 according to an embodiment of the invention.

FIG. 4A is a functional block diagram showing the information generating apparatus 11-1 of FIG. 2 according to an embodiment of the present invention.

FIG. 4B to FIG. 4D are schematic diagrams showing the process of the information generating apparatus 11-1 shown in FIG. 4A being modified multiple times according to design requirements according to an embodiment of the present invention.

FIG. 5A is a functional block diagram showing the information generating apparatus 11-1 of FIG. 2 according to another embodiment of the present invention.

FIG. 5B to FIG. 5D are schematic diagrams showing the process of the information generating apparatus 11-1 shown in FIG. 5A being modified multiple times according to design requirements according to another embodiment of the present invention.

11-1. . . Information generating device

A, B. . . Input

C. . . Output

GND. . . Ground voltage source

IN1, IN2. . . Logical contact

M1~M4. . . Metal layer

OUT. . . Information output contact

SW _(1,1) , SW _(2,1) ~SW _(2,2) , SW _(3,1) ~SW _(3,4) , SW _(4,1) ~SW _(4,8) . . . Switching element

VDD. . . System voltage source

Claims (10)

An information generating device includes: a first logical contact for connecting to a first logical value source; a second logical contact for connecting to a second logical value source; and an information output contact for outputting a logic information; and a plurality of switching elements SW _{(i, j),} where SW _{(i, j)} represents the i-th layer of the j-th switching element 1 i L,1 j 2 ^(i-1) , L is a positive integer, the switching element SW _{(i, j)} has a first input terminal, a second input terminal and an output terminal, and the output terminal of the switching component SW _{(i, j)} is selected connectable to the switching element SW _{(i, j)} of the first input or the second input terminal of the switching element SW _{(i, j)} of the plurality of switching elements SW _{(L, j)} and the first input terminal The second input end is respectively connected to the first logical contact and the second logical contact, and the first input end and the second input end of the other switching elements SW _{(i, j)} are respectively connected to the switching element SW _(i+1) The output of the _{2j-1) and} the output of the switching element SW _{(i+ 1, 2j)} , and the output of the switching element SW _{(1, 1)} is connected to the information output contact. The information generating apparatus according to claim 1, wherein an output end of the odd-numbered switching elements of the i-th layer switching element SW _{(i, j)} is connected to the first input end, and the i-th layer switching element SW The output ends of the even-numbered switching elements in _{(i, j)} are connected to the second input terminal; or the output ends and the second input ends of the odd-numbered switching elements in the i-th layer switching element SW _{(i, j)} Interconnected, and the output of the even-numbered switching elements of the i-th layer switching element SW _{(i, j)} is connected to the first input. The information generating apparatus according to claim 1, wherein an output end of the i-th layer switching element SW _{(i, j)} is connected to the first input end; or, an i-th layer switching element SW _{(i, j)} The output of the ₎ is connected to the second input. The information generating apparatus according to claim 1, wherein the switching elements SW _{(i, j) are} disposed in a L-i+1 metal layer of an integrated circuit. The information generating device of claim 1, wherein the switching elements SW _{(i, j) are} disposed on an i-th metal layer of an integrated circuit. The information generating device of claim 1, wherein the switching elements SW _{(i, j)} are switches or multiplexers. The information generating device of claim 1, wherein the switching elements SW _{(i, j)} each comprise: a first connecting end, and a first L-i+1 layer metal disposed in an integrated circuit a layer, the first connection end serves as the first input end; a second connection end is disposed on the L-i+1 layer metal layer, the second connection end serves as the second input end; a third a connection end disposed on the L-i+1 metal layer, the third connection end serving as the output end, and a wire disposed on the L-i+1 metal layer, the wire being configured and connected Between the first connection end and the third connection end, or the wire is disposed between the second connection end and the third connection end. The information generating device of claim 1, wherein the switching elements SW _{(i, j)} each comprise: a first connecting end disposed on an i-th metal layer of an integrated circuit, the a connection end is configured as the first input end; a second connection end is disposed on the ith layer of the metal layer, the second connection end serves as the second input end; and a third connection end is disposed at the ith a metal layer, the third connection end serves as the output end; and a wire disposed on the ith metal layer, the wire being disposed and connected between the first connection end and the third connection end, or The wire is disposed and connected between the second connection end and the third connection end. An operation method of an information generating device, as described in claim 1, wherein the operating method comprises: arranging the switching elements in different metal layers of an integrated circuit; modifying one of the integrated circuits a metal layer mask, wherein the metal layer mask corresponds to the i-th layer switching element SW _{(i, j)} ; and the output end of the odd-numbered switching elements of the i-th layer is connected to the first input end and An output end of the even-numbered switching elements of the i-th layer is connected to the second input end; or, an output end of the odd-numbered switching elements of the i-th layer is connected to the second input end, and the ith The output of the even-numbered switching elements of the layer is interconnected with the first input. An operation method of an information generating device, as described in claim 1, wherein the operating method comprises: arranging the switching elements in different metal layers of an integrated circuit; modifying one of the integrated circuits a metal layer reticle, wherein the metal layer reticle corresponds to the ith layer switching element SW _{(i, j)} ; and the output end of the ith layer switching element SW _{(i, j)} is connected to the first input end Or, the output end of the ith layer switching element SW _{(i, j)} is connected to the second input terminal.