TWI456911B - 用於雙二進位及非二進位解碼處理的系統及方法 - Google Patents
用於雙二進位及非二進位解碼處理的系統及方法 Download PDFInfo
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- TWI456911B TWI456911B TW102113634A TW102113634A TWI456911B TW I456911 B TWI456911 B TW I456911B TW 102113634 A TW102113634 A TW 102113634A TW 102113634 A TW102113634 A TW 102113634A TW I456911 B TWI456911 B TW I456911B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/1171—Parity-check or generator matrices with non-binary elements, e.g. for non-binary LDPC codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/3707—Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
- H03M13/6511—Support of multiple decoding rules, e.g. combined MAP and Viterbi decoding
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/6331—Error control coding in combination with equalisation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/6343—Error control coding in combination with techniques for partial response channels, e.g. recording
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- General Engineering & Computer Science (AREA)
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- Error Detection And Correction (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Claims (20)
- 一種資料處理系統，該資料處理系統包含：一樣本緩衝器，可操作來維持對應非二進位碼字的樣本組；一資料解碼器電路，可操作來：施加一非二進位資料解碼演算法到從該樣本組所得到的一解碼器輸入，以產生一非二進位解碼輸出；施加一二進位資料解碼演算法到該解碼器輸入，以產生一二進位解碼輸出；決定未滿足檢測的第一數目，以對應非二進位解碼輸出；決定未滿足檢測的第二數目，以對應二進位解碼輸出；至少部分基於未滿足檢測的該第一數目與未滿足檢測的該第二數目，來選擇該二進位解碼輸出與非二進位解碼輸出的其中一個以當作一選擇解碼結果。
- 如申請專利範圍第1項之資料處理系統，其中該非二進位解碼輸出係為第一非二進位解碼輸出，其中該二進位解碼輸出係為第一二進位解碼輸出，其中該資料解碼器電路係被進一步操作以：重新施加該非二進位資料解碼演算法到該選擇解碼結果所引導的該解碼器輸入，以產生第二非二進位解碼輸出；以及重新施加該二進位資料解碼演算法到該選擇解碼結果 所引導的該解碼器輸入，以產生第二二進位解碼輸出。
- 如申請專利範圍第1項之資料處理系統，其中施加該非二進位資料解碼演算法係使用非二進位H-矩陣，且其中施加該二進位資料解碼演算法係使用二進位H-矩陣。
- 如申請專利範圍第3項之資料處理系統，其中決定對應該非二進位解碼輸出的未滿足檢測之該第一數目包含：將該非二進位解碼輸出乘以該二進位H-矩陣以產生二進位等同物。
- 如申請專利範圍第1項之資料處理系統，其中在該非二進位碼字中的每一符號代表2N 圖案，其中N係為每一符號的非零位元數；且其中施加該二進位資料解碼演算法包括以具有單一位元符號來處理該非二進位碼字。
- 如申請專利範圍第1項之資料處理系統，其中當未滿足檢測的該第二數目小於未滿足檢測的該第一數目時，該二進位解碼輸出則會被選擇。
- 如申請專利範圍第1項之資料處理系統，其中當未滿足檢測的該第一數目小於未滿足檢測的該第二數目時，該非二進位解碼輸出則會被選擇。
- 如申請專利範圍第1項之資料處理系統，其中該系統進一步包含：一資料檢測器電路，可操作來施加一資料檢測演算法到該樣本組，以產生一檢測輸出，其中該解碼器輸入係從 該檢測輸出來取得。
- 如申請專利範圍第8項之資料處理系統，其中該資料檢測器電路係從包含以下的一群組選擇：Viterbi演算資料檢測器電路與最大後驗資料檢測器電路。
- 如申請專利範圍第1項之資料處理系統，其中該資料解碼器電路係為低密度奇偶檢驗電路。
- 如申請專利範圍第1項之資料處理系統，其中該資料處理系統係被實施當作從儲存裝置與接收裝置所組成群組選擇的部分裝置。
- 如申請專利範圍第1項之資料處理系統，其中該資料處理系統係被實施當作部分的積體電路。
- 一種資料處理方法，該資料處理方法包含：施加一非二進位資料解碼演算法到解碼器輸入以產生非二進位解碼輸出；施加一二進位資料解碼演算法到該解碼器輸入，以產生二進位解碼輸出；決定未滿足檢測的第一數目，以對應該非二進位解碼輸出；決定未滿足檢測的第二數目，以對應該二進位解碼輸出；以及至少部分基於未滿足檢測的該第一數目與未滿足檢測的該第二數目，來選擇該二進位解碼輸出與該非二進位解碼輸出的其中一個當作一選擇解碼結果。
- 如申請專利範圍第13項之方法，其中該非二進位 解碼輸出為第一非二進位解碼輸出，其中該二進位解碼輸出係為第一二進位解碼輸出，其中該方法進一步包含：重新施加該非二進位資料解碼演算法到該選擇解碼結果所引導的該解碼器輸入，以產生第二非二進位解碼輸出；以及重新施加該二進位資料解碼演算法到該選擇解碼結果所引導的該解碼器輸入，以產生第二二進位解碼輸出。
- 如申請專利範圍第14項之方法，其中施加該非二進位資料解碼演算法係使用非二進位H-矩陣，且其中施加該二進位資料解碼演算法係使用二進位H-矩陣。
- 如申請專利範圍第15項之方法，其中決定對應該非二進位解碼輸出的未滿足檢測之該第一數目包含：將該非二進位解碼輸出乘以該二進位H-矩陣以產生二進位等同物。
- 如申請專利範圍第13項之方法，其中當未滿足檢測的該第二數目小於未滿足檢測的該第一數目時，該二進位解碼輸出則會被選擇；且其中當未滿足檢測的該第一數目小於未滿足檢測的該第二數目時，該非二進位解碼輸出則會被選擇。
- 如申請專利範圍第13項之方法，其中該方法進一步包含：施加一資料檢測演算法到一樣本組，以產生一檢測輸出，其中該解碼器輸入係從該檢測輸出取得。
- 一種儲存裝置，該儲存裝置包含： 一儲存媒體；一頭組件，相關於該儲存媒體來配置並且可操作來提供對應該儲存媒體上之資訊的感應訊號；一讀取通道電路，包括：一類比前端電路，可操作來提供對應該感應訊號的類比訊號；一類比至數位轉換器電路，可操作來取樣該類比訊號，以產生一系列的數位樣本；一均衡器電路，可操作來均衡該等數位樣本以產生一樣本組；一樣本緩衝器，可操作來維持該樣本組；一資料檢測器電路，可操作來：施加一非二進位資料解碼演算法到從該樣本組取得的解碼器輸出，以產生一非二進位解碼輸出；施加一二進位資料解碼演算法到該解碼器輸入，以產生二進位解碼輸出；決定未滿足檢測的第一數目，以對應該非二進位解碼輸出；決定未滿足檢測的第二數目，以對應該二進位解碼輸出；至少部分基於未滿足檢測的該第一數目與未滿足檢測的該第二數目，來選擇該二進位解碼輸出與非二進位解碼輸出的其中一個以當作一選擇解碼結果。
- 如申請專利範圍第19項之儲存裝置，其中該非二 進位解碼輸出為第一非二進位解碼輸出，其中該二進位解碼輸出係為第一二進位解碼輸出，其中該資料解碼器電路進一步可操作以：重新施加該非二進位資料解碼演算法到該選擇解碼結果所引導的該解碼器輸入，以產生第二非二進位解碼輸出；以及重新施加該二進位資料解碼演算法到該選擇解碼結果所引導的該解碼器輸入，以產生第二二進位解碼輸出。
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| Application Number | Priority Date | Filing Date | Title |
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| US13/474,672 US8525707B1 (en) | 2012-05-17 | 2012-05-17 | Systems and methods for dual binary and non-binary decoding processing |
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| TW201406071A TW201406071A (zh) | 2014-02-01 |
| TWI456911B true TWI456911B (zh) | 2014-10-11 |
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| TW102113634A TWI456911B (zh) | 2012-05-17 | 2013-04-17 | 用於雙二進位及非二進位解碼處理的系統及方法 |
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| Country | Link |
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| US (1) | US8525707B1 (zh) |
| EP (1) | EP2665191B1 (zh) |
| JP (1) | JP5415638B2 (zh) |
| KR (1) | KR101385380B1 (zh) |
| CN (1) | CN103427843B (zh) |
| TW (1) | TWI456911B (zh) |
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| US10056920B1 (en) | 2015-11-03 | 2018-08-21 | Western Digital Technologies, Inc. | Data storage device encoding and interleaving codewords to improve trellis sequence detection |
| US10063257B1 (en) | 2015-11-03 | 2018-08-28 | Western Digital Technologies, Inc. | Data storage device encoding and interleaving codewords to improve trellis sequence detection |
| US9761273B1 (en) | 2015-11-03 | 2017-09-12 | Western Digital Technologies, Inc. | Data storage device encoding and interleaving codewords to improve trellis sequence detection |
| CN109429324B (zh) * | 2017-06-30 | 2021-03-05 | 中国电信股份有限公司 | 实现tti-b激活、去激活的方法、系统和基站 |
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- 2013-04-16 JP JP2013085447A patent/JP5415638B2/ja not_active Expired - Fee Related
- 2013-04-16 EP EP13163990.8A patent/EP2665191B1/en not_active Not-in-force
- 2013-04-17 KR KR1020130042407A patent/KR101385380B1/ko not_active IP Right Cessation
- 2013-04-17 TW TW102113634A patent/TWI456911B/zh not_active IP Right Cessation
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|---|---|
| TW201406071A (zh) | 2014-02-01 |
| JP2013243652A (ja) | 2013-12-05 |
| EP2665191A1 (en) | 2013-11-20 |
| CN103427843B (zh) | 2014-10-15 |
| CN103427843A (zh) | 2013-12-04 |
| KR20130129093A (ko) | 2013-11-27 |
| JP5415638B2 (ja) | 2014-02-12 |
| KR101385380B1 (ko) | 2014-04-14 |
| US8525707B1 (en) | 2013-09-03 |
| EP2665191B1 (en) | 2016-06-15 |
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