Claims (10)
一種垂直式半導體元件，包含：一絕緣基板，其具有一第一表面與一第二表面；位於該基板該第一表面與第二表面之間，貫穿該基板之複數導電栓，該複數導電栓形成一導電矩陣；一半導體層，形成於該第一表面上，其具有一第三表面與一第四表面，其中該第四表面面向該第一表面；一第一電極，形成於該第三表面上；以及一第二電極，形成於該第二表面上，用以電連接該導電矩陣。
A vertical semiconductor device comprising: an insulating substrate having a first surface and a second surface; between the first surface and the second surface of the substrate, a plurality of conductive plugs extending through the substrate, the plurality of conductive plugs Forming a conductive matrix; a semiconductor layer formed on the first surface, having a third surface and a fourth surface, wherein the fourth surface faces the first surface; a first electrode formed in the third And a second electrode formed on the second surface for electrically connecting the conductive matrix.
如申請專利範圍第1項所述之垂直式半導體元件，其中該基板包括一碳化矽(SiC)基板或一藍寶石(sapphire)基板。
The vertical semiconductor device of claim 1, wherein the substrate comprises a tantalum carbide (SiC) substrate or a sapphire substrate.
如申請專利範圍第2項所述之垂直式半導體元件，其中該半導體層包含一氮化鎵(gallium nitride,GaN)層，且該第一電極、該GaN層、該導電矩陣、與該第二電極形成一垂直式蕭特基位障二極體(Schottky barrier diode,SBD)。
The vertical semiconductor device of claim 2, wherein the semiconductor layer comprises a gallium nitride (GaN) layer, and the first electrode, the GaN layer, the conductive matrix, and the second The electrodes form a vertical Schottky barrier diode (SBD).
如申請專利範圍第2項所述之垂直式半導體元件，其中該半導體層包含：一具有第一導電型雜質摻雜之氮化鎵(gallium nitride,GaN)層；一具有第二導電型雜質摻雜之基極區，形成於該第三表面下之該GaN層中，且該基極區與該第一電極電連接；以及一具有第一導電型雜質摻雜之射極區，形成於該第三表面下之該基極區中，且該射極區與一形成於該第三表面上之第三電極電連接；其中，該第一電極、該半導體層、該第三電極、該導電
矩陣、與該第二電極形成一垂直式雙極接面電晶體(bipolar junction transistor,BJT)。
The vertical semiconductor device of claim 2, wherein the semiconductor layer comprises: a gallium nitride (GaN) layer doped with a first conductivity type impurity; and a second conductivity type impurity doped a base region of the impurity formed in the GaN layer under the third surface, wherein the base region is electrically connected to the first electrode; and an emitter region having a first conductivity type impurity doping, formed in the The base region under the third surface, and the emitter region is electrically connected to a third electrode formed on the third surface; wherein the first electrode, the semiconductor layer, the third electrode, the conductive
The matrix forms a vertical bipolar junction transistor (BJT) with the second electrode.
如申請專利範圍第2項所述之垂直式半導體元件，其中該半導體層包含：一具有第一導電型雜質摻雜之氮化鎵(gallium nitride,GaN)層；一具有第二導電型雜質摻雜之本體區，形成於該第三表面下之該GaN層中，且該本體區與該第一電極電連接；一具有第一導電型雜質摻雜之射極區，形成於該第三表面下之該本體區中，且該射極區與該第一電極電連接；以及一具有第二導電型雜質摻雜之注入區，形成於該GaN層與該基板之間，並藉由該導電矩陣與該第二電極電連接；且該垂直式半導體元件更包含：一介電層，形成於該第三表面上；以及一閘極，形成於該介電層上，其中，該第一電極、該半導體層、該導電矩陣、該第二電極、該介電層、與該閘極形成一垂直式絕緣閘雙極性電晶體(insulated gate bipolar transistor,IGBT)。
The vertical semiconductor device of claim 2, wherein the semiconductor layer comprises: a gallium nitride (GaN) layer doped with a first conductivity type impurity; and a second conductivity type impurity doped a bulk region formed in the GaN layer under the third surface, and the body region is electrically connected to the first electrode; an emitter region having a first conductivity type impurity doping, formed on the third surface In the body region, the emitter region is electrically connected to the first electrode; and an implant region having a second conductivity type impurity doping is formed between the GaN layer and the substrate, and the conductive region is The vertical semiconductor device further includes: a dielectric layer formed on the third surface; and a gate formed on the dielectric layer, wherein the first electrode The semiconductor layer, the conductive matrix, the second electrode, the dielectric layer, and the gate form a vertical insulated gate bipolar transistor (IGBT).
一種垂直式半導體元件製造方法，包含：提供一絕緣基板，其具有一第一表面與一第二表面；形成一半導體層於該第一表面上，且該半導體層具有一第三表面與一第四表面，其中該第四表面面向該第一表面；形成一第一電極於該第三表面上；形成複數穿孔貫穿該基板，且該複數穿孔形成一穿孔矩陣；形成複數導電栓於該複數穿孔中，以形成一導電矩陣；以
及形成一第二電極於該第二表面上，用以電連接該導電矩陣。
A method for fabricating a vertical semiconductor device, comprising: providing an insulating substrate having a first surface and a second surface; forming a semiconductor layer on the first surface, and the semiconductor layer has a third surface and a first surface a fourth surface, wherein the fourth surface faces the first surface; a first electrode is formed on the third surface; a plurality of perforations are formed through the substrate, and the plurality of perforations form a perforation matrix; and a plurality of conductive plugs are formed on the plurality of perforations Medium to form a conductive matrix;
And forming a second electrode on the second surface for electrically connecting the conductive matrix.
如申請專利範圍第6項所述之垂直式半導體元件製造方法，其中該基板包括一碳化矽(SiC)基板或一藍寶石(sapphire)基板。
The method of manufacturing a vertical semiconductor device according to claim 6, wherein the substrate comprises a tantalum carbide (SiC) substrate or a sapphire substrate.
如申請專利範圍第7項所述之垂直式半導體元件製造方法，其中該形成該半導體層之步驟，包含形成一氮化鎵(gallium nitride,GaN)層，且該第一電極、該GaN層、該導電矩陣、與該第二電極形成一垂直式蕭特基位障二極體(Schottky barrier diode,SBD)。
The method of manufacturing a vertical semiconductor device according to claim 7, wherein the step of forming the semiconductor layer comprises forming a gallium nitride (GaN) layer, and the first electrode, the GaN layer, The conductive matrix forms a vertical Schottky barrier diode (SBD) with the second electrode.
如申請專利範圍第7項所述之垂直式半導體元件製造方法，其中該形成該半導體層之步驟包含：形成一具有第一導電型雜質摻雜之氮化鎵(gallium nitride,GaN)層；於該第三表面下之該GaN層中，形成一具有第二導電型雜質摻雜之基極區，且該基極區與該第一電極電連接；以及於該第三表面下之該基極區中，形成一具有第一導電型雜質摻雜之射極區，且該射極區與一形成於該第三表面上之第三電極電連接；其中，該第一電極、該半導體層、該第三電極、該導電矩陣、與該第二電極形成一垂直式雙極接面電晶體(bipolar junction transistor,BJT)。
The method for fabricating a vertical semiconductor device according to claim 7, wherein the step of forming the semiconductor layer comprises: forming a gallium nitride (GaN) layer doped with a first conductivity type impurity; a pedestal region having a second conductivity type impurity doped in the GaN layer under the third surface, wherein the base region is electrically connected to the first electrode; and the base under the third surface Forming an emitter region doped with a first conductivity type impurity, and the emitter region is electrically connected to a third electrode formed on the third surface; wherein the first electrode, the semiconductor layer, The third electrode, the conductive matrix, and the second electrode form a vertical bipolar junction transistor (BJT).
如申請專利範圍第7項所述之垂直式半導體元件製造方法，其中該半導體層包括第一導電型雜質摻雜之氮化鎵(gallium nitride,GaN)層，且該形成該半導體層之步驟包含：形成該GaN層；
於該GaN層中，形成一具有第二導電型雜質摻雜之本體區，且該本體區與該第一電極電連接；於該本體區中，形成一具有第一導電型雜質摻雜之射極區，且該射極區與該第一電極電連接；以及於該GaN層與該基板之間，形成一具有第二導電型雜質摻雜之注入區，該注入區藉由該導電矩陣與該第二電極電連接；且該垂直式半導體元件製造方法更包含：形成一介電層於該第三表面上；以及形成一閘極於該介電層上，其中，該第一電極、該半導體層、該導電矩陣、該第二電極、該介電層、與該閘極形成一垂直式絕緣閘雙極性電晶體(insulated gate bipolar transistor,IGBT)。
The method of manufacturing a vertical semiconductor device according to claim 7, wherein the semiconductor layer comprises a first conductivity type impurity-doped gallium nitride (GaN) layer, and the step of forming the semiconductor layer comprises Forming the GaN layer;
Forming a body region doped with a second conductivity type impurity in the GaN layer, and the body region is electrically connected to the first electrode; and forming a doping with a first conductivity type impurity in the body region a polar region, wherein the emitter region is electrically connected to the first electrode; and between the GaN layer and the substrate, an implant region having a second conductivity type impurity doping is formed, wherein the implant region is formed by the conductive matrix The second electrode is electrically connected; and the vertical semiconductor device manufacturing method further comprises: forming a dielectric layer on the third surface; and forming a gate on the dielectric layer, wherein the first electrode The semiconductor layer, the conductive matrix, the second electrode, the dielectric layer, and the gate form a vertical insulated gate bipolar transistor (IGBT).