TWI456718B - Package structure and fabrication method thereof - Google Patents

Package structure and fabrication method thereof Download PDF

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Publication number
TWI456718B
TWI456718B TW100138823A TW100138823A TWI456718B TW I456718 B TWI456718 B TW I456718B TW 100138823 A TW100138823 A TW 100138823A TW 100138823 A TW100138823 A TW 100138823A TW I456718 B TWI456718 B TW I456718B
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TW
Taiwan
Prior art keywords
package structure
encapsulant
electrical connection
forming
positioning holes
Prior art date
Application number
TW100138823A
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Chinese (zh)
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TW201318125A (en
Inventor
林邦群
蔡岳穎
陳泳良
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矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW100138823A priority Critical patent/TWI456718B/en
Priority to CN2011103598808A priority patent/CN103077931A/en
Publication of TW201318125A publication Critical patent/TW201318125A/en
Application granted granted Critical
Publication of TWI456718B publication Critical patent/TWI456718B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

Landscapes

  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Claims (20)

一種封裝結構，係包括：封裝膠體；嵌埋並外露於該封裝膠體之底面之複數電性連接墊；嵌埋於該封裝膠體中且電性連接該電性連接墊之半導體晶片；以及形成於該封裝膠體上之複數定位孔。a package structure comprising: a package body; a plurality of electrical connection pads embedded and exposed on a bottom surface of the package body; a semiconductor wafer embedded in the package body and electrically connected to the electrical connection pad; a plurality of positioning holes on the encapsulant. 如申請專利範圍第1項所述之封裝結構，其中，復包括置晶墊，係嵌埋並外露於該封裝膠體之底面。The package structure according to claim 1, wherein the composite pad is embedded and exposed on the bottom surface of the encapsulant. 如申請專利範圍第1項所述之封裝結構，其中，復包括複數銲線，係電性連接該半導體晶片與電性連接墊。The package structure of claim 1, wherein the plurality of bonding wires are electrically connected to the semiconductor wafer and the electrical connection pads. 如申請專利範圍第1項所述之封裝結構，其中，該半導體晶片係覆晶接置於該電性連接墊上。The package structure of claim 1, wherein the semiconductor wafer is laminated on the electrical connection pad. 如申請專利範圍第1項所述之封裝結構，其中，復包括複數銲球，係接置於該電性連接墊上。The package structure of claim 1, wherein the plurality of solder balls are integrally attached to the electrical connection pad. 如申請專利範圍第1項所述之封裝結構，其中，該電性連接墊係包括複數堆疊之金屬層，該定位孔係位於該封裝膠體之底面，且該定位孔中具有該等金屬層。The package structure of claim 1, wherein the electrical connection pad comprises a plurality of stacked metal layers, the positioning holes are located on a bottom surface of the encapsulant, and the metal holes are disposed in the positioning holes. 如申請專利範圍第6項所述之封裝結構，其中，該等金屬層之材質由底至頂係為金/鎳/鈀/金(Au/Ni/Pd/Au)、金/鈀/鎳/鈀(Au/Pd/Ni/Pd)或銅/金/銅(Cu/Au/Cu)。The package structure according to claim 6, wherein the material of the metal layer is gold/nickel/palladium/gold (Au/Ni/Pd/Au), gold/palladium/nickel/from the bottom to the top. Palladium (Au/Pd/Ni/Pd) or copper/gold/copper (Cu/Au/Cu). 如申請專利範圍第1項所述之封裝結構，其中，該定位孔係位於該封裝膠體之頂面。The package structure of claim 1, wherein the positioning hole is located on a top surface of the encapsulant. 一種封裝結構之製法，係包括：於一第一承載板上形成置晶墊與電性連接墊；於該置晶墊上接置半導體晶片，並藉由銲線電性連接該半導體晶片與電性連接墊；於該第一承載板上形成包覆該半導體晶片、銲線、置晶墊與電性連接墊的封裝膠體，並於該封裝膠體上形成有複數定位孔；移除該第一承載板，且顯露該複數定位孔；於該封裝膠體具有該等定位孔之表面上接置第二承載板，該第二承載板具有複數對應連接各該定位孔的定位凸塊；於該電性連接墊上接置銲球；以及移除該第二承載板。A method for fabricating a package structure includes: forming a crystal pad and an electrical connection pad on a first carrier plate; attaching a semiconductor wafer to the pad, and electrically connecting the semiconductor chip and the electrical property by a bonding wire a bonding pad; forming an encapsulant covering the semiconductor wafer, the bonding wire, the pad and the electrical connection pad on the first carrier, and forming a plurality of positioning holes on the encapsulant; removing the first carrier a second locating plate is disposed on the surface of the encapsulant having the locating holes, and the second locating plate has a plurality of positioning lands corresponding to the locating holes; A solder ball is attached to the connection pad; and the second carrier plate is removed. 如申請專利範圍第9項所述之封裝結構之製法，其中，該複數定位孔之形成係包括於第一承載板上形成有柱體，且令該封裝膠體係包覆該柱體，以藉該柱體定義定位孔之輪廓，且移除該第一承載板的步驟復包括自該封裝膠體底面移除至少該部分柱體以顯露該複數定位孔。The method for manufacturing a package structure according to claim 9, wherein the forming of the plurality of positioning holes comprises forming a column on the first carrier plate, and the encapsulating system covers the column to borrow The cylinder defines a contour of the positioning hole, and the step of removing the first carrier plate includes removing at least the portion of the pillar from the bottom surface of the encapsulant to expose the plurality of positioning holes. 如申請專利範圍第10項所述之封裝結構之製法，其中，該柱體之材質自封裝膠體底面係依序為銅/金/鎳/鈀/金(Cu/Au/Ni/Pd/Au)或銅/金/鈀/鎳/鈀(Cu/Au/Pd/Ni/Pd)。The method for manufacturing a package structure according to claim 10, wherein the material of the column is copper/gold/nickel/palladium/gold (Cu/Au/Ni/Pd/Au) from the bottom surface of the package. Or copper/gold/palladium/nickel/palladium (Cu/Au/Pd/Ni/Pd). 如申請專利範圍第11項所述之封裝結構之製法，其中，移除至少該部分柱體之步驟係包括移除該柱體的銅層或部分銅層，並外露該柱體的金層或剩餘銅層。The method for manufacturing a package structure according to claim 11, wherein the step of removing at least the portion of the pillar comprises removing a copper layer or a portion of the copper layer of the pillar and exposing the gold layer of the pillar or The remaining copper layer. 如申請專利範圍第9項所述之封裝結構之製法，其中，該複數定位孔之形成係包括以模具封蓋該半導體晶片、銲線、置晶墊與電性連接墊，且該模具上係具有定位柱，以於形成該封裝膠體及移除該模具後，於該封裝膠體之頂面對應該定位柱處顯露出該等定位孔。The method for manufacturing a package structure according to claim 9, wherein the forming the plurality of positioning holes comprises covering the semiconductor wafer, the bonding wire, the crystal pad and the electrical connection pad with a mold, and the mold is attached Having a positioning post for forming the encapsulant and removing the mold, the positioning holes are exposed at the top of the encapsulant facing the positioning post. 如申請專利範圍第9項所述之封裝結構之製法，復包括進行切割步驟，以移除該封裝膠體具有該定位孔的部分。The method for manufacturing a package structure according to claim 9 further comprises performing a cutting step to remove a portion of the encapsulant having the positioning hole. 一種封裝結構之製法，係包括：提供一第一承載板，於該第一承載板上形成電性連接墊；於該電性連接墊上覆晶接置半導體晶片；於該第一承載板上形成包覆該半導體晶片與電性連接墊的封裝膠體，並於該封裝膠體上形成有複數定位孔；移除該第一承載板，且顯露該複數定位孔；於該封裝膠體具有該等定位孔之表面上接置第二承載板，該第二承載板具有複數對應連接各該定位孔的定位凸塊；於該電性連接墊上接置銲球；以及移除該第二承載板。A method for manufacturing a package structure includes: providing a first carrier plate, forming an electrical connection pad on the first carrier plate; and flipping the semiconductor wafer on the electrical connection pad; forming on the first carrier plate Encapsulating the semiconductor wafer and the electrical connection pad, and forming a plurality of positioning holes on the encapsulant; removing the first carrier and exposing the plurality of positioning holes; and having the positioning holes in the encapsulant The second carrier plate is connected to the surface, and the second carrier plate has a plurality of positioning protrusions corresponding to the positioning holes; the solder balls are attached to the electrical connection pads; and the second carrier plate is removed. 如申請專利範圍第15項所述之封裝結構之製法，其中，該複數定位孔之形成係包括於第一承載板上形成有柱體，且令該封裝膠體係包覆該柱體，以藉該柱體定義定位孔之輪廓，且移除該第一承載板的步驟復包括自該封裝膠體底面移除至少該部分柱體以顯露該複數定位孔。The method for manufacturing a package structure according to claim 15 , wherein the forming of the plurality of positioning holes comprises forming a column on the first carrier plate, and the encapsulating system covers the column to borrow The cylinder defines a contour of the positioning hole, and the step of removing the first carrier plate includes removing at least the portion of the pillar from the bottom surface of the encapsulant to expose the plurality of positioning holes. 如申請專利範圍第16項所述之封裝結構之製法，其中，該柱體之材質自封裝膠體底面係依序為銅/金/銅(Cu/Au/Cu)。The method for manufacturing a package structure according to claim 16, wherein the material of the pillar is copper/gold/copper (Cu/Au/Cu) from the bottom surface of the encapsulant. 如申請專利範圍第17項所述之封裝結構之製法，其中，移除至少該部分柱體之步驟係包括移除該柱體的銅層或部分銅層，並外露該柱體的金層或剩餘銅層。The method of manufacturing a package structure according to claim 17, wherein the step of removing at least the portion of the pillar comprises removing a copper layer or a portion of the copper layer of the pillar and exposing the gold layer of the pillar or The remaining copper layer. 如申請專利範圍第15項所述之封裝結構之製法，其中，該複數定位孔之形成係包括以模具封蓋該半導體晶片與電性連接墊，且該模具上係具有定位柱，以於形成該封裝膠體及移除該模具後，於該封裝膠體之頂面對應該定位柱處顯露出該等定位孔。The method for manufacturing a package structure according to claim 15, wherein the forming of the plurality of positioning holes comprises covering the semiconductor wafer and the electrical connection pad with a mold, and the mold has a positioning post for forming After the encapsulant and the mold are removed, the positioning holes are exposed at the top of the encapsulant facing the positioning post. 如申請專利範圍第15項所述之封裝結構之製法，復包括進行切割步驟，以移除該封裝膠體具有該定位孔的部分。The method of fabricating the package structure of claim 15 further comprises performing a cutting step to remove the portion of the encapsulant having the positioning hole.
TW100138823A 2011-10-26 2011-10-26 Package structure and fabrication method thereof TWI456718B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW100138823A TWI456718B (en) 2011-10-26 2011-10-26 Package structure and fabrication method thereof
CN2011103598808A CN103077931A (en) 2011-10-26 2011-11-14 Package structure and method for fabricating the same

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TW100138823A TWI456718B (en) 2011-10-26 2011-10-26 Package structure and fabrication method thereof

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TWI456718B true TWI456718B (en) 2014-10-11

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US10643863B2 (en) * 2017-08-24 2020-05-05 Advanced Semiconductor Engineering, Inc. Semiconductor package and method of manufacturing the same

Citations (1)

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TW201123374A (en) * 2009-12-28 2011-07-01 Siliconware Precision Industries Co Ltd Package structure and fabrication method thereof

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US5830800A (en) * 1997-04-11 1998-11-03 Compeq Manufacturing Company Ltd. Packaging method for a ball grid array integrated circuit without utilizing a base plate
CN2386534Y (en) * 1999-07-23 2000-07-05 亿光电子工业股份有限公司 Enclosing device for light-emitting diode
US6897566B2 (en) * 2002-06-24 2005-05-24 Ultra Tera Corporation Encapsulated semiconductor package free of chip carrier
CN101022100A (en) * 2006-10-13 2007-08-22 伟志电子(常州)有限公司 Light-emitting diode module

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TW201123374A (en) * 2009-12-28 2011-07-01 Siliconware Precision Industries Co Ltd Package structure and fabrication method thereof

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