TWI456584B - 多埠記憶體及操作 - Google Patents

多埠記憶體及操作 Download PDF

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Publication number
TWI456584B
TWI456584B TW099128319A TW99128319A TWI456584B TW I456584 B TWI456584 B TW I456584B TW 099128319 A TW099128319 A TW 099128319A TW 99128319 A TW99128319 A TW 99128319A TW I456584 B TWI456584 B TW I456584B
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TW
Taiwan
Prior art keywords
command
control
memory
control circuit
bus
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TW099128319A
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English (en)
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TW201120907A (en
Inventor
Dan Skinner
J Thomas Pawlowski
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Micron Technology Inc
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Publication of TW201120907A publication Critical patent/TW201120907A/zh
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Publication of TWI456584B publication Critical patent/TWI456584B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G06F13/1631—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1636—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using refresh
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Multimedia (AREA)
  • Bus Control (AREA)
  • Memory System (AREA)
  • Static Random-Access Memory (AREA)

Claims (18)

  1. 一種記憶體，其包含：兩個或更多個埠，每一埠包含一個或多個記憶體區域及用於回應於命令而控制對該一個或多個記憶體區域之存取的控制電路；及至少一個埠間控制匯流排，用於在該等埠中之兩者或更多者之該控制電路之間傳送命令；其中兩者或更多者之外部控制匯流排選擇性地被耦合至該兩個或更多個埠，該兩者或更多者之外部控制匯流排係不同於該至少一個埠間控制匯流排；及其中該兩個或更多個埠之每一者的該控制電路經組態以選擇是否回應自耦合至彼埠之該一外部控制匯流排或自該至少一埠間控制匯流排所接收之命令。
  2. 如請求項1之記憶體，其中少於所有該等埠係耦合至一埠間控制匯流排。
  3. 如請求項1至2中任一項之記憶體，其中該一個或多個記憶體區域包含選自由揮發性及非揮發性記憶體單元組成之群組之記憶體單元之庫。
  4. 如請求項1至2中任一項之記憶體，其中該等埠中之至少一者之該控制電路進一步經組態以選擇性地使彼控制電路與耦合至彼控制電路之一埠間控制匯流排隔離。
  5. 如請求項1至2中任一項之記憶體，其中該兩者或更多者之外部控制匯流排提供自一外部裝置所接收之命令。
  6. 如請求項1之記憶體，其中該等埠之至少一者包含一開 關，該開關經組態以選擇性地將該等埠之該至少一者的控制電路與該至少一埠間控制匯流排相隔離。
  7. 如請求項1之記憶體，其中該等埠中之至少一者之該控制電路經組態以選擇性地對自耦合至彼埠之該一外部控制匯流排、耦合至其之一第一埠間控制匯流排或耦合至其之一第二埠間控制匯流排接收的命令作出回應。
  8. 如請求項1之記憶體，其中該等埠中之每一者之該控制電路經組態以選擇性地將自一外部裝置接收之一命令傳遞至該至少一埠間控制匯流排。
  9. 如請求項1之記憶體，進一步包含：一內部資料匯流排，用於將資料值自該一個或多個記憶體區域傳送至一外部裝置，且用於將資料值自一外部裝置傳送至該一個或多個記憶體區域。
  10. 如請求項1之記憶體，其中兩個或更多個埠之至少一者之該控制電路經組態以僅對自耦合至彼控制電路之一個埠間控制匯流排接收之命令作出回應的控制電路。
  11. 如請求項1之記憶體，其中該等埠之每一者之該控制電路係難以程式化以回應接收自耦合至彼埠之該一外部控制匯流排或接收自該埠間控制匯流排之命令。
  12. 一種控制具有兩個或更多個埠之一多埠記憶體之方法，其中每一埠具有一個或多個記憶體區域及用於回應於命令而控制對該一個或多個記憶體區域之存取的控制電路，該方法包含：在該多埠記憶體之一第一埠之該控制電路處自一外部 匯流排接收一第一命令；自該第一埠之該控制電路，經由耦合於該第一埠之該控制電路及該多埠記憶體之一個或多個額外埠之間的一埠間控制匯流排，將該第一命令轉發至該多埠記憶體之該一個或多個額外埠之該控制電路，其中該一個或多個額外埠之每一者的該控制電路與該第一埠是分隔開的；使用該一個或多個額外埠之每一者的該控制電路選擇該一個或多個額外埠之該控制電路將回應自該第一埠之該控制電路經由該埠間控制匯流排轉發之該第一命令或將回應自位於該一個或多個額外埠處與該埠間控制匯流排不同之另一外部匯流排所接收之一第二命令；及當該一個或多個額外埠之該控制電路選擇回應自該第一埠之該控制電路經由該埠間控制匯流排所轉發之該第一命令時，在該第一埠之該控制電路處處理該第一命令以及在該一個或多個額外埠之該控制電路處處理該第一命令，以同時存取該第一埠及該一個或多個額外埠之記憶體區域。
  13. 如請求項12之方法，其中接收一第一命令包含接收一讀取命令或一寫入命令。
  14. 如請求項13之方法，其中接收該第一命令進一步包含接收與該命令相關聯之一位址。
  15. 如請求項14之方法，其中處理該第一命令進一步包含：若與該第一命令相關聯之該位址不匹配一特定埠之一記憶體區域之一位址，則在該特定埠之該控制電路處忽略 該第一命令。
  16. 如請求項12至15中任一項之方法，其中轉發該第一命令進一步包含將該第一命令自一個埠之該控制電路級聯至連續埠之該控制電路。
  17. 如請求項12至15中任一項之方法，其中轉發該第一命令進一步包含將該第一命令轉發至每一剩餘埠之該控制電路。
  18. 如請求項12至15中任一項之方法，進一步包含：使至少一個埠之該控制電路與該第一命令隔離。
TW099128319A 2009-08-24 2010-08-24 多埠記憶體及操作 TWI456584B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/546,258 US8769213B2 (en) 2009-08-24 2009-08-24 Multi-port memory and operation

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TWI456584B true TWI456584B (zh) 2014-10-11

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US (2) US8769213B2 (zh)
EP (1) EP2470999B1 (zh)
JP (1) JP5549897B2 (zh)
KR (1) KR101327665B1 (zh)
CN (1) CN102483724B (zh)
TW (2) TWI537976B (zh)
WO (1) WO2011028409A2 (zh)

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KR101781617B1 (ko) * 2010-04-28 2017-09-25 삼성전자주식회사 통합 입출력 메모리 관리 유닛을 포함하는 시스템 온 칩
US9275699B2 (en) * 2012-08-17 2016-03-01 Rambus Inc. Memory with alternative command interfaces
JP5998814B2 (ja) 2012-10-03 2016-09-28 株式会社ソシオネクスト 半導体記憶装置
US10019402B2 (en) 2016-05-12 2018-07-10 Quanta Computer Inc. Flexible NVME drive management solution via multiple processor and registers without multiple input/output expander chips

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JPH07160655A (ja) * 1993-12-10 1995-06-23 Hitachi Ltd メモリアクセス方式
US20020087751A1 (en) * 1999-03-04 2002-07-04 Advanced Micro Devices, Inc. Switch based scalable preformance storage architecture
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Also Published As

Publication number Publication date
TWI537976B (zh) 2016-06-11
KR101327665B1 (ko) 2013-11-12
EP2470999A2 (en) 2012-07-04
CN102483724B (zh) 2015-08-19
KR20120055673A (ko) 2012-05-31
JP2013506890A (ja) 2013-02-28
US8769213B2 (en) 2014-07-01
TW201120907A (en) 2011-06-16
US20140289482A1 (en) 2014-09-25
EP2470999B1 (en) 2016-11-16
WO2011028409A3 (en) 2011-06-03
JP5549897B2 (ja) 2014-07-16
US8930643B2 (en) 2015-01-06
EP2470999A4 (en) 2013-01-23
CN102483724A (zh) 2012-05-30
US20110047311A1 (en) 2011-02-24
WO2011028409A2 (en) 2011-03-10
TW201447912A (zh) 2014-12-16

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