TWI455315B - A ditch - type power transistor with a low gate / drain capacitance - Google Patents

Description

Ditch power transistor with low gate/drain capacitance

The present invention relates to a power MOSFET, and more particularly to a trench power MOSFET having a gate-drain capacitance ( _Cgd ).

Power transistors can withstand high voltages and high currents simultaneously. Among them, the trench type power transistor is mainly used as a signal source and a circuit switching element, and has a low on-resistance value and a high-voltage-resistant current, and can be applied to a notebook computer, a digital camera, a mobile phone, a power supply, a liquid crystal display ( LCD Monitor) and other consumer electronics products.

Referring to FIG. 1, the current trench power transistor 1 includes a drain structure 11, a well 12, a gate trench structure 13, and a source structure 14.

The drain structure 11 is first conductive (ie, n-type) and has a base layer 111 and a first layer 112 formed on the base layer 111. The main carrier concentration of the base layer 111 is greater than the main carrier concentration of the first portion layer 112, that is, the base layer 111 and the first portion layer 112 are respectively n ⁺ type and n type.

The well region 12 is opposite to the first conductivity second conductivity (ie, p-type) and physically contacts the first portion 112 of the drain structure 11 and is located on the first portion layer 112.

The gate trench structure 13 is formed in the first portion 112 of the drain structure 11 and the well region 12, and has a conductive block 132, and an isolation of the conductive block 132 from the first portion 112 and the well Dielectric layer 131 of region 12. The dielectric layer 131 is made of, for example, cerium oxide (SiO ₂ ), and the conductive block 132 is made of, for example, polycrystalline germanium and has electrical conductivity.

The source structure 14 has a first conductive region and a source region 141 formed on the well region 12, and a contact plug 142 that is in physical contact with the source region 141 and can be electrically connected externally. The main carrier concentration of the source region 141 is greater than the main carrier concentration of the well region 12, and the source region 141 and the drain structure 11 are separated by the well region 12, and the contact plug 142 is made of a metal material. For example, tungsten is composed.

When a predetermined voltage is applied to the conductive block 132 of the gate trench structure 13 and the base layer 111 of the gate structure 11, respectively, the well region 12 is adjacent to the region of the dielectric layer 131 of the gate trench structure 13 for supplying charge therefrom. The pole structure 11 flows to the source region 141 of the source structure 14 to form conduction.

Since the current trench power transistor 1 is turned on, the charge flows only at the well region 12 adjacent to the sidewall of the gate trench structure 13, so that the first layer 112 of the drain structure 11 is adjacent to the gate trench The area of the bottom wall of the structure 13 produces a large gate/drain capacitance, which is then amplified by the transistor to form a higher Miller effect capacitance, thereby increasing the turn-off time as a switching circuit component, and Reduce the component reaction speed, and easily short-circuit under low-frequency response conditions, or reduce the cut-off frequency under high-frequency response conditions, or the impedance is too low as an amplifier.

Accordingly, it is an object of the present invention to provide a trench power transistor having a low gate/drain capacitance with a low Miller effect capacitance and a high component response speed.

Thus, the trench power transistor having low gate/drain capacitance of the present invention comprises a drain structure, a well region, a gate trench structure, and a source structure. The drain structure is composed of a semiconductor material and includes a first conductive drain region, and a pocket region located in the drain region and having a main carrier concentration smaller than the drain region; the well region is opposite to The second conductivity of the first conductivity, and physically contacting the drain region and the pocket region; the gate trench structure is formed in the drain region and the well region, and includes a conductive block, and a The conductive block and the well-separated dielectric layer; the source structure includes a source region that is first conductive and that is not in contact with the drain structure by the well region.

The effect of the invention: the invention adds a pocket region with a main carrier concentration less than the drain region in the drain structure, and reduces the capacitance between the gate/drain, thereby reducing the Miller effect capacitance and reducing the transistor reaction Time to increase the speed of the transistor as a whole when switching between on and off.

The foregoing and other technical aspects, features and advantages of the present invention will be apparent from the following description of the preferred embodiments.

Referring to FIG. 2, a preferred embodiment of the trench power transistor 2 having a low gate/drain capacitance of the present invention includes a drain structure 21, a well region 22, a gate trench structure 23, and a source structure. twenty four.

The drain structure 21 includes a drain region 211 and a pocket region 212. The drain region 211 has a base layer 213, and a first portion layer 214 and a second portion layer 215 sequentially formed on the base layer 213.

The base layer 213 and the first and second layers 214 and 215 are formed into a first conductivity (ie, an n-conductivity type), and the equal layers 213, 214, and 215 are formed in an epitaxial manner, and the base layer 213 is formed. The concentration of the main carrier is not less than the concentration of the main carrier of the first layer 214, and the concentration of the main carrier of the first layer 214 is not less than the concentration of the main carrier of the second layer 215, that is, the base layer 213, The first portion layer 214 and the second portion layer 215 are respectively of an n ⁺ type, an n type, and an n ⁻ type. The pocket 212 is first conductive (i.e., n-conductive) and physically contacts the top of the first layer 214. The primary carrier concentration of the pocket 212 is less than the primary carrier concentration of the drain region 211.

The well region 22 physically contacts the second layer 215 of the drain structure 21 and is in a second conductivity (ie, p-type), the main carrier concentration of the well region 22 being greater than the main carrier of the second portion layer 215 Concentration, ie p-type.

The gate trench structure 23 is formed in the well region 22 and the first portion 214 of the drain structure 21, and correspondingly located on the pocket region 212 of the drain structure 21 to physically contact the pocket region 212. . The gate trench structure 23 includes a conductive block 232 that is electrically connected to the outside to receive external power, and a dielectric layer 231 that isolates the conductive block 232 from the well region 22 and the conductive block 232 from the gate structure 21. . The conductive block 232 is mainly composed of a polysilicon having a conductive property, and the dielectric layer 231 is an insulator and may be selected from cerium oxide.

The source structure 24 includes a source region 241 that physically contacts the top of the well region 22, and a contact plug 242 that is in physical contact with the source region 241 and electrically connected to the outside. The source region 241 passes through the dielectric layer. 231 is spaced from the conductive block 232 and is isolated from the drain structure 21 by the well region 22. The source region 241 is first conductive, and the main carrier concentration of the source region 241 is greater than the main carrier concentration of the well region 22. The contact plug 242 is formed of a material having a conductive property. In the preferred embodiment, the contact plug 242 is selected from the group consisting of tungsten, copper, aluminum, and a combination thereof is made of a material.

It should be noted that, in the preferred embodiment, the first conductivity is mainly an n-type semiconductor, and the second conductivity corresponds to the first conductivity and is mainly a p-type semiconductor. Of course, the first conductivity may also be a p-type semiconductor, and the second conductivity corresponds to an n-type semiconductor.

When a predetermined voltage is applied to the conductive block 232 of the gate trench structure 23 and the base layer 213 of the gate structure 21, the well region 22 is adjacent to the region of the dielectric layer 231 of the gate trench structure 23 for charging therefrom. The pole structure 21 flows to the source region 241 of the source structure 24 to form conduction.

The pocket region 212 of the drain structure 21 physically contacts the dielectric layer 231 of the gate trench structure 23, and the primary carrier concentration of the pocket region 212 is less than the primary carrier concentration of the first portion layer 214. When the preferred embodiment is turned on, the capacitance (C _o , oxide capacitance) defined by the dielectric layer 231 of the gate trench structure 23 and the depletion capacitance defined by the region of the gate structure 21 adjacent to the gate trench structure 23 ( C _d , depletion layer drain) is connected in series to become gate-drain capacitance (C _gd ). Since the concentration of the main carrier of the pocket 212 is smaller than the concentration of the main carrier of the first layer 214, and the capacitance value is proportional to the concentration of the main carrier, the depletion of the gate structure 21 including the pocket 212 is insufficient. The depletion capacitance defined by the region is lower than the depletion capacitance defined by the drain structure 21 of the current non-pocket region 212, further obtaining a low gate/drain capacitance, thereby significantly reducing the capacitance value generated by the Miller effect, so that the present invention has The trench-type power transistor 2 with low gate/drain capacitance has a high switching switching reaction speed as a whole, and reduces the time required to turn off the trench power transistor.

The trench type power transistor 2 having the low gate/drain capacitance described in the above preferred embodiment of the present invention can be more clearly understood by the following description of the fabrication method.

Referring to FIG. 3, the trench type power transistor 2 having a low gate/drain capacitance is first prepared by preparing an n ⁺ epitaxial wafer as the base layer 213, and then ethidium in the base layer 213. An n-type layer body 31 and an n-type layer body 32 are formed.

Referring to FIG. 4, a trench 33 recessed in the direction of the base layer 213 is formed on the top surface of the n-type layer body 32 by lithography and etching. Continuing, a dielectric layer 231, such as cerium oxide, which is mainly composed of an insulating material, is deposited in the trench 33.

Referring to FIG. 5, ions such as boron (B), gallium (Ga), and indium (In) are implanted from the top surface of the n-type layer body 32 and the bottom of the trench 33 toward the base layer 213 by ion implantation. A p-type dopant is formed to form an implant region 34 and a pocket region 212. The implant region 34 is formed on the n-type layer body 32. The pocket region 212 is formed on the n-type layer body 31, and the main carrier concentration of the n-type layer body 31 is not less than the n-type layer body 32. The concentration of the main carrier can be such that the implanted region 34 has a second conductivity by adjusting the concentration of the ion implant, the pocket region 212 is first conductive, and the main region of the pocket region 212 The sub-concentration is smaller than the main carrier concentration of the n, n-type layer bodies 31, 32.

In addition, since the implanted region 34 is formed downward from the top surface of the n-type layer body 32, the n-type layer body 32 is defined by the implanted region 34 as the implanted region 34 and a physical contact with the implant. a second layer 215 under the entrance region 34; the pocket region 212 is formed downward from a bottom portion of the trench 33, that is, a region adjacent to the top of the second portion layer 215, and the n-type layer body 31 is formed by the pocket region 212 is defined as the pocket 212 and a first layer 214 that physically contacts the pocket 212.

The conductive block 232 formed of a conductive material such as polysilicon is deposited on the remaining unfilled regions of the trench 33.

Referring to FIG. 2, the gate trench structure 23 including the dielectric layer 231 and the conductive block 232 is formed in the direction of the base layer 213 by ion implantation around the top of the implant region 34. The first conductive source region 241. The source region 241 defines the implant region 34 as the source region 241 and the well region 22 in physical contact with the source region 241.

Finally, a contact plug 242 is formed in the source region 241 in physical contact with the source region 241 to form the trench power transistor 2 having a low gate/drain capacitance.

In summary, the trench power transistor 2 having a low gate/drain capacitance of the present invention is in physical contact with the dielectric layer 231 of the gate trench structure 23 by the pocket region 212, and its main carrier concentration Less than the main carrier concentration of the first and second layers 214 and 215, the gate/drain capacitance can be reduced, thereby reducing the capacitance generated by the Miller effect, thereby improving the trench type of the low gate/drain capacitance of the present invention. Since the operating speed of the power transistor 2 is high, the object of the present invention can be achieved.

However, the above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention, All remain within the scope of the invention patent.

2‧‧‧Ditch-type transistors with low-gate/bagger capacitance

21‧‧‧汲polar structure

211‧‧‧Bungee Area

212‧‧‧Bag area

213‧‧‧ base layer

214‧‧‧ first floor

215‧‧‧ second floor

22‧‧‧ Well Area

23‧‧ ‧ gate structure structure

231‧‧‧ dielectric layer

232‧‧‧Electrical block

24‧‧‧ source structure

241‧‧‧ source area

242‧‧‧Contact plug

31‧‧‧n-type layer

32‧‧‧n ^- type layer

33‧‧‧ditch

34‧‧‧ implanted area

Figure 1 is a schematic cross-sectional view showing a current trench type power transistor;

Figure 2 is a cross-sectional view showing a preferred embodiment of the present invention;

Figure 3 is a schematic cross-sectional view showing a base layer, an n-type layer body, and an n ^- type layer body formed in sequence;

Figure 4 is a cross-sectional view showing the formation of a trench, an implanted region, and a pocket region;

Figure 5 is a cross-sectional view showing the formation of a dielectric layer and a conductive block in the trench.

2. . . Ditch-type transistor with low gate/drain capacitance

twenty one. . . Bungee structure

211. . . Bungee area

212. . . Pocket area

213. . . Base layer

214. . . First layer

215. . . Second layer

twenty two. . . Well area

twenty three. . . Gate structure

231. . . Dielectric layer

232. . . Conductive block

twenty four. . . Source structure

241. . . Source area

242. . . Contact plug

Claims (7)

A trench type power transistor having a low gate/drain capacitance includes: a drain structure composed of a semiconductor material and including a first conductive bungee region, and a main region located in the drain region The carrier concentration is smaller than the pocket region of the drain region; a well region is opposite to the second conductivity of the first conductivity, and physically contacts the drain region; a gate trench structure is formed at the drain And a region of the well region in contact with the pocket region and including a conductive block, and a dielectric layer separating the conductive block from the well region; and a source structure including a first conductivity a source region that is not in contact with the drain structure by the well region; wherein the drain region of the drain structure has a base layer in order, and a primary carrier concentration is not greater than the first layer of the base layer a layer, and a second carrier having a concentration of the main carrier not greater than the first layer, the well region being formed in the second layer, the pocket region being first conductive, formed in the first portion At the top of the layer, the concentration of the main carrier of the pocket region is smaller than the concentration of the main carrier of the first and second layers. A trench type power transistor having a low gate/drain capacitance according to claim 1 of the patent application, wherein the pocket region of the drain structure is formed by ion implantation. A trench type power transistor having a low gate/drain capacitance according to claim 2, wherein the first layer and the second layer of the drain structure are formed in an epitaxial manner. A trench type power transistor having a low gate/drain capacitance according to claim 3, wherein the conductive block of the gate trench structure is composed of polysilicon as a main material. The trench power transistor having a low gate/drain capacitance according to claim 4, wherein the source structure further comprises an electrically conductive and physically contactable source contact region Contact the plug. A trench type power transistor having a low gate/drain capacitance according to claim 5, wherein the first conductivity is an n-type semiconductor, and the second conductivity is a p-type semiconductor. A trench type power transistor having a low gate/drain capacitance according to claim 5, wherein the first conductivity is a p-type semiconductor and the second conductivity is an n-type semiconductor.