TWI455312B - A Power MOSFET Device and Manufacturing Method - Google Patents

Description

Power MOSFET device and manufacturing method thereof

The present invention relates to a power MOSFET device and a method of fabricating the same, and more particularly to a power MOSFET device for constructing a drain Schottky junction and a body region ohmic junction by different characteristic metals in the same contact channel, and a method of fabricating the same.

As shown in FIG. 1 , it is a schematic structural diagram of a conventional power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device. Taking an n-channel MOSFET as an example, it includes an n-epitaxial formed on the n + underlying substrate 100. In the layer 200, a plurality of trench gates 310 are disposed in the n- epitaxial layer 200, and a gate insulating layer 320 is disposed along the sidewalls and the bottom of the trench gate 310 to be insulated from the n- epitaxial layer 200. A p-type body region 400 and a source region 450 are also formed around the trench gate 310 at a top portion of the n- epitaxial layer 200. A dielectric layer 500 containing a low temperature oxide and borophosphon glass is also deposited on the top surface of the n- epitaxial layer 200, the trench gate 310, and the source region 450.

A plurality of contact trenches 600 are formed through the dielectric layer 500, the source regions 450, and the body regions 400 by etching, the bottom portions of which extend all the way into the epitaxial layer 200. An interface barrier conductive layer 700 made of a metal material is deposited on the top surface of the dielectric layer 500 and the sidewalls and the bottom surface of the contact trench 600. Also deposited on the interface barrier conductive layer 700 is a bonding metal layer 800 that fills the contact trench 600 and extends over the top surface of the dielectric layer 500. Subsequently, the electrode patterns of the semiconductor device are formed by photolithography, etching the connection metal layer 800 and the interface barrier conductive layer 700.

Between the side surface of the interface barrier conductive layer 700 and the high concentration doped body region 400, an ohmic junction is formed due to the metal-semiconductor contact; and at the bottom of the interface barrier conductive layer 700 A Schottky junction is formed between the epitaxial layer 200 doped with a low concentration. Among them, the ohmic junction has the characteristics of small resistance and linear symmetry of the IV (current-voltage) curve. Generally, if a dielectric material having a higher work function (such as a work function of 5.65 eV of platinum Pt, etc.) and a semiconductor are used in the interface barrier conductive layer 700. Contact can reduce the barrier height between the metal and the semiconductor, making the resistance of the ohmic junction smaller. The Schottky junction has an I-V curve with diode characteristics. Generally, if a metal material with a moderate work function is used to combine the semiconductor impurity concentration changes, the Schottky junction can be more rectified. The above work function refers to the minimum energy required for an electron to rise from the Fermi level to the metal surface at rest (ie, the vacuum level).

However, for the above-described conventional power MOSFET device, the ohmic junction formed on the side of the interface barrier conductive layer 700 shares the same interface barrier conductive layer 700 as the Schottky junction formed at the bottom, for example, in the interface barrier conductive layer 700. Although a metal material using a high work function can exhibit a small ohmic junction resistance, it must be turned on by a very high forward voltage, which greatly affects the performance of the Schottky junction. In order to achieve both the ohmic contact and the Schottky contact characteristics, it is often possible to select only the metal material to which the work function is compromised to form the interface barrier conductive layer 700, and thus the respective characteristics cannot be sufficiently exerted.

In addition, as shown by the broken line portion in FIG. 1, the bottom corner position of the contact channel 600 is not surrounded by the body region 400, but is in contact with the epitaxial layer 200 to form a Schottky junction, and the corner of the Schottky junction at the bottom will be There is a phenomenon in which the electric field is concentrated, so that it is easy to generate a large reverse leakage current at the bottom corner of the contact channel 600.

It is an object of the present invention to provide a power MOSFET device and a method of fabricating the same that can reduce reverse leakage current by surrounding a bottom corner of a contact channel by a body region; and form a Schottky junction by respectively depositing a metal and a semiconductor with different work functions. And ohmic junctions to play their respective characteristics.

In order to achieve the above object, the technical solution of the present invention provides a power MOSFET device comprising: an epitaxial layer disposed on a bottom substrate; a trench gate formed in a trench in the epitaxial layer; formed on top of the epitaxial layer Partially, and surrounding the body region of the trench gate; a source region formed at a top portion of the body region; a dielectric layer formed on a top surface of the trench gate and the source region; a plurality of contact channels formed through the dielectric layer and the source region; wherein the contact The bottom of the channel terminates in the body region such that the bottom corner of the contact channel is surrounded by the body region; and further includes a drift region formed in the body region below the contact channel and connected to the epitaxial layer; formed in the contact channel a Schottky junction of the bottom intermediate portion; an ohmic junction formed on the sidewall of the contact channel and the bottom corner surface thereof.

The power MOSFET device described above further includes a connection metal layer overlying the ohmic junction, Schottky junction surface, filling the contact channel and extending over the top surface of the dielectric layer.

The Schottky junction is formed by contacting an interface barrier conductive material with the drift region.

The ohmic junction is formed by contacting an interface barrier conductive material with the body region.

The interface barrier conductive material that forms an ohmic junction in contact with the body region is different from the interface barrier conductive material that contacts the drift region to form a Schottky junction.

The body region is further provided with an ion implantation region formed around the sidewalls of the contact channel and the bottom corner; the bottom corner of the contact channel is surrounded by the ion implantation region.

A method of fabricating a power MOSFET device comprising the steps of: a. forming an epitaxial layer on a bottom substrate; b. forming a trench gate in the epitaxial layer; c. forming an organic region by ion implantation in the epitaxial layer; d. The upper portion of the epitaxial layer is ion-implanted to form a source region; e. depositing a dielectric layer over the epitaxial layer; and further comprising the steps of: f. etching the dielectric layer to form a plurality of contact channels extending from the bottom to the body region; Depositing and etching to form a spacer layer; i. forming a drift connecting the epitaxial layer in a body region in the middle of the lower portion of the contact channel a first interface barrier conductive material is deposited, and a Schottky junction is formed in contact with the drift region in the middle of the bottom of the contact channel; 1. a second interface barrier conductive material is deposited, and the sidewall of the contact channel is The bottom corner contacts the body region to form an ohmic junction; the m. ohmic junction and the Schottky junction are deposited to form a connecting metal layer.

Between step f and step h, a step g of forming an ion implantation region by oblique ion implantation at the sidewalls and the bottom of the contact channel is further included.

The bottom of the contact channel terminates in the body region or the ion implantation region therein such that the bottom corner of the contact channel is surrounded by the body region or the ion implantation region.

In a preferred embodiment of the present invention, the spacer layer is formed by the anisotropic etch in the vertical direction on the side wall of the contact channel and the bottom corner thereof, and exposes the surface of the intermediate portion of the bottom portion of the contact channel.

The step h of forming the spacer layer described above is specifically achieved by depositing an insulating sacrificial material.

In the above step h, the sacrificial material which forms the spacer layer is an insulating material of cerium oxide SiO2 or cerium nitride SiN.

Between the above steps i and j, the step k of removing the insulating spacer layer is further included.

In another preferred embodiment of the present invention, in the step h, specifically, by depositing a second interface barrier conductive material, etching and forming a spacer layer covering the sidewall of the contact channel and a bottom corner thereof, and spacing the spacer The layer is in contact with the body region to form an ohmic junction.

In the above step j, the Schottky junction is realized by depositing a metal which can form a germanide in the middle portion of the bottom of the contact channel by using the spacer layer as a mask; the metal is titanium Ti, or tantalum Ta, or nickel. Ni.

In the above step i, specifically, in the body region in the middle of the contact channel, the drift region connected to the epitaxial layer is formed by ion implantation and partial inversion of the body region.

The power MOSFET device and the manufacturing method thereof provided by the invention have advantages over the prior art in that the present invention deposits a high work function characteristic conductive material in the sidewalls and bottom corners of the contact channel and the heavily doped body region. Contact to form an ohmic junction; a moderately conductive material that contacts the lightly doped epitaxial layer in the middle of the bottom of the contact channel to form a Schottky junction, thereby enabling the present invention to construct two different types of germanium interfaces of P/N in the same contact channel, and An ohmic contact and a Schottky contact are formed with metals of different work functions, so that the characteristics of small ohmic junction resistance and Schottky junction rectification can be simultaneously exhibited.

In the present invention, since the bottom corner of the contact channel is surrounded by the body region or the B+ boron P-type ion implantation region therein, the reverse leakage current of the contact channel corner position can be effectively reduced while ensuring the contact characteristics of the Schottky junction. . Moreover, since the Schottky junction is disposed on the single twin plane in the middle of the contact channel, the uniformity of the Schottky junction can be effectively improved.

MOSFET‧‧‧Metal Oxide Semiconductor Field Effect Transistor

10‧‧‧Bottom substrate

20‧‧‧ Epilayer

25‧‧‧ drift zone

30‧‧‧ trench

31‧‧‧ trench gate

32‧‧‧Gate insulation

40‧‧‧ body area

41‧‧‧Ion implantation zone

45‧‧‧Source area

50‧‧‧Dielectric layer

60‧‧‧Channel

71‧‧‧Schottky knot

72‧‧‧ Ohm knot

80‧‧‧Connected metal layer

90‧‧‧ spacer

100‧‧‧n+ bottom substrate

200‧‧‧n-epitaxial layer

310‧‧‧Tray gate

320‧‧‧Gate insulation

400‧‧‧p type body area

1 is a cross-sectional view showing a structure of a power MOSFET device provided by the prior art; FIG. 2 is a cross-sectional view showing a structure of a power MOSFET device according to the present invention; and FIG. 3 is a view showing a method of manufacturing a power MOSFET device according to the present invention. 1 is a flow chart of steps in FIG. 4; FIG. 4 is a schematic diagram showing steps of a method for manufacturing a power MOSFET device according to the present invention; and FIG. 8 is a manufacturing method of a power MOSFET device according to the present invention. FIG. 9 to FIG. 12 are schematic diagrams showing the steps of the manufacturing method of a power MOSFET device according to the present invention in Embodiment 2. .

Various embodiments of the present invention are described below in conjunction with the drawings.

Example 1

FIG. 2 is a cross-sectional view showing the structure of a power MOSFET device of the present invention. The n-channel power MOSFET device is exemplified, and includes an n+ heavily doped underlying substrate 10 and grown on the underlying substrate 10. An n- epitaxial layer 20; a plurality of trenches 30 extending to a certain depth in the epitaxial layer 20 are formed, and a conductive material such as polysilicon is filled therein to form the trench gate 31; along the sidewall of the trench gate 31 A thinner oxide is formed on the bottom and the trench gate 31 is insulated from the epitaxial layer 20 as the gate insulating layer 32.

At the top of the epitaxial layer 20, a p-type body region 40 is further formed around the trench gate 31. The top of the p-type body region 40 is further formed with an n++ type source region 45 by ion implantation; the body region 40, the source The pole region 45 is insulated from the trench gate 31 by a gate insulating layer 32. A dielectric layer 50 composed of a low temperature oxide and borophosphon glass is also deposited on the top surface of the epitaxial layer 20, the trench gate 31 and the source region 45 for isolating the trench gate 31 and the source region 45. s contact.

A plurality of contact trenches 60 are formed through the dielectric layer 50, extending all the way into the body region 40 such that the bottom corners of the contact trenches 60 are surrounded by the p-type body regions 40. An n-drift region 25 is also formed in the body region 40 by ion implantation, so that the bottom intermediate portion of the contact channel 60 is in contact with the n- epitaxial layer 20 through the drift region 25, and drifts in the middle of the bottom portion of the contact channel 60. A first interface barrier conductive material (abbreviated as a first conductive material) is deposited at a location where the regions 25 are connected to form a Schottky junction 71.

A second interface barrier conductive material (abbreviated as a second conductive material) is further deposited on a top surface of the dielectric layer 50, a surface of the sidewall of the contact trench 60 and a bottom corner region thereof, and a Schottky junction 71. An ohmic junction 72 is formed in contact with the p-body region 20 at the sidewall of the contact channel 60 and its bottom corner region. Also disposed on the second conductive material is a tie metal layer 80 that fills the contact channel 60 and extends over the top surface of the dielectric layer 50.

The above-mentioned interface barrier conductive materials respectively forming the Schottky junction 71 and the ohmic junction 72 are two metals having different work functions. At the side and bottom corner positions of the contact channel 60, a metal having a high work function is deposited in contact with the heavily doped p-type body region 40 to form an ohmic junction 72; in this embodiment, for example, a platinum Pt having a work function of 5.65 eV may be used, or A nickel such as a 5.15 eV work function or a metal such as tungsten germanium WSi2 is used to form the ohmic junction 72, so that the formed ohmic junction 72 has a lower resistance.

At the intermediate position of the bottom of the contact channel 60, the metal having a moderate work function is used to contact the lightly doped n-type drift region 25 to form the Schottky junction 71; in this embodiment, for example, The Schottky junction 71 is made of a titanium Ti having a work function of 4.33 eV or a metal such as 钽Ta having a work function of 4.25 eV, so that the rectifying effect of the formed Schottky junction 71 is better.

As shown in FIG. 7, in some preferred embodiments, a B+ boron p-type ion implantation region 41 formed around the ohmic junction 72 may be disposed in the p-type body region 40 to contact the channel 60. The bottom corner is surrounded by a B+ boron p-type ion implantation region 41.

The method of manufacturing the power MOSFET device provided with the B+ boron p-type ion implantation region 41 described above will be described below with reference to FIGS. 3 to 7, and FIG. 3 is a flow chart showing the steps of the manufacturing method.

First, in step a, an n- epitaxial layer 20 is grown on the n+ heavily doped underlying substrate 10; in step b, a trench 30 composed of hafnium oxide is formed on the surface of the n- epitaxial layer 20. Mode, and anisotropically etching the n- epitaxial layer 20 to a predetermined depth after passing through the trench 30 mask to form a plurality of trenches 30; along the sidewalls and bottom of the trench 30 Forming a gate insulating layer 32 generally composed of an oxide by a standard sacrificial oxide layer growth and etching process; depositing n+ doped polysilicon in the remaining space in the trench 30 and on the ceria trench 30 mask to A trench gate 31 is formed; the n+ doped polysilicon on the mask of the ceria trench 30 is etched back, and the trench 30 mask is stripped.

In steps c to d, the p-body region 40 is formed by p-ion implantation and diffusion at the top portion of the n- epitaxial layer 20, and then the trench 30 is surrounded in the p-body region 40 by n ion implantation. The gate insulating layer 32 forms a source region 45 of n++. Step e, a dielectric layer 50 of low temperature oxide and borophosphon glass is deposited on the trench gate 31, the n- epitaxial layer 20 and the n++ source region 45 for isolation from the trench gate 31 . In step f, a plurality of contact trenches 60 are formed through the dielectric layer 50 and the source region 45 by etching, such that the bottom of the contact trench 60 extends into the p-type body region 40.

As shown in FIG. 4, step g forms a B+ boron P-type ion implantation region 41 surrounding the sidewalls and the bottom of the contact channel 60 in the p-type body region 40 by oblique p-type ion implantation to enhance the p-type. Characteristic, the bottom of the contact channel 60 is surely surrounded by the B+ boron P-type ion implantation region 41.

As shown in FIG. 5, in step h, a spacer layer 90 is formed by depositing an insulating material such as SiO2 or SiN by chemical vapor deposition (CVD), and after the anisotropic dry etching in the vertical direction, the remaining The spacer layer 90 covers the sidewalls of the dielectric layer 50 and the contact channel 60, The bottom corner position of the channel 60 is contacted, but the surface of the bottom intermediate portion of the contact channel 60 is exposed.

Subsequently, in step i, the spacer layer 90 is used as a mask, and the B+ boron P-type ions at the bottom of the channel 60 are contacted by phosphorus ion implantation and partial inversion in the body region 40 at an intermediate position below the contact channel 60. The implantation region 41 and the p-type body region 40 are blocked to form an n-drift region 25 connecting the n- epitaxial layer 20. As can be seen from FIG. 5, at this time, the middle portion of the bottom of the contact channel 60 is in direct contact with the n-drift region 25, and the bottom corner of the contact channel 60 is surrounded by the B+ boron p-type ion implantation region in the p-type body region 40. Surrounded by 41.

As shown in FIG. 6, in step j, spacer layer 90 is also used as a mask, and a first conductive material is deposited in contact with n-drift region 25 at a position intermediate the bottom of contact channel 60 and n-drift region 25. The Schottky junction 71 is formed. As described above, the deposited first conductive material is a metal having a moderate work function. In this embodiment, a Ti or a metal such as tantalum Ta may be used in contact with the drift region 25 to form the Schottky junction 71. The rectifying effect of the base junction 71 is better.

As shown in Fig. 7, the insulating spacer layer 90 is removed by a wet cleaning process in step k. In the subsequent step 1, a second conductive material is deposited in contact with the p-type body region 40 on the top surface of the dielectric layer 50, the surface of the sidewall of the contact trench 60 and the bottom corner region thereof, and the Schottky junction 71. Ohmic junction 72. As described above, the deposited second conductive material is a high work function metal. In this embodiment, a metal such as platinum Pt, or nickel Ni, or tungsten germanium WSi2 may be used to form the ohmic junction 72 to make the ohmic junction 72. The resistance is smaller.

In step m, a connection metal layer 80 is deposited over the second conductive material that fills the contact trench 60 and extends over the top surface of the dielectric layer 50. The remainder of the fabrication of the power MOSFET device provided with the B+ boron p-type ion implantation region 41 can be completed in a standard manner.

If only the step g of forming the B+ boron p-type ion implantation region 41 surrounding the sidewall of the contact channel 60 and the bottom corner region thereof in the p-type body region 40 by ion implantation is removed, the step a to the step f, the step h The process flow to step m is equally applicable to the fabrication of a power MOSFET device in which the B+ boron p-type ion implantation region 41 is not provided as shown in FIG.

Example 2

As shown in FIG. 12, the power MOSFET device of this embodiment is similar in structure to the first and second embodiments, that is, the n-channel power MOSFET device includes an n+ bottom. a substrate 10 and an n- epitaxial layer 20 on the underlying substrate 10; a plurality of trenches 30 extending into the epitaxial layer 20, filling a conductive material to form a trench gate 31, and providing a gate insulating layer 32 to The epitaxial layer 20 is insulated and isolated. At the top of the epitaxial layer 20, a p-type body region 40 is formed around the trench gate 31; the top of the p-type body region 40 is further formed with an n++ type source region 45 by ion implantation; in the epitaxial layer 20, the trench The top surface of the gate 31 and source region 45 is also deposited with a dielectric layer 50 of low temperature oxide and borophosphon glass. A plurality of contact channels 60 are formed in the dielectric layer 50 such that a bottom corner of the contact channel 60 is surrounded by the p-type body region 40; and an n-drift region 25 is formed in the middle of the contact channel 60 to be connected to the epitaxial layer 20. The bottom intermediate portion of the contact channel 60 is brought into contact with the n-drift region 25.

The only difference is that the spacer layer included in the embodiment specifically deposits and etches a second conductive material formed on the sidewall of the contact channel 60 and the bottom corner region thereof. The electrically conductive spacer layer contacts the heavily doped p-type body region 40 to form an ohmic junction 72 at the side and bottom corners of the contact channel 60. The second conductive material is WSi2 (tungsten tungsten), p+ polysilicon or the like having a high work function characteristic, and thus the ohmic junction 72 formed in contact with the heavily doped p-type body region 40 has a smaller resistance.

A first conductor material is deposited between the second conductive material at the bottom of the contact channel 60 and at a location connected to the n-drift region 25. As in the above embodiment, the first conductor material is a metal such as titanium Ti or tantalum Ta having a moderate work function, and the Schottky junction 71 formed by contact with the lightly doped n-type drift region 25 is better in rectifying characteristics.

Covering the second conductive material on the sidewall of the contact channel 60 and the first conductive material contacting the bottom region of the bottom of the trench 60, a connection metal layer 80 is also provided which fills the contact trench 60 and extends to the dielectric layer 50. Above the top.

In some preferred embodiments, a B+ boron P-type ion implantation region 41 formed around the ohmic junction 72 may be disposed in the p-type body region 40 such that the bottom corner region of the contact channel 60 is B+ boron P. The -type ion implantation region 41 is surrounded.

The manufacturing method of the power MOSFET device provided with the B+ boron P-type ion implantation region 41 described above will be described below with reference to Figs. 8 to 12, wherein Fig. 8 is a flow chart showing the steps of the manufacturing method.

Similar to the first embodiment, first in step a, an n- epitaxial layer 20 is grown on the n+ heavily doped underlying substrate 10; in step b, on the surface of the n- epitaxial layer 20 Forming a trench 30 composed of cerium oxide and etching the n- epitaxial layer 20 to a predetermined depth after passing through the mask of the trench 30 by an anis-tropically etching to form a plurality of trenches a trench 30; along the sidewalls and bottom of the trench 30, through a standard sacrificial oxide growth and etching process to form a gate insulating layer 32, typically composed of an oxide; in the remaining space within the trench 30, and in the ruthenium dioxide trench An n+ doped polysilicon is deposited on the trench 30 mask to form the trench gate 31; the n+ doped polysilicon on the mask of the ceria trench 30 is etched back and the trench 30 mask is stripped.

In steps c to d, the p-body region 40 is formed by p-ion implantation and diffusion at the top portion of the n- epitaxial layer 20, and then the trench 30 is surrounded in the p-body region 40 by n ion implantation. The gate insulating layer 32 forms a source region 45 of n++. Step e, a dielectric layer 50 of low temperature oxide and borophosphon glass is deposited on the trench gate 31, the n- epitaxial layer 20 and the n++ source region 45 for isolation from the trench gate 31 . In step f, a plurality of contact trenches 60 are formed through the dielectric layer 50 and the source region 45 by etching, such that the bottom of the contact trench 60 extends into the p-type body region 40.

As shown in FIG. 9, step g forms a B+ boron p-type ion implantation region 41 surrounding the sidewalls and the bottom of the contact channel 60 in the p-type body region 40 by oblique p-type ion implantation to enhance the p-type. Characteristic, the bottom of the contact channel 60 is surely surrounded by the B+ boron p-type ion implantation region 41.

Starting from step h, unlike the above embodiment, as shown in FIG. 10, a second conductive material such as WSi2 (tungsten tungsten dioxide) or p+ polycrystalline germanium is deposited as a spacer layer, and after anisotropic dry etching, it is covered. The electrical layer 50 and the sidewalls of the contact trench 60, the bottom corner of the contact trench 60, expose the surface of the bottom intermediate region of the contact trench 60. The second electrically conductive material has a high work function characteristic and contacts the heavily doped p-type body region 40 at the side and bottom corners of the contact channel 60 to form an ohmic junction 72.

Then in step i, the second conductive material is used as a mask, and the B+ boron p-type at the bottom of the contact channel 60 is contacted by phosphorus ion implantation and partial inversion in the body region 40 at the intermediate position below the contact channel 60. The ion implantation region 41 and the p-type body region 40 are blocked to form an n-drift region 25 connecting the n- epitaxial layer 20. As can be seen from Fig. 10, at this time, the middle portion of the bottom of the contact channel 60 is in direct contact with the n-drift region 25, and at this time, the bottom corner of the contact channel 60 is surrounded by the B+ boron p-type ion implantation region 41.

As shown in FIG. 11, the second conductive material is also used as a mask in step j. At a position intermediate the bottom of the contact channel 60 to the n-drift region 25, a first conductive material is deposited in contact with the n-drift region 25 to form a Schottky junction 71. As described above, the deposited first conductive material is a metal having a moderate work function. In this embodiment, a Ti or a metal such as tantalum Ta may be used in contact with the drift region 25 to form the Schottky junction 71. The rectifying effect of the base junction 71 is better.

As shown in Fig. 12, in the subsequent step m, a connection metal layer 80 is deposited to cover the ohmic junction 72 contacting the sidewall of the trench 60, and the Schottky junction 71 contacting the bottom of the trench 60, which fills the contact. Channel 60 extends above the top surface of dielectric layer 50. The remainder of the fabrication of the power MOSFET device provided with the B+ boron p-type ion implantation region 41 can be completed in a standard manner.

If only the step g of forming the B+ boron p-type ion implantation region 41 surrounding the sidewall of the contact channel 60 and the bottom corner region thereof in the p-type body region 40 by ion implantation is removed, the above process flow can be equally applied to the fabrication. A power MOSFET device of the B+ boron p-type ion implantation region 41 is provided.

The manufacturing method provided in the present invention is equally applicable to a P-channel power MOSFET device as long as a semiconductor layer and a dopant having opposite polarities as in the embodiment are employed.

In combination with the above embodiments 1 and 2, the power MOSFET device and the method of fabricating the same according to the present invention, by depositing a conductive material having a high work function characteristic, are placed on the sidewalls and bottom corners of the contact channel 60 and the heavily doped body. The region 40 contacts the ohmic junction 72; it also forms a Schottky junction 71 in contact with the lightly doped epitaxial layer 20 at the bottom intermediate portion of the contact channel 60 by depositing a moderate electrical conductivity of the work function. Therefore, in the same contact channel 60, the present invention forms two different types of germanium interfaces of P/N, and forms ohmic contact and Schottky contact with metals of different work functions, which can simultaneously exhibit the small resistance of the ohmic junction 72 and the Schott. The characteristics of the base junction 71 rectification.

In addition, the bottom corner of the contact channel 60 is surrounded by the body region 40 or the B+ boron p-type ion implantation region 41 therein, which can effectively reduce the contact position of the Schottky junction 71 while effectively reducing the corner position of the contact channel 60. Reverse leakage current. Moreover, since the Schottky junction 71 is disposed on the single twin plane in the middle of the contact channel 60, the uniformity of the Schottky junction 71 can be effectively improved.

Although the present invention has been described in detail by the preferred embodiments thereof, it should be understood that the foregoing description should not be construed as limiting. Various modifications and alterations of the present invention will be apparent to those skilled in the art. Therefore, the scope of the invention should be limited by the scope of the appended claims.

10‧‧‧Bottom substrate

20‧‧‧ Epilayer

30‧‧‧ trench

31‧‧‧ trench gate

32‧‧‧Gate insulation

40‧‧‧ body area

45‧‧‧Source area

50‧‧‧Dielectric layer

60‧‧‧Channel

72‧‧‧ Ohm knot

80‧‧‧Connected metal layer

Claims (13)

A power MOSFET device comprising: an epitaxial layer (20) disposed on a bottom substrate (10); a trench gate (31) formed in a trench (30) in the epitaxial layer (20); formed on the epitaxial layer a top portion of the layer (20) and surrounding the body region (40) of the trench gate (31); a source region (45) formed at a top portion of the body region (40); formed at the trench gate (31) And a dielectric layer (50) on a top surface of the source region (45); a plurality of contact trenches (60) formed through the dielectric layer (50) and the source region (45); wherein the contact trench The bottom of the track (60) terminates in the body region (40) such that the bottom corner of the contact channel (60) is surrounded by the body region (40); and the body region formed in the middle of the contact channel (60) is further included (40) a drift region (25) connected to the epitaxial layer (20); a Schottky junction (71) formed in a bottom intermediate portion of the contact channel (60); the Schottky junction (71) Is formed by contact of the interface barrier conductive material with the drift region (25); an ohmic junction (72) formed on a sidewall of the contact channel (60) and a bottom corner surface thereof; the ohmic junction ( 72) is contacted by the interface barrier conductive material and the body region (40) Into; And, an interface barrier conductive material that forms the ohmic junction (72) in contact with the body region (40) is different from an interface barrier conductive material that forms the Schottky junction (71) in contact with the drift region . The power MOSFET device of claim 1, further comprising a connection metal layer (80) overlying the surface of the ohmic junction (72) and the Schottky junction (71), which fills the The channel (60) is contacted and extends over the top surface of the dielectric layer (50). The power MOSFET device of claim 1, wherein the body region (40) is further provided with an ion implantation region (41) formed around a sidewall and a bottom corner of the contact channel (60). The bottom corner of the contact channel (60) is surrounded by the ion implantation region (41). A method of fabricating a power MOSFET device comprising the steps of: a. forming an epitaxial layer (20) on a bottom substrate (10); b. forming a trench gate (31) in the epitaxial layer (20); c. The ion implantation in the epitaxial layer (20) forms a body region (40); d. ion implantation in the upper portion of the epitaxial layer (20) to form a source region (45); e. deposition over the epitaxial layer (20) to form a dielectric layer (50) The method further includes the steps of: f. etching the dielectric layer (50) to form a plurality of contact trenches (60) extending to the body region (40); h. depositing and etching to form the spacer layer (90) i. in the body region (40) in the middle of the lower portion of the contact channel (60), forming a drift region (25) connecting the epitaxial layer (20); Depositing a first interface barrier conductive material and contacting the drift region (25) in the middle of the bottom of the contact channel (60) to form a Schottky junction (71); 1. depositing a second interface barrier conductive material, and The sidewall of the contact channel (60) and its bottom corner are in contact with the body region (40) to form an ohmic junction (72); m. Ohm junction (72), Schottky junction (71) is deposited to form a connecting metal layer (80) . The method of fabricating a power MOSFET device according to claim 4, characterized in that, between step f and step h, further comprising forming ions by oblique ion implantation at sidewalls and bottom of the contact channel (60) Step g of the implantation zone (41). A method of fabricating a power MOSFET device according to claim 5, characterized in that the bottom of the contact channel (60) terminates in the body region (40) or in the ion implantation region (41) therein. The bottom corner of the contact channel (60) is surrounded by the body region (40) or the ion implantation region (41). The method of fabricating a power MOSFET device according to claim 4, wherein the spacer layer (90) is formed on the sidewall of the contact channel (60) by anisotropic etching in a vertical direction. The bottom corner exposes the surface of the bottom intermediate portion of the contact channel (60). The method of fabricating a power MOSFET device according to claim 4, wherein the step h of forming the spacer layer (90) is specifically performed by depositing an insulating sacrificial material. A method of fabricating a power MOSFET device according to claim 8, wherein in the step h, a sacrificial material forming the spacer layer (90) is deposited as an insulating layer of cerium oxide SiO2 or tantalum nitride SiN. material. The method of manufacturing a power MOSFET device according to claim 8 is characterized in that, between step i and step j, step k of removing the insulating spacer layer (90) is further included. The method of manufacturing a power MOSFET device according to claim 4, wherein in the step h, specifically, a second interface barrier conductive material is deposited and etched to form a contact channel (60). The sidewalls and the spacer layer (90) at the bottom corner thereof contact the spacer layer (90) with the body region (40) to form an ohmic junction (72). The method of manufacturing a power MOSFET device according to claim 4, wherein in the step j, the Schottky junction (71) is formed by using the spacer layer (90) as a mask. The bottom intermediate portion of the contact channel (60) is deposited by depositing a metal that can form a telluride; the metal is titanium Ti, or tantalum Ta, or nickel Ni. The method of fabricating a power MOSFET device according to claim 4, wherein the step i is specifically in the body region (40) in the middle of the contact channel (60), by ion implantation and partial reversal. The body region (40) is formed to form the drift region (25) connected to the epitaxial layer (20).