TWI451422B - Method and systems for programming differently sized margins and sensing with compensations at select states for improved read operations in non-volatile memory - Google Patents

Description

Stylized different size margins for improved read operations in non-volatile memory and methods and systems for compensating sensing in selected states

This invention relates to stylized non-volatile memory.

Semiconductor memory devices have become more and more popular for use in a variety of electronic devices. For example, non-volatile semiconductor memory is being used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, inactive computing devices, and other devices. Electrically erasable programmable read-only memory (EEPROM) - including flash EEPROM and electrically programmable read-only memory (EPROM) - is among the most popular non-volatile semiconductor memory.

An example of a flash memory system uses a NAND structure that includes a plurality of transistors arranged in series between two select gates. The serial transistors and select gates are referred to as a NAND string. Figure 1 is a top plan view showing a NAND string. Figure 2 is an equivalent circuit thereof. The NAND string illustrated in FIGS. 1 and 2 includes four serial transistors 100, 102, 104, and 106 sandwiched between a first select gate 120 and a second select gate 122. Select gate 120 connects the NAND string to bit line 126. Select gate 122 connects the NAND string to source line 128. The selection gate 120 is controlled by applying an appropriate voltage to the control gate 120CG via the select line SGD. The selection gate 122 is controlled by applying an appropriate voltage to the control gate 122CG via the selection line SGS. Each of the transistors 100, 102, 104, and 106 includes a control gate and a floating gate to form a gate element of a memory cell. For example, the transistor 100 includes a control gate 100CG and a floating gate 100FG. The transistor 102 includes a control gate 102CG and a floating gate 102FG. The transistor 104 includes a control gate 104CG and a floating gate 104FG. The transistor 106 includes a control gate 106CG and a floating gate 106FG. The control gate 100CG is connected to the word line WL3, the control gate 102CG is connected to the word line WL2, the control gate 104CG is connected to the word line WL1, and the control gate 106CG is connected to the word line WL0.

It should be noted that although Figures 1 and 2 show four memory cells in a NAND string, the use of four transistors is provided only as an example. A NAND string can have less than four memory cells or more than four memory cells. For example, some NAND strings will contain eight memory cells, 16 memory cells, 32 memory cells, and the like. The discussion herein is not limited to any particular number of memory cells in a NAND string.

A typical architecture for a flash memory system using a NAND structure would include several NAND strings. For example, Figure 3 shows three NAND strings 202, 204, and 206 with a memory array of more NAND strings. Each of the NAND strings shown in Figure 3 includes two select transistors or gates and four memory cells. For example, NAND string 202 includes select transistors 220 and 230, and memory cells 222, 224, 226, and 228. NAND string 204 includes select transistors 240 and 250, and memory cells 242, 244, 246, and 248. Each string is connected to the source line by means of a select gate (eg, select gate 230 and select gate 250). A select line SGS is used to control the source side select gate. Different NAND strings are connected to corresponding bit lines by select gates 220, 240, etc. controlled by select line SGD. In other embodiments, the selection lines do not have to be shared. The word line WL3 is connected to the control gate of the memory unit 222 and the memory unit 242. Word line WL2 is coupled to memory cell 224 and the control gate of memory cell 244. Word line WL1 is coupled to memory cell 226 and the control gate of memory unit 246. Word line WL0 is coupled to memory cell 228 and the control gate of memory unit 248. Thus, one bit line and the corresponding NAND string include one row of the memory cell array. Word lines (WL3, WL2, WL1, and WL0) include the columns of the array. Each word line connects the control gate of each memory cell in the column. For example, word line WL2 is coupled to the control gates of memory cells 224, 244, and 252.

NAND-type flash memory and related examples of its operation are provided in the following U.S. patents/patent applications, all of which are incorporated herein by reference: U.S. Patent No. 5,570,315; U.S. Patent No. 5,774,397; U.S. Patent No. 6,046,935; U.S. Patent No. 6,456,528, and U.S. Patent Application Serial No. 09/893,277, issued to

Each memory unit can store data (analog or digital). When storing one-bit digital data, the threshold voltage range of the memory unit (commonly referred to as a binary memory unit) is divided into two ranges, which are assigned to the logical data "1" and "0". In an example of a NAND flash memory, the threshold voltage value is negative after erasing the memory cell and is defined as a logic "1". The threshold voltage is positive after a stylized operation and is defined as a logic "0". When the threshold voltage value is negative and a read is attempted by applying 0 volts to the control gate, the memory cell will turn on to indicate that logic 1 is being stored. When the threshold voltage value is positive and a read operation is attempted by applying 0 volts to the control gate, the memory cell will not conduct, indicating that logic 0 is being stored. A multi-state memory unit can also store multiple information levels, for example, digital data for multiple bits. In the case of storing multiple data levels, the possible range of threshold voltage is divided into the number of data levels. For example, if four information levels are stored, there will be four threshold voltage ranges assigned to the data values "11", "10", "01" and "00", respectively. In an example of a NAND type memory, the threshold voltage value is negative after an erase operation and is defined as "11". Three different positive threshold voltage values are used for the states of "10", "01", and "00". The specific relationship between the data programmed into the memory unit and the range of threshold voltage values of the memory unit depends on the data encoding scheme employed by the memory units. For example, U.S. Patent No. 6,222,762, and U.S. Patent Application Serial No. 10/461,244, entitled "Tracking Cells For A Memory System", filed on Jun. 13, 2003, describes various materials for multi-state flash memory cells. The coding scheme, both of which are incorporated herein by reference. Moreover, embodiments in accordance with the present disclosure are applicable to memory cells that store more than two bits of data.

When programming an EEPROM or flash memory device, a stylized voltage is typically applied to the control gate and the bit line is grounded. The electrons are injected from the channel into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell rises, thereby causing the memory cell to be in a stylized state. The floating gate charge and threshold voltage values of the memory cell can indicate a particular state corresponding to the stored data. Further information on the stylization can be found in U.S. Patent Application Serial No. 10/379,608, filed on March 5, 2003: "Self Boosting Technique"; and U.S. Patent Application Serial No. 10/629,068, filed on Jul. 29, 2003. No.: "Detecting Over Programmed Memory", the entire contents of which are incorporated herein by reference.

The apparent charge offset stored on a floating gate can occur due to the coupling of the electric field based on the charge stored in the adjacent floating gate. Such a floating gate-to-floating gate coupling phenomenon is described in U.S. Patent No. 5,867,429, the disclosure of which is incorporated herein by reference. This floating gate-to-floating gate coupling phenomenon occurs more (though not exclusively) between adjacent memory cell groups that have been programmed at different times. For example, a first memory cell can be programmed to add a charge level to its floating gate corresponding to a set of data. Subsequently, one or more adjacent memory cells are programmed to add a charge level to their floating gate corresponding to a set of data. After stylizing one or more of the adjacent memory cells, the level of charge read from the first memory cell will appear due to the charge coupled to the adjacent memory cells of the first memory cell. It is different from the charge level when it is programmed. The coupling of the adjacent memory cells may cause the apparent charge level read from a selected memory cell to be offset by an amount sufficient to cause erroneous reading of the stored data.

As the memory cell continues to shrink in size, it is desirable to increase the normal stylized and erased distribution of the threshold voltage due to short channel effects, greater oxide thickness/coupling ratio variation, and more doping concentration variations to reduce The available separation between adjacent states. This effect will be significantly more significant for multi-state memory alignment using binary memory with only two states. Reducing the spacing between the word lines and the bit lines will also increase the coupling between adjacent floating gates. The effect of floating gates on floating gate coupling is more important for multi-state devices because of the allowable threshold voltage range and forbidden range in multi-state devices (two representing distinct memory states) The range between the different threshold voltage ranges is narrower than in the binary device. Therefore, the floating gate-to-floating gate coupling can cause the memory cell to move from a permissible threshold voltage range to a forbidden range.

Therefore, there is a need for a non-volatile memory that effectively manages the aforementioned problems of floating gate coupling.

The techniques described herein attempt to address the effects of floating gate coupling in non-volatile memory.

The non-volatile memory read operation compensates for floating gate coupling when the apparent threshold voltage value of the memory cell may have shifted. A reference memory value based on a charge level read from an adjacent memory cell can be used to read a memory cell of interest. Misreading adjacent memory cells can have a greater impact on a particular stylized approach, and more specifically, can have a greater impact on their methods when reading adjacent memory cells for a particular state or charge level. In one embodiment, the memory cells are programmed to create a wider margin between particular states, wherein misreading an adjacent memory cell would be more harmful. Moreover, in one embodiment, by reading based on reading at certain reference levels rather than at other reference levels (eg, where reference points have been created in which a wider margin has been created) The state of the adjacent memory cells compensates for the floating gate coupling to read the memory cells.

In one embodiment, a method of reading a non-volatile storage device is provided, the method responsive to receiving a request to read a first non-volatile storage element and reading an adjacent non-volatile storage element A second non-volatile storage element. Applying a first reference value to read the first non-volatile storage element at a level between the first stylized state and the second stylized state, and applying a second reference value to thereby The level between the stylized state and the third stylized state reads the first non-volatile storage element. Determining the first result when the second non-volatile storage element is in a first subset of physical states, using a result of applying the first reference value at the first level and applying the second reference value at the second level Information on non-volatile storage components. Determining the first result when the second non-volatile storage element is in a second subset of physical states, using a result of applying the first reference value at the first level and applying the second reference value at the third level Information on non-volatile storage components.

In one embodiment, a non-volatile memory system is provided that includes a first stylized first memory cell group from a set of memory cells and a second memory cell group from the group And a third memory unit from the group. Staging the first group to a first stylized state associated with the first threshold voltage range and programming the second group to a second stylized state associated with the second threshold voltage range . The first and second threshold voltage ranges define a first margin having a first magnitude between the first stylized state and the second stylized state. The third group is stylized to a third stylized state associated with a third threshold voltage range. The second threshold voltage value range and the third threshold voltage value range define a second margin having a second size between the second stylized state and the third stylized state, wherein the second size is smaller than the first size .

Other features, aspects, and objects of the embodiments of the disclosed technology will be apparent from the description and appended claims.

4 is a block diagram of an embodiment of a flash memory system that can be used to implement one or more embodiments of the present disclosure. Other systems and implementations can also be used. The memory cell array 302 is controlled by a row control circuit 304, a column control circuit 306, a c-source control circuit 310, and a p-well control circuit 308. A row control circuit 304 is coupled to the bit line of the memory cell array 302 for reading data stored in the memory cells for determining the state of the memory cells during a stylizing operation, and The potential level of the bit line is controlled to promote or disable stylization and erasure. Column control circuit 306 is coupled to the word lines to select the word lines, apply a read voltage, apply a programmed voltage combined with a bit line potential level controlled by row control circuit 304, and apply an erase voltage. The c-source control circuit 310 controls a common source connected to each memory cell. P-well control circuit 308 controls the p-well voltage.

The data stored in the memory cells is read by the row control circuit 304 and output to the external I/O lines via the data input/output buffer 312. The stylized data to be stored in the memory unit is input to the data input/output buffer 312 via the external I/O line and passed to the row control circuit 304. These external I/O lines are connected to controller 318.

Row control circuit 304 can include a plurality of sense blocks 320, each sense block being associated with one or more bit lines to perform a sensing operation. For example, a single sensing block can be associated with eight bit lines and includes a common portion and eight separate sensing modules for each bit line. For further details, reference is made to U.S. Patent Application Serial No. 11/026,536, filed on Dec. 29, 2004: "Non-Volatile Memory & Method with Shared Processing for an Aggregate of Sense Amplifiers", the entire disclosure of which is incorporated by reference. Incorporated herein. The sensing module 320 determines whether the on current or other parameter in a connected bit line is above or below a predetermined threshold level. The sensing module can determine the data stored in the sense memory unit and store the determined data in a data latch stack 322. The data latch stack 322 is used to store the data bits determined during the read operation. It is also used to store stylized data bits in memory during a stylized operation. In one embodiment, the data latch stack 322 of each sense module 320 includes three data latches. A sensing module can also include a bit line latch for setting a voltage condition on the connected bit line. For example, a predetermined state latched in the bit line latch can cause the connected bit line to be pulled to a specified stabilizing state (eg, Vdd).

Command data for controlling the flash memory device is input to the controller 318. The command data will inform the flash memory of the requested operation. The input command is passed to state machine 316, which is part of control circuit 315. State machine 316 controls row control circuit 304, column control circuit 306, c-source control circuit 310, p-well control circuit 308, and data input/output buffer 312. State machine 316 can also output status data for flash memory, such as READY/BUSY or PASS/FAIL.

Controller 318 is coupled to or can be coupled to a host system (e.g., a personal computer, digital camera, personal digital assistant, etc.). It maintains communication with the host that initiated the various commands, including, for example, storing data to or reading data from the memory array 302 and providing or receiving such data. Controller 318 converts such commands into command signals that can be interpreted and executed by command circuitry 314, which is part of control circuitry 315. Command circuit 314 remains in communication with state machine 316. Controller 318 typically includes a buffer memory for writing to the memory array or user data read from the memory array.

An exemplary memory system includes an integrated circuit including a controller 318 and one or more integrated circuit chips, each integrated circuit chip including a memory array and associated control, input/output And state machine circuit. There is a trend to integrate a system of memory arrays and controller circuits together on one or more integrated circuit wafers. The memory system can be partially embedded as part of the host system or can be included in a memory card (or other package) that can be swapped into the host system. Such a card may include the entire memory system (eg, including a controller) or only a memory array with associated peripheral circuitry (where the controller or control functions are embedded in the host). Therefore, the controller can be embedded in the host or included in the removable memory system.

Referring to Figure 5, an exemplary structure of a memory cell array 302 is illustrated. As an example, a NAND flash EEPROM divided into 1024 blocks is illustrated. The data stored in each block can be erased at the same time. In one embodiment, the block is the smallest unit of cells that are simultaneously erasable. The memory cell is erased by raising the p-well to an erase voltage (eg, 20 volts) and grounding the word line of a selected block. The source line and the bit line are floating. Erasing can be performed for the entire memory array, individual blocks, or units of another unit. The electrons are transferred from the floating gate to the p-well region and the threshold voltage value becomes negative (in one embodiment).

In each block of the example shown in Figure 5, there are 8,512 rows. Each block is usually divided into a number of pages, and the page can be a stylized unit. Other units of information used for stylization are also possible and predictable. In one embodiment, individual pages may be divided into segments, and the segments may include a minimum number of cells that are written once as a basic stylized operation. One or more data pages are typically stored in a memory cell column.

In each block of the example shown in Figure 5, there are 8,512 rows that are divided into even rows and odd rows. The bit lines are divided into even bit lines (BLe) and odd bit lines (BLo). In an odd/even bit line architecture, memory cells along a common word line and connected to odd bit lines are stylized at a time, and memories along a common word line and connected to even bit lines The body unit is stylized at another time. Figure 5 shows four memory cells connected in series to form a NAND string. Although the figure shows that there are four cells in each NAND string, more or less than four cells (eg, 16, 32, or other quantities) may be used. One terminal of the NAND string is connected to a corresponding bit line via a first selection transistor or gate (connected to the selected gate drain line SGD), and the other terminal is connected to the selection gate via a second selection transistor The source line SGS) is connected to the c-source.

During the reading and stylizing operations of an embodiment, 4256 memory cells are simultaneously selected. The selected memory cells have the same word line (eg, WL2) and the same type of bit line (eg, even bit lines). Therefore, 532 bytes of data can be read or programmed simultaneously. The simultaneously read or stylized data of 532 bytes form a logical page. Thus, in this example, a block can store at least 8 pages. When each memory unit stores two bits of data (eg, a multi-state unit), one or the like can store 16 pages (or, for example, each of the 8 pages includes 1064) Bytes). Blocks and pages of other sizes may also be used in various embodiments. In one embodiment, a set of simultaneously selected memory cells can store more than one page of data.

An architecture different from the architectures shown in Figures 4 and 5 can be used in accordance with various embodiments. In an embodiment, the bit lines are not divided into odd bit lines and even bit lines. Such architectures are generally referred to as full bit line architectures. In a full bit line architecture, all bit lines of a block are simultaneously selected during read and program operations. The memory cells along a common word line and connected to any bit line are simultaneously programmed. For more information on the different bit line architectures and associated operating techniques, refer to U.S. Patent Application Serial No. 11/099,133, filed on April 5, 2005, entitled "Compensating for coupling during Read Operations of Non-Volatile Memory", which is incorporated herein by reference in its entirety.

In the read and verify operations, the selected gate of the selected block is raised to one or more select voltages, and the unselected word lines (eg, WL0, WL1, and WL3) of the selected block are raised to a read pass. The voltage (eg, 4.5 volts) is such that the transistor operates as a pass gate. The selected word line (eg, WL2) of the selected block is connected to a reference voltage, and the level of the reference voltage is specified for each read and verify operation to determine the threshold voltage of the memory cell of interest is in this position. Above or below. For example, in a read operation of a 1-bit memory cell, the selected word line WL2 is grounded to detect whether the threshold voltage is higher than 0 volts. In the verify operation of a 1-bit memory cell, for example, the selected word line WL2 is connected to 0.8 V to verify whether the threshold voltage has reached 0.8 V as programmed. The source and p-well are 0 V during read and verify. The selected bit line (BLe) is precharged to, for example, a level of 0.7 V. If the threshold voltage is higher than the read or verify level, the potential level of the bit line of interest (BLe) will remain high due to the associated non-conducting memory cell. On the other hand, if the threshold voltage value is lower than the read or verify level, the potential level of the bit line of interest (BLe) is lowered to a low level due to the conductive memory cell, for example, less than 0.5 V. Other current and voltage sensing techniques can be used in accordance with different embodiments. During reading or sensing of the multi-state cell, state machine 316 steps through various predetermined control gate reference voltages corresponding to various memory states. The sensing module will trip at one of the voltages and will provide an output from the sensing module. The processor in the sensing module can determine the state of the memory generated by considering the (equivalent) trip event and information from the state machine regarding the applied control gate voltage. The binary code of the memory state is calculated and stored in the data latch.

During the stylization and verification operations, data to be programmed into a group of cells can be stored in the set of data latches 322 for each bit line. The drain of the memory and the p-well receive 0 V, while the control gate of the addressed memory cell receives a series of stylized pulses of increasing magnitude. In one embodiment, the magnitude of the pulses in the series ranges from 12 V to 24 V. In other embodiments, the range may be different, for example having a starting level above 12 V. During the stylization, verification operations are performed between the stylized pulses. The stylized levels of each of the parallel stylized units are read between each stylized pulse to determine if it has reached or exceeded the verify level it is being programmed into. The verification level can be the target minimum threshold voltage value of each unit in the corresponding memory state. A means of verifying stylization tests the continuity at a specified comparison point. Verify that the fully stylized unit is blocked to prevent further stylization. The voltage of a verified cell bit line rises from 0 V to Vdd (eg, 2.5 volts) for subsequent stylized pulses to terminate the stylization of their cells. In some cases, the number of pulses will be limited (eg, 20 pulses), and if the last pulse does not adequately program a given memory unit, then an error is assumed.

FIG. 6 illustrates a stylized voltage signal in accordance with an embodiment. This signal has a set of pulses of increasing magnitude. The magnitude of the pulses is increased by a predetermined step size with each pulse. In an embodiment of a memory unit that includes data storing a plurality of bits, an exemplary step size is 0.2 volts (or 0.4 volts). A verification pulse is applied between each stylized pulse. The signal shown in Figure 6 assumes a four-state memory cell and, therefore, includes three verify pulses. For example, there are three consecutive verify pulses between the stylized pulses 330 and 332. The first verify pulse 334 is shown at a 0 V verify voltage level. The second verify pulse 336 follows the first verify pulse at the second verify voltage level. The third verify pulse 338 follows the second verify pulse 336 at the third verify voltage level. A multi-state memory cell capable of storing data in eight states may need to perform verification operations at seven comparison points. Therefore, seven verify pulses are applied sequentially to perform seven verify operations with seven verify levels between two consecutive stylized pulses. Based on the seven verification operations, the system can determine the state of the memory unit. A means for reducing the verification time load is to use a more efficient verification process, for example, as disclosed in U.S. Patent Application Serial No. 10/314,055, filed on Dec. 5, 2002, entitled "Smart Verify for Multi-State Memories"; U.S. Patent Application Serial No. 11/259,799, filed on October 27, 2005, entitled "Method for Programming of Multi-State Non-Volatile Memory Using Smart Verify"; and October 27, 2005 U.S. Patent Application Serial No. 11/260,658, the entire disclosure of which is incorporated herein by reference.

The above erase, read and verify operations are performed in accordance with techniques well known in the art. Therefore, those skilled in the art can change many of the details explained.

At the end of a successful stylization process, the threshold voltage of the memory cell should be properly located in one or more of the threshold voltages of the programmed memory cells, or in the presence of an erased memory cell. One of the voltage limits is distributed. Figure 7 illustrates the threshold voltage distribution of a memory cell group as each memory cell stores two bits of data. Figure 7 shows a first threshold voltage value distribution E for the erased memory cell and three threshold voltage value distributions A, B and C for the programmed memory cell. In one embodiment, the threshold voltage value in the E distribution is negative, and the threshold voltage values in the A, B, and C distributions are positive.

Each of the distinct threshold voltage values shown in Figure 7 corresponds to a predetermined value of the set of data bits. The specific relationship between the data programmed into the memory unit and the threshold voltage level of the memory unit depends on the data encoding scheme employed by the units. In one embodiment, a Gray code assignment scheme is used to assign data values to the threshold voltage ranges such that if the threshold voltage of a floating gate is erroneously shifted to its neighboring physical state, only one The bit will be affected. However, in other embodiments, the Gray code is not used. An example assigns "11" to the threshold voltage range E (state E), assigns "10" to the threshold voltage range A (state A), and assigns "00" to the threshold voltage range B (state B), And assign "01" to the threshold voltage range C (state C). Although FIG. 7 shows four states, other multi-state structures may be used in accordance with embodiments of the present disclosure, including those that include more or less than four states.

Figure 7 shows three read reference voltages Vra, Vrb and Vrc for reading data from a memory cell. By testing whether the threshold voltage of a given memory cell is above or below Vra, Vrb, and Vrc, the system can determine which state the memory cell is in. If a memory cell is turned on at Vra, the memory cell is in state E. If a memory cell is turned on at Vrb and Vrc instead of Vra, the memory cell is in state A. The memory cell is in state B if the memory cell is turned on at Vrc instead of Vra and Vrb. If the memory cell is not conducting at Vra, Vrb or Vrc, then the memory cell is in state C. Figure 7 also shows three verification reference voltages Vva, Vvb and Vvc equally spaced from each other. When the memory cells are programmed to state A, the system tests whether their memory cells have a threshold voltage greater than or equal to Vva. When the memory cells are programmed to state B, the system will test whether the memory cells have a threshold voltage greater than or equal to Vvb. When the memory unit is programmed to state C, the system will determine if the memory unit has a threshold voltage greater than or equal to Vvc. The verify voltages define a threshold voltage range assigned to a particular physical state and a prohibited range therebetween. The verify level interval is provided with a sufficient margin between the highest threshold voltage of one state and the lowest threshold voltage of the next state. A large margin that normally occurs exists between the erased state E and the first stylized state A.

Figure 7 further illustrates full sequence stylization. In full sequence stylization, the memory unit is directly programmed from the erased state E to any of the stylized states A, B, or C. A certain number of memory cells to be programmed may be erased first so that all memory cells are in the erased state E. A series of stylized voltage pulses are then applied to the control gates of the selected memory cells to program the memory cells directly to state A, B or C. When some memory cells are programmed from state E to state A, other memory cells are programmed from state E to state B and/or from state E to state C.

Figure 8 illustrates an example of a two-pass technique of a stylized multi-state memory unit that stores data for two different pages (the next page and an upper page). The four states shown are: state E (11), state A (10), state B (00), and state C (01). For state E, both pages store a "1". For state A, the next page stores a "0" and the upper page stores a "1". For state B, both pages store "0". For state C, the next page stores "1" and the upper page stores "0". It should be noted that although a particular bit pattern has been assigned to each of these states, a different bit pattern may also be assigned. In the first pass of the stylization, the threshold voltage level of the memory unit is set according to the bit to be programmed into the lower logical page. If the bit system is logic "1", the threshold voltage will not change because it is in the proper state due to the previous erased result. However, as indicated by arrow 450, if the bit to be programmed is logic "0", the threshold level of the memory unit is increased to state A. He terminated the first stylization.

In the second pass of the stylization, the threshold voltage level of the memory unit is set according to the bit in the program that is being programmed to the upper logical page. If the logical page bit is to store a logic "1", no stylization will occur, because the memory unit is in state E or A depending on the stylization of the next page bit (both carry a page) One of the bits is "1"). If the upper page bit will become a logic "0", the threshold voltage is shifted. If the first pass causes the cell to remain in the erased state E, then in the second phase, as depicted by arrow 454, the memory cell is programmed to cause the threshold voltage to increase to state C. If the memory unit has been programmed to state A as a result of the first pass stylization, as depicted by arrow 452, the memory unit is further programmed in the second pass to increase the threshold voltage. To be in state B. The result of the second pass is to program the memory unit to a state designated for storing a logical "0" for the upper page without changing the data of the next page.

In one embodiment, if sufficient data is written to fill the entire page, a system can be set up to implement a full sequence of writes. If there is not enough data to write to the entire page, the stylization process can program the next page with the received data. When the follow-up data is received, the system then stylizes the upper page. In still another embodiment, the system can begin writing data using a two-pass technique, and if sufficient data is subsequently received to fill a memory cell of a whole word line (or a majority of a word line), then the Full sequence stylized mode. Further details of such an embodiment are disclosed in the inventor's Sergy Anatolievich Gorobets and Yan Li, U.S. Patent Application Serial No. 11/013,125, filed on Dec. 14, 2004, entitled "Pipelined Programming of Non-Volatile Memories Using Early Data, the entire contents of which is incorporated herein by reference.

Floating gate coupling can cause unrecoverable errors during read operations, which can necessitate error recovery performance during reading. The charge stored on the floating gate of a memory cell can go through a table due to the electric field coupling of the charge stored at the floating gate of another adjacent memory cell or other charge storage region (eg, a dielectric charge storage region) Observed offset. Although in theory, the electric field from the charge on the floating gate of any memory cell in a memory array can be coupled to the floating gate of any other memory cell in the array, it has the most impact on adjacent memory cells. Obvious and noteworthy. Adjacent memory cells may include: adjacent memory cells on the same bit line, adjacent memory cells on the same word line, or adjacent bit lines and adjacent word lines and thus in a diagonal direction Adjacent memory cells adjacent to each other. The apparent shift in charge can cause errors in reading the memory state of a memory cell.

The effect of floating gate coupling is most apparent in the case of staging a memory cell adjacent to the target memory cell following a target memory cell, however, its effects can also be seen in other situations. A charge placed on a floating gate adjacent to the memory cell, or a portion of the charge, will be effectively coupled to the target memory cell by electric field coupling, resulting in an apparent shift in the threshold voltage of the target memory cell. The apparent threshold voltage of a memory cell can be shifted after stylization to such an extent that it reads the reference voltage at the applied reference (which is intended for the memory cell in the memory state to be programmed) It will not be turned on or off (on).

Typically, the programming of the memory cell columns begins with a word line (WL0) adjacent to the source side select gate line. Thereafter, the programming is continued by the word lines (WL1, WL2, WL3, etc.) passing through the cell strings, such that the stylization of the word line (WLn) is completed (each cell of the word line is placed in it) In the final state, at least one material page is then stylized in an adjacent word line (WLn+1). This stylized pattern causes an apparent shift in the threshold voltage after the memory cell has been programmed due to floating gate coupling. For each word line except one of the last one of the string lines to be programmed, an adjacent word is threaded immediately after the stylization of the word line of interest is completed. The negative charge of the floating gate of the memory cell added to the adjacent, subsequently stylized word line increases the apparent threshold voltage of the memory cells on the word line of interest.

9A-10B illustrate the effect of floating gate coupling on a set of memory cells that are programmed using the full sequence of programs illustrated in FIG. FIG. 9B illustrates the distribution of threshold voltage values after stylization of a group of memory cells of the selected word line WLn. The distribution map 500 shows the actual threshold voltage distribution of the cells at WLn in the erased (unprogrammed) state E, and the distribution map 505 shows the actual threshold voltage distribution of the cells at WLn programmed to state A. The distribution map 510 illustrates the actual threshold voltage value distribution of the cells at WLn to state B, and the distribution map 520 illustrates the actual threshold voltage distribution of the cells at WLn programmed to state C. The set of memory cells can include each of the memory cells of the selected column or selected word line WLn, or only WLn connected to a particular type of bit line (even or odd). FIG. 9A illustrates a threshold voltage distribution of a memory cell adjacent to word line WLn+1 prior to stylization. The unit of WLn+1 is stylized after staging the unit of WLn. Since each cell at WLn+1 has been erased but not yet programmed, it does not adversely affect the floating gate coupling of the WLn cells. More importantly, it is in the same state as when WLn is programmed, so the cells of WLn have an apparent threshold voltage equivalent to the level verified during stylization.

FIG. 10A illustrates the threshold voltage distribution of the set of memory cells of WL _n+1 after stylization. The threshold voltage distribution E of the self-erasing of the memory cells has been programmed to the programmed threshold voltage distributions A, B and C. The memory system during sensing can be seen, the word line WL _n is placed after the word line WL _{n +} programmable memory of the charge on the floating gate of _a unit may change the state of WL _n memory cells of the memory. A word line WL and the field _{n + 1} of the charge on the floating gate of the associated memory coupled to the floating gate of the word line WL _n unit extreme. This electric field will result in an apparent shift in the threshold voltage of the memory cells at WL _n .

FIG. 10B illustrates the apparent threshold voltage value distribution of the memory cells at word line WL _n after staging WL _n+1 . The figure shows that each stylized state has four different corresponding threshold voltage value distributions. Based on the state programmed to the adjacent memory cells at word line WLn ₊₁ , the total distribution of each physical state can be broken down into four individual distributions. Each memory cell of the word line WL _n will experience a first level shift of the apparent threshold voltage, wherein each of the memory cell at WL _{n + 1} (on the same bit line) having a Stylized to the adjacent memory unit of state A. Each cell of the _n WL (which has a _{+ 1} in the adjacent cell in state B WL _n) for the second time offset experienced greater apparent threshold voltage. Each cell having an adjacent cell in state C at WLn ₊₁ will experience a third or even greater offset.

For the cell at state WL _n in state A, the distribution map 502 illustrates the presence of a cell adjacent to the memory cell (which remains in the erased state E) on word line WL _n+1 after stylization. Limit voltage. The distribution map 504 depicts the threshold voltage of a cell having an adjacent cell (which is programmed to state A) at word line WLn ₊₁ . Distribution map 506 depicts the threshold voltage of a cell having an adjacent cell (which is programmed to state B) at word line WLn ₊₁ . Distribution map 508 illustrates the threshold voltage of a memory cell having an adjacent cell (which is programmed to state C) at word line WLn ₊₁ .

Memory cells that are programmed to other states at WL _n experience similar coupling effects. Therefore, four individual threshold voltage value distribution maps are also shown for states B and C. Stylized state based on the subsequent word line WL _{n + 1} of the next memory cell, the memory cell is programmable to a state B is displayed at the word line WL _n having four different threshold voltage distribution 512 in FIG. , 514, 516 and 518. In the WL _n are stylized to the memory cell state C will likewise have four different distributions 522, 524 and 528 in FIG. It should be noted that the erase memory cells of WL _n will also experience these coupling effects. Since the normally occurring margin between the erased state E and the state A is generally sufficient such that the offset does not cause an error in reading the erased unit, the offsets are not shown. However, such effects exist and the disclosed techniques can also solve their problems.

An increase in the apparent threshold voltage of the memory cell can cause a read error. In FIG. 10B shows certain programmable memory cell WL _n of the initial state A to the threshold voltage such that it can be shifted to above the read reference voltage level Vrb. This can result in errors in reading. After the read reference voltage Vrb is applied, even if the memory cells are programmed to state A, they may not be turned on. The state machine and controller can determine that the memory cell is in state B instead of state A (after sensing Vb is applied and no conduction is sensed). The initial WL _n certain programmable memory cell to the state B read reference voltage may also be shifted to the top Vrc, thereby potentially resulting in the same manner as a read error.

11 illustrates a read technique that can be used to address some of the apparent voltage offset of the threshold voltage illustrated in FIG. 10B. In FIG. 11, depicted in FIG. 10B shows the distribution for each state of each of the four units of WL _n has been concentrated to the profile 530, 540, and 550, cumulative coupling effect on the memory of which represents a number of unit . The distribution map 530 represents the unit of WL _n in state A after stylizing WL _n+1 , the distribution map 540 represents the unit of WL _n in state B after stylizing WL _n+1 , and the distribution map 550 represents The unit of WL _n in state C after stylizing WL _n+1 . The distribution map 530 includes individual distribution maps 502-508, the distribution map 540 includes individual distribution maps 512-518, and the distribution map 550 includes individual distribution maps 522-528.

When the data on the _n read word line WL, the word line WL can read data of _{n + 1,} and if the word line WL _{n + 1} has disturbed the data on the data on the _n WL, WL of the read _n The process can compensate for the disturbance. For example, when the word line WL _n is read, the state or charge level information of the memory cell at the word line WL _n+1 can be determined to select an appropriate read reference voltage for reading the word line WL _n . Individual memory unit. Figure 11 shows the individual read reference voltages for reading WL _n of the word line WL _n based on the state of the memory cell adjacent to a _{+ 1.} In general, different offsets are used for the nominal read reference voltage (eg, 0 V, 0.1 V, 0.2 V, 0.3 V), and the results sensed with different offsets are selected as an adjacent word line. The state function of the memory unit. In one embodiment, to sense the memory cell of _n lines WL tellers use of such each of the different read reference voltages of the embodiment. For a given memory cell, the result of sensing at one of the read reference voltages can be selected based on the state of an adjacent memory cell at word line WLn+1. In certain embodiments, WLn + 1 determines the read operation is stored in the WL _{n + 1} of the actual data, while in other embodiments, WLn + 1 only determines the read operation of the charge level of such cells, It may or may not accurately reflect the data stored at WLn+1. In some embodiments, the level and/or level of numbers used to read WLn+1 may not be exactly the same as those used to read WLn. In some embodiments, some approximation of the floating gate threshold may be sufficient for WLn correction purposes. In one embodiment, the read result at WLn+1 can be stored in latch 322 of each bit line for use in reading WLn.

Read operations may first be performed on the nominal word line WLn at nominal read reference voltage levels Vra, Vrb, and Vrc, which do not compensate for any coupling effects. For a bit line having a memory cell in which adjacent memory cells at WL _n+1 are determined to be in state E, the result of reading at the nominal reference level is stored in the appropriate lock of the bit line In the memory. Subsequently, a read operation is performed using a first set of offsets for the read reference voltage for word line WLn. This read operation can use Vra1 (Vra+0.1 V), Vrb1 (Vrb+0.1 V), and Vrc1 (Vrc+0.1 V). For a bit line in which the memory cell has adjacent memory cells in state A at WLn ₊₁ , the result of using the reference values is stored. Subsequently, a read operation is performed with the second set of offsets using read reference levels Vra2 (Vra+0.2 V), Vrb2 (Vrb+0.2 V), and Vrc2 (Vrc+0.2 V). For a bit line in which the memory cell has an adjacent memory cell at state WL _n+1 , the result is stored in the latch of the bit line. Reference levels Vra3 (Vra+0.3 V), Vrb3 (Vrb+0.3 V), and Vrc3 (Vrc+0.3 V) are used with the third set of offsets and for which the memory cells have a state at WL _n+1 As a result of the storage of the bit lines of the adjacent memory cells of C, a read operation is performed for the word line WLn. In some embodiments, no offset is used at Vra due to the large normal margin between state E and state A. Such an embodiment is illustrated in FIG. 11 in which a single read reference voltage Vra is depicted at a state A level. Other embodiments may also use offsets for this level.

Different offsets to the nominal read reference voltage can be selected as a state function for a memory cell on an adjacent word line. For example, a set of offset values may include a 0 V offset corresponding to an adjacent cell in state E, one corresponding to a 0.1 V offset of an adjacent cell in state A, and one corresponding to an adjacent cell in state B. The 0.2 V offset, and a 0.3 V offset corresponding to the adjacent cells in state C. These offset values will vary depending on the implementation. In one embodiment, the offset values are equal to the apparent threshold voltage offset resulting from the programming of an adjacent cell to a corresponding state. For example, 0.3 V may represent an apparent threshold voltage shift of a cell at WL _n when an adjacent cell at WL _n+1 is subsequently programmed to state C. The offset value of each reference voltage need not be the same. For example, the offset value of the Vrb reference voltage can be 0 V, 0.1 V, 0.2 V, and 0.3 V, and the offset values of the Vrc reference voltage can be 0 V, 0.15 V, 0.25 V, and 0.35 V. In addition, the offset increments for each state need not be the same. For example, in one embodiment, a set of offset values of adjacent cells in states E, A, B, and C may include 0 V, 0.1 V, 0.3 V, and 0.4 V, respectively.

In one embodiment, it may be desirable to read by a plurality of individual read reference levels in a predetermined state and select the results based on the state of an adjacent memory cell to reduce the effect of floating gate coupling by about 50%. . By using these techniques, the word line threshold voltage value distribution of the memory cells can be effectively narrowed by about 50% when read by a sensing module.

It may be possible to construct a stylized process of non-volatile memory to reduce the apparent voltage deviation of the threshold voltage caused by the floating gate coupling. 12A through 12C illustrate a process for staging non-volatile memory for any particular memory unit by writing a particular page with reference to a particular page after writing an adjacent memory unit for a previous page. The memory cell reduces the floating gate to floating gate coupling. In the example shown in Figures 12A through 12C, each cell stores two-dimensional data per memory cell (using four data states). The erased state E stores the data 11, the state A storage data 01, the state B storage data 10, and the state C storage data 00. You can also use the data to other codes of the entity data status. Each memory unit stores one of two logical page data. For reference, these pages are referred to as the upper page and the lower page, but other markings may also be given. State A is encoded to store bit 0 on the upper page and bit 1 on the next page, state B is encoded to store bit 1 on the upper page and bit 0 on the next page, and state C is encoded to be on both pages Bit 0 is stored on both. Information page stylized the memory cell at WL _n of the word line in the first step of the drawing shown in FIG. 12A, and the second step shown in the schematic in FIG. 12C, etc. The information on a page unit stylized . If the next page data is to hold the data 1 for a unit, the threshold voltage of the memory unit remains in the state E during the first step. If the data is to be programmed to 0, the threshold voltage of the memory unit rises to state B'. State B' is a temporary state B with a verification level Vvb' (which is lower than Vvb).

In one embodiment, after the page data under the memory unit is programmed, the memory cells are stylized with reference to the pages below the adjacent memory cells at the adjacent word line WLn ₊₁ . For example, the page below the memory cell at WL2 shown in FIG. 3 can be programmed after the page below the memory cell at WL1. If the threshold voltage of the memory cell 224 rises from the state E to the state B' after the memory cell 226 is programmed, the floating gate coupling can raise the apparent threshold voltage of the memory cell 226. The cumulative coupling effect on the memory cells at WLn will widen the apparent threshold voltage distribution of the threshold voltages of the cells, as depicted in Figure 12B. The apparent broadening of the threshold voltage value distribution can be remedied when the page above the word line of interest is stylized.

FIG. 12C illustrates the process of staging the page above the memory unit at WLn. If a memory cell is in the erased state E and the page bit remains above 1, the memory cell remains in state E. If the memory cell is in state E and the page data bit is programmed to zero, the threshold voltage of the memory cell rises to the range of state A. If the memory cell is in the intermediate threshold voltage value distribution B' and the page data remains at 1, the memory component is programmed to the final state B. If the memory cell is in the intermediate threshold voltage value distribution B' and the page data on it becomes data 0, the threshold voltage of the memory cell rises to the range of state C. The process illustrated in Figures 12A-12C reduces the floating gate coupling effect because only page programming on adjacent memory cells affects the apparent threshold voltage of a given memory cell. An alternative state coding example of this technique moves from the intermediate state B' to the state C when the upper page data is 1, and moves to the state B when the upper page data is "0". Although FIG. 12A to FIG. 12C provide an example with reference to four data states and two data pages, the concepts taught in FIGS. 12A to 12C may be used for other states having more or less than four states and different numbers. The implementation of the page.

FIG. 13A illustrates the floating gate coupling effects of the stylized technique illustrated in FIGS. 12A-12C, and FIG. 13B illustrates a method of using a compensation offset to overcome some of these effects. As shown in FIG. 12C, the memory cells can be stylized during the second pass of staging the page data on the memory cells adjacent to word line WLn ₊₁ of word line WLn. During this second pass, the memory cell is programmed from state E to state A, or from intermediate state B' to state B or state C. The memory cell of the word line WLn of interest is shown in FIG. 13A, and is programmed after referring to the upper page of the memory cell under the word line WLn+1. Thus, the upper page stylization is shown in Figure 12C as the only stylization that affects the apparent threshold voltage of the memory cells at word line WLn.

The memory cells of word line WLn+1 undergo a threshold voltage change similar to that of state C from the intermediate state B' to the state C when staging from state E to state A. A memory cell adjacent to word line WLn+1 does not experience a significant increase in threshold voltage when programmed from intermediate state B' to state B, and has little effect on the apparent threshold voltage of each cell at WLn. The memory cells stylized to state A at WLn are represented by individual profiles 652, 654, 656, and 658, which respectively correspond to having state E, state B, state A, and state C at WL _n+1 . A unit of adjacent memory cells. The memory cells stylized to state B at WLn are represented by individual profiles 662, 664, 666, and 668, which respectively correspond to having state E, state B, state A, and state C at WL _n+1 . State B unit of adjacent memory cells. The memory cells stylized to state C at WLn are represented by individual profiles 672, 674, 676, and 678, which respectively correspond to having state E, state B, state A, and state C at WL _n+1 . State C unit of adjacent memory cells.

As shown in Figure 13A, some of the memory cells at WLn can have their apparent threshold voltage shifted to near or exceed the read reference voltage Vrb or Vrc. As previously discussed, the coupling effects can be applied to the WLn erase distribution, and the disclosed techniques can be equally applied to the WLn erase distribution. The effect on the erase unit is not primarily explained by the normal margin between state E and state C.

Figure 13B illustrates a read reference level offset that can be used with the stylization techniques illustrated in Figures 12A-12C. For clarity, profiles 652, 654, 656, and 658 are depicted in a single combined profile 651, and profiles 662, 664, 666, and 668 are depicted in combined profile 661, and profiles 672, 674, 676 and 678 are depicted in the combined profile 671. The distribution maps 650, 660, and 670 represent the units at WLn prior to stylizing the page material above WLn+1. In the embodiment illustrated in Figure 13B, similar coupling effects from cells staging to state A or state C on an adjacent word line are grouped together to form a single offset for each of the state levels. The result sensed by the offset reference voltages Vrb1 and Vrc1 is for a memory cell having an adjacent cell in state A or state C at word line WLn+1. The secondary coupling effects caused by the intermediate state B' stylized to state B can be ignored. The result of sensing when using the nominal reference voltages Vrb and Vrc is for a memory cell having an adjacent cell in state E or state B at word line WLn+1. In an embodiment, an additional offset for each particular state of WLn+1 may be used. Although the technique illustrated in Figure 13B additionally reduces the effects of floating gate coupling, errors may still exist.

Misreading an adjacent word line when attempting to determine an appropriate offset for reading the cell of interest may actually prove to be more problematic with the unit programmed with the techniques illustrated in Figures 12A-12C. When the read reference voltage Vrb is applied to the state B, a misread of a memory cell at the word line WLn+1 is considered. If the memory cell at WLn+1 is programmed to state A and is misread while in state B, then the nominal read reference voltage pair corresponding memory cell will be selected and reported at word line WLn. Read the result of the operation. Since it has been determined that the cell at WLn+1 is in state B, and thus only undergoes a minor change in the threshold voltage after stylizing WLn, floating gate coupling compensation is not used. However, in fact, the memory cell at WLn+1 will likely exhibit a strong influence on the apparent threshold voltage of the cell at WLn. The unit at WLn+1 may be at the top of the state A profile, which is why it was misread. Therefore, the memory cell at WLn+1 has experienced a large charge change at its floating gate when it is programmed from state E to the upper end of state A. A large change in the charge stored by the cell at WLn+1 will cause a significant shift in the apparent threshold voltage of the cell at WLn. However, there is no compensation for this offset due to a misread at WLn+1. Therefore, it is possible or even possible to misread the memory cells at WLn as a result of WLn+1 misreading.

A similar problem may occur if a stylized to adjacent memory cell at word line WLn+1 of state B is misread as being in state A. A memory cell that is read as being in state A and actually in state B at word line WLn+1 may have a threshold voltage at the lower end of the state B profile. The memory cell will experience very little threshold voltage change after staging a plurality of memory cells at WLn+1. Therefore, the apparent threshold voltage of the corresponding unit at WLn will have little or no offset. However, the result of the read operation at the WLn for the corresponding memory cell will select the result of the read at the compensated reference level. Since the memory cells of interest have not experienced significant shifts in apparent threshold voltages, selecting such results when using compensated reference levels can result in erroneous reads or errors at WLn.

In the prior art, memory cells have been programmed to various stylized states by means of equal interval verify levels as shown in Figures 13A-13B. In other words, the verify levels of state A, state B, and state C are equally spaced from one another such that the voltage difference between verify levels Vvb and Vva is equal to the voltage difference between verify levels Vvc and Vvb. An equal interval of stylized verification levels results in the same or substantially equal margins between the various stylized states. This margin corresponds to the range of inhibit voltages between physical states. The margin between state A and state B is defined by a maximum threshold voltage of a memory cell in state A and a minimum threshold voltage of a memory cell in state B. Sufficient margins are provided between stylized states to enable accurate readings to be implemented. Due to the floating gate coupling, the margin between physical states can be reduced and result in read errors.

In accordance with an embodiment of the present disclosure, an offset verification level is used when stylizing one or more selected states (eg, state B) to create a larger margin between certain states for improvedness Measure accuracy. In one embodiment, the offset compensation read reference level is not used at a level corresponding to a wider margin, but is used at other levels to provide a more efficient read for higher performance. The combination of the offset application of the offset reference level and the wider margin between the selected physical states provides an accurate sensing technique while maintaining a desired level of performance. 14 illustrates a set of threshold voltage values for a memory unit that is programmed according to an embodiment of the present disclosure. The profiles 678, 680, 684, and 688 illustrate the set of memory cells prior to stylizing the set of memory cells but staging the cells adjacent to the word line WLn+1.

In Figure 14, a stylized verification level Vvb1 is used when staging the memory unit to state B. The embodiment of Figure 14 can be used when stylized according to the techniques illustrated in Figures 12A-12C. The verification level Vvb1 is higher than the Vvb in the conventional operation shown in FIG. 12C, thereby creating a larger margin between the state A and the state B. The highest threshold voltage of any memory cell in state A remains the same as in the conventional technique. However, any cell in state B has the lowest threshold voltage offset in the positive direction. The increased verification level when the memory unit is programmed to state B increases the margin between state A and state B. As shown in Figure 14, the margin 683 between state A and state B is greater than the margin 685 between states B and C. Therefore, misreading is less likely to occur when sensed with the state B reference voltage level Vrb.

Distribution maps 682, 686, and 690 illustrate floating gate coupling effects after staging an adjacent word line WLn ₊₁ (e.g., as illustrated in Figure 12C). In FIG. 14, the Vrb read level is well spaced between the apparent A state profile 682 and the apparent B state profile 686. Therefore, misreading is less likely to occur because the Vrb read level does not overlap with the threshold voltage of any cell intended to be in state A, even after considering the coupling effects of adjacent word lines. In one embodiment, the reference level Vrb is offset from the conventional level used (eg, Vrb shown in FIG. 12C), the offset of which corresponds to the stylized verification level Vvb1 and its standard shown in FIG. 12C. The offset of the value Vvb is weighed. Since Vrb can be shifted far beyond the highest threshold voltage of any of the memory cells in state A, a single reference value Vrb can be used during reading and no compensation is applied.

Thus, in one embodiment, the read reference voltage offset is not used when reading at the state B level. In the embodiment shown in FIG. 14, the read reference voltage offset is used only for the highest state one state C. The larger margin between state A and state B, which exists due to the higher verify level, permits accurate reading at state B level without directly compensating for floating gate coupling. This technique not only reduces misreading, but also improves read time because additional readings are only used to select states with partial offset. In Figure 14, only one additional sensing operation is implemented. In addition to improved performance and read time, reducing the number of sensing operations reduces the complexity and size of the cache circuitry required to maintain data about adjacent memory cells when sensing a selected memory cell.

By way of an unrestricted example, in one embodiment, the following read reference and stylized verification levels can be used in implementing the technique illustrated in FIG. In the prior art described in FIGS. 12A-12C, in an exemplary system, it may be desirable for the margin between state A and state B to be on the order of 0.7 V and to the edge between state B and state C. The limits are roughly the same. Such prior art systems may utilize the following verification and read levels when staging data to the units and reading data from such units: Vva = 0.5 V, Vvb = 2.0 V, Vvc = 3.5 V, Vra = 0.0 V, Vrb = 1.5 V, and Vrc = 3.0 V. However, in Figure 14, the offset verification level of state B will result in a margin between state A and state B on the order of 0.7 V and a margin between state B and state C in such a system. On the order of 0.1 V. Typical read reference and stylized verification levels that can be used in Figure 14 to achieve such margins can include: Vva = 0.5 V, Vvb = 2.3 V, Vvc = 3.5 V, Vra = 0.0 V, Vrb = 1.8 V, Vrc = 3.0 V, and Vrc1 = 3.6 V. As an example, in the embodiment, since the Vrb is offset by the same amount, the difference between the read reference and the stylized verification level at each state remains the same when Vvb is shifted. Therefore, Vva-Vra=Vvb-Vrb=Vvc-Vrc.

15 is a flow chart illustrating an embodiment of a method for staging non-volatile memory to achieve different size margins as depicted in FIG. The stylized method illustrated in Figure 15 can be used to parallelize a group of memory cells, such as those connected to a single word line, in parallel. Figure 15 can also be used to program a selected memory cell of a word line, such as in an odd/even bit line architecture. In one embodiment, the first set of iterations (from step 860 to step 882) is used to program the first logical page of a memory cell group, and the second iteration (steps 860-882) can be used to store the memory. The second logical page of the unit group is stylized.

At step 850, the memory cells to be programmed are erased. Step 850 can include erasing more memory cells (eg, in blocks or other units) than the memory cells to be programmed. At step 852, soft programming is implemented to narrow the erased threshold voltage value distribution of the erased memory cells. Some memory cells can be in a deeper erased state than is required as a result of the erase process. Soft stylization applies a small stylized pulse to move the threshold voltage of the erased memory cell closer to the erased verify level. This will provide a narrower distribution of erased memory cells. At step 854, controller 318 issues a data load command and inputs it to command circuit 314 to allow data to be input to data input/output buffer 312. The input data is recognized as a command and is latched by state machine 316 via a command latch signal (not illustrated) that is input to command circuit 314. At step 856, the address data specifying the page address is input from the host to the column controller 306. The input data is recognized as a page address and latched via state machine 316, and the latch is implemented by an address latch signal input to command circuit 314. At step 858, the stylized page data of the addressed page is input to the data input/output buffer 312 for programmatic use. For example, in an exemplary embodiment, data for 532 bytes can be entered. The input data is latched into the appropriate register of the selected bit line. In some embodiments, the data is also latched in a second register of selected bit lines for use in a verify operation. At step 860, the controller issues a stylized command and inputs it to the data input/output buffer 312. The command is latched by state machine 316 via a command latch signal that is input to command circuit 314.

With the stylized command trigger, the data latched in step 858 is programmed into the selected memory unit controlled by state machine 316. By using stepped stylized voltage pulses, such as those depicted in the stylized voltage signal shown in Figure 6, the programmed voltage signal is applied to the appropriate word line corresponding to the page or other unit of the unit being programmed. . At step 862, the programmed pulse voltage level Vpgm is initialized to a start pulse (eg, 12 V) and a programmed counter PC maintained by state machine 316 is initialized to zero. At step 864, a first Vpgm pulse is applied to the selected word line. If a logic 0 is stored in a particular data latch to indicate that the corresponding memory cell should be stylized, the corresponding bit line is grounded. On the other hand, if logic 1 is stored in a particular latch to indicate that the corresponding memory cell should be maintained in its current data state, then the corresponding bit line is connected to V _DD to disable stylization.

At step 866, the status of the selected memory unit is verified. To date, the process illustrated in Figure 15 has advanced in accordance with conventional techniques. However, at step 866, the process includes a novel technique to create unequal interval margins that facilitate more accurate reading of the selection level. Create a large margin between the two stylized states. In one embodiment, a larger margin is created between the lower level states while maintaining the highest state within its nominal position. In one embodiment, verification is performed such that there is a large margin between state B and state A. In other embodiments, the highest level state or the higher level states may be forward biased by using a larger verify voltage at the same level. However, shifting the distribution to a total higher positive voltage may be unacceptable in some embodiments, where the voltage level (eg, Vpgm) is maintained at a certain maximum level due to minimizing stylized disturbances and the like. .

In one embodiment, the unequal interval verification levels are used at step 866 to create unequal margins. As shown in FIG. 14, the verification level Vvb1 of the second stylized state B is spaced from the verification level of the first stylized state (state A), and the interval is different from the third stylized state (state C). Verify the amount of separation between the level and the verification level of the second stylized state (state B). Verify that the levels Vva, Vvb, and Vvc define the lowest point of the minimum threshold voltage for their particular state. By using unequal interval verification levels, the margin created between state A and state B is greater than the margin created between state B and state C.

After sensing with the applied reference voltage, it is checked at step 868 whether all of the data latches store a logic one. If so, the stylization process is complete and successful because all selected memory cells have been programmed to their target state and verified. A pass status is reported at step 876. If it is determined at step 868 that not all of the data latches store a logic one, then the process continues to step 872 where the stylized counter PC is checked against a stylized limit value. A stylized limit value instance is 20, although other values may be used in various embodiments. If the stylized counter PC is not less than 20, then at step 874 it is determined if the number of memory units that have not been successfully programmed is less than or equal to a predetermined number. If the number of units that have not been successfully programmed is equal to or less than this number, then the process is flagged as pass and a pass status is reported at step 876. Unsuccessfully stylized bits can be corrected using error correction during read operations. If the number of units that have not been successfully programmed is greater than the predetermined number, the stylized process setting flag is failed and a failure status is reported at step 878. If the stylized counter PC is less than 20, the Vpgm level is increased by a step size and the stylized counter PC is incremented at step 880. After step 880, the process loops back to step 864 to apply the next Vpgm pulse.

As described, step 866 includes using unequal intervals of verification levels such that there are unequal interval margins for the stylized memory cells. 16 illustrates an embodiment of step 866 of FIG. At step 882, a first stylized state verification level Vva is applied. At step 884, the bit line is sensed by Vva applied to the memory cell at each bit line. At step 886, the result of the unit to be programmed to state A is stored. Step 886 can include setting a bit line of the data line to logic 1 to indicate that programming will continue for the memory unit, or set to logic 0 to indicate that the memory unit is at its target level. At or above, and should stop the stylization of the memory unit. At step 888, a second stylized state verification level Vvb1 is applied to each memory cell being verified. The verification level Vvb1 is spaced apart from the verification level Vva by a first amount. For example, Vva and Vvb1 may be spaced apart from each other by an amount equal to about 0.8 V. At step 890, the bit lines are sensed by Vvb1 applied to each memory cell. At step 892, the result is stored by indicating in the data latch of each bit line whether the corresponding memory cell has reached its target level. At step 894, a third verification level Vvc is applied for the third stylized state. The verification level Vvc is separated from the verification level Vvb1 by a second amount that is different from the first amount separating Vva and Vvb1. As shown in FIG. 14, the spacing between the verification levels Vvb1 and Vvc is less than the spacing between the verification levels Vva and Vvb1. At step 896, the bit line is sensed by Vvc applied to each memory cell. At step 898, for example, the results of the cells to be programmed to state C are stored by indicating in a data latch whether the cells should undergo further programming.

As shown in blocks 891 and 899, the unequal interval verification levels result in a first size margin between states A and B, and a second size margin between states B and C. The margin between states A and B is less than the margin between states B and C due to the Vvb verification level of the offset.

17 is a flow chart showing a general process for reading data in response to a request to read a particular page or pages or other data packets. In other embodiments, the process of Figure 17 can be implemented as part of a data recovery operation in response to a conventional read operation to detect errors. When reading data stylized according to the process shown in Figures 12A through 12C, any floating gate coupling disturbance caused by programming the pages below the adjacent memory cells will be on the page program of the cell of interest. It was corrected when it was changed. Therefore, when attempting to compensate for the floating gate coupling effects of adjacent memory cells, the process only needs to consider the coupling effects caused by staging the pages on adjacent memory cells.

At step 902 of FIG. 17, the upper page material of the subsequently stylized word line adjacent to the word line of interest is read. If it is not determined at step 904 that the page above the adjacent word line is stylized, then at step 908 the word line or page of interest is read without compensating for the floating gate coupling effect. If the page above the adjacent word line is stylized, the page of interest is read using the compensation of the floating gate coupling effect at step 906. In some embodiments, reading cells of adjacent word lines can result in determining the level of charge on adjacent word lines that may or may not accurately reflect the data stored thereon.

In one embodiment, a memory array retains a set of memory cells to store one or more flags. For example, a row of memory cells can be used to store a flag indicating whether the page below the corresponding column of the memory cell has been programmed, and another row is used to store a flag indicating whether the page above the corresponding column of the memory cell has been programmed. Standard. By examining an appropriate flag, it can be determined whether the page above the adjacent word line has been programmed. Further details of such a flag and the stylization process can be found in U.S. Patent No. 6,657,891 to "Semiconductor Memory Device For Storing Multi-Valued Data", which is incorporated herein by reference in its entirety.

Figure 18 illustrates an embodiment of a process for reading page data over an adjacent word line, which may be used at step 902 shown in Figure 17. The read reference voltage Vrc is applied to the word line at step 910, and the bit line is sensed as described above at step 912. At step 914, the sensed results are stored in appropriate latches. First choose to read in Vrc to uniquely determine the upper page data, because the next page data will be written to WL _n+1 under normal circumstances, and reading with Vra or Vrb will not guarantee the only result. The intermediate value B' (Fig. 12B) can overlap with the value.

At step 916, a flag indicating the page stylization associated with the page being read is checked. If the flag is not set as determined at step 918, then at step 920 the above page is not stylized to conclude that the process is terminated. If the flag is set, the upper page is assumed to be stylized. At step 922, the read reference voltage Vrb is applied to the word line associated with the page being read. The bit lines are sensed at step 924 and stored in the appropriate latches at step 926. At step 928, the read reference voltage Vra is applied. The bit lines are sensed at step 930, and the results are stored in the appropriate latches at step 932. At step 934, the data values stored by each of the read memory cells are determined based on the results of sensing steps 912, 924, and 930. At step 936, the data values can be stored in an appropriate data latch for final communication with the user. The upper page and the next page data are determined using conventional logic techniques that are dependent on the particular state code selected. For the example encodings illustrated in Figures 12A-12C, the next page data is Vrb* (the complement of the value stored when read in Vrb) and the upper page data is Vra*OR (Vrb and Vrc*). The process illustrated in Figure 18, although illustrated herein for reading WLn ₊₁ , can also be used to read WLn as described below.

Figure 19 is a flow chart illustrating an embodiment of reading data for a word line of interest when there is no need to compensate for floating gate coupling of an adjacent word line. At step 950, it is determined whether the upper or lower page associated with the word line of interest is being read. If the next page is being read, the read reference voltage Vrb is applied to the appropriate word line at step 952. The bit line is sensed at step 954 and the result is stored in the appropriate latch at step 956. At step 958, a flag is checked to determine if the page of interest contains the previous page material. If there is no set flag, any stylized data will be in the intermediate state B'. Therefore, Vrb does not produce any accurate sensing results, causing the process to continue at step 960, where Vra is applied to the word line. The bit line is re-sensed at step 962 and the result is stored at step 964. At step 966, a data value to be stored is determined. In one embodiment, if the memory cell is turned on, where Vrb (or Vra) is applied to the word line, the next page data is "1". Otherwise, the next page data is "0".

At step 950, if it is determined that the page address corresponds to the upper page, then an upper page reading process is performed at step 970. In one embodiment, since it is possible to address an unwritten page for reading, or another reason, the page reading at step 970 includes the same method as described in FIG. 18, including reading The flag and all three states.

20 is a flow diagram illustrating an embodiment of a process for reading data while compensating for floating gate coupling, such as may be performed at step 906 of FIG. At step 966, it is determined whether an offset is used to compensate for the floating gate coupling. Step 966 is implemented separately for each bit line. Use data from adjacent word lines to determine which bit lines need to use the offset. If an adjacent memory cell is in state E or B, the memory cells at the read word line do not need to use compensation during sensing. If the cell at WL _n+1 is in state E, it will not contribute any coupling because its threshold voltage is the same as before writing to the word line of interest. If a cell at WL _n+1 is in state B, it is stylized from intermediate state B' to state B, which is a small charge change and is negligible in most cases. A read offset will be used for each of the cells on WLn, where the cells have an adjacent memory cell at state WL or state C at WLn ₊₁ .

If it has been determined at step 967 that the page being read is the next page, then at step 968 Vrb is applied to the word line associated with the page being read. Reading with Vrb is sufficient to determine the page material for the code shown in Figures 12A through 12C. The bit line is sensed at step 969, and at step 970, the result is stored in the appropriate latch of the bit line. As shown in Figure 14, no compensation offset is applied at the Vrb level, so step 969 is the only lower page sensing implemented. Since the cells are programmed to create a larger margin between state A and state B, an accurate read can be achieved without compensating for the coupling. At step 971, the information of the next page is determined. If a unit is turned on in response to Vrb, the next page data is 1; otherwise, the next page data is 0. At step 972, the next page material is stored in a suitable latch for communication with the user.

If it is determined at step 967 that the page being read is a page, then at step 976 the compensation is used to read the previous page. Figure 21 is a flow diagram illustrating page read using an offset read reference level. In step 974 of FIG. 21, the read reference voltage Vrc is applied to the word line associated with the page being read. The bit line is sensed at step 975 and the result is stored in the appropriate latch in step 976. In step 977, Vrc is applied with an offset (e.g., 0.1 V) to the word line associated with the page being read. The bit line is sensed in step 978, and in step 979, the result stored in step 976 is overwritten for the result of the sensing at step 978 for any bit line that requires offset. Vrb is applied to the word line in step 980, and the bit line is sensed in step 981. In step 982, the result of the sensing at step 981 is stored. In step 983, Vra is applied to the word line associated with the page being read. The bit line is sensed at step 984 and the result is stored in the appropriate latch at step 985. In Figure 20, it is assumed that the normally generated margin between state E and state A is sufficiently large that no offset associated with Vra is required. In other embodiments, the offset can be used for the Vra level. The data values are determined in step 986, and the data values are stored in the appropriate data latches for communication with the user in step 987. In other embodiments, the order of reading (Vrc, Vrb, Vra) can be changed.

The invention has been described in detail above for the purposes of illustration and description. This document is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Numerous modifications and changes are possible in light of the above teachings. The embodiments were chosen to best explain the principles of the invention and the application of the embodiments of the invention, in which this invention. The scope of the invention is intended to be defined by the scope of the accompanying claims.

100FG. . . Floating gate

100CG. . . Control gate

102FG. . . Floating gate

102CG. . . Control gate

104FG. . . Floating gate

104CG. . . Control gate

106FG. . . Floating gate

106CG. . . Control gate

120CG. . . Control gate

122CG. . . Control gate

100. . . Transistor

102. . . Transistor

104. . . Transistor

106. . . Transistor

120. . . Select gate

122. . . Select gate

126. . . Bit line

128. . . Source line

SGD. . . Selection line

WL3. . . Word line

WL2. . . Word line

WL1. . . Word line

WL0. . . Word line

SGS. . . Selection line

202. . . NAND string

204. . . NAND string

206. . . NAND string

220. . . Select transistor

222. . . Memory unit

224. . . Memory unit

226. . . Memory unit

228. . . Memory unit

230. . . Select transistor

240. . . Select transistor

242. . . Memory unit

244. . . Memory unit

246. . . Memory unit

248. . . Memory unit

250. . . Select transistor

252. . . Memory unit

302. . . Memory cell array

304. . . Line control circuit

306. . . Column control circuit

308. . . P-well control circuit

310. . . C-source control circuit

312. . . Data input/output buffer

314. . . Command circuit

315. . . Control circuit

316. . . state machine

318. . . Controller

320. . . Sensing module

322. . . Data latch stack

330. . . Stylized pulse

332. . . Stylized pulse

334. . . First verification pulse

336. . . Second verification pulse

338. . . Third verification pulse

Figure 1 is a top view of a NAND string.

2 is an equivalent circuit diagram of the NAND string shown in FIG. 1.

FIG. 3 is a circuit diagram showing three NAND strings.

4 is a block diagram of an embodiment of a non-volatile memory system.

Figure 5 illustrates an exemplary organization of a memory array.

FIG. 6 illustrates a stylized voltage signal in accordance with an embodiment.

Figure 7 illustrates a set of exemplary threshold voltage values and a complete sequence of stylized processes.

Figure 8 illustrates an exemplary set of threshold voltage values and a two-pass stylization process.

FIG. 9A illustrates an exemplary threshold voltage value distribution of a memory cell group, wherein the memory cells are connected to a first word line prior to programming.

FIG. 9B illustrates an exemplary threshold voltage value distribution of a memory cell group, wherein the memory cells are programmed to be connected to a second word line adjacent to the first word line shown in FIG. 9A.

FIG. 10A illustrates a threshold voltage distribution after staging the memory cell group shown in FIG. 9A.

FIG. 10B illustrates the threshold voltage value distribution of the memory cell group shown in FIG. 9B after the memory cell group shown in FIG. 10A is programmed.

11 illustrates a threshold distribution of the memory cell shown in FIG. 10B with an offset read reference voltage, wherein the offset read reference voltage is used to compensate for floating gate coupling.

12A-12C illustrate an exemplary threshold voltage value distribution and a stylization process of a memory cell group, the stylization process after the first few pages of the adjacent memory cell group are stylized. One of the body unit groups is programmed to simplify the floating gate coupling effect.

13A-13B illustrate floating gate coupling effects of a memory cell programmed for use in accordance with the processes illustrated in FIGS. 12A-12C, and example read reference voltage values for compensating for floating gate coupling.

Figure 14 illustrates a stylized and read technique according to an embodiment, and a threshold voltage value distribution of a memory cell group programmed according to the stylization technique.

Figure 15 is a flow diagram illustrating one embodiment of a process for staging non-volatile memory to create a larger margin between selected memory states.

Figure 16 is a flow diagram illustrating one embodiment of a process for verifying the stylization of non-volatile memory to create a larger margin between selected memory states.

Figure 17 is a flow diagram illustrating an embodiment of a process for reading non-volatile memory.

Figure 18 is a flow diagram illustrating an embodiment of a process for reading page data from a non-volatile memory unit.

Figure 19 is a flow chart illustrating an embodiment of a process for reading data without resorting to compensation.

Figure 20 is a flow diagram illustrating an embodiment of a process for reading data using compensation for floating gate coupling.

Figure 21 is a flow diagram illustrating an embodiment of a process for reading information on a page using compensation for floating gate coupling.

(no component symbol description)

Claims (10)

A method of staging a non-volatile memory, comprising: programming a first non-volatile storage element group from a set of non-volatile storage elements to a first stylized state, the first stylized state Associated with a first threshold voltage range, the set of non-volatile storage elements are coupled to a first word line; and the second non-volatile storage element group from the set of non-volatile storage elements is programmed to a a second stylized state, the second stylized state being adjacent to the first stylized state and associated with a second threshold voltage range, the second threshold voltage range being a first margin and the first And limiting a voltage range range; and programming a third non-volatile storage element group from the group of non-volatile storage elements to a third stylized state, the third stylized state being adjacent to the second stylized state and Associated with a third threshold voltage range, the third threshold voltage range is distinguished from the second threshold voltage range by a second margin that is less than one of the first margins. The method of claim 1, wherein: programming the first memory cell group to the first stylized state comprises verifying whether the first memory cell group has reached a first state of the first stylized state Verifying the level; programming the second set of memory cells to the second stylized state includes verifying whether the second set of memory cells has reached a second verify level of the second stylized state, The second verification level is spaced apart from the first verification level by a first amount; and Stylizing the third memory cell group to the third stylized state includes verifying whether the third memory cell group has reached a third verify level of the third stylized state, the third verify bit And the second verification level is spaced apart from the second amount by a second amount. The method of claim 2, wherein the first threshold and a maximum threshold voltage of one of the memory cells of the first group programmed to the first stylized state are programmed to the second program The difference between the minimum threshold voltages of one of the memory cells of the second group of states is the same; the second margin and any memory of the second group programmed to the second stylized state The difference between the maximum threshold voltage of one of the body units and the minimum threshold voltage of one of the memory cells of the third group programmed to the third stylized state; verifying the second memory cell group Whether the group reaches the second verification level includes verifying that the lowest threshold voltage of any one of the memory units of the second group is located at or above the second verification level to establish the first The first threshold of the quantity; and the verifying whether the third memory unit group reaches the third verification level comprises verifying that the lowest threshold voltage of any one of the memory units of the third group is located in the first Three verification levels or above the third verification level To establish the second margin of the second amount. The method of claim 1, wherein: the first margin corresponds to a forbidden range of a threshold voltage between the first stylized state and the second stylized state; The second margin corresponds to a prohibited range of the threshold voltage between the second stylized state and the third stylized state. The method of claim 1, further comprising: programming a fourth non-volatile storage element group to a fourth stylized state, the fourth stylized state being adjacent to the first stylized state and being associated with a fourth The voltage limit range is related, and the fourth threshold voltage range includes a threshold voltage that is lower than the first threshold voltage range. The method of claim 1, further comprising: receiving a request to read the set of non-volatile storage elements, the set of non-volatile storage elements comprising a first non-volatile storage element; and a second non-volatile storage element Reading the charging information to respond to the request; if the charging information indicates that one or more predetermined levels of the second non-volatile storage element are programmed, reading the data from the first non-volatile storage; When the level between the first stylized state and the second stylized state is read, the coupling between the first non-volatile storage element and the second non-volatile storage element is not compensated. Compensating for the coupling between the first and second non-volatile storage elements when the level between the second stylized state and the third stylized state is read; and if the charging information does not indicate stylization Reading the data from the first non-volatile storage element by one or more predetermined levels of the second non-volatile storage element, without being between the first and second stylized states Compensating for the coupling between the first and second non-volatile storage elements when one of the levels is read, and without the level reading between the second and third stylized states, Compensating for coupling between the first and second non-volatile storage elements. A non-volatile memory system comprising: a plurality of non-volatile storage elements coupled to a first word line; a management circuit in communication with the plurality of non-volatile storage elements, the management circuit The plurality of non-volatile storage elements are programmed to a plurality of physical states: one or more non-volatile storage elements are programmed to a first stylized state, a second stylized state, and a third stylized state, the first The second stylized state corresponds to a threshold voltage between the threshold voltage corresponding to the first stylized state and the threshold voltage corresponding to the second stylized state; verifying that the plurality of programs are to be programmed to the first program Whether the non-volatile storage element of the state has reached a first target level corresponding to the first stylized state; verifying whether the plurality of non-volatile storage elements to be programmed to the second stylized state have A second target level corresponding to the second stylized state is reached, the second target level is spaced apart from the first target level by a first amount; and verifying that the plurality of characters are to be programmed to the first Whether programmable non-volatile storage element has reached the state corresponding to the third target level in one of said third programmable state, the third target level and the second target site Quasi-interval a second amount. The non-volatile memory system of claim 7, wherein: the second amount is less than the first amount. The non-volatile memory system of claim 7, wherein: verifying whether the storage element to be programmed to the first stylized state has reached the first target level and the verification is to be stylized to the second stylized Whether the state storage element has reached a second target level provides a first margin between the first stylized state and the second stylized state; verification will be programmed to the second stylized Whether the storage element of the state has reached the second target level and verifying whether the storage element to be programmed to the third stylized state has reached the third target level provides the second stylized state and the One of the smaller dimensions of the third stylized state is the second margin. The non-volatile memory system of claim 7, wherein the complex number is a first plurality, the management circuit receives a request to read the first plurality of non-volatile storage elements, and responds by: reading Adjacent to the second plurality of non-volatile storage elements of the first plurality; when reading the second plurality, the one or more of the adjacent non-volatile storage elements are programmed in the second plurality by the following steps Pre-positioning on time, reading data from each of the first plurality of non-volatile storage elements: when in between the first stylized state and the second stylized state Reading between each non-volatile storage element without compensating for coupling between the non-volatile storage element and the adjacent non-volatile storage element; When the level reading between the second stylized state and a third stylized state is performed, the coupling between each non-volatile storage element and the adjacent non-volatile storage element is compensated for each The non-volatile storage element reads data; when reading a second plurality, the following steps do not indicate that the one or more predetermined levels of the adjacent non-volatile storage element are programmed in the second plurality Reading, by the first plurality of non-volatile storage elements, data from each of the non-volatile storage elements when reading at a level between the first and second stylized states, Without compensating for coupling between each of the non-volatile storage elements and the adjacent non-volatile storage element; and when reading the level between the second and third stylized states, Each of the non-volatile storage elements and the Coupled between the non-volatile storage element nearly self-compensating each of the non-volatile storage elements to read data.