JP4912460B2 - Detecting individual size margin in nonvolatile memory read operation improvement and detection by compensation in selected state - Google Patents

Description

  The present invention relates to a program for nonvolatile memory.

  Semiconductor memory devices are commonly used in various electronic devices. For example, non-volatile semiconductor memories are used in mobile phones, digital cameras, personal digital assistants, mobile computers, non-mobile computers, and other devices. The most prevalent nonvolatile semiconductor memories are electrically erasable programmable read only memory (EEPROM) including flash EEPROM and electrically programmable read only memory (EPROM).

  One example of a flash memory system uses a NAND structure that includes a plurality of transistors arranged in series between two select gates. The transistor in series and the select gate are called a NAND string. FIG. 1 is a plan view showing one NAND string. FIG. 2 is an equivalent circuit thereof. The NAND string shown in FIGS. 1 and 2 includes four transistors 100, 102, 104, and 106 arranged in series between a first selection gate 120 and a second selection gate 122. Select gate 120 connects the NAND string to bit line 126. Select gate 122 connects the NAND string to source line 128. The selection gate 120 is controlled by applying an appropriate voltage to the control gate 120CG via the selection line SGD. The selection gate 122 is controlled by applying an appropriate voltage to the control gate 122CG via the selection line SGS. Each transistor 100, 102, 104, 106 has a control gate and a floating gate that form the gate element of the memory cell. For example, the transistor 100 includes a control gate 100CG and a floating gate 100FG. The transistor 102 includes a control gate 102CG and a floating gate 102FG. The transistor 104 has a control gate 104CG and a floating gate 104FG. The transistor 106 includes a control gate 106CG and a floating gate 106FG. The control gate 100CG is connected to the word line WL3, the control gate 102CG is connected to the word line WL2, the control gate 104CG is connected to the word line WL1, and the control gate 106CG is connected to the word line WL0. Yes.

  1 and 2 show four memory cells in a NAND string. However, note that the four transistors are provided as an example only. The NAND string may have less than four memory cells or may have more than four memory cells. For example, a NAND string may have 8, 16, 32, or other numbers of memory cells. The description here does not limit the number of memory cells in the NAND string to a specific number.

  A typical structure of a flash memory system using a NAND structure has a plurality of NAND strings. For example, FIG. 3 shows three NAND strings 202, 204, 206 in a memory array having more NAND strings. Each NAND string in FIG. 3 has two select transistors or gates and four memory cells. For example, the NAND string 202 includes select transistors 220 and 230 and memory cells 222, 224, 226 and 228. The NAND string 204 includes select transistors 240 and 250 and memory cells 242, 244, 246, and 248. Each string is connected to the source line by one select gate (eg select gates 230, 250). The selection line SGS is used to control the selection gate on the source side. Various NAND strings are connected to each bit line by select gates 220, 240, etc. controlled by select line SGD. In other embodiments, the selection lines are not necessarily shared. The word line WL3 is connected to the control gates of the memory cells 222 and 242. The word line WL2 is connected to the control gates of the memory cells 224 and 244. The word line WL1 is connected to the control gates of the memory cells 226 and 246. The word line WL0 is connected to the control gates of the memory cells 228 and 248. As can be seen, the bit lines and each NAND string comprise a column of memory cell arrays. Word lines (WL3, WL2, WL1, WL0) comprise array rows. Each word line connects the control gates of each memory cell in the row. For example, the word line WL2 is connected to the control gates of the memory cells 224, 244 and 252.

  Examples of NAND type flash memories and their operation are provided by the following US patents / patent applications. U.S. Patent No. 5,570,315, U.S. Patent No. 5,774,397, U.S. Patent No. 6,046,935, U.S. Patent No. 6,456,528 and U.S. Patent Application No. 09 / 893,277. (Publication No. US2003 / 0002348). The entirety of these applications is hereby incorporated by reference.

  Each memory cell can store data (analog or digital). When storing 1-bit digital data, the usable threshold voltage range of a memory cell, typically called a binary memory cell, is divided into two ranges assigned to logic data “1” and “0”. . In an example of the NAND flash memory, the threshold voltage becomes negative after erasing the memory cell, and is defined as logic “1”. The threshold voltage after the program operation becomes positive and is defined as logic “0”. If the threshold voltage is negative and a read operation is attempted with 0 volts applied to the control gate, the memory cell is turned on, indicating that a logic 1 is stored. If the threshold voltage is positive and a read operation is attempted with 0 volts applied to the control gate, the memory cell is not turned on, indicating that a logic 0 has been stored. A multi-state memory cell can also store multiple levels of information such as, for example, multiple bits of digital data. When storing multiple levels of data, the usable threshold voltage range is divided into multiple levels of data. For example, when four levels of information are stored, four threshold voltage ranges of data values “11”, “10”, “01”, and “00” are assigned. In an example of the NAND memory, the threshold voltage after the erase operation is negative and is defined as “11”. Three different positive threshold voltages are used for “10”, “01”, and “00”. The specific relationship between the data programmed in the memory cell and the threshold voltage range of the cell depends on the data encoding scheme employed in the memory cell. For example, US Pat. No. 6,222,762 filed Jun. 13, 2003 and US Patent Application No. 10 / 461,244, “Tracking Cells For A Memory System” (both herein incorporated by reference). Describes various data encoding schemes for multi-state flash memory cells. Furthermore, the embodiment of the present disclosure can be applied to a memory cell that stores data of 3 bits or more.

  When programming an EEPROM or flash memory device, a program voltage is typically applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell increases, so the memory cell is in the programmed state. The charge of the floating gate and the threshold voltage of the cell may indicate a certain state corresponding to the stored data. For details on programming, see “Self Boosting Technique” in US patent application Ser. No. 10 / 379,608, filed Mar. 5, 2003, and US Patent Application No. 10 / 629,068, filed Jul. 29, 2003. In “Detecting Over Programmed Memory”. Both applications are incorporated herein by reference.

  The apparent voltage shift stored in the floating gate may occur due to the coupling of electric fields based on the charge stored in the adjacent floating gate. This floating gate coupling phenomenon is described in US Pat. No. 5,867,429, the entirety of which is incorporated herein by reference. The floating-gate coupling phenomenon occurs most prominently between sets of adjacent memory cells programmed at different times, but not limited thereto. For example, the first memory cell can be programmed to add a level of charge to its floating gate corresponding to the set of data. Thereafter, one or more adjacent memory cells are programmed to add a level of charge to their floating gates corresponding to the set of data. After one or more of the adjacent memory cells are programmed, the charge level read from the first memory cell is affected by the charge on the adjacent memory cell (s) coupled to the first memory cell. Because of this, it looks different from when it was programmed. Coupling from adjacent memory cells may shift the apparent charge level read from the selected memory cell by an amount sufficient to lead to erroneous reading of stored data.

  As memory cell sizes continue to shrink, the inherent programming and erase distribution of threshold voltages increases due to short channel effects, larger oxide thickness / coupling ratio variations, and many channel dopant variations To reduce the available separation between adjacent states. This effect is more significant in multi-state memory than in binary memory using only two states. A reduction in spacing between word lines and bit lines also increases coupling between adjacent floating gates. Because the allowed threshold voltage range and the forbidden range in multi-state devices (range between two different threshold voltage ranges representing different memory states) are even narrower than in binary devices, the effect of coupling between floating gates is A greater concern for multi-state machines. Therefore, the memory cell may shift from the permitted threshold voltage range to the prohibited range due to coupling between floating gates.

  Accordingly, there is a need for a non-volatile memory that effectively manages the aforementioned problems of floating gate coupling.

  The techniques described herein attempt to address the effects of floating gate coupling in non-volatile memory.

  A non-volatile memory read operation can compensate for floating gate coupling when the apparent threshold voltage of the memory cell may have shifted. The memory cell of interest can be read using a reference value based on the level of charge read from adjacent memory cells. Misreading of neighboring cells can have a greater impact, especially in programming methodologies, and more particularly when reading neighboring cells for a particular state or charge level in those methodologies. In one embodiment, the memory cell is programmed to create a wider margin between certain conditions where misreading adjacent cells is more disruptive. Further, in one embodiment, the memory cell floats based on the state of the neighboring cell when reading a particular reference level, rather than when reading at a particular reference level, such as the reference level when a wider margin is created. Read by compensating for gate coupling.

  In one embodiment, a method of reading a non-volatile storage device that reads a second non-volatile storage element adjacent to a first non-volatile storage element in response to receiving a request to read the first non-volatile storage element is provided. Is done. The first criterion is applied to read the first non-volatile storage element at a level between the first program state and the second program state. The second criterion is applied to read the first non-volatile storage element at a level between the second program state and the third program state. The data of the first non-volatile storage element is the result of applying the first criterion at the first level and the second level when the second non-volatile element is in the first subset of the physical state. Determined using the result of applying the two criteria. Determining data for the first non-volatile storage element when the second non-volatile storage element is in the second subset of the physical state results from applying the first criterion at the first level, and Use the result of applying the second criterion at a level of 3.

  In one embodiment, a non-volatile including a first group of memory cells from a set of memory cells that are programmed together, a second group of memory cells from the set, and a third group of memory cells from the set. A memory system is provided. The first group is programmed to a first program state associated with a first range of threshold voltages. The second group is programmed to a second program state associated with a second range of threshold voltages. The first range and the second range of threshold voltages define a first margin of a first size between the first program state and the second program state. The third group is programmed to a third program state associated with a third range of threshold voltages. The second range and the third range of threshold voltages define a second margin between the second program state and a third program state of a second size that is smaller than the first size.

  Other features, aspects, and objects of the disclosed technology embodiments can be obtained from a review of the specification, figures, and claims.

It is a top view of a NAND string. FIG. 2 is an equivalent circuit diagram of the NAND string of FIG. 1. It is a circuit diagram which shows three NAND strings. 1 is a block diagram of one embodiment of a non-volatile memory system. 2 illustrates an exemplary configuration of a memory array. Fig. 5 shows a program voltage signal according to one embodiment. Fig. 4 illustrates an exemplary set of threshold voltage distribution and full sequence programming processes. Fig. 4 illustrates an exemplary set of threshold voltage distribution and two-path programming processes. Fig. 4 shows an exemplary threshold voltage distribution of a group of memory cells connected to a first word line before programming. FIG. 9B illustrates an exemplary threshold voltage distribution for a group of memory cells connected to a second word line adjacent to the first word line of FIG. 9A after programming. FIG. 9B shows the threshold voltage distribution of the group of memory cells of FIG. FIG. 10B shows the threshold voltage distribution of the group of memory cells of FIG. 9B after programming the group of memory cells shown in FIG. 10A. FIG. 10B shows the threshold distribution of the memory cell of FIG. 10B along with the offset read reference voltage used to compensate for floating gate coupling. (A) through (C) are the selection of data for a group of memory cells and a group of memory cells after programming a previous page for adjacent groups of memory cells to reduce floating gate coupling effects. Fig. 4 illustrates an exemplary threshold voltage distribution for a programming process for programming a page. FIG. 13 illustrates the effect of floating gate coupling on a memory cell programmed according to the process of FIGS. 12A-12C and an exemplary read reference voltage used to compensate for floating gate coupling. FIG. 13 illustrates the effect of floating gate coupling on a memory cell programmed according to the process of FIGS. 12A-12C and an exemplary read reference voltage used to compensate for floating gate coupling. FIG. 6 illustrates a programming and reading technique according to one embodiment and a threshold voltage distribution for a group of memory cells programmed according to the programming technique. 6 is a flowchart describing one embodiment of a process for programming non-volatile memory to create a larger margin during a selected memory state. 6 is a flowchart describing one embodiment of a process for verifying programming of a non-volatile memory to create a larger margin during a selected memory state. 3 is a flowchart illustrating one embodiment of a process for reading non-volatile memory. 6 is a flowchart illustrating one embodiment of a process for reading upper page data from a non-volatile memory cell. 6 is a flowchart illustrating one embodiment of a process for reading data without using compensation. 6 is a flow chart describing one embodiment of a process for reading data using floating gate coupling compensation. 6 is a flow chart describing one embodiment of a process for reading upper page data using floating gate coupling compensation.

  FIG. 4 is a block diagram of one embodiment of a flash memory system that can be used to implement one or more embodiments of the present disclosure. Other systems and implementations can also be used. The memory cell array 302 is controlled by a column control unit 304, a row control unit 306, a c source control unit 310, and a p well control unit 308. The column controller 304 reads data stored in the memory cell, determines the state of the memory cell during a program operation, and controls the potential level of the bit line that promotes or inhibits programming and erasing. Are connected to the bit lines of the memory cell array 302. The row controller 306 selects a word line, applies a read voltage, applies a program voltage combined with a bit line potential level controlled by the column controller 304, and applies an erase voltage. Connected to the word line. The c source control unit 310 controls the shared source connected to the memory cell. The p well controller 308 controls the p well voltage.

  Data stored in the memory cell is read by the column control unit 304 and output to the external I / O line via the data input / output buffer 312. Program data stored in the memory cell is input to the data input / output buffer 312 via the external I / O line and transferred to the column control unit 304. The external I / O line is connected to the control unit 318.

  The column controller 304 may include a plurality of detection blocks 320 each associated with one or more bit lines that perform a sensing operation. For example, a single detection block may be associated with 8 bit lines and may include one common portion and 8 separate detection modules for individual bit lines. For details, see US Patent Application No. 11 / 026,536, filed December 29, 2004, “Non-Volatile Memory & Method with Shared Processing for an Aggregate of Sense Amplifiers”. The entirety of this application is incorporated herein by reference. The detection module 320 determines whether the conduction current or other parameter of the connected bit line is above or below a predetermined threshold level. The detection module can determine the data stored in the detected memory cell and store the determined data in the data latch stack 322. Data latch stack 322 is used to store data bits that are determined during a read operation. Data latch stack 322 is also used to store data bits that are programmed into memory during a program operation. In one embodiment, the data latch stack 322 of each detection module 320 includes three data latches. The detection module may also include a bit line latch that is used to set a voltage state on the connected bit line. For example, according to a predetermined state latched by the bit line latch, the connected bit line is pulled to a state (for example, Vdd) designating program prohibition.

  Command data for controlling the flash memory device is input to the control unit 318. The command data notifies the flash memory which operation is requested. Input commands are forwarded to a state machine 316 that is part of the control circuit 315. The state machine 316 controls the column controller 304, the row controller 306, the c source controller 310, the p-well controller 308, and the data input / output buffer 312. The state machine 316 can also output flash memory state data such as READY / BUSY or PASS / FAIL.

  The control unit 318 is connected to or connectable to a host system such as a personal computer, a digital camera, or a personal digital assistant. The controller 318 communicates with a host that initiates commands to store or read data from the memory array 302 and to provide or receive such data. The control unit 318 converts such a command into a command signal that can be read and executed by the instruction circuit 314 that is a part of the control circuit 315. Command circuit 314 is in communication with state machine 316. In general, the control unit 318 includes a buffer memory for user data to be written to or read from the memory array.

  One exemplary memory system includes an integrated circuit with a controller 318, one or more integrated circuit chips, each with controls associated with the memory array, and input / output state machine circuits. ing. The memory array and system controller circuitry are often mounted together on one or more integrated circuit chips. The memory system may be incorporated as part of the host system, or may be incorporated in a memory card (or other package) that is removably inserted into the host system. Such a card may include an entire memory system (eg, including a controller) or a memory array (or controllers) with associated peripheral circuitry (a controller or control function incorporated within a host). You may have. Therefore, the control unit can be incorporated in the host or mounted in a removable memory system.

  FIG. 5 shows an example of the structure of the memory cell array 302. As an example, a NAND flash EEPROM divided into 1024 blocks will be described. Data stored in each block can be erased simultaneously. In one embodiment, a block is the smallest unit of cells that are simultaneously erased. The memory cell is erased by raising the p-well to an erase voltage (eg, 20 volts) and grounding the word line of the selected block. The source line and bit line are floating. Erasing can be performed on the entire memory array, separate blocks, or another unit of cells. Electrons move from the floating gate to the p-well region and (in one embodiment) the threshold voltage becomes negative.

  Each block in the example of FIG. 5 has 8,512 columns. Each block is usually divided into a number of pages that can be a unit of programming. Other units of data for programming are possible and are contemplated. In one embodiment, individual pages are divided into segments, which may include the minimum number of cells that are written at one time as a basic programming operation. One or more pages of data are typically stored in a row of memory cells.

  In each block in the example of FIG. 5, there are 8,512 columns divided into even columns and odd columns. The bit lines are divided into even bit lines (BLe) and odd bit lines (BLo). In an odd / even bit line architecture, memory cells along a common word line and connected to an odd bit line are programmed at a time. On the other hand, the memory cells along the common word line and connected to the even bit lines are programmed at another time. FIG. 5 shows four memory cells connected in series to form a NAND string. Although four cells are shown to be included in each NAND string, more or less than four cells may be used (eg, 16, 32 or other numbers). One terminal of the NAND string is connected to the corresponding bit line (select gate drain line SGD) via the first select transistor or gate. Another terminal is connected to the c source (selection gate source line SGS) via the second selection transistor.

  In one embodiment, 4,256 memory cells are simultaneously selected during read and programming operations. The selected memory cell has the same word line (for example, WL2) and the same type of bit line (for example, even bit line). Therefore, 532 bytes of data can be read or programmed simultaneously. These 532 bytes of data that are read or programmed at the same time form a logical page. Thus, in this example, one block can store at least 8 pages. If each memory cell stores 2 bits of data (eg, a multi-state cell), such a block can store 16 pages (ie, for example, each of the 8 pages contains 1064 bytes). Other sized blocks and pages can also be used as embodiments. In one embodiment, a set of simultaneously selected memory cells can store multiple pages of data.

  Architectures other than FIGS. 4 and 5 can be used in accordance with embodiments. In one embodiment, the bit lines are not divided into even bit lines and odd bit lines. Such an architecture is commonly referred to as an all bit line architecture. In an all bit line architecture, all the bit lines of a block are selected simultaneously between a read operation and a program operation. Memory cells along a common word line and connected to any bit line are programmed simultaneously. Details regarding various bit line architectures and associated manipulation techniques are described in US patent application Ser. No. 11 / 099,133, filed Apr. 5, 2005, “Compensating for coupling during Read,” which is incorporated herein by reference. It is disclosed in “Operations of Non-Volatile Memory”.

  In a read and verify operation, the select gate of the selected block is raised to one or more select voltages, while unselected word lines (eg, WL0, WL1, WL3) of the selected block are read paths. Raised to a voltage (eg, 4.5 volts), causing the transistor to operate as a pass gate. A selected word line (eg, WL2) of the selected block is connected to a reference voltage. This reference voltage level is specified for each read and verify operation to determine whether the threshold voltage of the corresponding memory cell is higher or lower than this level. For example, in a read operation of a 1-bit memory cell, the selected word line WL2 is grounded so that it can be detected whether or not the threshold voltage is higher than 0V. In the verify operation of the 1-bit memory cell, for example, the selected word line WL2 is connected to 0.8V as the programming progresses to verify whether or not the threshold voltage has reached 0.8V. The source and p-well are at 0V during read and verify. The selected bit line (BLe) is precharged to a level of 0.7V, for example. If the threshold voltage is higher than the read or verify level, the potential level of the corresponding bit line (BLe) is kept high for the associated non-conductive memory cell. On the other hand, when the threshold voltage is lower than the read or verify level, the potential level of the corresponding bit line (BLe) decreases to a low level of, for example, 0.5 V or less due to the conductive memory cell. Is done. Other current and voltage sensing techniques can be used according to embodiments. During reading or detection for multi-state cells, state machine 316 passes through a variety of predetermined control gate reference voltages that correspond to a variety of memory states. The detection module trips on one of the voltages and an output is provided from the detection module. The processor in the detection module can determine the resulting memory state by examining information about the trip event (s) and the control gate voltage applied from the state machine. A binary encoding for the memory state is calculated and stored in the data latch.

  During program and verify operations, data programmed into a set of cells can be stored in a set of data latches 322 for each bit line. The control gate of the addressed memory cell receives a series of programming pulses as it grows, while the drain and p-well of the memory receive 0V. In one embodiment, the magnitude of the pulses in the series ranges from 12V to 24V. In other embodiments, the range may be different, eg, having a starting level higher than 12V. During programming, a verify operation is performed between programming pulses. The program level of each cell programmed in parallel is read between each programming pulse to determine if it has reached or exceeded the verification level for the state being programmed. . The verification level may be the target minimum threshold voltage for the cell in the corresponding memory state. One means of verifying programming is to test continuity at special comparison points. Cells that are verified to be fully programmed are locked out to prevent additional programming. The voltage on the verify cell bit line is raised from 0V to Vdd (eg, 2.5 volts) during subsequent programming pulses, ending the programming process for those cells. In some cases, the number of pulses is limited (eg, 20 pulses) and an error is assumed if a given memory cell is not fully programmed by the last pulse.

  FIG. 6 shows the program voltage signal in one embodiment. This signal has a set of pulses that rise. The magnitude of the pulse increases by a predetermined step size with each pulse. In one embodiment with memory cells that store multiple bits of data, for example, the step size is 0.2 volts (or 0.4 volts). There is a verify pulse between each program pulse. Since the signal in FIG. 6 assumes a memory cell in four states, it has three verification pulses. For example, there are three consecutive verify pulses between the programming pulse 330 and the programming pulse 332. The first verify pulse 334 is shown as a verify voltage level of 0 volts. After the first verification pulse, there is a second verification pulse 336 at a second verification voltage level. After the second verification pulse 336, there is a third verification pulse 338 at a third verification voltage level. Multi-state memory cells that can store data in 8 states need to perform verify operations on 7 comparison points. Therefore, seven verification pulses are applied in succession between two consecutive programming pulses, and seven verification operations are performed at seven verification levels. Based on the seven verify operations, the system can determine the state of the memory cell. One way to reduce the time burden required for verification is to use a more efficient verification process. This is the case, for example, in US Patent Application No. 10 / 314,055 filed Dec. 5, 2002, “Smart Verify for Multi-State Memories”, US Patent Application No. 799, "Method for Programming of Multi-State Non-Volatile Memory Using Smart Verify", and US Patent Application No. 11 / 260,658, filed October 27, 2005, "Apparatus for Programming of Multi-State Non -Volatile Memory Using Smart Verify ". All of which are incorporated herein by reference.

  The above-described erase, read, and verify operations are performed according to known techniques. As such, many of the details described can be varied by one skilled in the art.

  At the end of a successful programming process, the threshold voltage of the memory cell is within one or more distributions of threshold voltages for the programmed memory cells, or within the distribution of threshold voltages of the erased memory cells as needed. Must be. FIG. 7 shows a threshold voltage distribution of a group of memory cells when each memory cell stores 2-bit data. FIG. 7 shows a first threshold voltage distribution E for erased memory cells and three threshold voltage distributions A, B, and C for programmed memory cells. In one embodiment, the threshold voltage of distribution E is negative and the threshold voltages of distributions A, B, and C are positive.

  Each of the different threshold voltage ranges in FIG. 7 corresponds to a predetermined value of a set of data bits. The special relationship between the data programmed into the memory cell and the threshold voltage level of the cell depends on the data encoding scheme employed for the cell. In one embodiment, data values are placed in the threshold voltage range using Gray code assignment so that only one bit is affected if the floating gate threshold is erroneously shifted to its adjacent physical state. Assigned. However, in other embodiments, Gray code is not used. For example, “11” is the threshold voltage range E (state E), “10” is the threshold voltage range A (state A), “00” is the threshold voltage range B (state B), and “01” is the threshold voltage range C. Assign to (state C). Although FIG. 7 illustrates four states, embodiments of the present disclosure may use other multi-state structures that include more or less than four states.

  FIG. 7 shows three read reference voltages Vra, Vrb and Vrc for reading data from the memory cell. By testing whether the threshold voltage of a given memory cell is higher or lower than Vra, Vrb and Vrc, the system can determine which state the memory cell is in. If the memory cell is conducting at Vra, the memory cell is in state E. If the memory cell conducts at Vrb and Vrc but not at Vra, the memory cell is in state A. If the memory cell conducts at Vrc but not at Vra and Vrb, the memory cell is in state B. If the memory cell is not conducting at Vra, Vrb and Vrc, the memory cell is in state C. FIG. 7 also shows three verification reference voltages Vva, Vvb and Vvc that are equally spaced from each other. When programming memory cells to state A, the system tests whether those memory cells have a threshold voltage greater than or equal to Vva. When the memory cell is programmed to state B, the system tests whether the memory cell has a threshold voltage greater than or equal to Vvb. When programming a memory cell to state C, the system determines whether the memory cell has a threshold voltage greater than or equal to Vvc. The verification voltage defines an assigned threshold voltage range between a specific physical state and a prohibited range. The verification levels are spaced apart to provide sufficient margin between the highest threshold voltage in one state and the lowest threshold voltage in the next state. A larger margin that occurs naturally exists between the erased state E and the first programmed state A.

  FIG. 7 further illustrates full sequence programming. In full sequence programming, the memory cell is programmed directly from erased state E to either programmed state A, B, or C. The population of memory cells to be programmed may be erased first such that all memory cells are in erased state E. A series of program voltage pulses are then applied to the control gate of the selected memory cell to program the memory cell directly into state A, B or C. Some memory cells are programmed from state E to state A, while other memory cells are programmed from state E to state B and / or from state E to state C.

  FIG. 8 shows an example of a two-pass technique for programming a multi-state memory cell that stores data for two different pages (a lower page and an upper page). Four states, state E (11), state A (10), state B (00), and state C (01) are shown. In state E, both pages store “1”. In the state A, the lower page stores “0” and the upper page stores “1”. In state B, both pages store “0”. In the state C, the lower page stores “1” and the upper page stores “0”. Although a specific bit pattern is assigned to each state, a different bit pattern can be assigned. In the first programming path, the threshold voltage level of the cell is set according to the bit programmed into the lower logical page. If the bit is a logic “1”, the threshold voltage is not changed because it is in the proper state as a result of being previously erased. However, if the bit being programmed is a logic “0”, the threshold level of the cell is increased to state A as indicated by arrow 450. It concludes the first programming path.

  In the second programming path, the threshold voltage level of the cell is set according to the bit programmed in the upper logical page. If the upper logical page bit stores a logic “1”, the cell is in one of states E or A depending on the programming of the lower page bit, both of which hold the “1” so the programming is Does not occur. If the upper page bit is a logic “0”, the threshold voltage is shifted. If the cell remains in erased state E by the first path, the cell is programmed in the second stage and the threshold voltage is increased to be in state C as indicated by arrow 454. If the cell is programmed in state A as a result of the first programming path, the memory cell is further programmed in the second path and the threshold voltage is increased to be in state B as indicated by arrow 452. . The result of the second path is to program the cell to a state that is designated to store logic “0” for the upper page without changing the data for the lower page.

  In one embodiment, if enough data is written to fill the entire page, the system is set to perform a full sequence write. If insufficient data has been written for all pages, the programming process can program the lower page with the received data. When the next data is received, the system programs the upper page. In yet another embodiment, the system starts writing data using a two-pass technique, and then enough data is subsequently received to fill the entire (or most) word line memory cells. Can be converted to full sequence programming mode. Further details of such an embodiment can be found in US Patent Application No. 11 / 013,125, “Pipelined Programming of Non-Volatile Memories Using Early Data”, inventors Sergy Anatolievich Gorobets and Yan Li, filing date December 14, 2004. Disclosed in the day. The entirety of which is incorporated herein by reference.

  Floating gate coupling can cause unrecoverable errors during read operations that may require performing error recovery during read. The charge stored on the floating gate of a memory cell may experience an apparent shift due to electric field coupling from the charge stored on the floating gate of an adjacent memory cell or other charge storage region (eg, a dielectric charge storage region). is there. In theory, the electric field from the charge on the floating gates of the memory cells in the memory array can be coupled to the floating gates of other memory cells in the array. On the other hand, the influence is most noticeable and noticeable in the adjacent memory cells. Adjacent memory cells are adjacent memory cells that are on the same bit line, adjacent memory cells that are on the same word line, or both adjacent bit lines and adjacent word lines, and therefore adjacent to each other diagonally Memory cells may be included. The apparent shift of charge can cause errors when reading the memory state of the memory cell.

  The effect of floating gate coupling is most noticeable in situations where a memory cell adjacent to the target memory cell is programmed following the target memory cell, but the effect may also be seen in other situations. The charge, or part of the charge, applied on the floating gate of the adjacent memory cell is effectively coupled to the target memory cell through electric field coupling, causing an apparent shift in the threshold voltage of the target memory cell. The apparent threshold voltage of the memory cell is turned on and off under the applied reference read reference voltage as programmed, after it is expected for the memory cell in the memory state that it was intended to be programmed. It can be shifted to such an extent that it does not conduct.

  Normally, a row of memory cells is programmed starting with the word line (WL0) adjacent to the source side select gate line. The programming is performed on the word line (WLn + 1) so that at least one page of data is programmed on the adjacent word line (WLn + 1) after the programming of the preceding word line (WLn) is completed (making each cell of the word line its final state). WL1, WL2, WL3, etc.) then proceed sequentially through the string of cells. This pattern of programming causes an apparent shift in the threshold voltage of the memory cell after it has been programmed due to floating gate coupling. For each word line except the last word line of the programmed string, adjacent word lines are programmed following completion of programming of the word line of interest. A negative charge that is added to the floating gate of a memory cell on an adjacent and later programmed word line raises the apparent threshold voltage of the memory cell on the word line of interest.

  9A-10B illustrate the effect of floating gate coupling on a set of memory cells programmed using full sequence programming as shown in FIG. FIG. 9B shows the threshold voltage distribution of a set of memory cells on the word line WLn selected after being programmed. Distribution 500 shows the actual threshold voltage distribution of cells in WLn in erased (unprogrammed) state E, distribution 505 shows the actual threshold voltage distribution in WLn programmed in state A, and distribution 510 shows the state. B shows the actual threshold voltage distribution of the cell at WLn programmed to B, and distribution 520 shows the actual threshold voltage distribution of the cell at WLn programmed to state C. The set of memory cells may include only each memory cell in a selected row or word line WLn, or only cells in WLn connected to a certain type of bit line (even or odd). FIG. 9A shows the threshold voltage distribution of the memory cells in the adjacent word line WLn + 1 before programming. The WLn + 1 cell is programmed after the WLn cell is programmed. Each cell at WLn + 1 is erased, but since it is not programmed, they do not adversely affect the floating gate coupling on the WLn cells. More importantly, they are in the same state as when WLn was programmed so that the cells of WLn have an apparent threshold voltage equal to the level verified during programming.

FIG. 10A shows the threshold voltage distribution of a set of WL _{n + 1} memory cells after being programmed. The memory cells are programmed to programmed threshold voltage distributions A, B and C from the erased threshold voltage distribution E. The charge applied to the floating gates of the memory cells on word line WL _{n + 1} after programming word line WLn can change the memory state of the memory cells on WL _n as seen by the memory system during detection. The electric field associated with the charge on the floating gate of word line WL _{n + 1} is coupled to the floating gate of the memory cell on word line WL _n . Electric field, causing a shift in the apparent threshold voltage of the memory cell at WL _n.

10B shows a threshold voltage distribution of the apparent memory cells of word line WL _n after programming _{WL n + 1.} Each program state is shown with four different corresponding threshold voltage distributions. The overall distribution for each physical state can be classified into four individual distributions based on the state in which adjacent memory cells on word line WL _{n + 1} are programmed. State A programmed into each memory cell of the word line WL _n having the (same bit on line) WL n + ₁ in the adjacent memory cell will experience a first level of shift in the threshold voltage of the apparent. Each cell in WL _n that has an adjacent cell in state B WL _{n + 1} experiences a second, larger shift in apparent threshold voltage. Each cell with neighboring cells in state C WL _{n + 1} experiences a third, larger shift.

For the WL _n cells in state A, distribution 502 shows the threshold voltages of those cells having adjacent memory cells on word line WL _n−1 that remained in the erased state E after programming. Distribution 504 shows the threshold voltage of cells having adjacent cells on word line WL _{n + 1} programmed to state A. Distribution 506 shows the threshold voltage of cells having adjacent cells on word line WL _{n + 1} programmed to state B. Distribution 508 shows the threshold voltages of memory cells having adjacent cells on word line WL _{n + 1} programmed to state C.

WL _n memory cells programmed to other states will experience similar coupling effects. Thus, the four individual threshold voltage distributions are also shown for state B and state C. A memory cell in word line WL _n programmed to state B has four different threshold voltage distributions 512, 514, 516, and 518 based on the state programmed after the adjacent memory cell in word line WL _{n + 1.} Conceivable. Memory cells programmed WL _n to state C likewise have four different distributions 522, 524, 526 and 528. Binding effect, it should be noted that experienced by the erased memory cells of WL _n. Since the margin that originally occurs between erased state E and state A is sufficient that the shift does not cause an error when reading the erased cell, the shift is not shown. However, there are implications and the disclosed techniques can handle them as well.

An increase in the apparent threshold voltage of the memory cell may cause a read error. As shown in FIG. 10B, some memory cells in WL _n that are initially programmed to state A may shift their threshold voltages beyond the read reference voltage level Vrb. As a result, an error may occur during reading. In the state where the read reference voltage Vrb is applied, these memory cells may not conduct even if they are programmed to state A. The state machine and controller may determine that the memory cell is in state B rather than state A (after not detecting conduction with Vrb applied). Some memory cells in WL _n that are initially programmed to state B may shift beyond the read reference voltage Vrc and cause read errors as well.

FIG. 11 illustrates a read technique that can be used to address some of the apparent shifts in threshold voltage shown in FIG. 10B. In FIG. 11, the four distributions of each state of the cell at WL _n shown in FIG. 10B are summarized in distributions 530, 540, and 550 that represent the cumulative effect of coupling on the population of memory cells. . Distribution 530 represents the cells of WL _n state A after programming the _{WL n + 1,} distribution 540 represents the cells of WL _n state B after programming the _{WL n + 1,} the state after distribution 550 has been programmed to WLn + 1 C represents a cell of WLn. Distribution 530 includes individual distributions 502 to 508, distribution 504 includes individual distributions 512 to 518, and distribution 550 includes individual distributions 522 to 528.

When reading the data on the word line WL _n, the data on the word line WL _{n + 1} can also be read. When the word line WL n _{+ 1} of the data is inhibited data WL _n, read process for WL _n is able to compensate for the inhibition. For example, when reading word line WL _n, state or charge level information of the word line WL n _{+ 1} of the memory cell can be determined to select appropriate read reference voltages for reading individual memory cells of word line WL _n . FIG. 11 shows individual read reference voltages for reading WL _n based on the state of adjacent memory cells on word line WL _{n + 1} . In general, various offsets (eg, 0V, 0.1V, 0.2V, 0.3V) with respect to the nominal read reference voltage are used, and the result detected at another offset is the result of the memory cell on the adjacent word line. Selected as a function of state. In one embodiment, the memory cells of word line WL _n are detected using each of the different read reference voltages. In the case of a predetermined memory cell, the result of detection at the appropriate one of the read reference voltages can be selected based on the state of the adjacent memory cell on word line WL _{n + 1} . In some embodiments, the read operation for WL _{n + 1} determines the actual data stored at WLn + 1. On the other hand, in other embodiments, the read operation for WL _{n + 1} only determines the charge level of these cells and may or may not accurately reflect the data stored in WL _{n + 1} . In some embodiments, the level and / or number of levels used to read WL _{n + 1} may not be exactly the same as that used to read WL _n . The WL _n correction purposes in some implementations, may be sufficient for some approximation of the floating gate threshold. In one embodiment, the result of reading WLn + 1 can be stored in a latch 322 for each bit line used when reading WLn.

A read operation can initially be performed for the word line WLn of interest for nominal read reference voltage levels Vra, Vrb and Vrc that do not compensate for coupling effects. The result read at the nominal reference level is stored in the appropriate latch for the bit line in the memory cell in which the neighboring cell of WLn + 1 is determined to be in state E. For the other bit lines, the data is ignored and WLn + 1 data is maintained. A read operation is then performed on the word line WLn using a first set of offsets relative to the read reference voltage. The read process can use Vra1 (Vra + 0.1V), Vrb1 (Vrb + 0.1V), and Vrc1 (Vrc + 0.1V). The result of using these reference values is stored for the bit line of the memory cell having an adjacent memory cell in state A WL _{n + 1} . Next, a read operation is performed with a second set of offsets using read reference levels Vra2 (Vra + 0.2V), Vrb2 (Vrb + 0.2V) and Vrc2 (Vrc + 0.2V). The result is stored in the bit line latch in the memory cell near WL _{n + 1} in state B. Read operation, the reference level Vra3 (Vra + 0.3V), Vrb3 (Vrb + 0.3V), and using Vrc3 (Vrc + 0.3V) is performed for the word line WL _n in the third set of offsets, the result is , Stored in state C WL _{n + 1} for those bit lines with adjacent cells and memory cells. In some embodiments, no offset is used in Vra because of the larger native margin between state E and state A. Such an embodiment is illustrated in FIG. 11 where a single read reference voltage Vra is shown at the state A level. Other embodiments may use an offset for this level as well.

Various offsets relative to the nominal read reference voltage can be selected as a function of the state of the memory cells on adjacent word lines. For example, the set of offset values may be 0V offset corresponding to state E neighbor cells, 0.1V offset corresponding to state A neighbor cells, 0.2V offset corresponding to state B neighbor cells, and state C neighbors. Includes a 0.3V offset corresponding to the cell. The offset value varies according to the implementation. In one embodiment, the offset value is equal to the apparent threshold voltage shift amount resulting from neighboring cells being programmed to the corresponding state. For example, 0.3V, when the neighboring cells of _{WL n + 1} is programmed to then state C, the may represent a shift in the apparent threshold voltage of the cell of WL _n. The offset value need not be the same for every reference voltage. For example, the offset value of the Vrb reference voltage may be 0V, 0.1V, 0.2V, and 0.3V. On the other hand, the offset value of the Vrc reference voltage may be 0V, 0.15V, 0.25V and 0.35V. Furthermore, the increment in offset need not be equal in every state. For example, the set of offsets in one embodiment may include 0V, 0.1V, 0.3V, and 0.4V for neighboring cells in states E, A, B, and C, respectively.

  In one embodiment, the effect of floating gate charge coupling can be expected to be reduced by about 50 percent by reading at a plurality of individual read reference levels in a predetermined state and selecting the result based on the state of the adjacent memory cell. . The threshold voltage distribution of the word line of the memory cell as read by the detection module can be effectively narrowed by about 50 percent using these techniques.

  The programming process for non-volatile memory can be structured to reduce the apparent shift in threshold voltage from floating gate coupling. 12A-12C illustrate non-volatile memory that reduces coupling between floating gates for a particular memory cell by writing to that particular memory cell for a particular page following a write to a memory cell adjacent to the previous page. The process of programming is disclosed. In the example of FIGS. 12A-12C, each cell uses two data states to store 2 bits of data per memory cell. The erase state E stores data 11, state A stores data 01, state B stores data 10, and state C stores data 00. Other encodings of data into physical data states can also be used. Each memory cell stores a portion of two logical pages of data. For reference, these pages are called the upper and lower pages, but other labels may be given. State A is encoded to store bit 0 for the upper page and bit 1 for the lower page. State B is encoded to store bit 1 for the upper page and bit 0 for the lower page. State C is encoded to store bit 0 for both pages. The lower page data for the memory cells in word line WLn is programmed in the first step shown in FIG. 12A, and the upper page data for the cell is programmed in the second step shown in FIG. 12C. If the lower page data must remain at data 1 for a particular cell, the cell's threshold voltage remains in state E during the first step. If the data has to be programmed to 0, the threshold voltage of the memory cell goes up to state B '. The state B ′ is a provisional state B having a verification level Vvb ′ lower than Vvb.

In one embodiment, after the lower page data of a memory cell is programmed, the adjacent memory cell of adjacent word line WL _{n + 1} is programmed for that lower page. For example, the lower page of the memory cell at WL2 in FIG. 3 may be programmed after the lower page for the memory cell at WL1. If the threshold voltage of memory cell 224 increases from state E to state B ′ after programming memory cell 226, floating gate coupling may increase the apparent threshold voltage of memory cell 226. The cumulative coupling effect of WLn on the memory cell broadens the apparent threshold voltage distribution of the cell threshold voltage, as shown in FIG. 12B. The apparent expansion of the threshold voltage distribution can be corrected when programming the upper page of the word line of interest.

  FIG. 12C shows the process of programming the upper page of WLn cells. If a memory cell is in erased state E and its upper page bit must remain at 1, the memory cell remains in state E. If a memory cell is in state E and its upper page data bit must be programmed to 0, the memory cell's threshold voltage is raised until it is within state A. If the memory cell is in the intermediate threshold voltage distribution B 'and its upper page data must remain at 1, the memory cell is programmed to the final state B. If the memory cell is in the middle threshold voltage distribution B 'and its upper page data must be data 0, the threshold voltage of the memory cell is raised to be within state C. The process illustrated by FIGS. 12A-12C reduces the effects of floating gate coupling, because only the upper page programming of neighboring memory cells achieves the apparent threshold voltage of a given memory cell. An example of alternating coding for this technique is to move from intermediate state B ′ to state C when upper page data is 1, and to state B when upper page data is “0”. . Although FIGS. 12A-12C show examples for four data states and two pages of data, the concepts taught by FIGS. 12A-12C can be applied to other implementations with more or less than four states and different page numbers. .

  FIG. 13A illustrates the effect of floating gate coupling on the programming techniques of FIGS. 12A-12C. FIG. 13B shows a readout method that uses compensation offsets to overcome some of these effects. The memory cells on word line WLn + 1 adjacent to word line WLn are programmed during the second pass to program its upper page data as shown in FIG. 12C. During this second pass, the memory cell is programmed either from state E to state A or from intermediate state B 'to state B or state C. The word line memory cells of WLn of interest are shown in FIG. 13A and are programmed to the upper page after the lower page of memory cells of word line WLn + 1 is programmed. Thus, the upper page programming depicted in FIG. 12C is the only programming to affect the apparent threshold voltage of the memory cells in word line WLn.

  A memory cell on word line WLn + 1 programmed from state E to state A experiences a similar change in threshold voltage as a cell programmed from intermediate state B 'to state C. The memory cells in adjacent word line WLn + 1 programmed from intermediate state B 'to state B do not experience a significant increase in threshold voltage and have little effect on the apparent threshold voltage of the WLn cell. The memory cells in WLn that are programmed to state A are represented by individual distributions 652, 654, 656, and 658 that correspond to cells having neighboring cells in WLn + 1 in state E, state B, state A, and state C, respectively. The memory cells in WLn that are programmed to state B are represented by individual distributions 662, 664, 666, and 668 corresponding to the cells in state B that have neighboring cells in WLn + 1 in state E, state B, state A, and state C, respectively. expressed. WLn memory cells programmed to state C are represented by individual distributions 672, 674, 676, and 678 corresponding to state C cells that have neighboring cells in state E, state B, state A, and WLn + 1 of state C, respectively. expressed.

  As shown in FIG. 13A, some memory cells in WLn may shift their apparent threshold voltages close to or beyond the read reference voltage Vrb or Vrc. . This can cause read errors. As described above, the described coupling effects are applicable to the erase distribution of WLn, and the disclosed technique is equally applicable to it. The effect on the erased cell will not be mainly described because it is the natural margin between state E and state C.

  FIG. 13B illustrates a read reference level offset that can be used with the programming techniques of FIGS. 12A-12C. For clarity, distributions 652, 654, 656, and 658 are shown in a single combined distribution 651, distributions 662, 664, 666, and 668 are shown in a combined distribution 661, and distributions 672, 674, 676 and 678 are shown in the combined distribution 671. Distributions 650, 660, and 670 represent WLn cells prior to programming the upper page data with WLn + 1. In the embodiment of FIG. 13B, similar effects of coupling from cells on adjacent word lines programmed to state A or state C are grouped together to form a single offset for each of these state levels. The result of detection at the offset reference voltages Vrb1 and Vrc1 is used for a memory cell having an adjacent cell on the word line WLn + 1 in the state A or the state C. Minor coupling effects resulting from programming from intermediate state B 'to state B are ignored. The result of detection when using the nominal reference voltages Vrb and Vrc is used for memory cells that have adjacent cells in the state E or state B word line WLn + 1. Additional offsets for each particular state of WLn + 1 can be used in one embodiment. Although the technique shown in FIG. 13B provides an additional reduction in the effects of floating gate coupling, errors may still exist.

The misreading of adjacent word lines when trying to determine the proper offset for reading the cell of interest has actually proved even more problematic for cells programmed with the techniques of FIGS. 12A-12C. There is a case. Consider the misreading of the memory cells in the word line WL _{n + 1} when the state B read reference voltage vrb is applied. When a memory cell at WLn + 1 is programmed to state A and misread as being in state B, the result of the corresponding memory cell read operation on word line WLn using the nominal read reference voltage is selected and reported. The WLn + 1 cell is in state B, so floating gate coupling compensation is not used because it is determined that it has only experienced minor changes in threshold voltage after programming WLn. In practice, however, the memory cell at WLn + 1 may have a strong effect on the apparent threshold voltage of the WLn cell. It is likely that the WLn + 1 cell is at the top of the state A distribution, which is why it was misread. Thus, a WLn + 1 memory cell experiences a large change in charge at its floating gate when programmed from state E to the top of state A. The large change in charge stored by the WLn + 1 cell causes a significant shift in the apparent threshold voltage of the WLn cell. However, this shift compensation is not used due to misreading at WLn + 1. Therefore, it is conceivable that the memory cell of WLn is misread as a result of misreading of WLn + 1, or the possibility is high.

  A similar problem may occur if an adjacent memory cell of word line WLn + 1 programmed to state B is misread as being in state A. In fact, the memory cell on word line WLn + 1 that is read as being in state A when it is in state B may have a threshold voltage at the lower end of the state B distribution. The memory cell will experience little change in threshold voltage after programming WLn + 1 memory cells. As a result, little or no apparent threshold voltage shift of the corresponding cell in WLn occurs. However, the result of the read operation at WLn of the corresponding memory cell selects the result of read at the compensation reference level. The memory cell of interest does not experience a significant shift in the apparent threshold voltage, so selecting a result when the compensation reference level is used can cause misreading or errors in WLn.

  In the prior art, programming memory cells in various programming states has been performed at equally spaced verification levels as shown in FIGS. 13A-13B. That is, since the verification levels for state A, state B, and state C are equally spaced from each other, the voltage difference between verification levels Vvb and Vva is equal to the voltage difference between verification levels Vvc and Vvb. The equal spacing of the programming verification levels results in a margin between various program states that are the same or substantially equal. The margin corresponds to the forbidden voltage range between physical states. The margin between state A and state B is determined by the maximum threshold voltage of the memory cell in state A and the minimum threshold voltage of the memory cell in state B. Sufficient margin is provided between program states so that an accurate read can be performed. Due to the floating gate coupling, the margin between physical states is reduced, which may cause read errors.

  In accordance with one embodiment of the present disclosure, shifted verification when programming one or more selected states, such as state B, to create a larger margin between specific states for improved detection accuracy Level is used. In one embodiment, the offset compensated read reference level is not used at a level corresponding to a wider margin, but is used at other levels to provide a more efficient read for higher performance. Combining a wider margin between selected physical states and selective application of an offset reference level provides an accurate sensing technique while maintaining a desired level of performance. FIG. 14 illustrates a threshold voltage distribution for a set of memory cells programmed according to one embodiment of the present disclosure. Distributions 678, 680, 684 and 688 show the set of memory cells after being programmed but before programming the cells in adjacent word line WLn + 1.

  The shifted program verify level Vvb1 is used in FIG. 14 when programming the memory cell to state B. The embodiment of FIG. 14 may be used when programming according to the techniques shown in FIGS. 12A-12C. The verification level Vvb1 is higher than the verification level of Vvb in the conventional operation shown in FIG. 12C so that a larger margin is created between the state A and the state B. The highest threshold voltage of any memory cell in state A remains the same as in conventional techniques. However, the lowest threshold voltage of any cell in state B is shifted in the positive direction. An increase in verification level when programming a memory cell to state B increases the margin between state A and state B. As shown in FIG. 14, the margin 683 between states A and B is larger than the margin 685 between states B and C. As a result, the possibility of misreading during detection at the state B reference voltage level Vrb is lower.

  Distributions 682, 686, and 690 show the effect of floating gate coupling after adjacent wordline WLn + 1 is programmed (eg, as shown in FIG. 12C). In FIG. 14, the Vrb read level is sufficiently separated between the apparent A state distribution 682 and the apparent B state distribution 686. As a result, even after considering the effect of coupling from adjacent word lines, the Vrb read level does not overlap with the threshold voltage of any cell that is intended to be in state A, so there is a low probability of misreading. In one embodiment, the reference level Vrb is shifted from the conventional usage level (Vrb in FIG. 12) by an amount corresponding to the shift of the program verification level Vvb1 from its nominal value Vvb shown in FIG. 12C. Since Vrb is shifted well beyond the highest threshold voltage of any memory cell in state A, a single reference value Vrb can be used during the read and no compensation can be applied.

  Thus, in one embodiment, the read reference voltage offset is not used when reading at state B level. In the embodiment of FIG. 14, the offset relative to the read reference voltage is used only for the highest state, state C. The larger margin that exists between state A and state B due to the effect of the higher verify level allows accurate reading at state B level without directly compensating for floating gate coupling. This technique not only reduces misreading, but also improves read time because additional reading at the offset level is used only in the selected state. In FIG. 14, only one additional detection operation is performed. In addition to improving performance and read time, the reduced number of sensing operations requires the complexity of the cache circuitry required to maintain data with respect to adjacent memory cells when sensing a selected memory cell. Reduce degree and size.

  By way of non-limiting example, the following read reference levels and program verification levels can be used as an embodiment when implementing the technique of FIG. In the prior art techniques as illustrated in FIGS. 12A-12C, the margin between state A and state B in one exemplary system is approximately 0.7V, and the margin between state B and state C. Is expected to be almost the same. In such a prior art system, Vva = 0.5V, Vvb = 2.0V, Vvc = 3.5V, Vra = 0.V when programming data in the cell or reading data from the cell. Verification levels and read levels of 0V, Vrb = 1.5V and Vrc = 3.0V are used. However, such a system of FIG. 14 has a margin of about 0.7V between state A and state B and about 0. It will have a margin of 1V. To achieve these margins, typical read reference levels and program verification levels that can be used in FIG. 14 are: Vva = 0.5V, Vvb = 2.3V, Vvc = 3.5V, Vra = 0.0V, Vrb = 1.8V, Vrc = 3.0V and Vrc1 = 3.6V may be included. In one embodiment as shown, the difference between the read reference level and the program verify level in each state remains the same as when Vvb is shifted because Vrb is shifted the same amount. Therefore, Vva-Vra = Vvb-Vrb = Vvc-Vrc.

  FIG. 15 is a flow chart describing one embodiment of a method for programming non-volatile memory to achieve a non-uniformly sized margin as shown in FIG. The programming method shown in FIG. 15 can be used to simultaneously program a group of memory cells, such as memory cells connected to a single word line. FIG. 15 can also be used to program selected memory cells in a word line, such as in an odd / even bit line architecture. In one embodiment, the first set of iterations from step 860 to step 882 is used to program the first logical page of the group of memory cells. The second iteration of steps 860 through 882 can be used to program a second logical page of the group of memory cells.

  The memory cell to be programmed is erased at step 850. Step 850 may include erasing more memory cells than programmed memory cells (eg, in blocks or other units). In step 852, soft programming is performed to narrow the distribution of erased threshold voltages for erased memory cells. Some memory cells may be in an erased state that is deeper than necessary as a result of the erase process. Soft programming can apply a small programming pulse to bring the threshold voltage of the erased memory cell closer to the erase verify level. This gives a narrower distribution for erased memory cells. In step 854, a data load command is issued by the controller 318 and input to the instruction circuit 314 so that data can be input to the data input / output buffer 312. Input data is recognized as a command and latched by the state machine 316 via a command latch signal (not shown) input to the instruction circuit 314. In step 856, address data designating a page address is input from the host to the row control unit 306. Input data is recognized as a page address and is latched through a state machine 316 which is accomplished by an address latch signal input to the instruction circuit 314. In step 858, the page of program data for the addressed page is input to data input / output buffer 312 for programming. For example, 532 bytes of data can be input as one exemplary embodiment. The input data is latched in the appropriate register for the selected bit line. In some embodiments, data is also latched in the second register for the selected bit line used for the verify operation. In step 860, a program command is issued by the control unit and input to the data input / output buffer 312. The command is latched by the state machine 316 via a command latch signal input to the instruction circuit 314.

The data triggered by the program command and latched in step 858 is programmed into the selected memory cell controlled by state machine 316. Using a step program voltage pulse, such as that shown in the program voltage signal of FIG. 6, the program voltage signal is applied to the appropriate word line corresponding to the page or other unit of the cell being programmed. . In step 862, Vpgm, the programming pulse voltage level, is initialized to the start pulse (eg, 12V) and the program counter PC maintained by the state machine 316 is initialized to zero. In step 864, a first Vpgm pulse is applied to the selected word line. If a logic zero is stored in a particular data latch indicating that the corresponding memory cell needs to be programmed, the corresponding bit line is grounded. On the other hand, if a logic 1 is stored in a particular latch, indicating that the corresponding memory cell needs to be maintained in its current data state, the corresponding bit line is set to V _DD to inhibit programming. Connected.

  In step 866, the state of the selected memory cell is verified. The process shown in FIG. 15 has so far proceeded according to well-known techniques. However, at step 866, the process includes a new technique that creates an unevenly spaced margin that facilitates more accurate reading of the selection level. A larger margin is created between the two programmed states. In one embodiment, the highest state remains in its nominal position, while a larger margin is created during the lower level state. In one embodiment, verification is performed such that a larger margin exists between states B and A. Also, in other embodiments, the highest level state or higher level state may be shifted in the positive direction by using a larger verify voltage at those levels. However, shifting the distribution to an overall higher positive voltage may result in some implementations where the voltage level (eg, Vpgm) should be kept at a certain maximum level, such as to minimize program disturbances etc. Then it is unacceptable.

  In one embodiment, the unevenly spaced verification levels are used at step 866 to create an uneven margin. As shown in FIG. 14, the verification level Vvb1 for the second program state B is separated from the verification level of the second program state (state B) in the third program state (state C). Is separated from the first program state (state A) by an amount different from the first amount. Verification levels Vva, Vvb, and Vvc define the lowest minimum threshold voltage for their particular state. By using non-uniformly spaced verification levels, the margin created between state A and state B is greater than the margin created between state B and state C.

After sensing with the applied reference voltage, in step 868, all of the data latches are checked to see if they are storing a logic one. When storing a logic one, the programming process is complete and successful because all selected memory cells have been programmed and verified against their target state. Pass status is reported at step 876. If it is determined in step 868 that not all of the data latches are storing logic ones, the process continues in step 872 where the program counter PC is checked against the program limit value. An example program limit value is 20, although other values may be used in various embodiments. If the program counter PC is greater than or equal to 20, it is determined in step 874 whether or not the number of memory cells that have not been successfully programmed is less than or equal to a predetermined number. If the number of cells that have not been successfully programmed is less than or equal to a predetermined number, the process is flagged as passing and a passing status is reported at step 876. Bits that were not successfully programmed can be corrected using error correction during the read process. If the number of successfully programmed memory cells is greater than a predetermined number, the programming process is flagged as failing and a failing status is reported at step 878. If the program counter PC is less than 20, the V _pgm level is increased by the step size, and the program counter PC is increased at step 880. After step 880, the process loops back to step 864 to apply the next V _pgm pulse.

  As described, step 866 includes using non-uniformly spaced verification levels such that there are non-uniformly spaced margins for programmed memory cells. FIG. 16 illustrates one embodiment of step 866 of FIG. In step 882, the first program state verification level Vva is applied. In step 884, the bit lines are detected with Vva applied to the memory cells of each bit line. In step 886, the result of the cell to be programmed to state A is stored. In step 886, the data latch for the bit line can be set to logic 1 to indicate that programming must continue for that memory cell. Alternatively, in step 886, the data latch for the bit line is set to logic 0 to indicate that the memory cell is at or above its target level and programming of the memory cell needs to be stopped. Can do. In step 888, the second program state verification level Vvb1 is applied to each memory cell being verified. The verification level Vvb1 is separated from the verification level Vva by a first amount. For example, Vva and Vvb1 can be separated from each other by an amount equal to about 0.8V. In step 890, the bit line is detected with Vvb1 applied to each memory cell. The result is stored in 892 by indicating whether the memory cell corresponding to the data latch for each bit line has reached its target level. In step 894, a third verification level Vvc is applied for the third program state. The verification level Vvc is separated from the verification level Vvb1 by a second amount different from the first amount that separates Vva and Vvb1. As shown in FIG. 14, the interval between the verification levels Vvb1 and Vvc is smaller than the interval between the verification levels Vva and Vvb1. In step 896, the bit line is detected with Vvc applied to each memory cell. In step 898, the result is stored for the cell to be programmed to state C, for example by indicating in a data latch whether the cell needs to undergo additional programming.

  As shown in boxes 891 and 899, the non-uniformly spaced verification levels result in a first size margin between states A and B and a second size margin between states B and C. Let The margin between states A and B is larger than the margin between states B and C because it is a shifted Vvb verification level.

  FIG. 17 is a flowchart illustrating the overall process of reading data that is performed in response to a request to read a particular page or pages or other groups of data. In other embodiments, the process of FIG. 17 can be programmed as part of a data recovery operation after detecting an error in response to a conventional read process. When reading data programmed according to FIGS. 12A-12C, perturbations from floating gate coupling due to programming of the lower page of adjacent cells are corrected when programming the upper page of the cell of interest. Thus, when attempting to compensate for the effects of floating gate coupling from neighboring cells, the process need only consider coupling effects due to programming of the upper page of the neighboring cell.

  In step 902 of FIG. 17, the upper page data of the word line that is adjacent to the word line of interest and is programmed later is read. In step 904, if the upper page of the adjacent word line is not programmed as determined, the word line or page of interest is read in step 908 without compensating for the effects of floating gate coupling. If the upper page of the adjacent word line is programmed, the page of interest is read using compensation for floating gate coupling effects at step 906. In some embodiments, the charge level on an adjacent word line is determined by reading a cell on the adjacent word line. The charge level may or may not accurately reflect the data stored on the adjacent word line.

  In one embodiment, a set of memory cells is reserved for the memory array to store one or more flags. For example, a column of memory cells can be used to store a flag that indicates whether the lower page of each row of memory cells has been programmed. Another column can be used to store a flag that indicates whether the upper page of each row of memory cells has been programmed. By checking the appropriate flag, it can be determined whether the upper page of the neighboring word line has been programmed. Details about such flags and programming processes are described in US Pat. No. 6,657,891, Shibata et al., “Semiconductor Memory Device For Storing Multi-Valued Data,” which is incorporated by reference in its entirety. Are incorporated herein by reference.

  FIG. 18 illustrates one embodiment of a process for reading the upper page data of an adjacent word line that can be used in step 902 of FIG. At step 910, the read reference voltage Vrc is applied to the word line, and at step 912, the bit line is detected as described above. The result of the detection is stored in the appropriate latch at step 914. Reading first with Vrc is chosen to uniquely determine the upper page data since the lower page data is usually already written to WLn + 1. Since the intermediate distribution B '(FIG. 12B) can overlap these values, reading with Vra or Vrb does not guarantee a unique result.

In step 916, a flag is checked indicating upper page programming associated with the page being read. If in step 918 the flag is not set as determined, then in step 920 the process ends with the conclusion that the upper page is not programmed. If the flag is set, the upper page is assumed to be programmed. In step 922, a read reference voltage Vrb is applied to the word line associated with the page being read. In step 924, the bit line is detected and in step 926, the result is stored in the appropriate latch. In step 928, the read reference voltage Vra is applied. In step 930 the bit line is detected and in step 932 the result is stored in the appropriate latch. In step 934, the data value stored in each of the read memory cells is determined based on the results of detection steps 912, 924, and 930. In step 936, the data value can be stored in an appropriate data latch for final communication to the user. Upper page data and lower page data are determined using well-known logic techniques that depend on the particular state coding selected. For the exemplary coding illustrated in FIGS. 12A-12C, the lower page data is Vrb ^* (the complement of the value stored when reading with Vrb) and the upper page data is Vra ^* OR (Vrb and Vrc). ^* ). Although the process of FIG. 18 is described here as being used to read WL _{n + 1} , it can also be used to read WL _n as described below.

  FIG. 19 is a flowchart illustrating an embodiment of reading data of a word line of interest when compensation for floating gate coupling from adjacent word lines is not required (step 908 of FIG. 17). In step 950, it is determined whether the upper page associated with the word line of interest has been read or the lower page has been read. If the lower page is being read, in step 952, the read reference voltage Vrb is applied to the appropriate word line. In step 954 the bit line is detected and in step 956 the result is stored in the appropriate latch. In step 958, the flag is checked to determine whether the page of interest contains upper page data. If no flag is set, the programmed data is in the intermediate state B '. Therefore, since Vrb does not produce an accurate sensing result, the process continues to step 960 where Vra is applied to the word line. In step 962, the bit line is re-detected and in step 964 the result is stored. In step 966, the stored data value is determined. In one embodiment, when the memory cell is turned on with Vrb (or Vra) applied to the word line, the lower page data is “1”. In other cases, the lower page data is “0”.

  If it is determined in step 950 that the page address matches the upper page, an upper page read process is performed in step 970. In one embodiment, the upper page read in step 970 reads the flag and all three states because an unwritten upper page may be addressed for reading, or for another reason. Including the same method described in FIG.

FIG. 20 is a flowchart describing one embodiment of a process for reading data while compensating for floating gate coupling so that step 906 of FIG. 17 can be performed. Whether an offset is used to compensate for floating gate coupling is determined at step 966. Step 966 is performed separately for each bit line. Data from adjacent word lines is used to determine which bit lines need to use the offset. If the adjacent cell is in state E or B, the memory cell in the word line being read does not require compensation applied during sensing. When the WL _{n + 1} cell is in state E, its threshold voltage was the same as before the word line of interest was written, so it did not facilitate the coupling. When WL _{n + 1} cells are in state B, they are programmed from an intermediate state B ′, which is a small charge change and can be ignored in most situations. The read offset is used for WL _n cells with WL _{n + 1} adjacent memory cells in state A or state C.

  If it is determined in step 967 that the page read is the lower page, Vrb is applied to the word line associated with the page read in step 968. Reading with Vrb is sufficient to determine the lower page data for the encoding shown in FIGS. 12A-12C. In step 969, the bit line is detected and in step 970 the result is stored in the appropriate latch for the bit line. As shown in FIG. 14, step 969 is the only lower page detection performed because no compensation offset is applied at the Vrb level. Since the cell is programmed to create a larger margin between state A and state B, an accurate read can be achieved without compensating for coupling. Lower page data is determined at step 971. When a cell is turned on according to Vrb, its lower page data is 1. Otherwise, the lower page data is zero. In step 972, the lower page data is stored in an appropriate latch for communication to the user.

  If it is determined in step 967 that the page to be read is the upper page, in step 976 the upper page is read using compensation. FIG. 21 is a flowchart for explaining the upper page read using the offset read reference level. In step 974 of FIG. 21, a read reference voltage Vrc is applied to the word line associated with the page being read. In step 975 the bit line is detected and in step 976 the result is stored in the appropriate latch. In step 977, the sum of Vrc and offset (eg, 0.1V) is applied to the word line associated with the page being read. In step 978, a bit line is detected. In step 979, the result of the detection in step 978 is used to overwrite the result stored in step 976 for any bit line that requires an offset. In step 980, Vrb is applied to the word line, and in step 981, the bit line is detected. The result detected in step 981 is stored in step 982. In step 983, Vra is applied to the word line associated with the page being read. In step 984, the bit line is detected and in step 985 the result is stored in the appropriate latch. In FIG. 20, it is assumed that the margin originally generated between state E and state A is sufficient to avoid the need for an offset associated with Vra. In other embodiments, Vra level offsets can be used. In step 986, the data value is determined, and in step 987, the data value is stored in an appropriate data latch for communication to the user. In other embodiments, the read order (Vrc, Vrb, Vra) may be changed.

  The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments best illustrate the principles of the invention and its practical application, so that those skilled in the art can make use of various modifications and variations to suit their particular intended use. It was chosen to make the most of the present invention. It is intended that the scope of the invention be defined by the claims appended hereto.

Claims (22)

A method for reading non-volatile memory, comprising:
Receiving a request to read the first non-volatile storage element;
Reading in response to the request a second non-volatile storage element adjacent to the first non-volatile storage element and capable of storing data in at least four physical states;
The four physical states include a first physical state, a second physical state having a higher charge level than the first physical state, a third physical state having a higher charge level than the second physical state, and a third physical state. A fourth physical state having a higher charge level than the state,
A first reference for reading the first non-volatile storage element at a level between a first program state and a second program state having a charge level that is higher by a first amount than the first program state Applying
In order to read the first non-volatile storage element at a level between the second program state and a third program state having a charge level that is a second amount higher than the second program state. Applying the criteria;
The second amount is less than the first amount;
When the second non-volatile storage element is in the first physical state or the third physical state , the result of applying the first criterion at a first level, and the second level at the second level Determining data of the first non-volatile storage element using a result of applying a criterion;
A result of applying the first criterion at the first level when the second non-volatile storage element is in the second physical state or the fourth physical state; and the first non-volatile storage element And using the result of applying the second criterion at a third level offset by a second level by a floating gate coupling between the first nonvolatile memory element and the second nonvolatile storage element, Determining data of sex memory elements;
A method for reading a non-volatile storage element comprising: The first non-volatile storage element is part of a set of non-volatile storage elements coupled to a first word line;
Programming a set of non-volatile storage elements into a plurality of physical states including the first program state, the second program state, and the third program state;
A step of non-volatile storage elements of said set to be programmed to said first programmed state is to verify whether reached a first target level corresponding to said first programmed state,
A second target, wherein the set of non-volatile storage elements programmed to the second program state corresponds to the second program state and is spaced from the first target level by a first amount; Verifying whether the level has been reached,
The set of non-volatile storage elements programmed to the third program state corresponds to the third program state and is spaced from the second target level by a second amount that is less than the first amount. Verifying whether a third target level is reached, and
The method of claim 1 comprising: Applying the first criterion at the first level does not compensate for floating gate coupling between the first non-volatile storage element and the second non-volatile storage element;
Applying the second criterion at the second level does not compensate for floating gate coupling between the first and second non-volatile storage elements;
3. Applying the second criterion at the third level compensates for floating gate coupling between the first non-volatile storage element and the second non-volatile storage element. the method of. Determining the data of the first non-volatile storage element when the second non-volatile storage element is in the second physical state or the fourth physical state ;
Applying a first voltage corresponding to the first reference at the first level to a control gate of the first non-volatile storage element to detect conduction of the first non-volatile storage element; When,
Applying a second voltage corresponding to the second reference at the second level to the control gate of the first non-volatile storage element to detect conduction of the first non-volatile storage element. Process,
Applying a third voltage corresponding to the second reference at the third level and equal to a voltage obtained by adding an offset to the second voltage to the control gate of the first nonvolatile memory element; Detecting conduction of the first non-volatile storage element;
Selecting the result of applying the first voltage, selecting the result of applying the third voltage, and ignoring the result of applying the second voltage; Determining the data of a storage element;
The method according to any one of claims 1 3 including.   The offset is substantially different from an apparent change in threshold voltage of the first non-volatile storage element based on the floating gate coupling between the first non-volatile storage element and the second non-volatile storage element. The method of claim 4 being equal. The first physical state is an erased state;
The second physical state is the first program state;
The third physical state is the second program state;
The method according to any one of the fourth physical state claim 1 wherein Ru third programmed state der 5. The second non-volatile storage element stores upper page data and lower page data;
Reading the second non-volatile storage element in response to the request comprises reading the upper page data of the second non-volatile storage element;
The second level and the third level of the second reference are based on the upper page data of the second nonvolatile storage element and not on the lower page data;
The first physical state or the third physical state corresponds to the second non-volatile storage element storing the first data of the upper page;
The said 2nd physical state or the said 4th physical state respond | corresponds to the said 2nd non-volatile storage element which memorize | stores the 2nd data of the said upper page. Method. The first non-volatile storage element stores data of a first logical page and a second logical page;
The second non-volatile storage element stores data of a third logical page and a fourth logical page;
The data of the second logical page stored by the first non-volatile storage element is after programming the data of the third logical page stored by the second non-volatile storage element. The method of any one of claims 1 to 6, programmed prior to programming the data stored for the fourth logical page by the second non-volatile storage element. The first non-volatile storage element is connected to a first word line;
The second non-volatile storage element is connected to a second word line adjacent to the first word line;
The programming of data in a non-volatile storage element connected to the first word line is initiated before programming data in a non-volatile storage element connected to the second word line. 9. The method according to any one of items 8.   The method of any one of claims 1 to 9, wherein the first non-volatile storage element is a multi-state NAND flash memory device. The first non-volatile storage element is part of an array of flash memory devices;
The method of any one of claims 1 to 10, wherein the array is removable from a host system. A plurality of non-volatile storage elements capable of storing data in at least four physical states;
A management circuit in communication with the plurality of non-volatile storage elements,
The management circuit includes:
Receiving a request to read a first non-volatile storage element and reading a second non-volatile storage element adjacent to the first non-volatile storage element in response to the request;
The second nonvolatile memory element includes a first physical state, a second physical state having a higher charge level than the first physical state, a third physical state having a higher charge level than the second physical state, and a third Data can be stored in a fourth physical state having a higher charge level than the physical state;
A first reference for reading the first non-volatile storage element at a level between a first program state and a second program state having a charge level that is higher by a first amount than the first program state Apply
To read the first non-volatile storage element at a level between the second program state and the third program state that has a charge level that is a second amount higher than the second program state. Reading the first non-volatile storage element by applying the criteria of:
The second amount is less than the first amount;
When the second non-volatile storage element is in the first physical state or the third physical state , the result of applying the first criterion at a first level, and the second level at the second level Using the result of applying the criteria to determine the data of the first non-volatile storage element;
A result of applying the first criterion at the first level when the second non-volatile storage element is in the second physical state or the fourth physical state; and the first non-volatile storage element And using the result of applying the second criterion at a third level offset by a second level by a floating gate coupling between the first nonvolatile memory element and the second nonvolatile storage element, A non-volatile memory system for determining data of a sexual storage element. The first non-volatile storage element is part of a set of non-volatile storage elements coupled to a first word line;
The management circuit is
Programming the set of non-volatile storage elements into a plurality of physical states including the first program state, the second program state, and the third program state;
It said non-volatile storage elements of said set to be programmed to a first programmed state, to verify whether reaches the first target level corresponding to said first programmed state,
The set of non-volatile storage elements programmed to the second program state corresponds to the second program state and is separated from the first target level by a first amount. Verify that the target level has been reached,
The set of non-volatile storage elements programmed to the third program state corresponds to the third program state and is spaced from the second target level by a second amount that is less than the first amount. The non-volatile memory system according to claim 12, wherein it is verified whether or not a third target level is reached. Applying the first criterion at the first level does not compensate for floating gate coupling between the first non-volatile storage element and the second non-volatile storage element;
Applying the second criterion at the second level does not compensate for floating gate coupling between the first and second non-volatile storage elements;
14. Applying the second criterion at the third level compensates for floating gate coupling between the first and second non-volatile storage elements. Non-volatile memory system. When the second non-volatile storage element is in the second physical state or the fourth physical state ,
Applying a first voltage corresponding to the first reference at the first level to a control gate of the first non-volatile storage element to detect conduction of the first non-volatile storage element;
Applying a second voltage corresponding to the second reference at the second level to the control gate of the first non-volatile storage element to detect conduction of the first non-volatile storage element. ,
Applying a third voltage corresponding to the second reference at the third level and equal to a voltage obtained by adding an offset to the second voltage to the control gate of the first nonvolatile memory element; Detecting conduction of the first non-volatile storage element;
The first nonvolatile memory is selected by selecting the result of applying the first voltage, selecting the result of applying the third voltage, and ignoring the result of applying the second voltage. 15. The nonvolatile memory system according to any one of claims 12 to 14, wherein the management circuit determines data of the first nonvolatile storage element by determining the data of an element.   The offset is substantially different from an apparent change in threshold voltage of the first non-volatile storage element based on the floating gate coupling between the first non-volatile storage element and the second non-volatile storage element. The non-volatile memory system of claim 15, which is equal. The first physical state is an erased state;
The second physical state is the first program state;
The third physical state is the second program state;
The fourth physical state nonvolatile memory system according to either one of said third programmed state der Ru claims 12 to 16. The second non-volatile storage element stores upper page data and lower page data;
Reading the second non-volatile storage element in response to the request comprises reading the upper page data of the second non-volatile storage element;
The second level and the third level of the second reference are based on the upper page data of the second nonvolatile storage element and not on the lower page data;
The first physical state or the third physical state corresponds to the second non-volatile storage element storing the first data of the upper page;
The said 2nd physical state or the said 4th physical state respond | corresponds to the said 2nd non-volatile storage element which memorize | stores the 2nd data of the said upper page. Non-volatile memory system. The first non-volatile storage element stores data of a first logical page and a second logical page;
The second non-volatile storage element stores data of a third logical page and a fourth logical page;
The data of the second logical page stored by the first non-volatile storage element is after programming the data of the third logical page stored by the second non-volatile storage element. 18. A non-volatile memory system according to any one of claims 12 to 17 programmed prior to programming the data stored for the fourth logical page by the second non-volatile storage element. . The first non-volatile storage element is connected to a first word line;
The second non-volatile storage element is connected to a second word line adjacent to the first word line;
The programming of data into a non-volatile storage element connected to the first word line is initiated prior to programming data of a non-volatile storage element connected to the second word line. The non-volatile memory system according to any one of 19.   21. The nonvolatile memory system according to any one of claims 12 to 20, wherein the first nonvolatile storage element is a multi-state NAND flash memory device. The first non-volatile storage element is part of an array of flash memory devices;
The non-volatile memory system according to any one of claims 12 to 21, wherein the array is removable from a host system.

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