KR20080111458A - Programming defferently sized margins and sensing with compensations at select states for improved read operations in non-volatile memory - Google Patents

Abstract

Non-volatile memory read operations compensate for floating gate coupling when the apparent threshold voltage of a memory cell may have shifted. A memory cell of interest can be read using a reference value based on a level of charge read from a neighboring memory cell. Misreading the neighboring cell may have greater effects in particular programming methodologies, and more specifically, when reading the neighboring cell for particular states or charge levels in those methodologies. In one embodiment, memory cells are programmed to create a wider margin between particular states where misreading a neighboring cell is more detrimental. Further, memory cells are read in one embodiment by compensating for floating gate coupling based on the state of a neighboring cell when reading at certain reference levels but not when reading at other reference levels, such as those where a wider margin has been created. ® KIPO & WIPO 2009

Description

PROGRAMMING DEFFERENTLY SIZED MARGINS AND SENSING WITH COMPENSATIONS AT SELECT STATES FOR IMPROVED READ OPERATIONS IN NON-VOLATILE MEMORY}

The present invention relates to programming a nonvolatile memory.

Semiconductor memory devices are increasingly used in various electronic devices. For example, nonvolatile semiconductor memory may include cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices. Used in the field. Electrically erasable programmable read only memory (EPROM) (including flash EEPROM) and electrically programmable read only memory (EPROM) are the most widely used nonvolatile One of the semiconductor memories.

An example of a flash memory system uses a NAND structure, which includes a structure sandwiching a plurality of transistors sandwiched between two select gates and connected in series. The transistors connected in series, and the select gate, are referred to as a NAND string. 1 is a top view illustrating one NAND string. 2 is an equivalent circuit thereof. 1 and 2 include four transistors 100, 102, 104, and 106 sandwiched between a first select gate 120 and a second select gate 122 and connected in series. Select gate 120 connects the NAND string to bit line 126. Select gate 122 connects the NAND string to source line 128. The select gate 120 is controlled by applying an appropriate voltage to the control gate 120G via the select line SGD. The select gate 122 is controlled by applying an appropriate voltage to the control gate 122G through the select line SGS. Each of the transistors 100, 102, 104, and 106 includes a control gate and a floating gate that form the gate element of the memory cell. For example, transistor 100 includes control gate 100CG and floating gate 100FG. Transistor 102 includes control gate 102CG and floating gate 102FG. Transistor 104 includes control gate 104CG and floating gate 104FG. Transistor 106 includes control gate 106CG and floating gate 106FG. Control gate 100CG is connected to word line WL3, control gate 102CG is connected to word line WL2, control gate 104CG is connected to word line WL1, and control gate 106CG ) Is connected to the word line WL0.

Note that although FIGS. 1 and 2 show four memory cells in a NAND string, the use of four transistors is provided only as an example. A NAND string can have fewer than four memory cells or can have more than four memory cells. For example, some NAND strings may include eight memory cells, sixteen memory cells, thirty-two memory cells, and the like. The description herein is not limited to any particular number of memory cells in the NAND string.

A typical architecture for a flash memory system using a NAND structure may include several NAND strings. For example, FIG. 3 shows three NAND strings 202, 204 and 206 of a memory array with many NAND strings. Each of the NAND strings of FIG. 3 includes two select transistors or gates and four memory cells. For example, NAND string 202 includes select transistors 220 and 230 and memory cells 222, 224, 226 and 228. NAND string 204 includes select transistors 240 and 250 and memory cells 242, 244, 246 and 248. Each string is connected to the source line by one select gate (eg, select gate 230 and select gate 250). The select line SGS is used to control the source side select gate. Various NAND strings are connected to each bit line by select gates 220, 240, etc., which are controlled by select line SGD. In other embodiments, the select lines do not necessarily need to be common. The word line WL3 is connected to the control gates for the memory cell 222 and the memory cell 242. The word line WL2 is connected to the control gates for the memory cell 224 and the memory cell 244. The word line WL1 is connected to the control gates for the memory cell 226 and the memory cell 246. The word line WL0 is connected to the control gate for the memory cell 228 and the memory cell 248. As can be seen, the bit line and each NAND string comprise a column of an array of memory cells. Word lines WL3, WL2, WLl, and WLO include rows of the array. Each word line connects the control gates of each memory cell in a row. For example, the word line WL2 is connected to the control gates for the memory cells 224, 244 and 252.

Related examples of NAND type flash memory and its operation are described in the following U.S. patent / patent applications: U.S. Patent No. 5,570,315, U.S. Patent No. 5,774,397, U.S. Patent No. 6,046,935, U.S. Patent No. 6,456,528 US Patent Application Serial No. 09 / 893,277 (Publication US2003 / 0002348), all of which are incorporated herein by reference.

Each memory cell can store data (analog or digital). When storing one bit of digital data, the range of possible threshold voltages of a memory cell, typically referred to as a binary memory cell, is divided into two ranges assigned to logical data "1" and "0". In one example of a NAND type flash memory, the threshold voltage is a negative value after the memory cell is erased and defined as logic "1". The threshold voltage after the program operation is a positive value and is defined as logic "0". When the threshold voltage is negative and a read is attempted by applying 0 volts to the control gate, the memory cell is turned on to indicate that a logic one is stored. When the threshold voltage is positive and a read operation is attempted by applying 0 volts to the control gate, the memory cell is not turned on, which indicates that logic zero is not stored. Multi-state memory cells may also store multiple levels of information, such as multiple bits of digital data. When storing multiple levels of data, the range of possible threshold voltages is divided into multiple data levels. For example, if four levels of information are stored, there may be four threshold voltage ranges assigned to data values "11", "10", "01", and "00". In one example of a NAND type memory, the threshold voltage after the erase operation is negative and defined as "11". Threshold voltages with three different positive values are used for states "10", "01", and "00". The specific relationship between the data programmed into the memory cell and the threshold voltage range of the cell depends on the data encoding scheme adopted for the memory cell. For example, US Pat. No. 6,222,762 and US Pat. App. No. 10 / 461,244, entitled "Tracking Cells For A Memory System", filed Jun. 13, 2003, disclose a variety of data for multi-state flash memory cells. The encoding scheme is described, and both documents are incorporated herein by reference in their entirety. Additionally, embodiments in accordance with the present disclosure are applicable to memory cells that store more than two bits of data.

When programming an EEPROM or flash memory device, a program voltage is typically applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged, and the threshold voltage of the memory cell is raised so that the memory cell is in a programming state. The floating gate charge and the threshold voltage of the cell can represent a particular state corresponding to the stored data. For more information on programming, see US Patent Application No. 10 / 379,608, entitled "Self Boosting Technique," filed March 5, 2003., and US Patent Application No. 10 / 629,068, titled "Detecting Over." Programmed Memory ", filed Jul. 29, 2003. These two applications are incorporated herein by reference in their entirety.

A shift in the apparent charge stored on the floating gate can occur due to the coupling of the electric field due to the charge stored in the neighboring floating gate. Floating gate to floating gate coupling phenomena is described in US Pat. No. 5,867,429, which is incorporated herein by reference in its entirety. Floating gate to floating gate coupling occurs most clearly, but not necessarily, between sets of adjacent memory cells that are programmed at different times. For example, a first memory cell is programmed so that the level of charge is added to the floating gate corresponding to the data set. Subsequently, one or more adjacent memory cells are programmed so that the level of charge is added to the floating gate corresponding to the data set. After one or more contiguous memory cells are programmed, the charge level read from the first memory cell may appear different than when programmed, because the effect of the charge on adjacent memory cell (s) is 1 is coupled to the memory cell. Coupling from adjacent memory cells may shift the apparent charge level read from the selected memory cell by an amount sufficient to cause an error in reading stored data.

As memory cells continue to shrink in size, the natural programming and erase distributions of the threshold voltages increase due to short channel effects, larger oxide thickness / coupling ratio changes, and more channel dopant variations. It is expected that this will reduce the availability of separation between adjacent states. This effect is much greater for multistate memory than binary memory using only two states. Reducing the space between word lines and the space between bit lines can also increase coupling between adjacent floating gates. The impact of floating gate to floating gate coupling is a more important concern for multi-state devices because, between multi-state devices, the allowed threshold voltage range and the prohibited range (between two separate threshold voltage ranges representing individual memory states) Range) is narrower than that of binary devices. Thus, due to the floating gate to floating gate coupling, the memory cell is eventually shifted from the allowed threshold voltage range to the prohibited range.

Thus, there is a need to have a non-volatile memory that effectively manages the problems of floating gate coupling mentioned above.

The technique described herein is intended to address the effects of floating gate coupling in nonvolatile memory.

When the apparent threshold voltage of the memory cell can be shifted, the nonvolatile memory read operation can compensate for floating gate coupling. The memory cell is read using a reference value based on the level of charge read from the neighboring memory cell. Incorrectly reading a neighboring cell can have a big impact on a particular programming method, especially when reading a neighboring cell for a particular state or charge level in this method. In one embodiment, the memory cell is programmed to create a wider margin between certain states in which misreading a neighboring cell has a more detrimental effect. Furthermore, the memory cells, in one embodiment, are plotted based on the state of neighboring cells when reading at some reference level, but not at other reference levels, such as where wider margins are generated. Read by compensating the gate coupling.

In one embodiment, a method of reading nonvolatile storage is provided, wherein the method of reading nonvolatile storage is adjacent to the first nonvolatile storage device in response to receiving a request to read the first nonvolatile storage device. Read the second nonvolatile storage element. The first reference is applied to read the first nonvolatile storage element at a level between the first programming state and the second programming state, and the second reference is at a level between the second programming state and the third programming state. It is applied to read the nonvolatile storage element. The data of the first nonvolatile storage element may result in the application of the first reference at the first level and the second reference at the second level when the second nonvolatile storage element is in the first subset of physical states. It is determined using the result of applying. When the second nonvolatile storage element is in a second subset of physical states, determining the data of the first nonvolatile storage element is the result of applying the first criterion at the first level and the second at the third level. This is done using the results of applying the criteria.

A nonvolatile memory system is provided in one embodiment, wherein the nonvolatile memory system includes a first group of memory cells from a set of memory cells that are programmed together, a second group of memory cells from the set, and the set A third group of memory cells from. The first group is programmed to a first programming state associated with a first range of threshold voltages, and the second group is programmed to a second programming state associated with a second range of threshold voltages. The first range of threshold voltages and the second range of threshold voltages define a first margin of a first magnitude between the first programming state and the second programming state. The third group is programmed to a third programming state associated with the third range of threshold voltages. The second range of threshold voltages and the third range of threshold voltages define a second margin of a second magnitude between the second and third programming states, the second magnitude being smaller than the first magnitude.

Other features, embodiments, and objects of various embodiments of the technology described herein can be seen by reviewing the description, the drawings, and the claims.

1 is a top view of a NAND string.

FIG. 2 is an equivalent circuit diagram of the NAND string of FIG. 1.

3 is a circuit diagram illustrating three NAND strings.

4 is a block diagram of one embodiment of a nonvolatile memory system.

5 shows an exemplary structure of a memory array.

6 illustrates a program voltage signal according to an embodiment.

7 illustrates an example set of threshold voltage distributions and a full sequence programming process.

8 shows an exemplary set of threshold voltage distributions and a two-pass programming process.

9A shows an example threshold voltage distribution for a group of memory cells connected to a first word line before being programmed.

9B shows an exemplary threshold voltage distribution for a group of memory cells connected to a second word line adjacent to the first word line of FIG. 9A after being programmed.

Figure 10A shows the threshold voltage distribution for the group of memory cells of Figure 9A after being programmed.

FIG. 10B shows the threshold voltage distribution for the group of memory cells of FIG. 9B after programming the group of memory cells shown in FIG. 10A.

FIG. 11 illustrates the threshold distribution of the memory cells of FIG. 10B with an offset read reference voltage used to compensate for floating gate coupling.

12A-12C illustrate an example of a programming process and group of memory cells for programming a selection page of data for a group of memory cells after previous page programming for a group of adjacent memory cells to reduce floating gate coupling effect. Red threshold voltage distribution.

13A and 13B illustrate exemplary read reference voltages used to compensate for the effects of floating gate coupling and floating gate coupling for memory cells programmed according to the process of FIGS. 12A-12C.

14 illustrates a programming and reading technique and a threshold voltage distribution of a group of memory cells programmed according to the programming technique, according to one embodiment.

15 is a flow diagram illustrating one embodiment of a process for programming a nonvolatile memory to create a larger margin between select memory states.

16 is a flow diagram illustrating one embodiment of a process for verifying programming of a nonvolatile memory to create a larger margin between select memory states.

17 is a flow diagram illustrating one embodiment of a process for reading a nonvolatile memory.

18 is a flow diagram illustrating one embodiment of a process for reading upper page data from nonvolatile memory cells.

19 is a flow diagram illustrating one embodiment of a process for reading data without using compensation.

20 is a flow diagram illustrating one embodiment of a process for reading data while using compensation for floating gate coupling.

21 is a flow diagram illustrating one embodiment of a process for reading top page data using compensation for floating gate coupling.

4 is a block diagram illustrating one embodiment of a flash memory system that may be used to implement one or more embodiments of the present invention. Other systems and embodiments can be used. The memory cell array 302 is controlled by the column control circuit 304, the row control circuit 304, the c-source control circuit 310 and the p-well control circuit 308. The column control circuit 304 is connected to the bit line of the memory cell array 302 to read data stored in the memory cells, determine the state of the memory cells during a programming operation, and control the potential level of the bit line to program and Promote or inhibit eradication. Row control circuit 306 is coupled to the word line to select the word line, apply a read voltage, apply a program voltage coupled with the bit line potential level controlled by column control circuit 304, and erase voltage. Is applied. The c-source control circuit 310 controls a common source connected to the memory cells. P-well control circuit 308 controls the p-well voltage.

Data stored in the memory cells is read by the column control circuit 304 and output to external I / O through the data input / output buffer 312. Program data to be stored in the memory cells is input to the data input / output buffer 312 via an external I / O line and transferred to the column control circuit 304. An external I / O line is connected to the controller 318.

The column control circuit 304 can include a plurality of sense blocks 330, each associated with one or more bit lines that perform a sense operation. For example, a single sense block may be associated with eight bit lines, and may include one common portion, and may include eight individual sense modules for individual bit lines. For a more detailed description, see US patent application Ser. No. 11 / 026,536, entitled "Non-Volatile Memory & Method with Shared Processing for an Aggregate of Sense Amplifiers," filed Dec. 29, 2004. The document is incorporated herein by reference in its entirety. The sensing module 320 determines whether the conduction current, or other parameter, at the connected bit line is above or below a predetermined threshold level. The sensing module can determine the data stored in the sensed memory cell, and store the data stored in the data latch stack 322. The data latch stack 322 is used to store the data bits determined during the read operation. It is also used to store data bits that are programmed into memory during program operation. In one embodiment, the data latch stack 322 for each sense module includes three data latches. The sensing module may also include a bit line latch used to set the voltage condition on the connected bit line. For example, the predetermined state latched in the bit line latch results in the connected bit line being in a state that specifies program prohibition (eg, Vdd).

Command data for controlling the flash memory device is input to the controller 318. Command data tells flash memory what action is requested. The input command is passed to the state machine 316 which is part of the control circuit 315. State machine 316 controls column control circuit 304, row control circuit 306, c-source control 310, p-well control circuit 308, and data input / output buffer 312. The state machine 316 may also output state data in flash memory, such as READY / BUSY or PASS / FAIL.

The controller 318 may be connected to or may be connected to a host system such as a personal computer, digital camera, personal digital assistant, or the like. This initiates commands such as storing data in or reading data from the memory array 302 and communicating with a host that provides or receives this data. The controller 318 converts this command into a command signal that can be interpreted and executed by the command circuit 314 that is part of the control circuit 315. The command circuit 314 is in communication with the state machine 316. Controller 318 typically includes buffer memory for user data that is written to or read from the memory array.

One example memory system includes one integrated circuit that includes a controller 318, and one or more integrated circuits, each of which includes a memory array and its associated control circuitry, input / output circuitry, and state machine circuitry. Circuit chips. There is a tendency to integrate the memory array and controller circuit of a system together on one or more integrated circuit chips. The memory system may be embedded as part of the host computer, or may be included in a memory card (or other package) that is removably inserted into the host system. Such a card may include the entire memory system (eg, including a controller) or may only include memory array (s) having only relevant peripheral circuits (having a controller or control function embedded in the host). . Thus, the controller can be embedded in the host or can be included in a removable memory system.

5, an exemplary structure of a memory cell array 302 is described. For example, a NAND flash EEPROM that is divided into 1,024 blocks is described. Data stored in each block can be erased at the same time. In one embodiment, the block is the smallest cell unit that can be erased simultaneously. Memory cells are erased by raising the p-well to an erase voltage (eg, 20 volts) and grounding the word lines of the selected block. Source lines and bit lines are floating. Erasing may be performed on the entire memory array or individual blocks, or may be performed on another cell basis. Electrons are transferred from the floating gate to the p-well region, and the threshold voltage (in one example) is negative.

In the example of FIG. 5, there are 8,512 columns in each block. Each block is typically divided into pages, which can be a unit of programming. Other data units for programming are also possible and may be considered. In one embodiment, individual pages may be divided into segments, and these segments may include the fewest number of cells written at a time as a basic programming operation. One or more data pages are typically stored in one row of memory cells.

In each block of the example in FIG. 5, there are 8,512 columns divided into even columns and odd columns. The bit lines are divided into even bit lines BLe and odd bit lines BLO. In odd / even bit line architectures, memory cells along a common word line and connected to odd bit lines are programmed at one time, while memory cells along a common word line and connected to even bit lines are programmed at another time. do. 5 shows four series of memory cells connected in series to form a NAND string. Although four memory cells are shown to be included in each NAND string, more or less than four may be used (eg, 16, 32, or another). One terminal of the NAND string is connected to the corresponding bit line through a first select transistor or a select gate (which is connected to a Select Gate Drain line (SGD)), and another terminal of the NAND string It is connected to the c-source via a second select transistor, which is connected to a Select Gate Source line (SGS).

During the read and program operations of one embodiment, 4,256 memory cells are selected simultaneously. The selected memory cells have the same word line (eg WL2) and the same kind of bit line (eg odd bit lines). Thus, 532 bytes of data can be read or programmed simultaneously. These 532 bytes of data being read and programmed at the same time form one logical page. Thus, in one example, one block can store at least eight pages. When each memory cell stores two bits of data (e.g., a multi-state cell), such a block can store 16 pages (or, for example, each of the eight pages contains 1064 bytes). You can). Other sized blocks and pages may also be used with the various embodiments. In one embodiment, a set of memory cells that are simultaneously selected may store more than one data page.

Architectures other than FIGS. 4 and 5 may be used in accordance with various embodiments. In one embodiment, the bit lines are not divided into odd bit lines and even bit lines. This architecture is commonly referred to as all bit line architectures. In all bit line architectures, all of the bit lines of a block are simultaneously selected during read and program operations. Memory cells along a common word line and connected to any bit line are programmed simultaneously. For more information regarding other bit line architectures and related operable technologies, see US Patent Application No. 11 / 099,133, entitled "Compensating for coupling during Read Operations of Non-Volatile Memory," 200.04.05. Application), which is hereby incorporated by reference in its entirety.

In the read and verify operations, the select gates of the selected block are raised to one or more select voltages, and the unselected word lines (e.g., WLO, WLl, and WL3) of the selected block are read pass voltages (e.g., For example, to 4.5 volts), allowing the transistor to operate as a pass gate. The unselected word lines (e.g., WL2) of the selected block are connected to a reference voltage, the level of which is specified for each read and verify operation because the threshold voltage of the associated memory cell is above this level. Or to determine if it is below. For example, in a read operation of one bit memory cell, the selected word line WL2 is grounded, so it is determined whether the threshold voltage is higher than zero volts (0V). In the verify operation of one bit memory cell, the selected word line WL2 is connected to 0.8V, so as the programming proceeds it is verified whether or not the threshold voltage has reached 0.8V. Source and p-well are at 0V during read and verify. The select bit line BLe is precharged to a level of, for example, 0.7V. If the threshold voltage is higher than the read or verify level, the potential level of the associated bit line BLe remains at a high level because of the associated nonconductive memory cell. In other words, if the threshold voltage is lower than the read or verify level, because of the conductive memory cell, the potential level of the associated bit line BLe decreases to a lower level (e.g., less than 0.5V). Other current and voltage sensing techniques can be used in accordance with various embodiments of the present invention. During the read or detect of a multi-state cell, state machine 316 steps through various predetermined control gate reference voltages according to various memory states. During the read or sense of multiple state cells, state machine 316 steps through a predefined control gate reference voltage corresponding to various memory states. The sense module trips at one of several voltages, and the output is provided from the sense module. The processor in the sensing module may determine the resulting memory state by considering the tripping event (s) and by considering information about the applied control gate voltage from the state machine. The binary encoding for the memory state is calculated and stored in the data latch.

During the program operation and the verify operation, data to be programmed in the set of cells may be stored in the set of data latches 322 for each bit line. The drain and p-well of the memory receive 0V, while the control gates of the addressed memory cells receive programming pulses of increasing magnitude. In one embodiment, the series of pulses ranges from 12V to 24V. In other embodiments, this range may vary, for example having a starting level higher than 12V. During programming, verify operations can be performed between programming pulses. It is determined whether the programming level of each cell programmed in parallel has reached or exceeded the verify level for the state being read and programmed between each programming pulse. The verify level can be the target minimum threshold voltage for the cells in the corresponding memory state. One means of verifying programming is to test the conductivity at specific comparison points. Cells that are verified as fully programmed are locked out to prevent further programming. The voltage of the verified cells bit line is raised from 0 V to Vdd (eg 2.5 volts) during subsequent programming pulses to terminate the programming process for these cells. In some cases, the number of pulses is limited (eg 20 pulses), and if a given memory cell is not sufficiently programmed by the last pulse, an error has been considered.

6 illustrates a program voltage signal according to an embodiment. This signal has a set of pulses with increasing magnitudes. The magnitude of the pulses is increased with each pulse by a predetermined step size. In one embodiment including memory cells that store a plurality of data bits, an exemplary step size is 0.2 volts (or 0.4 volts). There are verify pulses between each of the programming pulses. The signal of FIG. 6 represents four state memory cells, so it contains three verify pulses. For example, there are three sequential verify pulses between programming pulses 330 and 332. The first verify pulse 34 is shown at the 0V verify voltage level. The first verify pulse 334 is shown at the 0 V verify voltage level. The second verify pulse 336 follows the first verify pulse at the second verify voltage level. The third verify pulse 338 follows the second verify pulse at the third verify level. A multi-state memory cell capable of storing data in eight states may need to perform a verify operation at seven comparison points. Thus, seven verify pulses are applied sequentially to perform seven verify operations at seven verify levels between two consecutive programming pulses. Based on the seven verify operations, the system can determine the state of the memory cell. One means of reducing the time added due to verification is to use a more efficient verification process, such as, for example, US Patent Application No. 10 / 314,055 (named "Smart Verify for Multi-State Memories"). , Filed Dec. 5, 2002, US Patent Application No. 11 / 259,799, entitled "Method for Programming of Multi-State Non-Volatile Memory Using Smart Verify", filed Oct. 27, 2005, and US patent Application No. 11 / 260,658, entitled "Apparatus for Programming of Multi-State Non-Volatile Memory Using Smart Verify", filed 2205.10.27. All of these documents are incorporated by reference in their entirety. Incorporated herein.

The erase, read, and verify operations described above are performed in accordance with techniques known in the art. Therefore, many of the detailed descriptions described may be variously modified by those skilled in the art.

At the end of a successful programming process, the threshold voltages of the memory cells must be in one or more distributions of the threshold voltages for the programmed memory cells or suitably within the distribution of the threshold voltages for the erased memory cells. 7 shows the threshold voltage distribution for a group of memory cells as each memory cell stores two bits of data. 7 shows a first threshold voltage distribution E for erased memory cells and three threshold voltage distributions A, B, and C for programmed memory cells. In one embodiment, the threshold voltages in distribution E are negative and the threshold voltages in distributions A, B, and C are positive values.

Each individual threshold voltage range of FIG. 7 corresponds to predetermined values for the set of data bits. The specific relationship between the data programmed into the memory cells and the threshold voltage levels of the cell depends on the data encoding scheme adopted for the cells. In one embodiment, the data value is assigned to the threshold voltage range using gray code assignment, so that only one bit, even if the threshold voltage of the floating gate incorrectly shifts to its neighboring physical state. This is affected. However, in other embodiments gray coding is not used. As an example, "11" is assigned to threshold voltage range E (state E), "10" is assigned to threshold voltage range A (state A), and threshold voltage range B is "00" is assigned to (state B), and "01" is assigned to the threshold voltage range C (state C). Although FIG. 7 illustrates four states, embodiments in accordance with the present disclosure may also be used with other multi-state structures that include more or less than four states.

7 shows three read reference voltages Vra, Vrb, and Vrc for reading data from memory cells. By testing whether the threshold voltages of a given memory cell are above or below Vra, Vrb and Vrc, the system can determine which state the memory cell is in. If the memory cell is in a conductive state at Vra, then the memory cell is in state E. If the memory cell is in the conductive state at Vrb and Vrc but not at the Vra, then the memory cell is in state (A). If the memory cell is conducting at Vrc but not at Vra and Vr, then the memory cell is in state (C). 7 also shows three verification reference voltages Vva, Vvb and Vvc, which are evenly spaced from each other. In programming memory cells to state A, the system tests whether these memory cells have a threshold voltage greater than Vva or a threshold voltage equal to Vva. In programming memory cells to state B, the system tests whether these memory cells have a threshold voltage greater than Vvb or the same threshold voltage as Vvb. In programming memory cells to state C, the system determines whether the memory cells have a threshold voltage greater than Vvc or a threshold voltage equal to Vvc. The verify voltage defines the range of threshold voltages assigned to a particular physical state and forbidden ranges between them. The verify levels are spaced apart to provide sufficient margin between the highest threshold voltage in one state and the lowest threshold voltage in the next state. There is a larger margin naturally occurring between the erase state E and the first programming state A.

7 also shows full sequence programming. In full sequence programming, memory cells are programmed into either of the programming states A, B, or C directly from the erase state E, so that a bunch of memory cells to be programmed can be erased first so that all of the memory cells Is in the erased state (E). A series of programming voltage pulses are applied to the control gate of the selected memory cells to program the memory cells directly to state A, B or C. Some memory cells are programmed from state (E) to state (A), other memory cells are programmed from state (E) to state (B) and / or from state (E) to state (C).

8 shows an example of a two-pass technique for programming multi-state memory cells for two different pages, a lower page and an upper page. Four states are shown: state (E) 11, state (A) 10, state (B) (00), and state (C) (01). For state E, both pages store "1". For state A, the lower page stores "0" and the upper page stores "1". For state B, both pages store "0". For state C, the lower page stores "1" and the upper page stores "0". Note that although specific bit patterns are assigned to each of the states, other bit patterns may also be assigned. In the first programming pass, the threshold voltage level of the cell is set according to the bit to be programmed into the lower logical page. If the bit is a logic " 1, " the threshold voltage does not change because it is in the proper state as a result of the earlier erasing. However, if the bit to be programmed is a logic "0", the threshold level of the cell is increased to be state A, as shown by arrow 450. This is the first programming pass in conclusion.

In the second programming pass, the threshold voltage level of the cell is set according to the bit programmed into the upper logical page. If the upper logical bit has to store a logic "1", no programming takes place because the cell is in either state (E) or state (A), depending on the programming of the lower page bit, all of which are " It has a 1 "top page bit. If the upper page bit should be a logic "0", then the threshold voltage is shifted. If the cell remains in the erased state E in the first pass, then the cell is programmed in the second phase so that the threshold voltage increases to be in state C as shown by arrow 454. If the cell is programmed to state A as a result of the first programming pass, then the memory cell is also programmed in the second pass so that the threshold voltage is increased to be in state B as shown by arrow 452. . The result of the second pass is to program the cell with the specified state to store logic "0" for the upper page without changing the data for the lower page.

In one embodiment, the system may be configured to perform full sequence writing if enough data is written to fill the entire page. If not enough data is written for the entire page, then the programming process can program the lower page with the received data. When subsequent data is received, the system programs the upper page. In another embodiment, the system begins writing data using a two-pass technique, and if enough data is subsequently received to fill the memory cells of the entire (or most) word line, the full sequence Switch to programming mode. A more detailed description of this embodiment is described in US patent application Ser. No. 11 / 013,125, entitled "Pipelined Programming of Non-Volatile Memories Using Early Data", Dec. 14, 2004. Applicant, inventors: Sergy Anatolievich Gorobets and Yan Li. Which is hereby incorporated by reference in its entirety.

Floating gate coupling can cause unrecoverable errors during read operations that may require performing error recovery during reads. The charge stored on the floating gate of the memory cell causes apparent shifts due to electrical field coupling from charge stored in the floating gate or other charge storage region (e.g., dielectric charge storage region) of the neighboring memory cell. You can experience it. In theory, the electric field from the charge on the floating gate of any memory cell in the memory array can be connected to the floating gate of any other memory cell in the array, the effect of which is most obvious and obvious with the adjacent memory cells. Adjacent memory cells are neighboring memory cells on the same bit line, neighboring memory cells on the same word line, or adjacent neighboring each other in a diagonal direction on both neighboring bit lines and neighboring word lines. It may include memory cells. The apparent shift in charge can result in errors in reading the memory state of the memory cell.

The effect of floating gate coupling is most apparent in the situation where a memory cell adjacent to the target memory cell is subsequently programmed into the target memory cell, but the effect can also be observed in other situations. The charge or a portion of the charge placed on the floating gate of the adjacent memory cell is effectively coupled to the target memory through electric field coupling, resulting in an apparent shift in the threshold voltage of the target memory cell. The apparent threshold voltage of the memory cell may be shifted to such an extent that after being programmed, the read reference voltage does not turn on and off (conduct) under the applied reference, as expected for the memory cell in the memory state.

Typically, a row of memory cells is programmed starting with word line WL0 adjacent to the source side select gate line. Thus, programming proceeds sequentially by word lines WLl, WL2, WL3, etc. through strings of cells, so that at least one data page has completed programming of the previous word line WLn (each of the word lines). After the cell is put into its final state, it is programmed to the adjacent word line WLn + 1. This programming pattern causes an apparent shift in the threshold voltages of the memory cells due to floating gate coupling after they are programmed. For all word lines other than the last word line of the string to be programmed, adjacent word lines are programmed following the completion of programming of that word line. Negative charge added to the floating gate of memory cells on a word line that is subsequently contiguous then increases the apparent threshold voltage of the memory cells on that word line.

9A-10B illustrate the effect of floating gate coupling on a set of memory cells that are programmed using full sequence programming as shown in FIG. 9B shows a threshold voltage distribution for a set of memory cells of a selected word line WLn after being programmed. Distribution 500 shows the actual threshold voltage distribution of cells in WLn in an erased (unprogrammed) state E, and distribution 505 shows the actual threshold of cells in WLn programmed to state A. Shows a voltage distribution, distribution 510 shows the actual threshold voltage distribution of cells in WLn programmed to state B, and distribution 520 shows the actual threshold voltage of cells in WLn programmed to state C The threshold voltage distribution is shown. The set of memory cells may only include each memory cell of the selected row or word line WLn or cells of WLn connected to a particular type of bit line (even or odd). 9A shows threshold voltage distributions for memory cells in adjacent word line WLn + 1 prior to programming. The cells of WLn + 1 are programmed after programming the cells of WLn. Since each cell at WLn + 1 has been erased and not yet programmed, they do not cause any reverse floating gate coupling effect on the cells of WLn. More importantly, they are in the same state in which they are present when programming WLn, so the cells in WLn have an apparent threshold voltage equal to the level verified during programming.

Figure 10A shows the threshold voltage distribution for a set of WLn + 1 memory cells after programming. The memory cells are programmed from the erased threshold voltage distribution (E) to the programmed threshold voltage distributions (A, B, and C). The charge placed on the floating gates of the memory cells of word line WLn + 1 after programming the word line WLn may change the memory state of the memory cells of WLn as observed by the memory system during sensing. . The electric field associated with the charges on the floating gates of word line WLn + 1 is coupled to the floating gate of the memory cells in word line WLn. The electric field may cause an apparent shift in the threshold voltage of the memory cells at WLn.

Figure 10B shows the apparent threshold voltage distribution for memory cells in word line WLn after programming WLn + 1. Each programming state is shown with four different corresponding threshold voltage distributions. The overall distribution for each physical state can be divided into four individual distributions based on the state in which adjacent memory cells in the word line WLn + 1 are programmed. Each memory cell in word line WLn having an adjacent memory cell at WLn + 1 (on the same bit line) programmed to state A experiences a first shift level at its apparent threshold voltage. Each cell at WLn with an adjacent cell at WLn + 1 in state B experiences a second larger shift in apparent threshold voltage. Each cell with an adjacent memory cell in state C experiences a third larger shift.

For cells at WLn in state A, distribution 502 is the threshold voltage for those cells having adjacent memory cells on word line WLn + 1 remaining in erased state E after programming. Indicates. Distribution 504 represents the threshold voltage for cells with adjacent cells in word line WLn + 1 that are programmed to state A. Distribution 506 represents the threshold voltage for cells with adjacent cells in word line WLn + 1 that are programmed to state B. Distribution 508 represents the threshold voltage for cells with adjacent cells in word line WLn + 1 that are programmed to state C.

Memory cells in WLn programmed to different states experience similar coupling effects. Thus, four individual threshold voltage distributions are also shown for state B and state C. FIG. Memory cells in word line WLn programmed to state B may have four different threshold voltage distributions 512 and 514 based on the subsequently programmed state of adjacent memory cells in word line WLn + 1. , 516, and 518). The memory cells of WLn programmed to state C likewise have four different distributions 522, 524, 526, and 528. It should be noted that erased memory cells of WLn also experience coupling effects. The shift is not shown because the naturally occurring margin between the erased state (E) and state (A) is generally sufficient, so that the shifting does not cause any error in reading the erased cells. However, these effects exist and the technology disclosed can handle these well.

An increase in the apparent threshold voltage of the memory cells can cause a read error. As shown in FIG. 10B, some memory cells of WLn programmed into the original state A may have a threshold voltage shifted beyond the read reference voltage level Vrb. This may result in errors in reading. When a read reference voltage Vrb is applied, these memory cells may not conduct even though they are programmed to state A. The state machine and controller may determine that the memory cells are in state B rather than in state A (after Vrb has not detected any conduction). Some memory cells of WLn originally programmed to state B may also shift beyond the read reference voltage Vrc, which could potentially cause a read error in the same manner.

FIG. 11 illustrates a read technique that can be used to handle some of the apparent shifts in the threshold voltage shown in FIG. 10B. In FIG. 11, four distributions for each state of the cells in WLn shown in FIG. 10B have been reduced to distributions 530, 540, and 550 indicating the cumulative effect of coupling on a group of memory cells. . Distribution 530 represents cells of WLn in state A after programming WLn + 1, distribution 540 represents cells of WLn in state B after programming WLn + 1, And distribution 550 represents the cells of WLn in state C after programming WLn + 1. Distribution 530 distributes individual distributions 502-508, distribution 540 distributes individual distributions 512-518, and distribution 550 distributes individual distributions 522-528. do.

In reading the data on the word line Wln, the data of the word line WLn + 1 can also be read, and if the data on the word line WLn + 1 interferes with the data on the WLn, then the read process for the WLn. Can compensate for such disturbances. For example, when reading the word line WLn, the state or charge level information for the memory cells in the word line WLn + 1 is an appropriate read criterion for reading the individual memory cells of the word line WLn. Can be determined to select the voltage. 11 shows the individual read reference voltages for reading WLn based on the state of adjacent memory cells in word line WLn + 1. In general, different offsets (eg, OV, 0.1V, 0.2V, 0.3V) are used for the nominal read reference voltages, and the state of the memory cell on the neighboring word line results from sensing at different offsets. Is selected as a function of In one embodiment, memory cells in the word line WLn are sensed using each of the different read reference voltages. For a given memory cell, the result from sensing at the appropriate one of the read reference voltages may be selected based on the state of the adjacent memory cell at word line WLn + 1. In some embodiments, the read operation for WLn + 1 determines the actual data stored at WLn + 1, while in other embodiments, the read operation for WLn + 1 only determines the charge level of these cells, which is The data stored in WLn + 1 may or may not be reflected. In some embodiments, the levels and / or number of levels used to read WLn + 1 may not be exactly the same as used to read WLn. Any approximation of the floating gate threshold voltage value may be sufficient for WLn correction in some embodiments. In one embodiment, the result of the read at WLn + 1 may be stored in latch 322 at each bit line to be used in reading the WLn.

A read operation may first be performed for the corresponding word line WLn at nominal read reference voltage levels Vra, Vrb, and Vrc that do not compensate for any coupling effect. The result of the read at the nominal reference level is stored in the appropriate latch for the bit lines with memory cells whose neighboring cell at WLn + 1 is determined to be in state E. For other bit lines, data is ignored, and WLn + 1 data is maintained. A read operation is then performed on word line WLn using the first set of offsets for the read reference voltage. The read process may use Vra1 (Vra + 0.1V), Vrbl (Vrb + 0.1V) and Vrcl (Vrc + 0.1V). The result of using these reference values is stored for bit lines with memory cells having neighboring memory cells at WLn + 1 in state A. A read operation is then performed using the second set of offsets using Vra2 (Vra + 0.2V), Vrb2 (Vrb + 0.2V) and Vrc2 (Vrc + 0.2V). The result is stored in the latch for bit lines with memory cells having neighbors at WLn + 1 in state B. A read operation is performed on word line WLn using a third set of offsets using Vra3 (Vra + 0.3V), Vrb3 (Vrb + 0.3V) and Vrc3 (Vrc + 0.3V), and the result is Stored for those bit lines with memory cells having neighboring cells at WLn + 1 in state C. In some embodiments, due to the greater natural margin between state E and state A, no offsets are used in Vra. Such an embodiment is shown in FIG. 11 in which a single read reference voltage Vra is shown at the state A level. Other embodiments may also use offsets for this level.

Different offsets for the nominal read reference voltage may be selected as a function of the state of the memory cell on the adjacent word line. For example, the set of offset values corresponds to an 0V offset corresponding to an adjacent cell in state E, a 0.1V offset corresponding to an adjacent cell in state A, and an adjacent cell in state B. 0.2V offset, and 0.3V offset corresponding to the adjacent cell in state (C). Offset values vary depending on the embodiment. In one embodiment, the offset values are equal to the amount of shift in the apparent threshold voltage resulting from the adjacent cell programmed to the corresponding state. For example, 0.3V may represent a shift in apparent threshold voltage for the cell at WLn when the adjacent cell at WLn + 1 is subsequently programmed to state C. Offset values need not be the same for all reference voltages. For example, the offset values for the Vrb reference can be OV, 0.1V, 0.2V, and 0.3V, while the offset values for the Vrc reference voltage can be OV, 0.15V, 0.25V, and 0.35V. In addition, the increments in the offsets need not be the same for all states. For example, in one embodiment the offset set may include OV, 0.1V, 0.3V, and 0.4V for adjacent cells in states E, A, B, and C, respectively.

In one embodiment, reading using a plurality of individual read reference levels for a given state, and selecting the result based on the state of adjacent memory cells, affects the floating gate charge coupling by about 50 percent. It can be expected to reduce. As read by the sensing module, the threshold voltage distribution for the word line of memory cells can be effectively narrowed by about 50 percent using this technique.

It is possible to configure a programming process for nonvolatile memory to reduce the apparent shift in threshold voltage from floating gate coupling. 12A-12C reduce floating gate to floating gate coupling by writing to a particular memory cell for a particular page after writing to adjacent memory cells for a previous page, for any particular memory cell. A process for programming a nonvolatile memory is described. In the example of Figures 12A-12C, each cell stores two bits of data per memory cell, using four data states. The erased state E stores the data 11, the state A stores the data 01, the state B stores the data 10, and the state C stores the data 00. Save it. Several other methods of encoding data into the physical data state may also be used. Each memory cell stores a portion of two logical data pages. For reference purposes, these pages are referred to as the top page and the bottom page, but may be given other names. State A is encoded to store bit 0 for the upper page, and is encoded to store bit 1 for the lower page, state B is encoded to store bit 1 for the upper page, and Is encoded to store bit 0 for, and state C is encoded to store bit 0 for both pages. The lower page data for the memory cells in the word line WLn is programmed in the first step shown in FIG. 12A, and the upper page data for the cells is programmed in the second step shown in FIG. 12C. If the lower page data should hold data 1 for the cell, then the cell's threshold voltage is maintained in state E during the first step. If the data is to be programmed to zero, the threshold voltage of the memory cell is raised to state B '. State B 'is an interim state B with a lower verify level Vvb' than Vvb.

In one embodiment, after the lower page data for a memory cell is programmed, neighboring memory cells in adjacent word line WLn + 1 are programmed with respect to their lower page. For example, the lower page data for memory cells in WL2 of FIG. 3 may be programmed after the lower page for memory cells in WL1. Floating gate coupling raises the apparent threshold voltage of memory cell 226 if the threshold voltage of memory cell 224 rises from state E to state B 'after programming memory cell 226. You can. The cumulative coupling effect on the memory cells at WLn widens the apparent threshold voltage distribution of the threshold voltage for the cells, as shown in FIG. 12B. The apparent widening of the threshold voltage distribution can be cured when programming the upper page for that word line.

12C shows the process of programming the upper page for the cell at WLn. If the memory cell is in the erase state (E), and the upper page bit should be kept at 1, the memory cell is kept in the state (E). If the memory cell is in the erase state E, and the upper page bit should be programmed to zero, the threshold voltage of the memory cell is raised to be within the range for state A. If the memory cell is in the intermediate threshold voltage distribution B ', and its upper page data must remain 1, then the memory cell is programmed to its final state B. If the memory cell is in the intermediate threshold voltage distribution B ', and its upper page data must remain zero, the threshold voltage of the memory cell is raised to fall within the range for state C. The process illustrated by FIGS. 12A-12C reduces the effect of floating gate coupling, because only upper page programming of neighboring memory cells affects the apparent threshold voltage of a given memory cell. An example of alternate state coding for this technique is to move from intermediate state (B ') to state (C) when the upper page data is 1, and state when the upper page data is' 0'. Go to (B). Although FIGS. 12A-12C provide examples of four data states and two data pages, the concepts described by FIGS. 12A-12C may have more or fewer states than four and different numbers of pages. It may be applied to other embodiments.

FIG. 13A illustrates the influence of floating gate coupling on the programming technique of FIGS. 12A-12C, and FIG. 13B illustrates a read method using compensation offsets to overcome some of these effects. The memory cells of word line WLn + 1 adjacent to word line WLn are programmed during the third pass so that their upper page data is programmed as shown in FIG. 12C. During the second pass, the memory cells are programmed from state E to state A or from intermediate state B 'to state B or state C. The memory cells of the corresponding word line WLn are shown in FIG. 13A, and the lower pages for the memory cells in the word line WLn + 1 are programmed with respect to their upper page after programming. Thus, the upper page programming shown in FIG. 12C is only programming that affects the apparent threshold voltage for the memory cell at word line WLn.

The memory cell of word line WLn + 1 programmed from state E to state A experiences a similar change in threshold voltage as in cells programmed from intermediate state B 'to state C. . Memory cells of adjacent word lines WLn + 1 programmed from state B 'to intermediate B experience little increase in threshold voltage and have little effect on the apparent threshold voltages of the cells in WLn. can not do it. The memory cells of WLn programmed to state A are assigned to cells having neighboring cells at state E, at state B, at state A, and at WLn + 1 in state C, respectively. It is represented by the corresponding individual distributions 652, 654, 656, and 658. The memory cells of WLn programmed to state B each have a neighboring cell at state E, at state B, at state A, and at WLn + 1 in state C, respectively. B) represented by the individual distributions 662, 664, 666, and 668 corresponding to the cells. The memory cells of WLn programmed to state C each have a neighboring cell at state E, at state B, at state A, and at WLn + 1 in state C, C) represented by the individual distributions 672, 674, 676, and 678 corresponding to the cells.

As shown in FIG. 13A, some memory cells of WLn may have their apparent threshold voltages shifted to or near the read reference voltage Vrb or Vrc or beyond the read reference voltage Vrb or Vrc. This can cause reading errors. As described above, the described coupling effect is applicable to the WLn cancellation distribution, and the disclosed technique is equally applicable. The effect on the erased cells has not been explained in principle because of the natural margin between state (E) and state (C).

13B shows offsets for the read reference level that may be used with the programming technique of FIGS. 12A-12C. For clarity, the distributions 652, 654, 656, and 658 are shown as a single combined distribution 651, and the distributions 662, 664, 666, and 668 are shown as a combined distribution 661. , And distributions 672, 674, 676, and 678 are shown as combined distribution 671. Distributions 650, 660, and 670 represent the cells of WLn before programming the upper page data at WLn + 1. In the embodiment of FIG. 13B, similar coupling effects from cells on adjacent word lines programmed from state A to state C are grouped together to form a single offset for each of these state levels. The result of the sensing at offset reference voltages Vrbl and Vrcl is used for memory cells having adjacent cells at word line WLn + 1 in state A or state C. Minor coupling effects from programming from intermediate state B 'to state B are ignored. The result of the sensing when using the nominal reference voltages Vrb and Vrc is used for memory cells with adjacent cells in word line WLn + 1 in state E or state B. Additional offsets for each particular state of WLn + 1 may be used in one embodiment. Although the technique shown in FIG. 13B provides further reduction in the effects of floating gate coupling, errors may still exist.

Misreading of adjacent word lines can be more problematic for cells that are actually programmed with the techniques of FIGS. 12A-12C when trying to determine an appropriate offset for reading that cell. When the read reference voltage Vrb is applied to the state B, misreading of the memory cell in the word line WLn + 1 is taken into account. If the memory cell at WLn + 1 is programmed to state A, and is incorrectly read as being in state B, the read for the corresponding memory cell at word line WLn using a nominal read reference voltage. The result of the action is selected and reported. No compensation for floating gate coupling is used because it is determined that the cell at WLn + 1 is in state B and therefore only experiences a slight change in threshold voltage after programming WLn. In fact, however, a memory cell at WLn + 1 can show a strong effect on the apparent threshold voltage of the cell at WLn. The cell at WLn + 1 may be at the upper end of the state (A) distribution, which is why it is misread. Thus, the memory cell at WLn + 1 experiences a large change in charge at its floating gate when programmed from state E to the upper end of state A. The charge stored by the cell at WLn + 1 The large change in causes a large shift in the apparent threshold voltage of the cell at WLn. However, no compensation for this shift is used because of a misread at WLn + 1. Thus, the memory cell at WLn may be misread as a result of misread WLn + 1.

If the adjacent memory cell in word line WLn + 1 programmed to state B is misread as in state A, similar problems may occur. The memory cell in word line WLn + 1, which is read as being in state A, may have a threshold voltage at the lower end of the state B distribution when in fact state B. After programming the memory cell at WLn + 1, the memory cell experiences a very small change in threshold voltage. As a result, a very small shift in the apparent threshold voltage of the corresponding cell in WLn may occur or no shift occurs. However, the result of the read operation at WLn for the corresponding memory cell selects the result from the read at the compensated reference level. Since the memory cell has not experienced a large shift in the apparent threshold voltage, selecting a result when the compensated reference level is used can cause a misread or error in WLn.

In the prior art, programming memory cells with various program states has been performed using equally spaced verify levels shown in FIGS. 13A-13B. This means that the verify levels for states A, B, and C are spaced at equal intervals from each other, so that the difference in voltage between verify level Vvb and verify level Vva is verified. It is equal to the difference in voltage between level Vvc and verify level Vvb. Due to the equal spacing of the programming verify levels, the margin between the various programming states is the same or substantially the same. This margin corresponds to the forbidden voltage region between physical states. The margin between state A and state B is defined by the maximum threshold voltage of the memory cell in state A and the minimum threshold voltage of the memory cell in state B. Sufficient margin is provided between programming states so that accurate read operations can be performed. Because of floating gate coupling, the margin between physical states is reduced and consequently errors in reading may occur.

According to an embodiment of the present invention, the shifted verify level is used when programming one or more selected states, for example state B, so that a larger margin between certain states for improved sensing accuracy. Is generated. In one embodiment, the offset-compensated read reference level is not used at the level corresponding to the wider margin, but at other levels to provide more efficient reads for higher performance. The combination of wider margins between selective physical states and selective application of offset reference levels provides accurate sensing techniques while maintaining the required level of performance. Figure 14 illustrates a threshold voltage distribution for a set of memory cells programmed according to one embodiment of the present invention. Distributions 678, 680, 684, and 688 illustrate a set of memory cells after programming but before programming of cells in adjacent word line WLn + 1.

The shifted program verify level Vvbl is used in FIG. 14 when programming memory cells to state B. FIG. The embodiment of FIG. 14 may be used in programming according to the techniques shown in FIGS. 12A-12C. The verify level Vvbl is higher than Vvb in the conventional operation shown in Fig. 12C, so a larger margin is created between state A and state B. The highest threshold voltage of any memory cell in state A remains the same as in the prior art. However, the lowest threshold voltage of any cell in state B is shifted in the positive direction. Increased verify level when programming memory cells to state B increases the margin between state A and state B. FIG. As shown in FIG. 14, the margin 683 between state A and state B is greater than the margin 685 between state B and state C. As shown in FIG. As a result, less misreading may occur when sensing the reference voltage level Vrb in state B. FIG.

Distributions 682, 686, and 690 show the effect of floating gate coupling after neighboring word line WLn + 1 has been programmed (eg, as shown in FIG. 12C). In FIG. 14, the Vrb read level is well spaced between the apparent A state distribution 682 and the apparent B state distribution 686. As a result, less misreading can occur because the Vrb read level does not overlap the threshold voltage of any cell to be in state A, even after the coupling effect from the neighboring word lines is taken into account. In one embodiment, the reference level Vrb is a previously used level (e.g., FIG. Is shifted from Vrb of 12C). Since Vrb can be shifted beyond the highest threshold voltage of any memory cell in state A, a single reference value Vrb can be used during reading, and no compensation is applied.

Thus, an offset to the read reference voltage is not used in the read in state B in one embodiment. In the embodiment of Fig. 14, only the offset for the read reference voltage is used only for the state C, which is the highest. The larger margin between state A and state B, which is present by the higher verify level, allows accurate readings at state B level without directly compensating the floating gate coupling. This technique not only reduces false readings but also improves read time, since additional readouts at offset levels are only used in the selected state. In FIG. 14 only one additional sensing operation is performed. In addition to improving performance and read time, a reduced number of sensing operations reduce the complexity and size of cache circuitry needed to maintain data about adjacent memory cells when sensing a selected memory cell.

As a non-limiting example, the following reading criteria and program verify levels may be used in one embodiment when implementing the technique of FIG. In the prior art described in Figures 12A-12C, the margin between state A and state B can be expected to be about 0.7 in one exemplary system, and between state B and state C The margin is expected to be about the same. This prior art system has a Vva = 0.5V, Vvb = 2.0V, Vvc = 3.5V, Vra = 0.0V, Vrb = 1.5V, and Vrc = 3.0V when programming to and reading from the cell. Verify and read levels can be used. However, in FIG. 14, the shifted verification level for state B results in such a system having a margin between state A and state B of about 0.7 V and a state B of about 0.1 V. Have a margin between states (C). Typical readout criteria and program verify levels that can be used in FIG. 14 to achieve this margin include Vva = 0.5V, Vvb = 2.3V, Vvc = 3.5V, Vra = 0.0V, Vrb = 1.8V, Vrc = 3.0V, And Vrcl = 3.6V. In one embodiment as illustrated, the difference in read criterion and program verify level in each state remains the same when Vvb is shifted, because Vrb is shifted by the same amount. Thus, Vva-Vra = Vvb-Vrb = Vvc-Vrc.

FIG. 15 is a flow diagram illustrating one embodiment of a method of programming a nonvolatile memory to achieve a margin with non-uniform size as shown in FIG. 14. The programming method shown in FIG. 15 can be used to program a group of memory cells in parallel, such as connected to a single word line. 15 may also be used to program select memory cells of a word line, such as an even / odd bit line architecture. In one embodiment, the first iteration set from step 860 through step 882 is used to program the first logical page for the group of memory cells, and the second iteration through steps 860-882. The set can be used to program a second logical page for a group of memory cells.

The memory cells to be programmed are erased in step 850, where step 850 includes erasing more memory cells than the memory cells to be programmed (e.g., in block or other units). In step 852, soft programming is performed to narrow the distribution of erased threshold voltages for erased memory cells. Some memory cells may be in an erased state deeper than necessary as a result of the erase process. Soft programming may apply small programming pulses to move the threshold voltage of the erased memory cells closer to the erased verify level. This provides a narrow distribution for erased memory cells. In step 854 a data load command is issued by the controller 318 and input to the command circuit 314 so that data is input to the data input / output buffer 312. The input data is recognized as a command and latched by the state machine 316 via a not shown command latch signal input to the command circuit 314. In step 856, address data specifying a page address is input from a host to a row controller 306. The input data is recognized as a page address and latched through the state machine 316, which is affected by the addressed latch signal input to the command circuit 314. In step 858, a page of program data for the addressed page is input to the data input / output buffer 312 for programming. For example, 532 bytes of data may be input in an example embodiment. The input data is latched in the appropriate register for the selected bit line. In some embodiments, the data is also latched in the second register for the selected bit line to be used for the verify operation. In step 860, a program command is issued by the controller and input to the data input / output buffer 312. The command is latched by the state machine 316 via a command latch signal input to the command circuit 314.

The data triggered by the program command and latched in step 858 is programmed into selected memory cells controlled by the state machine 316. Using stamped program voltage pulses, such as those shown in the program voltage signal of FIG. 6, the program voltage signal is applied to an appropriate word line corresponding to the page or other unit of cells being programmed. In step 862, Vpgm, the programming pulse voltage level is initialized to a start pulse (e.g., 12V), and a program counter (PC), maintained by state machine 316, is initialized at zero. In step 864, a first Vpgm pulse is applied to the selected word line. If logic zero is stored in a particular data latch indicating that the corresponding memory cell should be programmed, the corresponding bit line is grounded. On the other hand, if logic 1 is stored in a particular data latch indicating that the corresponding memory cell should be maintained in the current data state, the corresponding bit line is connected to V _DD to inhibit programming.

In step 866, the state of selected memory cells is verified. Up to now, the process shown in FIG. 15 proceeds according to known techniques. However, in step 866 the process includes a novel technique for generating non-uniformly spaced margins that facilitate more accurate reading of the selection level. Larger margins are created between the two programming states. In one embodiment, larger margins are created between the lower levels, while the highest state is maintained at the nominal position. In one embodiment, verification is performed so that a larger margin exists between state B and state A. In other embodiments, the highest or higher level state can also be shifted in the positive direction by using a larger verify voltage at these levels. However, shifting the distribution to a higher positive voltage as a whole is not acceptable in some embodiments where the voltage level (eg, Vpgm) must be kept at a certain maximum level for such reasons as to minimize program disturb. .

In one embodiment, non-uniformly spaced verification levels are used in step 866 to generate non-uniform margins. As shown in FIG. 14, the verify level Vvb1 for the second programming state B is from the first programming state, i.e., the verify level for state A, to the third programming state, i. The verify level for is spaced by an amount different from the amount spaced apart from the second programming state, i.e., the verify level for state (B). Verify levels (Vva, Vvb, and Vvc) define the lowest minimum threshold voltage for their particular state. By using unequally spaced verification levels, the margin generated between state A and state B is greater than the margin generated between state B and state C.

After sensing with an applied reference voltage, it is checked whether all data latches are storing logic 1 at step 868. If so, the program process is complete and successful because all selected memory cells have been programmed and verified in their target state. The status of the pass is reported at step 876. If at step 868 it is determined that not all of the data latches are storing logic 1, the process continues at step 872 where the program counter PC is checked for a program limit value. One example of a program limit value is 20, although other values may be used in various embodiments. If the program counter PC is not less than 20, then in step 874 it is determined whether the number of unsuccessfully programmed memory cells is less than or equal to the predetermined number. If the number of unsuccessfully programmed cells is equal to or less than this number, the process is flagged as passed and the status of the pass is reported at step 876. Bits that were not successfully programmed can be corrected using error correction during the read process. If the unsuccessfully programmed memory cells are larger than the predetermined number, the program process is flagged as a failure and the status of the failure is reported at step 878. If the program counter PC is less than 20, the Vpgm level is increased by the step size, and the program counter PC is incremented at step 880. After step 880, the process returns to step 864 to apply the next Vpgm pulse.

As described, step 866 includes the use of non-uniformly spaced verify levels such that non-uniformly spaced margins exist for programmed memory cells. FIG. 16 illustrates one embodiment of step 866 of FIG. 15. In step 882, a first programming state verify level Vva is applied. In step 884, a bit line is sensed with Vva applied to the memory cell at each bit line. In step 886, the result is stored for the cells that are programmed to state A. Step 886 sets the data latch for the bit line to logic 1 indicating that programming is continuing for that memory cell, or the memory cell is at or above the target level for that memory cell. Programming may include setting to logic 0 indicating that it should be stopped. In step 888, a second programming state verify level Vvb1 is applied to each memory cell being verified. The verify level Vvb1 is spaced apart from the verify level Vva by a first amount. For example, Vva and Vvbl may be spaced apart from each other by an amount equal to about 0.8V. In step 890, the bit lines are sensed as Vvb1 applied to each memory cell. The result is stored at 892 by indicating in the data latch for each bit line whether the corresponding memory cell has reached its target level. In step 894, a third verify level Vvc is applied for the third programming state. The verify level Vvc is spaced apart from the verify level Vvb1 by a second amount different from the first amount that separates Vva and Vvb1. As shown in FIG. 14, the interval between verify levels Vvb1 and Vvc is smaller than the interval between verify levels Vva and Vvbl. In step 896, the bit line is sensed with Vvc applied to each memory cell. In step 898, the result for the cells programmed to state C is stored, for example by indicating in the data latch whether the cells should experience subsequent programming.

As shown in boxes 891 and 899, non-uniformly spaced verify levels result in a first size margin between states A and B and a second size margin between states B and C. The margin between states A and B is larger than the margin between states B and C due to the shifted Vvb verify level.

FIG. 17 is a flow diagram illustrating an overall process for reading data that is performed in response to a request to read a specified one or more pages or other data group. In other embodiments, the process of FIG. 17 may be performed as part of a data recovery operation after detecting an error in response to a conventional read process. When reading data programmed according to the process of FIGS. 12A-12C, any perturbation from floating gate coupling due to programming of the lower page of neighboring cells results in programming the upper page of that cell. Corrected. Thus, in order to compensate for the floating gate coupling effect from neighboring cells, the process only needs to consider the coupling effect due to programming of the upper page of neighboring cells.

In step 902 of Fig. 17, upper page data for a subsequently programmed word line neighboring the word line is read. If the top page of a neighboring word line is not programmed as determined in step 904, then that word line or page is read without compensating for the floating gate coupling effect in step 908. If the upper page of a neighboring word line is programmed, the page is read using a compensation for the floating gate coupling effect at step 906. In some embodiments, by reading the cells of a neighboring word line, the charge level on the neighboring word line is determined as a result, which may or may not accurately reflect the stored data.

In one embodiment, the memory array holds a set of memory cells to store one or more flags. For example, a column of memory cells can be used to store a flag indicating whether the bottom page of each row of memory cells has been programmed, and another column is the top page for each row of memory cells. Can be used to store a flag indicating whether it has been programmed. By checking the appropriate flag, it can be determined whether the upper page for the neighboring word line has been programmed. A more detailed description of these flags and the process for programming can be found in US Pat. No. 6,657,891 (Inventor: Shibata et al., Titled "Semiconductor Memory Device For Storing Multi-Valued Data") Which is incorporated herein by reference in its entirety.

FIG. 18 illustrates one embodiment of a process for reading top page data for a neighboring word line that may be used in step 902 of FIG. 17. The read reference voltage Vrc is applied to the word line in step 910, and in step 912 the bit line is sensed as described above. The result of the sensing is stored in the appropriate latch in step 914. First the read at Vrc is chosen to uniquely determine the top page data, because the bottom page data has already been written normally to WLn + 1, and the read at Vra or Vrb yields unique results. It is not guaranteed because the intermediate distribution B '(FIG. 12B) may overlap these values.

In step 916, a flag indicating upper page programming associated with the page being read is checked. If the flag was not set as determined in step 918, the process ends with the conclusion that the upper page was not programmed in step 920. If the flag is set, it is assumed that the upper page has been programmed. A read reference voltage Vrb is applied to the word line associated with the page read in step 922. In step 924, the bit lines are sensed and the result is stored in an appropriate latch in step 926. In step 928, a read reference voltage Vra is applied. In step 930, the bit line is sensed and the result is stored in the appropriate latch in step 932. In step 934, the data value stored by each of the memory cells being read is determined based on the results of the sensing steps 12, 924 and 930. The data values may be stored in an appropriate data latch at step 936 for ultimate delivery to the user. Upper page and lower page data are determined using known logic techniques that depend on the particular state encoding selected. For the example coding described in FIGS. 12A-12C, the lower page data is vrb * (complement of the value stored upon reading in Vrb), and the upper page data is Vra * OR (Vrb AND Vrc *) . Although the process of FIG. 18 has been described herein as being used to read WLn + 1, it may be used to read WLn as described below.

FIG. 19 is a flowchart illustrating an embodiment for reading data of a word line when no compensation for floating gate coupling from neighboring word lines is required (step 908 of FIG. 17). In step 950, it is determined whether the upper or lower page associated with the word line is being read. If the upper page is being read, the read reference voltage Vrb is applied to the appropriate word line at step 952. In step 954, the bit line is detected, and in step 956 the result is stored in the appropriate latch. In step 958, a flag is checked to determine whether the page contains upper page data. If no flag is set, any programmed data is in an intermediate state B '. Thus, Vrb does not produce any accurate sensing results, so the process continues at step 960 where Vra is applied to the word line. The bit line is rediscovered at step 962 and the result is stored at step 964. In step 966, the data value to be stored is determined. In one embodiment, if the memory cell is turned on and Vrb (or Vra) is applied to the word line, the lower page data is "1". If not, the bottom page data is "0".

If the page address is determined to correspond to the upper page at step 950, then the upper page reading process is performed at step 970. In one embodiment, reading the top page in step 970 includes the same method as described in FIG. 18, which includes reading a flag and three states, because an unwritten top page is read or This can be done for another reason.

20 is a flow diagram illustrating an example of a process for reading data while compensating for floating gate coupling, which may be performed, for example, at step 906 of FIG. In step 966 it is determined whether to use an offset to compensate for floating gate coupling. Step 966 is performed separately for each bit line. Data from neighboring word lines is used to determine which bit line offset needs to be used. If the neighboring cell is in state E or B, the memory cell at the word line being read does not need compensation applied during sensing. If the cell at WLn + 1 is in state E, it does not contribute to any coupling because the threshold voltage is the same as before the word line was written. If the cell at WLn + 1 is in state B, it is programmed from the intermediate state B ', which is a small change in charge, and can be ignored in most cases. The read offset is used for those cells on WLn with neighboring memory cells at WLn + 1 in state A or state C.

If at step 967 it is determined that the page being read is the lower page, then Vrb is applied to the word line associated with the page being read at step 968. Reading in Vrb is sufficient to determine the lower page data for the encoding shown in Figures 12A-12C. In step 969, the bit line is sensed, and in step 970, the result is stored in an appropriate latch for the bit lines. As shown in FIG. 14, no compensation offsets were applied at the Vrb level, so only the bottom page detection is performed at step 969. Since the cells are programmed to produce a larger margin between states A and B, accurate reading can be achieved without coupling compensation. Data for the lower page is determined at step 971. If the cell is turned on in response to Vrb, the lower page data is 1, otherwise the lower page data is 0. In step 972, the bottom page data is stored in an appropriate latch for delivery to the user.

If it is determined in step 967 that the page being read is an upper page, the upper page is read using the compensation in step 976. 21 is a flow chart illustrating upper page reading using the offset reading reference level. In step 974 of FIG. 21, a read reference voltage Vrc is applied to the word line associated with the page being read. The bit line is sensed at step 975 and the result is stored in the appropriate latch at step 976. In step 997, the sum of Vrc and an offset (e.g., 0.1V) is applied to the word line associated with the page being read. In step 978, the bit line is sensed, and in step 979 the result of the detection in step 978 is used to overwrite the result stored in step 976 for any bit line for which an offset is required. Used for overwriting. In step 980, Vrb is applied to the word line, and in step 981 the bit line is sensed. The result of the sensing at step 981 is stored at step 982. Vra is applied to the word line associated with the page read in step 983. The bit line is sensed in step 984 and the result is stored in a suitable latch in step 985. In FIG. 20, it is assumed that the naturally occurring margin between state E and state A is sufficient such that the offset associated with Vra is unnecessary. In other embodiments, offsets to Vra levels may be used. The data values are determined in steps 986 and 987 and the data values are stored in the appropriate data latches for delivery to the user. In other embodiments, the order of reading (Vrc, Vrb, Vra) may be changed.

The foregoing detailed description of the invention is provided for illustrative and illustrative purposes. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above description. In order to best explain the principles of the present invention, and to best explain the principles of its practical application, others skilled in the art of the present invention will find it suitable for various embodiments and specific uses. In order to best utilize the present invention in various modified forms contemplated, the embodiments described above have been selected. The scope of the invention is defined by the claims appended hereto.

Claims (26)

A method of reading non-volatile storage, Receiving a request to read a first nonvolatile storage element; Reading a second nonvolatile storage element in response to the request, wherein the second nonvolatile storage element is adjacent to the first nonvolatile storage element and can store data in at least four physical states; , Applying a first reference to read the first nonvolatile storage element at a level between a first programming state and a second programming state; Applying a second reference to read the first nonvolatile storage element at a level between the second programming state and the third programming state; Using the result of applying the first criterion at a first level and the result of applying the second criterion at a second level, when the second non-volatile storage element is in a first subset of the physical states, the Determining data of the first nonvolatile storage element; And When the second non-volatile storage element is in the second subset of physical states, using the result of applying the first reference at the first level and the result of applying the second reference at the third level, And determining the data of the first non- volatile storage element. The method of claim 1, The application of the first reference at the first level does not compensate for floating gate coupling between the first nonvolatile storage element and the second nonvolatile storage element, Application of the second reference at the second level does not compensate for floating gate coupling between the first nonvolatile storage element and the second nonvolatile storage element, and The application of the second reference at the third level compensates for the floating gate coupling between the first nonvolatile storage element and the second nonvolatile storage element. The method of claim 2, When the second nonvolatile storage element is in the second subset of the physical states, determining data of the first nonvolatile storage element may include: Applying a first voltage corresponding to the first reference at the first level to a control gate of the first nonvolatile storage element and sensing conduction of the first nonvolatile storage element; Applying a second voltage corresponding to the second reference at the second level to the control gate of the first nonvolatile storage element and sensing conduction of the first nonvolatile storage element; Applying a third voltage corresponding to the second reference at the third level to the control gate of the first nonvolatile storage element and sensing conduction of the first nonvolatile storage element; Is equal to the sum of the second voltage and the offset; Selecting the result of applying the first voltage, selecting the result of applying the third voltage, and ignoring the result of applying the second voltage, thereby causing the data of the first non-volatile storage element And determining the nonvolatile storage device. The method of claim 2, The offset is substantially equal to an apparent change in a threshold voltage of the first nonvolatile storage element based on the floating gate coupling between the first nonvolatile storage element and the second nonvolatile storage element. A method of reading a nonvolatile storage device. The method of claim 1, The first nonvolatile storage element is part of a set of nonvolatile storage elements connected to a first word line, the method further comprising: Programming the set of nonvolatile storage elements in a plurality of physical states including the first programming state, the second programming state, and the third programming state; Verifying whether the set of non-volatile storage elements to be programmed to the first state has reached a first target level corresponding to the first state; Verifying whether the set of nonvolatile storage elements to be programmed to the second state has reached a second target level corresponding to the second state, wherein the second target level is a first from the first target level; Spaced apart by; And verifying whether the set of nonvolatile storage elements to be programmed to the third state has reached a third target level corresponding to the third state, And wherein the third target level is spaced apart from the second target level by a second amount less than the first amount. The method of claim 1, The first subset of physical states comprises the first programming state and the third programming state, and And wherein said second subset of physical states comprises said second programming state and an erased state. The method of claim 6, The first programming state is adjacent to the erase state and the second programming state, and And said second programming state is adjacent to said first programming state and said third programming state. The method of claim 1, The second nonvolatile storage device stores upper page data and lower page data; Reading the second nonvolatile storage element in response to the request includes reading the top page data for the second nonvolatile storage element, The first level and the second level for the second reference are based on the upper page data but not the lower page data for the second non-volatile storage element, The first subset of physical states corresponds to the second non-volatile storage element storing first data for the upper page, And wherein said second subset of physical states corresponds to said second nonvolatile storage element storing second data for said upper page. The method of claim 1, The first nonvolatile storage device stores data for a first logical page and a second logical page, The second nonvolatile storage device stores data for a third logical page and a fourth logical page, The data for the second logical page stored by the first nonvolatile storage element is stored in the second nonvolatile storage after programming the data for the third logical page stored by the second nonvolatile storage element. And programmed by the device prior to programming the data stored for the fourth logical page. The method of claim 1, The first nonvolatile storage device is connected to a first word line; The second nonvolatile storage element is connected to a second word line adjacent to the first word line, Here, programming of data for nonvolatile storage elements connected to the first word line is started before programming of data for nonvolatile storage elements connected to the second word line begins. How to read volatile storage. The method of claim 1, And wherein said first non-volatile storage element is a multi-state NAND flash memory device. The method of claim 1, And wherein said first non-volatile storage element is a multi-state NAND flash memory device. The method of claim 1, The first non-volatile storage element is part of an array of flash memory devices, And said array is removable from a host system. A nonvolatile memory system, A plurality of nonvolatile storage elements capable of storing data in at least four physical states; And a management circuit in communication with the plurality of nonvolatile storage elements, The management circuitry receives a request to read a first nonvolatile storage element, and in response to the request reads a second nonvolatile storage element adjacent to the first nonvolatile storage element, The management circuit applies a first reference to read the first nonvolatile storage element at a level between a first programming state and a second programming state, and a level between the second programming state and the third programming state. Read the first nonvolatile storage element by applying a second reference to read the first nonvolatile storage element at The management circuit uses the result of applying the first criterion at a first level and the result of applying the second criterion at a second level, such that the second nonvolatile storage element is assigned to the first subset of physical states. When present, determine the data of the first nonvolatile storage element, The management circuit uses the result of applying the first criterion at the first level and the result of applying the second criterion at a third level, such that the second non-volatile storage element has a second subset of the physical states. And when at, determine the data of the first non- volatile storage element. The method of claim 14, The application of the first reference at the first level does not compensate for floating gate coupling between the first nonvolatile storage element and the second nonvolatile storage element, Application of the second reference at the second level does not compensate for floating gate coupling between the first nonvolatile storage element and the second nonvolatile storage element, and The application of the second reference at the third level compensates for the floating gate coupling between the first nonvolatile storage element and the second nonvolatile storage element. The method of claim 15, The management circuit, By applying a first voltage corresponding to the first reference at the first level to a control gate of the first nonvolatile storage element and sensing conduction of the first nonvolatile storage element; By applying a second voltage corresponding to the second reference at the second level to the control gate of the first nonvolatile storage element and sensing conduction of the first nonvolatile storage element; By applying a third voltage corresponding to the second reference at the third level to the control gate of the first nonvolatile storage element and sensing conduction of the first nonvolatile storage element, the third voltage is Equal to the sum of the second voltage and the offset; By selecting the result of applying the first voltage, selecting the result of applying the third voltage, and ignoring the result of applying the second voltage, And determine the data of the first nonvolatile storage element when the second nonvolatile storage element is in the second subset of the physical states. The method of claim 15, The offset is substantially equal to an apparent change in threshold voltage of the first nonvolatile storage element based on the floating gate coupling between the first nonvolatile storage element and the second nonvolatile storage element. Volatile Memory System. The method of claim 14, The first nonvolatile storage element is part of a set of nonvolatile storage elements connected to a first word line, and the management circuitry includes: Program the set of non-volatile storage elements into a plurality of physical states including the first programming state, the second programming state, and the third programming state; Verify whether the set of non-volatile storage elements to be programmed to the first state has reached a first target level corresponding to the first state; Verify whether the set of nonvolatile storage elements to be programmed to the second state has reached a second target level corresponding to the second state, wherein the second target level is a first amount from the first target level; Spaced apart by; Verify whether the set of nonvolatile storage elements to be programmed to the third state has reached a third target level corresponding to the third state, Wherein the third target level is spaced apart from the second target level by a second amount less than the first amount. The method of claim 14, The first subset of physical states comprises the first programming state and the third programming state, and And the second subset of physical states comprises the second programming state and an erase state. The method of claim 19, The first programming state is adjacent to the erase state and the second programming state, and And the second programming state is adjacent to the first programming state and the third programming state. The method of claim 14, The second nonvolatile storage device stores upper page data and lower page data; Reading the second nonvolatile storage element in response to the request includes reading the top page data for the second nonvolatile storage element, The first level and the second level for the second reference are based on the upper page data but not the lower page data for the second non-volatile storage element, The first subset of physical states corresponds to the second non-volatile storage element storing first data for the upper page, And the second subset of physical states corresponds to the second non- volatile storage element storing second data for the upper page. The method of claim 14, The first nonvolatile storage device stores data for a first logical page and a second logical page, The second nonvolatile storage device stores data for a third logical page and a fourth logical page, The data for the second logical page stored by the first non-volatile storage element is determined after programming the data for the third logical page stored by the second non-volatile storage element and the second. And program the data stored for the fourth logical page prior to programming by the nonvolatile storage element. The method of claim 14, The first nonvolatile storage device is connected to a first word line; The second nonvolatile storage element is connected to a second word line adjacent to the first word line, Here, programming of data for nonvolatile storage elements connected to the first word line is started before programming of data for nonvolatile storage elements connected to the second word line begins. Volatile Memory System. The method of claim 14, And said first non-volatile storage element is a multi-state NAND flash memory device. The method of claim 14, And said first non-volatile storage element is a multi-state NAND flash memory device. The method of claim 14, The first non-volatile storage element is part of an array of flash memory devices, And said array is removable from a host system.

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