TWI450089B - System and method for testing hard disk ports of a motherboard - Google Patents

Description

Motherboard multi-hard disk test system and method

The invention relates to a motherboard multi-hard disk test system and method.

After the motherboard is assembled, it undergoes a full functional test, including testing of various defects on the motherboard. At present, there are usually multiple SATA/SAS (SATA: Serial Advanced Technology Attachment, SAS: Serial Attached SCSI, Serial Attached SCSI Interface) hard disk drives on the motherboard, after PCI-E (PCI Express). After the expansion card is expanded, it is dozens of flaws, and the network storage device has more hard drives. The general practice of testing these flaws is that the tester attaches all hard drives to the hard drive for functional testing. If each hard disk drive uses a hard disk as the test device, one is because the price of the hard disk is generally higher, and the second is that the hard disk is too large for the test device to be inconvenient to maintain, the third is the loss, and the fourth is that the hard disk is vulnerable. Vibration affects the test results. At the same time, if the testers test each other one by one, they need to re-plug the hard disk after each test, and restart the test program, which will cause cost and time waste in mass production applications.

In view of the above, it is necessary to provide a motherboard multi-hard disk test system and method.

The motherboard multi-hard disk test system for testing a plurality of hard disks of the motherboard to be tested, the plurality of hard disks of the motherboard to be tested and the plurality of hard disks of one test device The test device further includes a MUX (Multiplexer) chip, a storage device, and a pointing device. The system includes: a switching channel module, configured to translate the to-be-tested nickname of the motherboard to be tested into a corresponding MUX chip. The channel number is connected to the storage device by switching the channel corresponding to the channel number in the MUX chip to form a data transmission path from the motherboard to be tested to the storage device; and writing the verification data module, when the storage device is connected to the MUX chip After the data transmission path is used, the verification data is written into the storage device; and the verification data module is used to read the written verification data from the storage device via the data transmission path. The test board is used to verify whether the check data read and read is consistent; the sending module is used to pass the I/O when the check data written and read are inconsistent MUX chip The MUX chip displays the information of the abnormality to be tested according to the information driving indication device according to the information; the transmitting module is further configured to pass the I/O direction when the verification data written and read is consistent The MUX chip sends the normal information to be tested, and the MUX chip drives the pointing device to display the normal information to be tested according to the information; the data module is erased, and when the verified data written and read is consistent, the data is erased and stored. The verification data written in the device.

A motherboard multi-hard disk test method includes the following steps: (a) selecting a test target from a plurality of hard disks of the motherboard to be tested, and translating the nickname into a channel number corresponding to the MUX chip in the test device (b) MUX chip switching and the channel corresponding to the channel number are connected to the storage device of the test device to form a data transmission path from the motherboard to be tested to the storage device; (c) when the storage device is connected to the MUX chip, The MUX chip drive indicating device displays the nickname of the to-be-tested device; (d) the motherboard to be tested writes the verification data to the storage device via the data transmission path and stores it; (e) the motherboard to be tested passes through the data transmission path The verification data is read from the storage device; (f) when the verification data written and read is inconsistent, the test is ended; (g) when the verification data written and read is identical, the write storage device is erased. (h) when the motherboard to be tested has an untested hard disk, return to step (a), when all the hard disks of the motherboard to be tested are tested, the indicating device is displayed to be tested. Motherboard test IT success.

Compared with the prior art, the present invention can automatically test all the SATA/SAS hard disks of the motherboard at one time, and does not affect the test effect due to the vibration of the hard disk during the test, thereby saving the cost and time of the test.

FIG. 1 is an architectural diagram of a preferred embodiment of a multi-hard disk test system for a motherboard of the present invention. The motherboard multi-hard disk test system 10 runs on the host 1, and the host board 11 to be tested in the host 1 is connected to the test device 2. The test device 2 includes a MUX chip 21, a storage device 22, an I/O port 25, an I/O port conversion module 24, a pointing device 23, and a SATA/SAS port containing at least one SATA/SAS port. Group 20. The pointing device 23 is driven by the MUX wafer 21. Wherein, each of the SATA/SAS group 20 has a corresponding number in the order of arrangement, and six 埠 are taken as an example in the figure; the number of channels of the MUX chip 21 can be customized according to the number of turns actually required to be tested, and The wafer channels are also numbered in the order in which they are arranged.

As shown in FIG. 2, it is a schematic diagram of the connection mode between the motherboard to be tested and the hard disk of the test device. All the SATA in the SATA/SAS 埠 group 12 of the motherboard 11 to be tested (the 埠 also has a corresponding number in the order, 6 埠 in the figure as an example) and the SATA in the SATA/SAS 埠 group 20 of the test device 2 Connected, the connection mode is a one-to-one correspondence, for example, the 埠A1 of the motherboard 11 to be tested is connected to the 埠B1 of the test device 2, the 埠A2 of the motherboard 11 to be tested is connected to the 埠B2 of the test device 2, and so on. . The SATA in the SATA/SAS group 20 of the testing device 2 is connected to the channel of the MUX chip 21 (the six channels in the figure are taken as an example), and the connection mode is that the apostrophe corresponds to the channel number one by one, such as a test device. The 埠C1 of 2 is connected to the channel D1 of the MUX wafer 21, the 埠C2 of the test device 2 is connected to the channel D2 of the MUX wafer 21, and so on. The MUX wafer 21 is connected to the storage device 22.

As shown in FIG. 1 and FIG. 2, the motherboard multi-hard disk test system 10 selects the nickname to be tested from the SATA/SAS group 12, and translates the nickname into the channel number corresponding to the MUX chip 21, and then The channel number is transmitted to the I/O埠 conversion module 24 via the I/O port 13 of the motherboard 11 to be tested and the I/O port 25 of the test device 2, and the I/O埠 conversion module 24 receives the channel. The channel number obtained is converted into a control signal of the MUX chip 21, such as an I2C (Inter-Integrated Circuit) or an SPI (Serial Peripheral Interface) signal to switch the MUX chip. The channel of 21 is connected to the storage device 22 to form a data transmission path for transferring data from the motherboard 11 to be tested to the storage device 22.

The motherboard multi-drive test system 10 stores the verification data in the storage device 22 via the selected nickname and the channel of the MUX wafer 21. The storage device 22 is equivalent to a hard disk for storing verification data, which may be an SSD (Solid, Solid State Drive) or an HDD (Hard Disk Drive).

After the switching channel succeeds, the control signal of the MUX chip 21 controls the indicating device 23 to indicate the nickname currently being tested, and indicates the currently being tested according to the verification result of the verification data by the motherboard multi-hard disk testing system 10. If the 埠 is normal, it is also possible to control the pointing device 23 to display the information that all the cockroaches have been tested. In this embodiment, the indicating device 23 can be a seven-segment LED (Light Emitting Diode) digital tube, and the displayed value indicates the nickname being tested. For example, the display value flashes to indicate that the current test is being performed.埠 Abnormal, the value stability indicator is displayed as normal, and then “∟” or other non-numeric marks indicate that all 埠 has been tested.

As shown in FIG. 3, it is a functional module diagram of the multi-hard disk test system of the motherboard of the present invention. The motherboard multi-hard disk test system 10 includes: a switch channel module 101, a detection channel module 102, a write verification data module 103, a read verification data module 104, a verification module 105, and a transmission module 106. And erasing the data module 107.

The switching channel module 101 is configured to switch the corresponding channel of the MUX chip 21 connected to the device to be tested to be connected to the storage device 22. In this embodiment, the switching channel module 101 translates the to-be-measured nickname selected from the SATA/SAS group 12 into the channel number corresponding to the MUX chip 21, and passes the I/O 埠 13 of the motherboard 11 to be tested. And the I/O port 25 of the test device 2 transmits the channel number to the I/O埠 conversion module 24, and the I/O埠 conversion module 24 converts the channel number into a control signal of the MUX chip 21. For example, an I2C or SPI control signal is used to control the MUX chip 21 to switch the channel to the storage device 22. Thereby, a data transmission path from the motherboard 11 to be tested to the storage device 22 is formed.

The detection channel module 102 is configured to detect whether the storage device 22 of the test device 2 is connected. In the preferred embodiment, if the connection is good, the host 1 will indicate one more removable disk and continue testing; if not connected , then host 1 has no indication and the test fails. In other embodiments, it may be otherwise indicated whether the storage device 22 is connected to the MUX wafer 21. When the storage device 22 is connected to the MUX wafer 21, the MUX wafer 21 drives the pointing device 23 to display the nickname currently being tested.

The write verification data module 103 is configured to send a write command to the storage device 22, and the write command passes through the formed data transmission path, that is, one to be tested and corresponding to the selected one from the SATA/SAS group 12. The SATA/SAS port of the test device 2 is transferred to the storage device 22 via the channel switched by the MUX chip 21 and stored.

The read check data module 104 is configured to send a read command to the storage device 22 to read the check data just written into the storage device 22, and the read command passes the check data from the storage device 22 through the data transfer path. read out.

The verification module 105 verifies whether the defect to be tested is normal by comparing whether the verification data read from the storage device 22 and the verification data written to the storage device 22 are identical.

The transmitting module 106 is configured to send the MUX chip 21 the normal or abnormal information currently being tested. In this embodiment, when the verification module 105 verifies that the written and read verification data are consistent, the sending module 106 transmits the current test normal information to the I/O埠13 and the I/O埠25 to An I/O conversion module 24, the I/O conversion module 24 converts information into a control signal of the MUX chip 21 to control the MUX chip 21 to drive the indication device 23 to stably display the nickname currently being tested. The current test is normal. On the other hand, when the verification module 105 verifies that the written data is inconsistent with the read verification data, the sending module 106 transmits the current test abnormal information to the I/O conversion module 24, and the I/O conversion mode. The group 24 converts the information into control signals of the MUX wafer 21 to drive the pointing device 23 to flash the nickname currently being tested to indicate the current test 埠 anomaly. After the switching channel module 101 has switched all the channels of the MUX chip 21, the transmitting module 106 sends an end signal through the I/O port 13 of the motherboard 11 to be tested and the I/O port 25 of the testing device 2. And to the I/O conversion module 24, the I/O conversion module 24 converts the end signal into a control signal of the MUX chip 21, and controls the MUX chip 21 to drive the indication device 23 to display a non-value symbol such as "∟" The symbol indicates that all 埠 has been tested.

The erasure data module 107 is used to erase the verification data in the storage device 22. When the verification module 105 verifies that the written and read verification data are consistent, that is, after the current test function is normal, the erase data module 107 sends a delete command to erase the write and store verification in the storage device 22. data.

As shown in FIG. 4, it is a flowchart of a preferred embodiment of the multi-hard disk test method for the motherboard of the present invention.

In step S201, the switching channel module 101 selects a to-be-tested one from the SATA/SAS group 12 of the motherboard 11 to be tested, and the switching channel module 101 translates the to-be-tested nickname into a channel number corresponding to the MUX chip 21. The channel number is transmitted to the I/O埠 conversion module 24 via the I/O port 13 of the motherboard 11 to be tested and the I/O port 25 of the test device 2, and the I/O埠 conversion module 24 will The channel number is converted into a control signal of the MUX chip 21, such as an I2C or SPI control signal, to switch the channel of the MUX chip 21 to the storage device 22 to form a data transmission from the motherboard 11 to the storage device 22 to be tested. path.

In step S202, the detection channel module 102 detects whether the storage device 22 and the MUX wafer 21 are connected. In this embodiment, if it is connected, the host indicates one more removable magnetic disk, and proceeds to step S203; if not, the host does not have any indication, and proceeds to step S208, and the test fails.

In step S203, the MUX chip 21 drives the pointing device 23 to display the nickname of the test to be tested.

In step S204, the write verification data module 103 sends a write command to the storage device 22, and the write command writes the verification data to the storage device 22 through the data transmission path formed in step S201 and stores it.

Step S205, the read verification data module 104 sends a read command to the storage device 22, and the read command re-sends the verification data just written into the storage device 22 from the path of the transmission data formed in step S201. The storage device 22 is read out to the motherboard 11 to be tested.

In step S206, the verification module 105 verifies whether the test target is normal by comparing whether the check data read from the storage device 22 and the check data written to the storage device 22 are consistent. When the verification module 105 verifies that the written and read verification data is inconsistent, the process goes to step S207; if it is consistent, that is, the currently tested function is normal, the process goes to step S209.

In step S207, the sending module 106 sends the current test 埠 abnormal information to the I/O 埠 conversion module 24 through the I/O 埠 13, I/O 埠 25, and the I/O 埠 conversion module 24 converts the information. The control signal of the MUX chip 21 is used to drive the pointing device 23 to flash the nickname currently being tested to indicate the current test 埠 abnormality, and proceeds to step S208 to indicate that the test has failed and ends the test.

Step S209, the sending module 106 sends the current test normal information to the I/O埠 conversion module 24 through the I/O埠13, I/O埠25, and the I/O埠 conversion module 24 converts the information. The control signal of the MUX chip 21 is used to drive the pointing device 23 to stably display the nickname currently being tested to indicate that the current test is normal.

In step S210, the erasure data module 107 sends a delete command to erase the verification data written and stored in the storage device 22.

In step S211, if there are untested defects in the SATA/SAS group 12, the process returns to step S201. If all the ports in the SATA/SAS group 12 are tested, the process proceeds to step S212, and the test is successful, and the transmission module 106 is sent. The tested information is sent to the I/O埠 conversion module 24 through the I/O埠13 and the I/O埠25, and the I/O埠 conversion module 24 converts the information into the control of the MUX chip 21. The signal is used to drive the pointing device 23 to indicate all the information that has been tested.

In step S204, when the verification data cannot be written, the test system is exited and the test fails.

In step S205, when the verification data cannot be read, the test system is exited and the test fails.

In step S210, when the verification data cannot be erased, the test system is exited and the test fails.

It should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, and the present invention is not limited thereto. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that Modifications or equivalents are made without departing from the spirit and scope of the invention.

1. . . Host

11. . . Host board to be tested

12,20. . . SATA/SAS group

13,25. . . I/O埠

2. . . Test device

twenty one. . . MUX chip

twenty two. . . Storage device

twenty three. . . Indicator device

twenty four. . . I/O埠 conversion module

10. . . Motherboard multi-hard disk test system

101. . . Switching channel module

102. . . Detection channel module

103. . . Write verification data module

104. . . Read verification data module

105. . . Verification module

106. . . Sending module

107. . . Erase data module

1 is a block diagram of a preferred embodiment of a multi-hard disk test system for a motherboard of the present invention.

FIG. 2 is a schematic diagram showing the connection manner between the motherboard to be tested and the hard disk of the test device.

FIG. 3 is a functional block diagram of a multi-hard disk test system for a motherboard of the present invention.

4 is a flow chart of a preferred embodiment of a multi-hard disk test method for a motherboard of the present invention.

10. . . Motherboard multi-hard disk test system

101. . . Switching channel module

102. . . Detection channel module

103. . . Write verification data module

104. . . Read verification data module

105. . . Verification module

106. . . Sending module

107. . . Erase data module

Claims (10)

A motherboard multi-hard disk test system for testing a plurality of hard disks of a motherboard to be tested, wherein a plurality of hard disks of the motherboard to be tested are connected to a plurality of hard disks of a test device, The testing device also includes a MUX chip, a storage device, and a pointing device, the system comprising:
The switching channel module is configured to translate the to-be-tested nickname of the motherboard to be tested into a channel number corresponding to the MUX chip, and switch the channel corresponding to the channel number in the MUX chip to be connected with the storage device to form a host from the host to be tested. The data transfer path from the board to the storage device;
Writing a verification data module, after the storage device is connected to the MUX chip, the verification data is written into the storage device through the above data transmission path;
The check data module is configured to read the written verification data from the storage device to the motherboard to be tested via the data transmission path;
a verification module for verifying whether the verification data written and read by the above is consistent;
a sending module, configured to send, by the I/O, the information of the abnormality to be tested to the MUX chip when the verification data written and read is inconsistent, and the MUX chip displays the abnormality to be tested according to the information driving indication device. News;
The transmitting module is further configured to send normal information to be tested to the MUX chip through the I/O when the verification data written and read is consistent, and the MUX chip displays the normal to be tested according to the information driving indication device. And the erasing data module, when the verification data written and read is consistent, the verification data written in the storage device is erased. The motherboard multi-hard disk test system according to claim 1, wherein the MUX chip drive prompting device displays the current test nickname after being connected to the storage device. The motherboard multi-hard disk test system according to claim 1, wherein the test device further comprises an I/O埠 conversion module, and the I/O埠 conversion module is I/ from the motherboard to be tested. O埠 receives the translated channel number and converts the channel number into a control signal of the MUX chip, and the MUX chip switches the channel according to the control signal. The motherboard multi-hard disk test system according to claim 3, wherein the sending module is further configured to: when the hard disk of the motherboard to be tested is tested, pass the I/O to the MUX. The chip transmits the test completed information, and the I/O conversion module converts the information into a control signal of the MUX chip, and the MUX chip drives the indication device to display the tested information according to the control signal. The motherboard multi-hard disk test system according to claim 1, wherein the storage device is a solid state hard disk or a hard disk drive. A method for testing a hard disk of a motherboard, the method comprising the following steps:
(a) selecting one to be tested from the plurality of hard disks of the motherboard to be tested, and translating the apostrophe into a channel number corresponding to the MUX chip in the test device;
(b) MUX chip switching the channel corresponding to the channel number is connected with the storage device of the testing device to form a data transmission path from the motherboard to be tested to the storage device;
(c) after the storage device is connected to the MUX chip, the MUX wafer drive indicating device displays the nickname of the to-be-tested device;
(d) the motherboard to be tested writes the verification data to the storage device via the above data transmission path and stores it;
(e) the motherboard to be tested reads the verification data from the storage device via the above data transmission path;
(f) when the written and read verification data are inconsistent, the test is ended; or (g) when the verification data is written and read, the verification data written to the storage device is erased;
(h) When the motherboard to be tested has an untested hard disk, return to step (a), or when the hard disk of the motherboard to be tested is tested, display the test board to be tested by the indicating device. Successful information. The method for testing a multi-hard disk of a motherboard according to claim 6 of the patent application, the method further comprising: before step (a):
The plurality of hard disks of the motherboard to be tested are connected to the plurality of hard disks of the test device one by one. The method for testing a hard disk of a motherboard according to item 6 of the patent application, wherein the step (b) comprises:
The I/O埠 conversion module of the test device receives the translated channel number from the I/O埠 of the motherboard to be tested;
The I/O埠 conversion module converts the channel number into a control signal of the MUX chip;
The MUX chip switches the channel number to be connected to the storage device according to the control signal. The method for testing a multi-hard disk of a motherboard according to item 8 of the patent application, the step (f) further includes:
The motherboard to be tested sends the information of the abnormality to be tested to the I/O埠 conversion module;
The I/O埠 conversion module converts the information into a control signal of the MUX chip;
The MUX chip drives the pointing device to display an abnormal nickname to be tested according to the control signal. The method for testing a multi-hard disk of a motherboard according to claim 8 of the patent application, wherein the step (g) further comprises:
The motherboard to be tested sends the normal information to be tested to the I/O conversion module;
The I/O埠 conversion module converts the received information into a control signal for the MUX chip;
The MUX chip drives the pointing device to display a normal nickname to be tested according to the control signal.