TWI449144B - Semiconductor package and its substrate - Google Patents

Description

Semiconductor package and substrate thereof

The present invention relates to a semiconductor package and a substrate thereof, and more particularly to a semiconductor package for improving reliability and a substrate thereof.

Compared to the Wire Bond technology, the Flip Chip Package is characterized in that the electrical connection between the semiconductor wafer and the package substrate is transmitted through the solder bumps instead of the usual gold wires. At present, the surface of the semiconductor wafer has an electronic pad, and the package substrate also has a corresponding electrical contact pad. A solder bump can be appropriately disposed between the semiconductor wafer and the package substrate, so that the semiconductor wafer is The active face down mode is disposed on the package substrate, wherein the solder bumps provide electrical input/output (I/O) and mechanical connection between the semiconductor wafer and the package substrate.

In the general flip chip process, conductive bumps are formed on the electrode pads of the semiconductor wafer, and metal bumps are formed on the electrical contact pads of the package substrate, and the bumps are connected to facilitate the semiconductor wafer and the package. Alignment bonding of the two substrates; then, soldering the conductive bumps to the metal bumps on the electrical contact pads of the corresponding package substrate under a solder reflow temperature condition sufficient to melt the conductive bumps, Thereby solder bumps are formed. Thereafter, a primer is used to couple the semiconductor wafer to the package substrate to ensure the integrity and reliability of the electrical connection between the semiconductor wafer and the package substrate.

Please refer to FIGS. 1A to 1F for a schematic cross-sectional view of a conventional semiconductor wafer 1.

As shown in FIG. 1A, an insulating layer 10 is formed on a substrate body 1a having a plurality of pads 100, and the insulating layer 10 exposes each of the pads 100.

As shown in FIG. 1B, a first insulating protective layer 11 is formed on the insulating layer 10, and a plurality of first openings 110 are formed on the first insulating protective layer 11 so that the pads 100 are exposed to each other. Each of the first openings 110.

As shown in FIG. 1C, a metal layer 12 is formed on the pad 100 in the first opening 110 and extends onto the surface of the first insulating protective layer 11. The metal layer 12 can be sequentially divided into a titanium layer 120 and a copper layer 121.

As shown in FIG. 1D, a second insulating protective layer 13 is formed on the metal layer 12, and the second insulating protective layer 13 is formed on the second opening 130, so that the second insulating protective layer 13 is sweet. The shape of the ring is such that the metal layer 12 is exposed to the second opening 130.

As shown in FIG. 1E, a photoresist layer 14 is formed on the second insulating protective layer 13, and the photoresist layer 14 is formed with an opening 140 to expose the metal layer 12 in the second opening 130. Next, a conductive bump 15 is formed on the metal layer 12 in each of the openings 140 by electroplating.

As shown in FIG. 1F, the photoresist layer 14 and the underlying metal layer 12 are removed and a dicing process is performed to diced the semiconductor wafer 1 into a plurality of semiconductor wafers. Then, the conductive bumps 15 are reflowed, and the semiconductor wafer is flip-chip bonded to a package substrate (not shown) by the conductive bumps 15'.

However, in the conventional semiconductor wafer 1, the occupied area of the first insulating protective layer 11 and the occupied area of the second insulating protective layer 13 are too large, so that uneven stress is likely to occur, resulting in the second insulating protective layer. 13 peeling occurred.

Therefore, how to overcome the problems of the above-mentioned prior art has become a problem that is currently being solved.

In view of the above-mentioned deficiencies of the prior art, the present invention provides a semiconductor substrate, comprising: a substrate body having a plurality of pads; a first insulating protective layer formed on the substrate body, and the first insulating protective layer is defined a plurality of corresponding opening pads corresponding to the solder pads, wherein the first insulating protective layer in each of the opening regions forms a first opening for exposing the solder pads, and the first insulation protection outside the opening regions a groove is formed on the surface of the layer to surround the first opening in the opening region; a metal layer is formed on the opening region of the first insulating protective layer and extends to be exposed to each of the first a second insulating protective layer is formed on the metal layer, and a plurality of second openings are formed to expose a portion of the surface of the metal layer to the second opening; and the plurality of conductive bumps The block is disposed on the metal layer exposed in the second opening.

The present invention further provides a semiconductor substrate comprising: a substrate body; a line build-up structure disposed on the substrate body, the line build-up structure having a plurality of pads; and a first insulating protective layer formed on the line build-up layer Structurally, the first insulating protective layer defines a plurality of opening regions corresponding to the bonding pads, and the first insulating protective layer in each of the opening regions forms a first opening for exposing the bonding pad, and a groove is formed on a surface of the first insulating protective layer outside the opening area to surround the first opening in the opening area; and a metal layer is formed in the opening of the first insulating protective layer And extending to a solder pad exposed in each of the first openings; a second insulating protective layer is formed on the metal layer, and a plurality of second openings are formed to expose a part of the surface of the metal layer And the plurality of conductive bumps are disposed on the metal layer exposed in the second opening.

The present invention further provides a semiconductor package, comprising: a substrate body having a plurality of pads; a first insulating protective layer formed on the substrate body, wherein the first insulating protective layer defines a plurality of corresponding pads a first opening for exposing the pad, and a groove for forming a surface of the first insulating protective layer outside the opening region is formed on the first insulating protective layer in each of the opening regions The metal layer is formed on the opening region of the first insulating protective layer and extends to the solder pads exposed in each of the first openings; a second insulating protective layer is formed on the metal layer, and a plurality of second openings are formed to expose a portion of the surface of the metal layer to the second opening; the plurality of conductive bumps are exposed to the respective a metal substrate on the second opening; a package substrate is bonded to the conductive bump; and a glue is formed between the first insulating protective layer and the package substrate to cover the conductive bump, A portion of the colloid is formed in the groove.

The present invention further provides a semiconductor package comprising: a substrate body; a line build-up structure disposed on the substrate body, the line build-up structure having a plurality of pads; and a first insulating protective layer formed on the line The first insulating protective layer defines a plurality of opening regions corresponding to the bonding pads, and the first insulating protective layer in each of the opening regions forms a first opening for exposing the bonding pad, and a groove is formed on a surface of the first insulating protective layer outside the opening area to surround the first opening in the opening area; a metal layer is formed on the first insulating protective layer And a second insulating protective layer is formed on the metal layer, and a plurality of second openings are formed to make a part of the surface of the metal layer Exposed to the second opening; the plurality of conductive bumps are disposed on the metal layer exposed in each of the second openings; the package substrate is bonded to the conductive bump; and the colloid is formed on the first An insulating protective layer and the package substrate are Covering the conductive bump, and forming a portion of the colloid in the recess.

In the above semiconductor package and the substrate thereof, the line build-up structure may have at least one dielectric layer, a circuit layer formed on the dielectric layer, and a dielectric layer formed in the dielectric layer and electrically connected to the circuit layer. The plurality of conductive blind vias have a pad, and the first insulating protective layer is formed on the wiring layer and the dielectric layer.

In the foregoing semiconductor package and the substrate thereof, an insulating layer may be formed on the substrate body.

In the foregoing semiconductor package and the substrate thereof, the metal layer may include a first metal layer and a second metal layer, the first metal layer is partially buried in the first insulating protective layer, and the second metal layer is Formed on the first metal layer.

In addition, in the foregoing semiconductor package and the substrate thereof, the aperture of the second opening may be smaller than the projection width of the opening area.

It can be seen that the semiconductor package of the present invention and the substrate thereof are formed by forming a groove around the outside of the opening region, that is, forming the groove on the surface of the first insulating protective layer around the conductive bump. The difference in the occupied area between the first insulating protective layer and the second insulating protective layer in the opening region is reduced to avoid the problem that the second insulating protective layer is peeled off due to uneven stress.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper" and "one" as used in the specification are merely for convenience of description, and are not intended to limit the scope of the invention, and the relative relationship is changed or adjusted. Substantially changing the technical content is also considered to be within the scope of the invention.

2A to 2F are schematic cross-sectional views showing a first embodiment of the method of fabricating the semiconductor substrate 2 of the present invention.

As shown in FIG. 2A, an insulating layer 20 is formed on a substrate body 2a having a plurality of first pads 200, and the insulating layer 20 exposes the first pads 200.

In this embodiment, the substrate body 2a is a wafer, and in other embodiments, the substrate body 2a may also be a germanium substrate or a glass substrate.

Furthermore, the material of the first pad 200 may be aluminum, and the material of the insulating layer 20 may be tantalum nitride (SiN) or tantalum oxygen compound (SiO _x ) as a passivation layer. .

Moreover, since the processes performed on each of the first pads 200 are the same, only a single first pad 200 is shown in the drawings.

As shown in FIG. 2B, a first insulating protective layer 21 is formed on the insulating layer 20, and the surface of the first insulating protective layer 21 defines an opening region A corresponding to the first pad 200.

Then, a plurality of first openings 210 are formed in the opening region A of the first insulating protective layer 21 through the lithography process, so that the first pads 200 are correspondingly exposed to the first openings 210. At the same time, the recess 211 is formed outside the opening area A of the first insulating protective layer 21, so that the first insulating protective layer 21 has a donut shape, and the recess 211 surrounds the first opening 210.

In this embodiment, the material of the first insulating protective layer 21 may be Polyimide (PI), Benezocy-clobutene (BCB) or Polybenzoxazole (PBO).

Moreover, the range of the opening area A can be varied as needed, approximately around the position of the first pad 200 or the area surrounded by the groove 211. The groove 211 may be a continuous groove or a discontinuous groove. The shape of the groove may be a circle, a square or a polygon, and a plurality of grooves 211 may be arranged in a concentric manner.

As shown in FIG. 2C, a metal layer 22 is formed on the first pad 200 in the first opening 210 and extends to the surface of the opening region A of the first insulating protective layer 21, and extends to the opening region. A is external to the surface of the first insulating protective layer 21.

In the present embodiment, the metal layer 22 is used as an under bump metallization (UBM) and can be divided into a first metal layer 220 and a second metal layer 221. The material forming the first metal layer 220 may be titanium (Ti), and the material forming the second metal layer 221 may be copper (Cu).

As shown in FIG. 2D, a second insulating protective layer 23 is formed on the metal layer 22 of the opening region A, and the second insulating protective layer 23 is formed on the second opening 230 to protect the second insulating layer. The layer 23 is in the shape of a donut and a portion of the surface of the metal layer 22 is exposed to the second opening 230.

In this embodiment, the metal layer 22 can also serve as a current conducting path required for the metal plating material to be described later, and the material of the second insulating protective layer 23 can be made of polyimide (PI) or benzocyclobutene. Benezocy-clobutene (BCB) or Polybenzoxazole (PBO).

Moreover, the aperture d of the second opening 230 is smaller than the projection width of the opening area A (ie, the width of the label A in the figure) or the aperture D of the first opening 210.

As shown in FIG. 2E, a photoresist layer 24 is formed on the second insulating protective layer 23, and the photoresist layer 24 is formed with an opening 240 to expose the metal layer 22 in the second opening 230. Next, a conductive bump 25 is formed on the metal layer 22 in the opening 240 by electroplating.

In this embodiment, the material forming the conductive bumps 25 may be a solder material.

As shown in FIG. 2F, the photoresist layer 24 and the underlying metal layer 22 are removed, and the recess 211 is exposed to form a semiconductor substrate 2 having a recess 211 around the conductive bump 25.

In the method of the present invention, the first insulating protective layer 21 is formed with a recess 211 in the periphery of the opening region A, so that the first insulating protective layer 21 and the second insulating protective layer 23 are in a donut shape. The occupied area of the first insulating protective layer 21 and the second insulating protective layer 23 in the opening area A are approximately equal, so that the method of the present invention can make the first and the lower side of the conductive bump 25 compared with the prior art. The stress of the second insulating protective layers 21, 23 is uniformly dispersed to avoid the problem that the second insulating protective layer 23 is peeled off.

Further, as shown in Fig. 2F', it is a schematic cross-sectional view showing a second embodiment of the method for fabricating the semiconductor substrate 2' of the present invention. The difference between this embodiment and the first embodiment is only in the addition of the line build-up structure, and other related processes are substantially the same, and therefore will not be described again.

In this embodiment, the substrate body 2a has at least one first bonding pad 200, and the insulating layer 20 is formed on the substrate body 2a and exposes the first bonding pads 200 on the insulating layer 20. A line buildup structure 26 is formed.

In addition, the circuit build-up structure 26 has at least one dielectric layer 260, a circuit layer 261 formed on the dielectric layer 260, and a dielectric layer 260 formed in the dielectric layer 260 and electrically connected to the circuit layer 261 and the first The plurality of conductive vias 262 of the pad 200, the circuit layer 261 has a second pad 263, and the first insulating layer 21 is formed on the dielectric layer 260 and the circuit layer 261 to make the second The pad 263 corresponds to the first opening 210 exposed to the first insulating protective layer 21.

For the process of the subsequent fabrication of the conductive bumps 25', reference may be made to the steps of the second embodiment of the first embodiment, and therefore no further details are provided.

Referring to FIG. 3, a second singulation process is performed to cut the semiconductor substrate 2 into a plurality of semiconductor wafers, and the conductive bumps 25 are reflowed to make the semiconductor wafers pass the conductive bumps 25'. The flip chip is bonded to a package substrate 30, and a colloid 31 is formed between the first insulating protective layer 21 and the package substrate 30 to serve as a primer and to cover the conductive bump 25', and a part of the colloid 31 is formed. In the recess 211, a semiconductor package 3 is formed.

The present invention provides a semiconductor substrate 2 including a substrate body 2a having a first bonding pad 200, a first insulating protective layer 21 formed on the substrate body 2a, and a metal layer 22 formed on the first bonding pad 200. a second insulating protective layer 23 formed on the metal layer 22, and a conductive bump 25' disposed on the metal layer 22.

The surface of the first insulating protective layer 21 defines an opening area A corresponding to the first bonding pad 200, and a first opening 210 is formed on the surface of the first insulating protective layer 21 in the opening area A, The first pad 200 is exposed to the first opening 210, and a groove 211 is formed on the surface of the first insulating protection layer 21 outside the opening area A, so that the groove 211 surrounds the first opening 210.

The metal layer 22 is formed on the first pad 200 in the first opening 210 and extends to the surface of the opening area A of the first insulating protection layer 21. The metal layer 22 includes a first metal layer 220 bonded to the first insulating protective layer 21 and a second metal layer 221 formed on the first metal layer 220.

The second insulating layer 23 is formed on the second metal layer 221, and a second opening 230 is formed to expose a portion of the surface of the second metal layer 221 to the second opening 230.

The conductive bump 25' is disposed on the second metal layer 221 of the second opening 230.

In one embodiment, the substrate body 2a has an insulating layer 20, and the first insulating protective layer 21 is formed on the insulating layer 20.

In another embodiment, the substrate body 2' has a circuit build-up structure 26 disposed between the substrate body 2a and the first insulating protective layer 21, and the circuit build-up structure 26 has at least one dielectric layer. 260, a circuit layer 261 formed on the dielectric layer 260, and a conductive via 262 formed in the dielectric layer 260 and electrically connected to the circuit layer 261, and the circuit layer 261 has a second pad 263. The first insulating protective layer 21 is formed on the dielectric layer 260 and the circuit layer 261, so that the second bonding pad 263 is exposed to the first opening 210 of the first insulating protective layer 21. The metal layer 22 and its upper structure are formed on the second pad 263 as shown in FIG. 2F'.

In summary, the semiconductor package of the present invention and the substrate thereof are formed by forming a recess on the surface of the first insulating protective layer around the conductive bump to make the first insulating protective layer under the conductive bump and the first The difference in the occupied area of the two insulating protective layers is not large, so that the peeling of the second insulating protective layer can be avoided, thereby effectively achieving the purpose of improving reliability.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

1. . . Semiconductor wafer

1a, 2a, 2a’. . . Substrate body

10,20. . . Insulation

100. . . Solder pad

11,21. . . First insulating protective layer

110,210. . . First opening

12,22. . . Metal layer

120. . . Titanium layer

121. . . Copper layer

13,23. . . Second insulating protective layer

130,230. . . Second opening

14,24. . . Photoresist layer

140,240. . . Opening

15,15’,25,25’. . . Conductive bump

2,2’. . . Semiconductor substrate

200. . . First pad

211. . . Groove

220. . . First metal layer

221. . . Second metal layer

26. . . Line buildup structure

260. . . Dielectric layer

261. . . Circuit layer

262. . . Conductive blind hole

263. . . Second pad

3. . . Semiconductor package

30. . . Package substrate

31. . . colloid

A. . . Opening area

D, d. . . Aperture

1A to 1F are schematic cross-sectional views of a conventional semiconductor wafer having conductive bumps;

2A to 2F are schematic cross-sectional views showing a first embodiment of a method of fabricating a semiconductor substrate of the present invention;

2F' is a schematic cross-sectional view showing a second embodiment of the method for fabricating a semiconductor substrate of the present invention;

Figure 3 is a schematic cross-sectional view of a semiconductor package formed in accordance with Figure 2F.

2. . . Semiconductor substrate

2a. . . Substrate body

20. . . Insulation

200. . . First pad

twenty one. . . First insulating protective layer

210. . . First opening

211. . . Groove

twenty two. . . Metal layer

220. . . First metal layer

221. . . Second metal layer

twenty three. . . Second insulating protective layer

230. . . Second opening

25’. . . Conductive bump

A. . . Opening area

Claims (12)

A semiconductor substrate includes: a substrate body having a plurality of pads; a first insulating protective layer formed on the substrate body, wherein the first insulating protective layer defines a plurality of opening regions corresponding to the pads, each a first opening for exposing the pad is formed on the first insulating protective layer in the opening region, and a groove is formed on a surface of the first insulating protective layer outside each of the opening regions to make the concave The trench surrounds the first opening in the opening region; the metal layer is formed on the opening region of the first insulating protective layer and extends to the solder pad exposed in each of the first openings; the second insulation protection a layer is formed on the metal layer, and a plurality of second openings are formed to expose a portion of the surface of the metal layer to the second opening, wherein the first insulating protective layer in the opening region is a second insulating protective layer on the metal layer, and the occupied area of the first insulating protective layer in the opening region is approximately equal to the occupied area of the second insulating protective layer on the metal layer; and the plurality of conductive bumps Provided in a metal layer exposed in the second opening . A semiconductor substrate includes: a substrate body; a line build-up structure is disposed on the substrate body, the line build-up structure has a plurality of solder pads; and a first insulating protective layer is formed on the line build-up structure, And the first insulating protective layer defines a plurality of opening regions corresponding to the bonding pads, and the first insulating protective layer in each of the opening regions forms a first opening for exposing the bonding pads, and each of the openings is opened a groove is formed on a surface of the first insulating protective layer outside the hole region to surround the first opening in the opening region; and a metal layer is formed on the opening region of the first insulating protective layer And extending to a solder pad exposed in each of the first openings; a second insulating protective layer is formed on the metal layer, and a plurality of second openings are formed to expose a part of the surface of the metal layer a second opening, wherein the first insulating protective layer in the opening region corresponds to the second insulating protective layer on the metal layer, and the occupied area of the first insulating protective layer in the opening region is approximately equal to the The occupied area of the second insulating protective layer on the metal layer; and the plurality of conductive bumps are disposed on the metal layer exposed in the second opening. The semiconductor substrate according to claim 2, wherein the circuit build-up structure has at least one dielectric layer, a circuit layer disposed on the dielectric layer, and is formed in the dielectric layer and electrically connected The conductive via hole of the circuit layer, the circuit layer has the solder pad, and the first insulating protective layer is formed on the circuit layer and the dielectric layer. The semiconductor substrate according to claim 1 or 2, wherein the substrate body is formed with an insulating layer. The semiconductor substrate of claim 1 or 2, wherein the metal layer comprises a first metal layer and a second metal layer, the first metal The layer portion is embedded in the first insulating protective layer, and the second metal layer is formed on the first metal layer. The semiconductor substrate according to claim 1 or 2, wherein the aperture of the second opening is smaller than the projection width of the opening area. A semiconductor package includes: a substrate body having a plurality of pads; a first insulating protective layer formed on the substrate body, and the first insulating protective layer defines a plurality of opening regions corresponding to the pads; a first opening for exposing the pad is formed on the first insulating protective layer in each of the opening regions, and a groove is formed on a surface of the first insulating protective layer outside each of the opening regions to enable the hole a recess surrounding the first opening in the opening region; a metal layer formed on the opening region of the first insulating protective layer and extending to the solder pad exposed in each of the first openings; the second insulation a protective layer is formed on the metal layer, and a plurality of second openings are formed to expose a portion of the surface of the metal layer to the second opening, wherein the first insulating protective layer in the opening region Corresponding to the second insulating protective layer on the metal layer, and the occupied area of the first insulating protective layer in the opening region is approximately equal to the occupied area of the second insulating protective layer on the metal layer; the plurality of conductive bumps Provided in a metal layer exposed in each of the second openings ; Package substrate, based on the bound conductive bumps; and colloid system is formed in the insulating protective layer and the first package substrate Between the coating, the conductive bump is partially covered, and the colloid is formed in the groove. A semiconductor package includes: a substrate body; a line build-up structure is disposed on the substrate body, the line build-up structure has a plurality of pads; and a first insulating protective layer is formed on the line build-up structure, And the first insulating protective layer defines a plurality of opening regions corresponding to the bonding pads, and the first insulating protective layer in each of the opening regions forms a first opening for exposing the bonding pad, and each of the openings is opened a groove is formed on a surface of the first insulating protective layer outside the hole region to surround the first opening in the opening region; and a metal layer is formed on the opening region of the first insulating protective layer And extending to a solder pad exposed in each of the first openings; a second insulating protective layer is formed on the metal layer, and a plurality of second openings are formed to expose a part of the surface of the metal layer a second opening, wherein the first insulating protective layer in the opening region corresponds to the second insulating protective layer on the metal layer, and the occupied area of the first insulating protective layer in the opening region is approximately equal to the Occupied area of the second insulating protective layer on the metal layer A plurality of conductive bumps, lines provided on each of the exposed opening in the second metal layer; package substrate, based on the bound conductive bumps; and colloid system is formed in the insulating protective layer and the first package substrate Between the coating, the conductive bump is partially covered, and the colloid is formed in the groove. The semiconductor package of claim 8, wherein the circuit build-up structure has at least one dielectric layer, a circuit layer disposed on the dielectric layer, and is formed in the dielectric layer and electrically And connecting a plurality of conductive blind vias of the circuit layer, and the circuit layer has the solder pad, and the first insulating protective layer is formed on the circuit layer and the dielectric layer. The semiconductor package of claim 7 or 8, wherein the substrate body is formed with an insulating layer. The semiconductor package of claim 7 or 8, wherein the metal layer comprises a first metal layer and a second metal layer, the first metal layer portion being embedded in the first insulating protective layer, The second metal layer is formed on the first metal layer. The semiconductor package of claim 7 or 8, wherein the aperture of the second opening is smaller than the projection width of the opening area.