TWI447860B - Non-volatile memory and method for fabricating the same - Google Patents

Description

Non-volatile memory and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a non-volatile memory and a method of fabricating the same.

With the popularity of consumer electronics and the widespread use of system products, there is an increasing demand for memory with low power consumption, low cost, high read/write speed, small size and high capacity density. Therefore, the practice of mixing a plurality of functionally distinct components on a single semiconductor substrate arises. An example is an embedded non-volatile memory in which non-volatile memory and logic circuits are mixed on a single wafer.

In logic circuits, in addition to circuit components used to control memory or perform operations, non-volatile memory is also typically included. In general, the gate structure of a non-volatile memory is formed by patterning a layer of a conductor material by performing a lithography process and an etching process.

With the rapid development of semiconductor process technology, in order to improve the speed and performance of components, the integration of integrated circuits must be continuously improved, and the area occupied by each memory cell of the memory component must be reduced. Therefore, how to make non-volatile memory using a simple manufacturing method and using fewer masks under a limited wafer area will be an extremely important issue at present.

In view of this, the present invention provides a method of manufacturing a non-volatile memory which is a gate last process.

The present invention further provides a non-volatile memory having a memory cell of a smaller size.

The present invention provides a method of manufacturing a non-volatile memory. First, a substrate is provided. Next, a patterned mask layer is formed on the substrate, and the patterned mask layer has a plurality of openings. Thereafter, a plurality of first spacers are formed on the sidewalls of the patterned mask layer in each of the openings. A gate dielectric layer is then formed on the substrate between adjacent first spacers in each of the openings. Then, a conductor layer is formed on the substrate, filling at least the opening and covering the first spacer. Next, the conductor layer is planarized to form a plurality of gate structures. Thereafter, the patterned mask layer is removed, and a doped region is formed in the substrate between the adjacent two gate structures. Further, a plurality of second spacers are formed on the sidewalls of the gate structure. Next, a contact plug is formed between the adjacent two second spacers.

The present invention further provides a non-volatile memory comprising a plurality of gate structures, a plurality of doped regions, a plurality of second spacers, and a plurality of contact window plugs. The gate structure is disposed on the substrate, and each gate structure includes a control gate and a gate dielectric layer. The control gate is disposed on the substrate, and each of the control gates has two first spacers on both sides. The gate dielectric layer is disposed between the control gate and the substrate. The doped region is disposed in a substrate between adjacent two gate structures. The second spacer is disposed on a sidewall of the gate structure. The contact window plug is disposed between the adjacent two second gap walls.

Based on the above, the method for manufacturing a non-volatile memory of the present invention first forms a first spacer in the opening, and then planarizes the conductor layer filled in the opening to form a gate structure, which can help to reduce each The size of the memory cell. In addition, a self-aligned contact window is formed between adjacent two second spacers, which can effectively prevent defects caused by process errors and ensure component quality.

Furthermore, the non-volatile memory of the present invention has a first spacer on each side of each of the control gates, so that the size of the memory cell is small.

The above described features and advantages of the present invention will be more apparent from the following description.

1A through 1H are schematic cross-sectional views showing a manufacturing process of a non-volatile memory according to an embodiment of the present invention.

Referring to FIG. 1A, a substrate 100 is provided. The substrate 100 is, for example, a semiconductor substrate such as an N-type or P-type germanium substrate, a tri-five semiconductor substrate, or the like. In general, substrate 100 includes a main component area and a peripheral circuit area. In the semiconductor device process, for example, a memory system process or the like is performed in the main device region, and a logic process or the like is performed in the peripheral circuit region, for example. In this embodiment, the following is an example of forming a non-volatile memory in a logic process, but is not intended to limit the scope of the present invention.

Referring to FIG. 1A, the pad layer 102 and the patterned mask layer 104 are sequentially formed on the substrate 100. The material of the underlayer 102 is, for example, ruthenium oxide, and the formation method thereof is, for example, a thermal oxidation method or a chemical vapor deposition method. The patterned mask layer 104 has, for example, an opening 105 to expose a portion of the surface of the pad layer 102. The material of the patterned mask layer 104 is, for example, tantalum nitride. The method for forming the patterned mask layer 104 is, for example, first forming a layer of mask material (not shown) on the substrate 100 by chemical vapor deposition, and then sequentially performing a lithography process and an etching process to remove a portion of the mask. Formed by a layer of material.

It should be noted that, in this step, the configuration of the opening 105 between the patterned mask layers 104 is designed according to the area of the subsequent pre-formed gate structure, that is, the formation position of the opening 105 is the subsequent pre-formed gate structure. Area.

Referring to FIG. 1B, a high temperature oxide (HTO) 106 is formed on the substrate 100. The high temperature oxide layer 106 conformally covers the pad layer 102 and the patterned mask layer 104. The method of forming the high temperature oxide layer 106 is, for example, a thermal oxidation method. Thereafter, a first spacer 108 is formed on the sidewall of the patterned mask layer 104 in the opening 105. The top surface height of the first spacer 108 is, for example, lower than the top surface height of the patterned mask layer 104. The material of the first spacers 108 may be a charge storage material that traps charges therein, such as tantalum nitride, tantalum oxide, tantalum titanate or tantalum oxide. The first spacers 108 are formed by, for example, forming a charge storage material layer (not shown) filled in the openings 105 on the substrate 100 by chemical vapor deposition, and then performing an anisotropic etching process to remove the partial charges. A layer of material is stored to form a spacer structure on the sidewalls of the patterned mask layer 104. Removing a portion of the charge storage material layer to form the first spacers 108 is, for example, a reactive ion etch (RIE) process. In an embodiment, during the reactive ion etching process, the high temperature oxide layer 106 between the adjacent first spacers 108 and the partially exposed pad layer 102 are also removed to form a pad layer. 102a.

Referring to FIG. 1C, in an embodiment, an oxide layer (not shown) may be formed on the substrate 100 by in-situ steam generation (ISSG), and then wet. The wet dip process is removed by a wet dip process. The wet immersion process not only removes the oxide layer formed by the in-situ steam generation process, but also removes the oxide on the top surface of the patterned mask layer 104 to form the high temperature oxide layer 106'. The solvent used in the wet soaking process is, for example, a hydrofluoric acid solution (HF). It is explained here that when the anisotropic etching process is performed to form the first spacers 108, the material of the pad layer 102a or the first spacers 108 may be damaged, so that the active in-situ steam generation is used. By forming an oxide on the substrate 100 and then removing the oxide by a wet immersion process, the material damaged in the previous process can be removed to avoid subsequent processes being affected. Accordingly, a gate dielectric layer 110 is formed on the substrate 100. A gate dielectric layer 110 is formed between adjacent first spacers 108 in the opening 105. The material of the gate dielectric layer 110 is, for example, ruthenium oxide, and the formation method thereof is, for example, an oxidation method.

Referring to FIG. 1D, a conductor layer 112 is formed on the substrate 100, which fills at least the opening 105 and covers the first spacers 108. The material of the conductor layer 112 is, for example, doped polysilicon, and the formation method thereof is, for example, a chemical vapor deposition method. Next, the planarization process of the conductor layer 112 is performed such that the top surface of the conductor layer 112 is approximately equal to the top surface of the patterned mask layer 104 to form a gate structure. The planarization process is, for example, a chemical mechanical polishing (CMP), and the patterned mask layer 104 is used as a polishing stop layer.

Referring to FIG. 1E, in an embodiment, an oxidation process may be selectively performed to form a portion of the conductor layer 112 to form an oxide. During the oxidation process, only the upper half of the conductor layer 112 is oxidized as the cap layer 112a, and the lower half of the conductor layer 112 maintains the original conductor material as the control gate 112b. The gate dielectric layer 110, the first spacers 108, the control gates 112b, and the cap layer 112a are, for example, gate structures 124 that collectively function as non-volatile memory.

In addition, in another embodiment, it is not necessary to form an oxide on the upper half of the conductor layer 112, but another dielectric layer (not shown) is directly formed on the conductor layer 112 as a cap layer.

Referring to FIG. 1F, the patterned mask layer 104 is removed to form an opening 114. The method of removing the patterned mask layer 104 may be a dry etching method or a wet etching method. When the patterned mask layer 104 is removed, the high temperature oxide layer 106' disposed on the sidewalls of the gate structure 124 can serve as the first spacer 108 and the control gate 112b. Thereafter, a doped region 116 is formed in the substrate 100 between adjacent two gate structures 124. The doped region 116 is, for example, a heavily doped region to serve as a source region or a drain region of the non-volatile memory. The method of forming the doping region 116 is performed, for example, by using the gate structure 124 as a mask for the ion implantation process.

Referring to FIG. 1G, a second spacer 118 is formed on the sidewall of the gate structure 124 in the opening 114. The material of the second spacers 118 is, for example, tantalum nitride. The second spacers 118 are formed by, for example, forming a layer of spacer material (not shown) filled in the opening 114 on the substrate 100 by chemical vapor deposition, and then performing an anisotropic etching process to remove a portion of the gap. A layer of wall material forms a second spacer 118 on the sidewall of the high temperature oxide layer 106'.

Referring to FIG. 1H, a dielectric layer 120 is formed on the substrate 100. The dielectric layer 120, for example, covers the gate structure 124 and fills at least the gap between two adjacent second spacers 118 in the opening 114. Dielectric layer 120, for example, is selected to have a different etch selectivity than second spacers 118, which may be tantalum oxide. Thereafter, a portion of the dielectric layer 120 and a portion of the pad layer 102a are removed to form a contact opening 120a. Contact window opening 120a is, for example, formed between adjacent two second spacers 118 on doped region 116. The contact window opening 120a is, for example, sequentially performing a lithography process and an etching process. Since the etch selectivity of the dielectric layer 120 is different from the etch selectivity of the second spacers 118, the contact opening 120a is, for example, a self-aligned contact (SAC) opening. In particular, when the portion of the dielectric layer 120 is removed to form the contact opening 120a, the gate can be prevented by the second spacer 118 disposed on the sidewall of the gate structure 124 even if an alignment error occurs. The pole structure 124 is damaged. Next, a layer of conductive material is filled in the contact opening 120a to form a contact plug 122 between the adjacent two spacers 118. The material of the contact window plug 122 is, for example, tungsten, copper, aluminum or other suitable metal.

The method for fabricating the non-volatile memory of the above embodiment is a gate last process, which defines the pre-formed position of the gate structure 124 by patterning the opening 105 of the mask layer 104, and then opening 105. The first spacer 108 and the control gate 112b are formed, and after the patterned mask layer 104 is removed, the second spacer 118 and the contact plug 122 between the adjacent two spacers 118 are formed. The use of a chemical mechanical polishing process to planarize the conductor layer filled in the opening 105 to form the control gate 112b can help to reduce the size of each memory cell. In addition, by forming a self-aligned contact window between the adjacent two second spacers 118, defects caused by process errors such as alignment errors can be effectively prevented to ensure component quality.

The structure of the non-volatile memory of the present invention will be described below by taking FIG. 1H as an example.

Referring to FIG. 1H, the non-volatile memory includes a gate structure 124, a doped region 116, a second spacer 118, and a contact plug 122. The gate structure 124 is disposed on the substrate 100. The doped region 116 is disposed in the substrate 100 between the adjacent two gate structures 124. The second spacers 118 are disposed on sidewalls of the gate structures 124. The contact window plug 122 is disposed between the adjacent two second spacers 118.

The substrate 100 is, for example, a semiconductor substrate such as an N-type or P-type germanium substrate, a tri-five semiconductor substrate, or the like. For example, a pad layer 102a is disposed on the substrate 100. The pad layer 102a is, for example, between the gate structure 124 and the substrate 100 and between the second spacers 118 and the substrate 100. The material of the underlayer 102a is, for example, cerium oxide. In an embodiment, the substrate 100 is further provided with a dielectric layer 120. The dielectric layer 120 covers, for example, the gate structure 124 and the second spacers 118, and the contact plug 122 is disposed, for example, in the dielectric layer 120. The material of the dielectric layer 120 is, for example, ruthenium oxide.

Each gate structure 124 includes a control gate 112b, a gate dielectric layer 110 and two first spacers 108. The control gate 112b is disposed on the substrate 100, and has two recessed portions 126 on both sides of the control gate. That is, the top area of the control gate 112b is, for example, greater than the bottom area, and the recess 126 is disposed at a position below the control gate 112b near the gate dielectric layer 110. The material of the control gate 112b is, for example, doped polysilicon. The gate dielectric layer 110 is disposed between the control gate 122b and the pad layer 102a. The material of the gate dielectric layer 110 is, for example, hafnium oxide. The first spacers 108 are respectively disposed in the recesses 126. In an embodiment, the first spacer 108 is in contact with the control gate 112b. The material of the first spacers 108 may be a material that traps charges therein, such as tantalum nitride, tantalum oxide, barium titanate or tantalum oxide. In an embodiment, each of the gate structures 124 further includes a cap layer 112a disposed on the control gate 112b. The material of the cap layer 112a may be an oxide such as an oxide doped with polysilicon.

In one embodiment, the non-volatile memory further includes a high temperature oxide layer 106' disposed between the gate structure 124 and the second spacers 118 and disposed between the first spacers 108 and the pad layer 102a. The high temperature oxide layer 106' disposed on the sidewall of the gate structure 124 can be used, for example, to protect the first spacer 108 and the control gate 112b.

The second spacers 118 are disposed on the pad layer 102a above the doped regions 116. In an embodiment, the etch selectivity of the second spacers 118 is different from the etch selectivity of the dielectric layer 120. The material of the second spacers 118 is, for example, tantalum nitride.

The contact window plug 122 is, for example, a self-aligned contact window plug disposed on the doped region 116 between the adjacent two second spacers 118 and in contact with the doped region 118. The material of the contact window plug 122 is, for example, tungsten, copper, aluminum or other suitable metal.

In summary, the method for manufacturing a non-volatile memory of the present invention defines a pre-formed position of the gate structure by using an opening configuration of the patterned mask layer, and then forms a first spacer and a conductor as a control gate in the opening. The layer is formed by planarizing the conductor layer, thereby effectively reducing the size of the memory cell. Moreover, the method of the present invention forms a second spacer on the sidewall of the gate structure and forms a self-aligned contact window between the adjacent two spacers, thereby effectively preventing defects caused by process errors and ensuring Component quality.

The non-volatile memory of the present invention has a small size by arranging a depressed portion on both sides of the control gate and arranging the first spacer in the depressed portion.

In addition, the non-volatile memory of the present invention and the method of fabricating the same can be applied to existing semiconductor components, particularly in the process of embedded non-volatile memory, and can be integrated with existing logic processes. The process is simple and can reduce the use of the mask and reduce the manufacturing cost.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Base

102, 102a. . . Cushion

104. . . Patterned mask layer

105, 114. . . Opening

106, 106’. . . High temperature oxide layer

108. . . First spacer

110. . . Gate dielectric layer

112. . . Conductor layer

112a. . . Roof layer

112b. . . Control gate

116. . . Doped region

118. . . Second spacer

120. . . Dielectric layer

120a. . . Contact window opening

122. . . Contact window plug

124. . . Gate structure

126. . . Depression

1A through 1H are schematic cross-sectional views showing a manufacturing process of a non-volatile memory according to an embodiment of the present invention.

100. . . Base

102a. . . Cushion

106’. . . High temperature oxide layer

108. . . First spacer

110. . . Gate dielectric layer

112. . . Conductor layer

112a. . . Roof layer

112b. . . Control gate

114. . . Opening

116. . . Doped region

118. . . Clearance wall

120. . . Dielectric layer

120a. . . Contact window opening

122. . . Contact window plug

124. . . Gate structure

126. . . Depression

Claims (17)

A method of fabricating a non-volatile memory, comprising: providing a substrate; forming a patterned mask layer on the substrate, and the patterned mask layer has a plurality of openings; the patterning in each of the openings Forming a plurality of first spacers on sidewalls of the mask layer; forming a gate dielectric layer on the substrate between adjacent ones of the plurality of openings; forming a conductor layer on the substrate, at least Filling the openings and covering the first spacers; performing a planarization process on the conductor layer to form a plurality of gate structures; removing the patterned mask layer; between adjacent gate structures a doped region is formed in the substrate; a plurality of second spacers are formed on sidewalls of the gate structures, and the second spacers are not covered by the conductor layer; and the gate structures are Forming a high temperature oxide layer between each of the second spacers, a portion of the high temperature oxide layer is located under the gate structures, and the high temperature oxide layer is formed before the gate structures are formed; A contact window plug is formed between the two gap walls. The method for manufacturing a non-volatile memory according to claim 1, after performing the planarization process, further comprising performing an oxidation process to form an oxide in an upper portion of the conductor layer. Non-volatile memory as described in claim 1 In the manufacturing method, the high temperature oxide layer is conformally formed on the substrate after forming the patterned mask layer and before forming the first spacers. The method for manufacturing a non-volatile memory according to the first aspect of the invention, after forming the patterned mask layer and before forming the first spacers, further comprising: performing an in-situ steam generation (in- Situ steam generation, ISSG) process; and a wet dip process. The method of manufacturing the non-volatile memory of claim 1, wherein the method of forming the contact plug comprises: forming a dielectric layer on the substrate; forming a contact window in the dielectric layer Opening; and filling a contact material window with a layer of conductive material. The method of fabricating a non-volatile memory according to claim 5, wherein the etching selectivity of the dielectric layer is different from the etching selectivity of the second spacer. The method for manufacturing a non-volatile memory according to claim 1, wherein a top surface height of the first spacers is lower than a top surface height of the patterned mask layer. The method for manufacturing a non-volatile memory according to claim 1, wherein the material of the first spacers comprises tantalum nitride. The method for manufacturing a non-volatile memory according to claim 1, wherein the material of the second spacers comprises tantalum nitride. A non-volatile memory comprising: a plurality of gate structures disposed on a substrate, each of the gate structures comprising: a control gate is disposed on the substrate, the control gate has two first spacers on both sides thereof; and a gate dielectric layer disposed between the control gate and the substrate; a plurality of doped regions, Arranging respectively in the substrate between two adjacent gate structures; a plurality of second spacers respectively disposed on sidewalls of each of the gate structures, and the second spacers are not configured by the control gate Covering a high temperature oxide layer disposed between each of the gate structures and each of the second spacers, and a portion of the high temperature oxide layer is located under the gate structures; and a plurality of contact window plugs are respectively disposed Between adjacent two second gap walls. The non-volatile memory of claim 10, wherein each of the gate structures further comprises a cap layer disposed on the control gate. The non-volatile memory of claim 10, further comprising a dielectric layer disposed on the substrate, and the contact plugs are disposed in the dielectric layer. The non-volatile memory of claim 12, wherein the etching selectivity of the dielectric layer is different from the etching selectivity of the second spacer. The non-volatile memory of claim 10, wherein each of the first spacers is in contact with the control gate. The non-volatile memory of claim 10, wherein each of the contact window plugs is a self-aligned contact window plug. Non-volatile memory as described in claim 10 The body, wherein the materials of the first spacers comprise tantalum nitride. The non-volatile memory of claim 10, wherein the material of the second spacers comprises tantalum nitride.