TWI446504B - Chip package structure and packaging method thereof - Google Patents

Chip package structure and packaging method thereof Download PDF

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Publication number
TWI446504B
TWI446504B TW099112326A TW99112326A TWI446504B TW I446504 B TWI446504 B TW I446504B TW 099112326 A TW099112326 A TW 099112326A TW 99112326 A TW99112326 A TW 99112326A TW I446504 B TWI446504 B TW I446504B
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lead frame
pad
wafer
ground
power
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TW099112326A
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TW201138045A (en
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Wei Chen
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Silergy Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

晶片封裝結構及其封裝方法Chip package structure and packaging method thereof

本發明關於一種晶片封裝結構及其封裝方法，屬於半導體元件及其製造方法。The present invention relates to a chip package structure and a method of packaging the same, and to a semiconductor device and a method of fabricating the same.

在半導體產業中，積體電路的生產主要可分為三個階段：積體電路的設計、積體電路的製作以及積體電路的封裝。在積體電路的製作中，晶片由晶圓製作、形成積體電路以及切割晶圓等步驟完成。當晶圓內部的積體電路完成之後，再在晶圓上配置有多個焊墊，以使最終由晶圓切割所形成的晶片可經由這些焊墊而向外電連接於一承載器。承載器例如為一引線框架或者一封裝基板。晶片可以打線接合或者覆晶接合的方式連接至承載器上，使得晶片的這些焊墊可電連接於承載器的接點，以構成一晶片封裝結構。In the semiconductor industry, the production of integrated circuits can be divided into three stages: the design of integrated circuits, the fabrication of integrated circuits, and the packaging of integrated circuits. In the fabrication of the integrated circuit, the wafer is completed by steps of fabricating, forming an integrated circuit, and dicing the wafer. After the integrated circuit inside the wafer is completed, a plurality of pads are disposed on the wafer, so that the wafers finally formed by the wafer dicing can be electrically connected to a carrier via the pads. The carrier is, for example, a lead frame or a package substrate. The wafers can be bonded to the carrier by wire bonding or flip chip bonding so that the pads of the wafer can be electrically connected to the contacts of the carrier to form a chip package structure.

以引線框架為晶片承載件的半導體封裝件，例如四方扁平式半導體封裝件或者四方扁平無管腳式半導體封裝件等，其製作方式均是在一具有載片台及多個引腳的引線框架上粘置該半導體晶片，並且通過多條接合引線電連接該晶片表面上的接觸焊墊和與其對應的多個引腳，然後以封裝膠體包覆該晶片以及接合引線而形成一半導體封裝件。A semiconductor package having a lead frame as a wafer carrier, such as a quad flat semiconductor package or a quad flat unpinned semiconductor package, is fabricated in a lead frame having a carrier and a plurality of leads The semiconductor wafer is adhered thereon, and the contact pads on the surface of the wafer and a plurality of pins corresponding thereto are electrically connected through a plurality of bonding wires, and then the wafer is coated with the encapsulant and the bonding wires are bonded to form a semiconductor package.

由於封裝件上晶片集成度的提高，為了保證電性品質和減少雜訊，在進行封裝件的結構設計時，通常必須使晶片具有接地(GND)和電源(IN)功能以及開關信號功能(LX)，使其符合電性要求。Due to the increased integration of the wafer on the package, in order to ensure the electrical quality and reduce the noise, the structure of the package must be designed to have the ground (GND) and power (IN) functions as well as the switching signal function (LX). ) to make it meet electrical requirements.

現有技術中，通常是利用多條引線分別將引線框架的接地引腳、電源引腳、開關引腳對應的連接到晶片上的的接地焊墊、電源焊墊和開關信號焊墊。In the prior art, a grounding pin, a power pin, and a switch pin of a lead frame are respectively connected to a ground pad, a power pad, and a switch signal pad on a wafer by using a plurality of leads.

以單片晶片的封裝結構為例，圖1A所示為現有一種晶片封裝結構的俯視示意圖，其包括一晶片101、一引線框架103以及多條引線。晶片101配置於該引線框架的載片台104上，多條引線106跨越該載片台104將晶片101上的接觸焊墊102電連接至該引線框架103的相應的外接引腳105上。以圖1A所示的晶片封裝結構為例，晶片101上的具有相同電位的一組接地焊墊和一組電源焊墊，以及開關信號焊墊均通過接合引線106直接連接至引線框架103上的對應引腳105。顯然，採用這種晶片封裝結構，增加了接地引線的長度，即增加了引線電阻，使得晶片101的功率損耗增加。對於某些應用場合，由於晶片101上的接觸焊墊102以及引線框架103上的引腳105排列，使得接合引線106不可避免的會有相互交叉的情況，進一步增加了引線連接的複雜性，並且各引線相互之間的干擾增加，使得晶片工作可靠性和穩定性下降，並且晶片制程需要的矽片面積也較大。Taking a package structure of a single wafer as an example, FIG. 1A is a top plan view of a conventional chip package structure including a wafer 101, a lead frame 103, and a plurality of leads. The wafer 101 is disposed on the stage 104 of the lead frame, and the plurality of leads 106 electrically connect the contact pads 102 on the wafer 101 to the corresponding external pins 105 of the lead frame 103 across the stage 104. Taking the chip package structure shown in FIG. 1A as an example, a set of ground pads and a set of power pads having the same potential on the wafer 101, and the switch signal pads are directly connected to the lead frame 103 through the bonding wires 106. Corresponding to pin 105. Obviously, with such a chip package structure, the length of the ground lead is increased, that is, the lead resistance is increased, so that the power loss of the wafer 101 is increased. For some applications, since the contact pads 102 on the wafer 101 and the leads 105 on the lead frame 103 are arranged, the bonding leads 106 inevitably cross each other, further increasing the complexity of the wire bonding, and The interference between the leads is increased, so that the reliability and stability of the wafer are degraded, and the area of the wafer required for the wafer process is also large.

如圖1B所示，如果需要對晶片101的功能進行擴展，則需要在原有晶片的基礎上重新進行電路設計以及佈局，接觸焊墊102和接合引線106的排布會更加複雜，也需要增加較大面積的矽片。As shown in FIG. 1B, if the function of the wafer 101 needs to be expanded, the circuit design and layout need to be re-established on the basis of the original wafer. The arrangement of the contact pads 102 and the bonding leads 106 is more complicated and needs to be increased. Large area of sepals.

本發明的目的在於克服現有技術存在的不足，而提出一種新的晶片封裝結構及其封裝方法，它根據晶片接觸焊墊的類型採用不同的連接方式，以解決晶片損耗大、散熱難，接合引線過多以及封裝晶片功能擴展的局限問題。The object of the present invention is to overcome the deficiencies of the prior art, and to provide a new chip package structure and a packaging method thereof, which adopt different connection modes according to the type of wafer contact pads to solve the problem of large wafer loss, heat dissipation, and bonding leads. Excessive and limited limitations of packaged chip functionality.

本發明的目的是通過如下技術方案來完成的，一種晶片封裝結構，包括：晶片，該晶片上具有多個第一接觸焊墊和第二接觸焊墊；一引線框架，包括具有用於向外部連接的多個引腳，並且該晶片配置於該引線框架上；一組第一接合引線，用以將該第一接觸焊墊直接電連接至該引線框架；一組第二接合引線，用以將第二接觸焊墊電連接至該引線框架的多個引腳。The object of the present invention is achieved by the following technical solution, a chip package structure comprising: a wafer having a plurality of first contact pads and second contact pads thereon; a lead frame including the same for external use Connecting a plurality of pins, and the wafer is disposed on the lead frame; a set of first bonding wires for electrically connecting the first contact pads directly to the lead frame; and a set of second bonding wires for A second contact pad is electrically connected to the plurality of pins of the lead frame.

該第一接觸焊墊為具有相同電位的接地焊墊，該一組第一接合引線為接地接合引線，該第二接觸焊墊包括一組電位變化的開關信號焊墊和具有相同電位的電源焊墊，與開關信號焊墊連接的第一部分第二接合引線為開關信號接合引線，與電源焊墊連接的第二部分第二接合引線為電源接合引線。The first contact pad is a ground pad having the same potential, the set of first bond wires being a ground bond wire, the second contact pad comprising a set of potential-changing switch signal pads and a power supply having the same potential The pad, the first portion of the second bond wire connected to the switch signal pad is a switch signal bond wire, and the second portion of the second bond wire connected to the power pad is a power bond wire.

該開關信號接合引線和接地接合引線設置在該引線框架的同一側，並將電源接合引線設置在該引線框架的相對的另一側。The switch signal bond wire and ground bond wire are disposed on the same side of the lead frame and the power bond wire is disposed on the opposite side of the lead frame.

該信號接合引線和接地接合引線呈交錯排列佈置。The signal bond wires and the ground bond wires are arranged in a staggered arrangement.

本發明還包括有一用以包覆該晶片以及焊墊的封裝體，該引線框架暴露於該封裝體外。The invention also includes a package for encasing the wafer and the pad, the lead frame being exposed to the exterior of the package.

一種晶片封裝方法，包括以下步驟：步驟(1)：提供至少一個需進行封裝的晶片，該晶片上具有第一接觸焊墊和第二接觸焊墊；步驟(2)：提供一引線框架，其上具有提供向外部連接的多個引腳；步驟(3)：將該晶片相應地安裝在該引線框架上；步驟(4)：提供一組第一接合引線，以將第一接觸焊墊直接電連接至該引線框架；步驟(5)：提供一組第二接合引線，以將第二接觸焊墊直接電連接至該引線框的多個引腳。A chip packaging method comprising the steps of: (1) providing at least one wafer to be packaged, the wafer having a first contact pad and a second contact pad; and (2): providing a lead frame, Having a plurality of pins for providing external connection; step (3): mounting the wafer on the lead frame correspondingly; and step (4): providing a set of first bonding wires to directly connect the first contact pads Electrically connected to the lead frame; step (5): providing a set of second bond wires to electrically connect the second contact pads directly to the plurality of pins of the lead frame.

該步驟(4)中，第一接觸焊墊為具有相同電位的接地焊墊，該第一接合引線為接地接合引線；該步驟(5)中，與該一組第二接合引線連接的第二接觸焊墊，包括一組電位變化的開關信號焊墊和具有相同電位的電源焊墊，與開關信號焊墊連接的部分第二接合引線為信號接合引線，與電源焊墊連接的部分第二接合引線為電源接合引線。In the step (4), the first contact pad is a ground pad having the same potential, the first bonding wire is a ground bonding wire; and in the step (5), the second bonding wire is connected to the second bonding wire. The contact pad comprises a set of potential changing switching signal pads and a power pad having the same potential, and a portion of the second bonding leads connected to the switching signal pads are signal bonding leads and a second bonding of the power pads The leads are power bond leads.

本發明進一步包括：將該開關信號接合引線和接地接合引線設置在該引線框架的同一側，並將電源接合引線設置在該引線框架的相對的另一側。The invention further includes disposing the switch signal bond lead and the ground bond lead on the same side of the lead frame and disposing the power bond lead on the opposite side of the lead frame.

本發明進一步包括，將該信號接合引線和接地接合引線呈交錯排列佈置。The invention further includes arranging the signal bond wires and the ground bond wires in a staggered arrangement.

本發明進一步包括：設置一封裝體，用以包覆該晶片以及焊墊，並將該引線框架暴露於該封裝體外。The invention further includes providing a package for covering the wafer and the pad and exposing the lead frame to the outside of the package.

採用本發明優選實施例的晶片封裝結構以及封裝方法，可以方便的實現：The chip package structure and the packaging method using the preferred embodiment of the present invention can be conveniently implemented:

(1)對具有相同電位的接地接觸焊墊採用直接連接至引線框架的連接方式，減小了接地引線的長度，即減小了引線電阻，從而降低了功率損耗；晶片的接地引線直接連接至引線框架，減小了接地引線和引線框架上的載片台之間的間隙，使得散熱效果較好；另外，採用這種方式，熱量可以直接經由接地引線直接傳遞到引線框架上，因此熱阻較小，散熱好；對於電源管理類晶片，通常採用外接電容、電阻的方式來設置晶片的工作頻率，採用本發明實施例該的封裝結構，則外接電容可以直接連接在電源引腳和引線框架的接地回路，保證了電容回路最小，連線最短，因此由連線引起的走線電感最小，增加了晶片的工作穩定性和可靠性，減小了晶片承受的應力，也使得晶片的尺寸最小。(1) The ground contact pads having the same potential are connected directly to the lead frame, which reduces the length of the ground lead, that is, reduces the lead resistance, thereby reducing power loss; the ground lead of the wafer is directly connected to The lead frame reduces the gap between the ground lead and the stage on the lead frame, so that the heat dissipation effect is better; in addition, in this way, heat can be directly transmitted to the lead frame directly via the ground lead, so the thermal resistance Smaller, better heat dissipation; for power management type wafers, the working frequency of the wafer is usually set by means of external capacitors and resistors. With the package structure of the embodiment of the invention, the external capacitor can be directly connected to the power supply pin and the lead frame. The grounding loop ensures the minimum capacitance loop and the shortest wiring. Therefore, the wiring inductance caused by the wiring is the smallest, which increases the working stability and reliability of the wafer, reduces the stress on the wafer, and minimizes the size of the wafer. .

(2)接地引線和開關信號引線交錯並列排列佈置使得晶片的制程所使用的矽片面積較小。(2) The grounding lead and the switching signal leads are staggered and arranged side by side so that the wafer used in the wafer process has a small area.

(3)不用複雜的引線連接，焊墊的佈置即可以在已有晶片基礎上實現其功能的擴展，其實現方式更加方便和靈活。(3) Without the complicated lead connection, the arrangement of the pad can realize the expansion of its function on the basis of the existing wafer, and the implementation manner is more convenient and flexible.

以下結合附圖對本發明的優選實施例進行詳細描述，但本發明並不僅僅限於這些實施例。本發明涵蓋任何在本發明的精髓和範圍上做的替代、修改、等效方法以及方案。為了使公眾對本發明有徹底的瞭解，在以下本發明優選實施例中詳細說明了具體的細節，而對本領域技術人員來說沒有這些細節的描述也可以完全理解本發明。The preferred embodiments of the present invention are described in detail below with reference to the drawings, but the invention is not limited to the embodiments. The present invention encompasses any alternatives, modifications, equivalents and alternatives to the spirit and scope of the invention. The details of the invention are described in detail in the preferred embodiments of the present invention, and the invention may be fully understood by those skilled in the art.

圖2所示的是本發明一實施例的晶片封裝結構的示意圖，該實施例的晶片封裝結構包括晶片201、引線框架203、第一接合引線206-1和第二接合引線206-2。晶片201上具有第一接觸焊墊202-1和第二接觸焊墊202-2，其中第一接觸焊墊202-1和第二接觸焊墊202-2配置於晶片201的邊緣處，以方便於進行打線制程。2 is a schematic diagram of a wafer package structure according to an embodiment of the present invention. The wafer package structure of the embodiment includes a wafer 201, a lead frame 203, a first bonding wire 206-1, and a second bonding wire 206-2. The wafer 201 has a first contact pad 202-1 and a second contact pad 202-2, wherein the first contact pad 202-1 and the second contact pad 202-2 are disposed at the edge of the wafer 201 for convenience. For the wire bonding process.

引線框架203包括多個向外部連接的引腳205，第一接合引線206-1將第一接觸焊墊202-1直接電連接至引線框架203，第二接合引線206-2將第二接觸焊墊202-2電連接至該引線框架203的多個引腳205。The lead frame 203 includes a plurality of externally connected pins 205, the first bonding wires 206-1 directly electrically connect the first contact pads 202-1 to the lead frame 203, and the second bonding wires 206-2 to the second contact pads Pad 202-2 is electrically coupled to a plurality of pins 205 of the leadframe 203.

由於封裝件上晶片集成度的提高，為了保證電性品質和減少雜訊，在進行封裝件的結構設計時，通常必須使該晶片201具有接地(GND)和電源(IN)功能以及信號開關功能(LX)，使其符合電性要求。這裏，以第一接觸焊墊202-1為接地焊墊、第二接觸焊墊202-2為電源焊墊和開關信號焊墊為例，將接地焊墊直接連接至引線框架203的第一接合引線206-1為接地引線，將電源焊墊連接至引線框架的電源引腳的第二接合引線206-2為電源引線，將開關信號焊墊連接至引線框架的開關引腳的第二接合引線206-2為開關信號引線。該接地引線和開關信號引線分佈在該引線框架203的同一側，並且兩者呈並列交錯排列佈置，該電源引線分佈在該引線框架203的相對的另一側。對應的，晶片201上的接地焊墊和開關信號焊墊位於該晶片的同一側，並且兩者成並列交錯排列佈置，電源焊墊位於該晶片的相對的另一側。Due to the increase in wafer integration on the package, in order to ensure electrical quality and reduce noise, it is generally necessary to have the grounding (GND) and power (IN) functions and signal switching functions of the package 201 when designing the package. (LX) to make it meet electrical requirements. Here, taking the first contact pad 202-1 as the ground pad and the second contact pad 202-2 as the power pad and the switch signal pad as an example, the ground pad is directly connected to the first bond of the lead frame 203. The lead 206-1 is a ground lead, the second bond lead 206-2 connecting the power pad to the power pin of the lead frame is a power lead, and the switch signal pad is connected to the second bond lead of the switch pin of the lead frame 206-2 is the switching signal lead. The ground lead and the switch signal lead are distributed on the same side of the lead frame 203, and the two are arranged in a staggered arrangement, and the power lead is distributed on the opposite side of the lead frame 203. Correspondingly, the ground pad and the switch signal pad on the wafer 201 are located on the same side of the wafer, and the two are arranged in a staggered arrangement, and the power pads are located on the opposite side of the wafer.

以電源管理類晶片為例，圖3所示為該晶片的電路原理圖，包括上開關管Q1，下開關管Q2，電源以及地。則對該晶片的封裝則要求其具有電源引腳IN、接地引腳GND以及開關引腳LX，因此可以採用圖2所示的本發明實施例該的封裝結構。即晶片的電源焊墊通過一組第二接合引線即電源引線跨過該引線框架直接連接至引線框架的電源引腳，開關信號焊墊通過一組第二結合引線即開關引線擴過該引線框架直接連接至引線框架的開關引腳，接地焊墊通過一組第一接合引線即接地引線直接連接至該引線框架。Taking a power management type chip as an example, FIG. 3 is a circuit schematic diagram of the chip, including an upper switch tube Q1, a lower switch tube Q2, a power source, and a ground. Then, the package of the wafer is required to have the power supply pin IN, the ground pin GND, and the switch pin LX. Therefore, the package structure of the embodiment of the present invention shown in FIG. 2 can be used. That is, the power pad of the wafer is directly connected to the power pin of the lead frame through a set of second bond wires, that is, the power lead, across the lead frame, and the switch signal pad is extended through the lead frame through a set of second bond wires, ie, switch leads. Directly connected to the switch pin of the lead frame, the ground pad is directly connected to the lead frame through a set of first bond leads, ie, ground leads.

採用圖2所示的晶片封裝結構，其需要的接地引線的長度較小，因此由引線產生的引線電阻較小，使得晶片的功率損耗較小；晶片的接地引線直接連接至引線框架，減小了接地引線和引線框架上的載片台之間的間隙，使得散熱效果較好；另外，採用這種方式，熱量可以直接經由接地引線直接傳遞到引線框架上，因此熱阻較小，散熱好。The chip package structure shown in FIG. 2 requires a small length of the ground lead, so that the lead resistance generated by the lead is small, so that the power loss of the wafer is small; the ground lead of the wafer is directly connected to the lead frame, reducing The gap between the ground lead and the carrier on the lead frame makes the heat dissipation better; in addition, in this way, heat can be directly transmitted to the lead frame directly via the ground lead, so the thermal resistance is small and the heat dissipation is good. .

並且，開關引線和接地引線位於引線框架的同一側，電源引線位於引線框架的相對的另一側，其中該開關引線和接地引線呈交錯並列排列佈置。And, the switch lead and the ground lead are on the same side of the lead frame, and the power lead is located on the opposite side of the lead frame, wherein the switch lead and the ground lead are arranged in a staggered arrangement.

對電源管理類晶片，通常採用外接電阻、電容的方式來調節電源晶片的工作頻率，在該實施例中，外接電容可以連接在引線框架的電源引腳和引線框架上載片台的地電位，因此電容回路最小，引線也最短，也使得整體尺寸較小。For the power management chip, the operating frequency of the power chip is usually adjusted by using an external resistor and a capacitor. In this embodiment, the external capacitor can be connected to the power supply pin of the lead frame and the ground potential of the lead frame. The capacitor loop is the smallest and the leads are also the shortest, which also makes the overall size small.

電壓應力如公式(1)計算，The voltage stress is calculated as in formula (1).

因此可知，採用實施例所示的封裝結構，該接合引線的走線電感較小，因此，承受的電壓應力也較小。Therefore, it can be seen that with the package structure shown in the embodiment, the wiring inductance of the bonding wire is small, and therefore, the voltage stress to be received is also small.

採用現有技術，如果需要對晶片的功能進行擴展，如圖1B所示則需要在原有晶片的基礎上重新進行電路設計以及佈局，接觸焊墊和接合引線的排布會更加複雜，也需要增加較大面積的矽片。According to the prior art, if the function of the wafer needs to be expanded, as shown in FIG. 1B, the circuit design and layout need to be re-established on the basis of the original wafer, and the arrangement of the contact pads and the bonding leads is more complicated, and it is also necessary to increase the ratio. Large area of sepals.

圖4所示為採用本發明在原有晶片基礎上需進行功能擴展的晶片封裝結構的示意圖。採用本發明實施例的晶片封裝結構，如果需要對晶片201的功能進行擴展，則只需要在原晶片結構佈局的基礎上，沿原佈局方向增加一定面積的矽片，以及相應的接合引線、接觸焊墊，不影響原有引線以及焊墊的排列佈置，其實現更加方便和靈活。如圖4所示的晶片封裝結構為例，該晶片201包括接地、電源、開關功能以及相應的控制電路部分207，其中接地、電源、開關信號功能按照本發明實施例所示的晶片封裝結構進行封裝。如果需要在原有晶片基礎上進行新功能的擴展，則僅在原晶片佈局沿線上增加較小面積的矽片、以及對應的引腳、焊墊，即可以在不影響原有引線以及焊墊的排列佈置的基礎上實現晶片功能的擴展。圖4中其他的內容與圖2所示的相同。FIG. 4 is a schematic diagram showing a wafer package structure to be expanded on the basis of the original wafer by the present invention. According to the chip package structure of the embodiment of the present invention, if it is required to expand the function of the wafer 201, it is only necessary to add a certain area of the cymbal in the original layout direction on the basis of the original wafer structure layout, and the corresponding bonding leads and contact welding. The pad does not affect the arrangement of the original leads and the pads, which is more convenient and flexible. For example, the chip package structure shown in FIG. 4 includes a ground, a power supply, a switching function, and a corresponding control circuit portion 207, wherein the ground, power, and switching signal functions are performed according to the chip package structure shown in the embodiment of the present invention. Package. If it is necessary to expand the new functions on the basis of the original wafer, only a small area of the dies and corresponding pins and pads can be added along the original wafer layout, that is, the original leads and the pads can be arranged without affecting the arrangement. The expansion of the wafer function is realized on the basis of the arrangement. The other contents in Fig. 4 are the same as those shown in Fig. 2.

圖5所示為採用本發明的晶片封裝方法的流程圖，其包括以下步驟：S501：提供一個需進行封裝的晶片，該晶片上具有第一接觸焊墊和第二接觸焊墊；S502：提供一引線框架，其上具有提供向外部連接的多個引腳；S503：提供一組第一接合引線，以將第一接觸焊墊直接電性連接至該引線框架；S504：提供一組第二接合引線，以將第二接觸焊墊直接電性連接至該引線框的多個引腳。5 is a flow chart showing a wafer packaging method using the present invention, comprising the steps of: S501: providing a wafer to be packaged, the wafer having a first contact pad and a second contact pad; S502: providing a lead frame having a plurality of pins for providing external connections; S503: providing a set of first bonding wires to electrically connect the first contact pads directly to the lead frame; S504: providing a second set The leads are bonded to electrically connect the second contact pads directly to the plurality of leads of the lead frame.

圖6是以具有接地、電源和開關信號功能的晶片為例，來具體說明採用本發明實施例的晶片封裝方法的流程圖，其包括以下步驟：S601：提供一個需進行封裝的晶片，該晶片上具有接地焊墊、電源焊墊和開關信號焊墊；S602：提供一引線框架，其上具有提供向外部連接的多個引腳；S603：在晶片一側提供接地引線，以將接地焊墊直接電性連接至該引線框架；S604：在與接地引線側的相對一側設置電源引線，以將電源焊墊直接電性連接至該引線框架的電源引腳；S605：與接地引線同側，並呈交錯並列設置開關信號引線，以將開關焊墊直接電性連接至該引線框架的開關引腳。6 is a flow chart illustrating a wafer packaging method using an embodiment of the present invention, which includes a wafer having a function of grounding, power, and switching signals, and includes the following steps: S601: providing a wafer to be packaged, the wafer Having a ground pad, a power pad, and a switch signal pad; S602: providing a lead frame having a plurality of leads for external connection; S603: providing a ground lead on the wafer side to ground the pad Directly electrically connected to the lead frame; S604: providing a power lead on the side opposite to the ground lead side to electrically connect the power supply pad directly to the power supply pin of the lead frame; S605: on the same side as the ground lead The switch signal leads are staggered and arranged in parallel to electrically connect the switch pads directly to the switch pins of the lead frame.

採用本發明的晶片封裝方法，需要的接地引線的長度較小，因此由引線產生的引線電阻較小，使得晶片的功率損耗較小；晶片的接地引線直接連接至引線框架，減小了接地引線和引線框架上的載片台之間的間隙，使得散熱效果較好；另外，採用這種方式，熱量可以直接經由接地引線直接傳遞到引線框架上，因此熱阻較小，散熱好。並且，可以很方便的實現晶片數目的擴展，而不用複雜的引線連接，焊墊的佈置，以及需要考慮從各個晶片的位置佈置等問題。With the chip packaging method of the present invention, the required length of the ground lead is small, so the lead resistance generated by the lead is small, so that the power loss of the wafer is small; the ground lead of the wafer is directly connected to the lead frame, and the ground lead is reduced. The gap between the stage and the stage on the lead frame makes the heat dissipation better; in addition, in this way, heat can be directly transmitted to the lead frame directly via the ground lead, so that the thermal resistance is small and the heat dissipation is good. Moreover, it is convenient to realize the expansion of the number of wafers without complicated wiring connections, arrangement of solder pads, and problems such as positional arrangement from individual wafers.

以上特定實施例通過圖示和文字描述對本發明的晶片封裝結構以及晶片封裝方法進行了詳細描述。這些實施例並不是完全詳盡的，也不限制該發明僅為該的具體實施例。顯然，根據上述教導，可以做很多的修改和變化。例如，本發明以具有接地、電源和信號引腳的晶片為例，說明了不同類型的接合引線、以及引線之間的排列組合方式。但是依據本發明的教導可以推知其他的晶片類型，以及其他的引線結合方式等。本說明書選取並具體描述這些實施例，是為了最好地解釋本發明的原理和實際應用，從而使所屬技術領域技術人員能最好地利用這個發明。修改的實施例同樣也適用於預期的特定應用。本發明的範圍為申請專利範圍全部範圍以及其等效物。The above specific embodiments have described the wafer package structure and the wafer package method of the present invention in detail by way of illustration and text. The examples are not intended to be exhaustive or to limit the invention to the specific embodiments. Obviously, many modifications and variations are possible in light of the above teaching. For example, the present invention is exemplified by wafers having ground, power, and signal pins, illustrating different types of bond wires, and the arrangement of the arrangements between the leads. However, other wafer types, as well as other wire bonding methods, etc., can be inferred in accordance with the teachings of the present invention. The present invention has been chosen and described in detail to explain the principles of the invention, The modified embodiments are equally applicable to the particular application contemplated. The scope of the invention is the full scope of the claims and the equivalents thereof.

101．．．晶片101. . . Wafer

102．．．接觸焊墊102. . . Contact pad

103．．．引線框架103. . . Lead frame

104．．．載片台104. . . Slide table

105．．．引腳105. . . Pin

106．．．接合引線106. . . Bonding lead

201．．．晶片201. . . Wafer

202-1．．．第一接觸焊墊202-1. . . First contact pad

202-2．．．第二接觸焊墊202-2. . . Second contact pad

203．．．引線框架203. . . Lead frame

204．．．載片台204. . . Slide table

205．．．引腳205. . . Pin

206-1．．．第一接合引線206-1. . . First bond wire

206-2．．．第二接合引線206-2. . . Second bonding wire

圖1A所示為採用現有技術的一種單片晶片封裝結構的示意圖；1A is a schematic view showing a monolithic chip package structure using the prior art;

圖1B所示為採用圖1A所示的晶片封裝結構功能擴展的示意圖；FIG. 1B is a schematic diagram showing the function expansion of the chip package structure shown in FIG. 1A; FIG.

圖2所示為依據本發明實施例的晶片封裝結構的示意圖；2 is a schematic view showing a chip package structure according to an embodiment of the present invention;

圖3所示為圖2所示的一種晶片的電路原理框圖；3 is a circuit block diagram of a wafer shown in FIG. 2;

圖4所示為依據本發明實施例的晶片功能擴展的封裝結構示意圖；4 is a schematic diagram showing a package structure of a function expansion of a wafer according to an embodiment of the present invention;

圖5所示為依據本發明的第一示例晶片封裝方法的流程圖；Figure 5 is a flow chart showing a first exemplary wafer packaging method in accordance with the present invention;

圖6所示為依據本發明的第二示例晶片封裝方法的流程圖。Figure 6 is a flow chart showing a second exemplary wafer packaging method in accordance with the present invention.

201．．．晶片201. . . Wafer

202-1．．．第一接觸焊墊202-1. . . First contact pad

202-2．．．第二接觸焊墊202-2. . . Second contact pad

203．．．引線框架203. . . Lead frame

204．．．載片台204. . . Slide table

205．．．引腳205. . . Pin

206-1．．．第一接合引線206-1. . . First bond wire

206-2．．．第二接合引線206-2. . . Second bonding wire

Claims (10)

一種晶片封裝結構，其特徵在於該晶片封裝結構包括：晶片，該晶片上具有多個第一接觸焊墊和第二接觸焊墊；一引線框架，包括具有用於向外部連接的多個引腳，並且該晶片配置於該引線框架上；一組第一接合引線，用以將該第一接觸焊墊直接電連接至該引線框架；及一組第二接合引線，用以將該第二接觸焊墊電連接至該引線框架的該多個引腳，其中，該第一接觸焊墊為具有相同電位的接地焊墊，該一組第一接合引線為接地接合引線，該第二接觸焊墊包括一組電位變化的開關信號焊墊和具有相同電位的電源焊墊，與該開關信號焊墊連接的該一組第二接合引線之第一部分為開關信號接合引線，與該電源焊墊連接的該一組第二接合引線之第二部分為電源接合引線，其中，該開關信號接合引線和該接地接合引線呈交錯排列佈置。 A chip package structure, comprising: a wafer having a plurality of first contact pads and a second contact pad thereon; a lead frame including a plurality of pins for external connection And the wafer is disposed on the lead frame; a set of first bonding wires for electrically connecting the first contact pads directly to the lead frame; and a set of second bonding wires for the second contact The pad is electrically connected to the plurality of pins of the lead frame, wherein the first contact pad is a ground pad having the same potential, the set of first bonding wires being a ground bonding wire, the second contact pad a switch signal pad including a set of potential changes and a power pad having the same potential, and the first portion of the set of second bond wires connected to the switch signal pad is a switch signal bond lead connected to the power pad The second portion of the set of second bond wires is a power bond wire, wherein the switch signal bond wires and the ground bond wires are arranged in a staggered arrangement. 根據申請專利範圍第1項所述的晶片封裝結構，其中，該開關信號接合引線和該接地接合引線設置在該引線框架的同一側，並將該電源接合引線設置在該引線框架的相對的另一側。 The chip package structure of claim 1, wherein the switch signal bond wire and the ground bond wire are disposed on a same side of the lead frame, and the power bond wire is disposed on the opposite side of the lead frame One side. 根據申請專利範圍第1項所述的晶片封裝結構，其 中，進一步包括：外接電容直接連接在電源引腳和該引線框架的接地迴路。 The chip package structure according to claim 1, wherein The method further includes: the external capacitor is directly connected to the power pin and the ground loop of the lead frame. 根據申請專利範圍第2項所述的晶片封裝結構，其中，進一步包括：外接電容直接連接在電源引腳和該引線框架的接地迴路。 The chip package structure of claim 2, further comprising: an external capacitor directly connected to the power supply pin and the ground return of the lead frame. 根據申請專利範圍第1至4項中任一項所述的晶片封裝結構，其中，進一步包括一封裝體，用以包覆該晶片以及該焊墊，其中該引線框架暴露於該封裝體外。 The chip package structure according to any one of claims 1 to 4, further comprising a package for covering the wafer and the pad, wherein the lead frame is exposed to the outside of the package. 一種晶片封裝方法，包括以下步驟：步驟(1)：提供一個需進行封裝的晶片，該晶片上具有第一接觸焊墊和第二接觸焊墊；步驟(2)：提供一引線框架，其上具有提供向外部連接的多個引腳；步驟(3)：將該晶片相應地安裝在該引線框架上；步驟(4)：提供一組第一接合引線，以將該第一接觸焊墊直接電連接至該引線框架；及步驟(5)：提供一組第二接合引線，以將該第二接觸焊墊直接電連接至該引線框架的該多個引腳，其中該步驟(4)中，該第一接觸焊墊為具有相同電位的接地焊墊，該一組第一接合引線為接地接合引線，該步驟(5)中，與該一組第二接合引線連接的該第二接觸焊墊，包括一組電位變化的開關信號焊墊和具有相同電位的電源焊墊，與該開關信號焊墊連接的該一組第二接合引線之第一部分為信號接合引線，與該電源焊墊連接的該一 組第二接合引線之第二部分為電源接合引線，其中，將該開關信號接合引線和該接地接合引線呈交錯排列佈置。 A chip packaging method comprising the steps of: (1): providing a wafer to be packaged, the wafer having a first contact pad and a second contact pad; and (2): providing a lead frame thereon Having a plurality of leads for providing external connection; step (3): mounting the wafer on the lead frame correspondingly; and step (4): providing a set of first bonding leads to directly connect the first contact pads Electrically connected to the lead frame; and step (5): providing a set of second bonding wires to electrically connect the second contact pads directly to the plurality of pins of the lead frame, wherein the step (4) The first contact pad is a ground pad having the same potential, the set of first bond wires is a ground bond wire, and the second contact pad connected to the set of second bond wires in the step (5) a pad comprising a set of potential-changing switch signal pads and a power pad having the same potential, and the first portion of the set of second bond wires connected to the switch signal pads is a signal bond lead connected to the power pad The one The second portion of the set of second bond wires is a power bond wire, wherein the switch signal bond wires and the ground bond wires are arranged in a staggered arrangement. 根據申請專利範圍第6項所述的晶片封裝方法，其中，將該開關信號接合引線和該接地接合引線設置在該引線框架的同一側，並將該電源接合引線設置在該引線框架的相對的另一側。 The chip packaging method according to claim 6, wherein the switch signal bonding wire and the ground bonding wire are disposed on the same side of the lead frame, and the power bonding wire is disposed on the opposite side of the lead frame The other side. 根據申請專利範圍第6項所述的晶片封裝方法，其中，進一步包括：將外接電容直接連接在電源引腳和該引線框架的接地迴路。 The chip packaging method of claim 6, further comprising: directly connecting the external capacitor to the power supply pin and the ground return of the lead frame. 根據申請專利範圍第7項所述的晶片封裝方法，其中，進一步包括：將外接電容直接連接在電源引腳和該引線框架的接地迴路。 The chip packaging method of claim 7, further comprising: directly connecting the external capacitor to the power supply pin and the ground return of the lead frame. 根據申請專利範圍第6至9項中任一項所述的晶片封裝方法，其中，進一步包括：設置一封裝體，用以包覆該晶片以及該焊墊，並將該引線框架暴露於該封裝體外。 The chip packaging method according to any one of claims 6 to 9, further comprising: providing a package for covering the wafer and the bonding pad, and exposing the lead frame to the package in vitro.
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