TW201138045A - Chip package structure and its packaging method - Google Patents

Chip package structure and its packaging method Download PDF

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Publication number
TW201138045A
TW201138045A TW099112326A TW99112326A TW201138045A TW 201138045 A TW201138045 A TW 201138045A TW 099112326 A TW099112326 A TW 099112326A TW 99112326 A TW99112326 A TW 99112326A TW 201138045 A TW201138045 A TW 201138045A
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Taiwan
Prior art keywords
pad
wafer
lead frame
bonding
lead
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TW099112326A
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Chinese (zh)
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TWI446504B (en
Inventor
Wei Chen
xiao-chun Tan
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Silergy Corp
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Publication of TW201138045A publication Critical patent/TW201138045A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

The present invention relates to a chip package structure and its packaging method. The structure includes at least one chip, wherein each chip has a plurality of first contact solder pads and a plurality of second contact solder pads; a leadframe having a plurality of leads for connecting to outside, the chip being arranged on the leadframe; a set of first bonding wires for electrically connecting the first contact solder pads to the leadframe directly; and a set of second bonding wires for electrically connecting the second contact solder pads to the plurality of leads of the leadframe. The present invention is able to conveniently realize low-loss and easy-to-cool chips, and reduce the package size of the chip thereby facilitating function expansion of the chip.

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201138045 六、發明說明： 【發明所屬之技術領域】 本發明關於一種晶片封裝結構及其封裝方法，屬於半 導體元件及其製造方法》 【先前技術】 在半導體產業中，積體電路的生產主要可分爲三個階 段：積體電路的設計、積體電路的製作以及積體電路的封 裝。在積體電路的製作中，晶片由晶圓製作、形成積體電 路以及切割晶圓等步驟完成。當晶圓內部的積體電路完成 之後’再在晶圓上配置有多個焊墊，以使最終由晶圓切割 所形成的晶片可經由這些焊墊而向外電連接於一承載器。 承載器例如爲一引線框架或者一封裝基板。晶片可以打線 接合或者覆晶接合的方式連接至承載器上，使得晶片的這 些焊墊可電連接於承載器的接點，以構成一晶片封裝結構 〇 以引線框架爲晶片承載件的半導體封裝件，例如四方 扁平式半導體封裝件或者四方扁平無管腳式半導體封裝件 等，其製作方式均是在一具有載片台及多個引腳的引線框 架上粘置該半導體晶片，並且通過多條接合引線電連接該 晶片表面上的接觸焊墊和與其對應的多個引腳，然後以封 裝膠體包覆該晶片以及接合引線而形成一半導體封裝件。 由於封裝件上晶片集成度的提高，爲了保證電性品質 和減少雜訊，在進行封裝件的結構設計時’通常必須使晶 -5- 201138045 片具有接地（GND )和電源（IN )功能以及開關信號功能 (LX)，使其符合電性要求。 現有技術中，通常是利用多條引線分別將引線框架的 接地引腳、電源引腳、開關引腳對應的連接到晶片上的的 接地焊墊、電源焊墊和開關信號焊墊。 以單片晶片的封裝結構爲例，圖1A所示爲現有一種 晶片封裝結構的俯視示意圖，其包括一晶片1 0 1、一引線 框架1 03以及多條引線。晶片1 0 1配置於該引線框架的載 片台104上，多條引線106跨越該載片台104將晶片101 上的接觸焊墊1 02電連接至該引線框架1 03的相應的外接 引腳105上。以圖1A所示的晶片封裝結構爲例，晶片 1 0 1上的具有相同電位的一組接地焊墊和一組電源焊墊， 以及開關信號焊墊均通過接合引線106直接連接至引線框 架103上的對應引腳105。顯然，採用這種晶片封裝結構 ，增加了接地引線的長度，即增加了引線電阻，使得晶片 1 0 1的功率損耗增加。對於某些應用場合，由於晶片1 〇 1 上的接觸焊墊102以及引線框架103上的引腳105排列， 使得接合引線106不可避免的會有相互交叉的情況，進一 步增加了引線連接的複雜性，並且各引線相互之間的干擾 增加’使得晶片工作可靠性和穩定性下降，並且晶片制程 需要的矽片面積也較大。 如圖1 B所示，如果需要對晶片1 〇 1的功能進行擴展 ’則需要在原有晶片的基礎上重新進行電路設計以及佈局 ’接觸焊墊102和接合引線106的排布會更加複雜，也需 -6- 201138045 要增加較大面積的矽片。 【發明內容】 本發明的目的在於克服現有技術存在的不足，而提出 一種新的晶片封裝結構及其封裝方法，它根據晶片接觸焊 墊的類型採用不同的連接方式，以解決晶片損耗大、散熱 難，接合引線過多以及封裝晶片功能擴展的局限問題。 本發明的目的是通過如下技術方案來完成的，一種晶 片封裝結構，包括’· 晶片，該晶片上具有多個第一接觸焊墊和第二接觸焊 墊； 一引線框架，包括具有用於向外部連接的多個引腳， 並且該晶片配置於該引線框架上； 一組第一接合引線，用以將該第一接觸焊墊直接電連 接至該引線框架； 一組第二接合引線，用以將第二接觸焊墊電連接至該 引線框架的多個引腳。 該第一接觸焊墊爲具有相同電位的接地焊墊，該一組 第一接合引線爲接地接合引線，該第二接觸焊墊包括一組 電位變化的開關信號焊墊和具有相同電位的電源焊墊，與 開關信號焊墊連接的第一部分第二接合引線爲開關信號接 合引線，與電源焊墊連接的第二部分第二接合引線爲電源 接合引線。 該開關信號接合引線和接地接合引線設置在該引線框 201138045 架的同一側，並將電源接合引線設置在該引線框架的相對 的另一側。 該信號接合引線和接地接合引線呈交錯排列佈置。 本發明還包括有一用以包覆該晶片以及焊墊的封裝體 ，該引線框架暴露於該封裝體外。 —種晶片封裝方法，包括以下步驟： 步驟（1 ):提供至少一個需進行封裝的晶片，該晶 片上具有第一接觸焊墊和第二接觸焊墊； 步驟（2 ):提供一引線框架，其上具有提供向外部 連接的多個引腳； 步驟（3 ):將該晶片相應地安裝在該引線框架上； 步驟（4 ):提供一組第一接合引線，以將第一接觸 焊墊直接電連接至該引線框架； 步驟（5 ):提供一組第二接合引線，以將第二接觸 焊墊直接電連接至該引線框的多個引腳。 該步驟（4)中’第一接觸焊墊爲具有相同電位的接 地焊墊，該第一接合引線爲接地接合引線；該步驟（5 ) 中，與該一組第二接合引線連接的第二接觸焊墊，包括一 組電位變化的開關信號焊墊和具有相同電位的電源焊墊， 與開關信號焊墊連接的部分第二接合引線爲信號接合引線 ’與電源焊墊連接的部分第二接合引線爲電源接合引線。 本發明進一步包括：將該開關信號接合引線和接地接 合引線設置在該引線框架的同一側，並將電源接合引線設 置在該引線框架的相對的另一側》 -8 - 201138045 本發明進一步包括，將該信號接合引線和接地接合引 線呈交錯排列佈置。 本發明進一步包括：設置一封裝體，用以包覆該晶片 以及焊墊，並將該引線框架暴露於該封裝體外。 採用本發明優選實施例的晶片封裝結構以及封裝方法 ，可以方便的實現： (1)對具有相同電位的接地接觸焊墊採甩直接連接 至引線框架的連接方式，減小了接地引線的長度，即減小 了引線電阻，從而降低了功率損耗；晶片的接地引線直接 連接至引線框架，減小了接地引線和引線框架上的載片台 之間的間隙，使得散熱效果較好；另外，採用這種方式， 熱量可以直接經由接地引線直接傳遞到引線框架上，因此 熱阻較小，散熱好； 對於電源管理類晶片，通常採用外接電容、電阻的方 式來設置晶片的工作頻率，採用本發明實施例該的封裝結 構，則外接電容可以直接連接在電源引腳和引線框架的接 地回路，保證了電容回路最小，連線最短，因此由連線引 起的走線電感最小，增加了晶片的工作穩定性和可靠性， 減小了晶片承受的應力，也使得晶片的尺寸最小。 (2 )接地引線和開關信號引線交錯並列排列佈置使 得晶片的制程所使用的矽片面積較小。 (3 )不用複雜的引線連接，焊墊的佈置即可以在已 有晶片基礎上實現其功能的擴展，其實現方式更加方便和 靈活。 -9 201138045 【實施方式】 以下結合附圖對本發明的優選實施例進行詳細描述， 但本發明並不僅僅限於這些實施例。本發明涵蓋任何在本 發明的精髓和範圍上做的替代、修改、等效方法以及方案 。爲了使公眾對本發明有徹底的瞭解，在以下本發明優選 實施例中詳細說明了具體的細節，而對本領域技術人員來 說沒有這些細節的描述也可以完全理解本發明。 圖2所示的是本發明一實施例的晶片封裝結構的示意 圖’該實施例的晶片封裝結構包括晶片20 1、引線框架 203、第一接合引線206- 1和第二接合引線206-2。晶片 201上具有第一接觸焊墊2 02-1和第二接觸焊墊2 02-2，其 中第一接觸焊墊202- 1和第二接觸焊墊202-2配置於晶片 20 1的邊緣處，以方便於進行打線制程。 引線框架203包括多個向外部連接的引腳205，第一 接合引線206_1將第一接觸焊墊202- 1直接電連接至引線 框架203，第二接合引線206-2將第二接觸焊墊202-2電 連接至該引線框架203的多個引腳2 05。 由於封裝件上晶片集成度的提高，爲了保證電性品質 和減少雜訊，在進行封裝件的結構設計時，通常必須使該 晶片20 1具有接地（GND )和電源（IN )功能以及信號開 關功能（LX )，使其符合電性要求》這裏，以第一接觸焊 墊202- 1爲接地焊墊、第二接觸焊墊202-2爲電源焊墊和 開關信號焊墊爲例，將接地焊墊直接連接至引線框架203 -10- 201138045 的第一接合引線206-1爲接地引線，將電源焊墊連 線框架的電源引腳的第二接合引線206-2爲電源引 開關信號焊墊連接至引線框架的開關引腳的第二接 2 06-2爲開關信號引線。該接地引線和開關信號引 在該引線框架203的同一側，並且兩者呈並列交錯 置，該電源引線分佈在該引線框架203的相對的另 對應的，晶片2 0 1上的接地焊墊和開關信號焊墊位 片的同一側，並且兩者成並列交錯排列佈置，電源 於該晶片的相對的另一側。 以電源管理類晶片爲例，圖3所示爲該晶片的 理圖，包括上開關管Q1，下開關管Q2，電源以及 對該晶片的封裝則要求其具有電源引腳IN、接 GND以及開關引腳LX，因此可以採用圖2所示的 實施例該的封裝結構。即晶片的電源焊墊通過一組 合引線即電源引線跨過該引線框架直接連接至引線 電源引腳，開關信號焊墊通過一組第二結合引線即 線擴過該引線框架直接連接至引線框架的開關引腳 焊墊通過一組第一接合引線即接地引線直接連接至 框架。 採用圖2所不的晶片封裝結構’其需要的接地 長度較小，因此由引線產生的引線電阻較小，使得 功率損耗較小；晶片的接地引線直接連接至引線框 小了接地引線和引線框架上的載片台之間的間隙’ 熱效果較好；另外’採用這種方式’熱量可以直接 接至引 線，將 合引線 線分佈 排列佈 -側。 於該晶 焊墊位 電路原 地。則 地引腳 本發明 第二接 框架的 開關引 ，接地 該引線 引線的 晶片的 架，減 使得散 經由接 -11 - 201138045 地引線直接傳遞到引線框架上，因此熱阻較小，散熱好。 並且，開關引線和接地引線位於引線框架的同一側， 電源引線位於引線框架的相對的另一側，其中該開關引線 和接地引線呈交錯並列排列佈置。 對電源管理類晶片，通常採用外接電阻、電容的方式 來調節電源晶片的工作頻率，在該實施例中，外接電容可 以連接在引線框架的電源引腳和引線框架上載片台的地電 位’因此電容回路最小，引線也最短，也使得整體尺寸較 小0 電壓應力如公式（1)計算， V = L~ dt 因此可知，採用實施例所示的封裝結構，該接合引線 的走線電感較小，因此，承受的電壓應力也較小。 採用現有技術，如果需要對晶片的功能進行擴展，如 圖1B所示則需要在原有晶片的基礎上重新進行電路設計 以及佈局，接觸焊墊和接合引線的排布會更加複雜，也需 要增加較大面積的矽片。 圖4所示爲採用本發明在原有晶片基礎上需進行功能 擴展的晶片封裝結構的示意圖。採用本發明實施例的晶片 封裝結構，如果需要對晶片20 1的功能進行擴展，則只需 要在原晶片結構佈局的基礎上，沿原佈局方向增加一定面 積的矽片，以及相應的接合引線、接觸焊墊，不影響原有 -12- 201138045 引線以及焊墊的排列佈置，其實現更加方便和靈活。如圖 4所示的晶片封裝結構爲例，該晶片20 1包括接地、電源 、開關功能以及相應的控制電路部分2 0 7，其中接地、電 源、開關信號功能按照本發明實施例所示的晶片封裝結構 進行封裝。如果需要在原有晶片基礎上進行新功能的擴展 ’則僅在原晶片佈局沿線上增加較小面積的矽片、以及對 應的.引腳、焊墊，即可以在不影響原有引線以及焊墊的排 列佈置的基礎上實現晶片功能的擴展。圖4中其他的內容 與圖2所示的相同。 圖5所示爲採用本發明的晶片封裝方法的流程圖，其 包括以下步驟： S5〇 1 :提供一個需進行封裝的晶片，該晶片上具有第 一接觸焊墊和第二接觸焊墊； S 5 02 :提供一引線框架，其上具有提供向外部連接的 多個引腳； S 5 〇3 :提供一組第一接合引線，以將第一接觸焊墊直 接電性連接至該引線框架； S 5 04 :提供一組第二接合引線，以將第二接觸焊墊直 接電性連接至該引線框的多個引腳。 圖6是以具有接地、電源和開關信號功能的晶片爲例 ’來具體說明採用本發明實施例的晶片封裝方法的流程圖 ，其包括以下步驟： S 601 :提供一個需進行封裝的晶片，該晶片上具有接 地焊墊、電源焊墊和開關信號焊墊； -13- 201138045 S 6 02 :提供一引線框架，其上具有提供向外部連接的 多個引腳； 5603 :在晶片一側提供接地引線，以將接地焊墊直接 電性連接至該引線框架； 5604 :在與接地引線側的相對一側設置電源引線，以 將電源焊墊直接電性連接至該引線框架的電源引腳； S 6 05 :與接地引線同側，並呈交錯並列設置開關信號 引線，以將開關焊墊直接電性連接至該引線框架的開關引 腳。 採用本發明的晶片封裝方法，需要的接地引線的長度 較小，因此由引線產生的引線電阻較小，使得晶片的功率 損耗較小；晶片的接地引線直接連接至引線框架，減小了 接地引線和引線框架上的載片台之間的間隙，使得散熱效 果較好；另外，採用這種方式，熱量可以直接經由接地引 線直接傳遞到引線框架上，因此熱阻較小，散熱好。並且 ，可以很方便的實現晶片數目的擴展，而不用複雜的引線 連接，焊墊的佈置，以及需要考慮從各個晶片的位置佈置 等問題。 以上特定實施例通過圖示和文字描述對本發明的晶片 封裝結構以及晶片封裝方法進行了詳細描述。這些實施例 並不是完全詳盡的，也不限制該發明僅爲該的具體實施例 。顯然，根據上述教導，可以做很多的修改和變化。例如 ，本發明以具有接地、電源和信號引腳的晶片爲例，說明 了不同類型的接合引線、以及引線之間的排列組合方式。 -14- 201138045 但是依據本發明的教導可以推知其他的晶片類型，以及其 他的引線結合方式等。本說明書選取並具體描述這些實施 例，是爲了最好地解釋本發明的原理和實際應用，從而使 所屬技術領域技術人員能最好地利用這個發明。修改的實 施例同樣也適用於預期的特定應用。本發明的範圍爲申請 專利範圍全部範圍以及其等效物。 【圖式簡單說明】 圖1A所示爲採用現有技術的一種單片晶片封裝結構 的示意圖； 圖1B所示爲採用圖1A所示的晶片封裝結構功能擴展 的示意圖： 圖2所示爲依據本發明實施例的晶片封裝結構的示意 圖； _ 圖3所示爲圖2所示的一種晶片的電路原理框圖； 圖4所示爲依據本發明實施例的晶片功能擴展的封裝 結構示意圖； 圖5所示爲依據本發明的第一示例晶片封裝方法的流 程圖； 圖6所示爲依據本發明的第二示例晶片封裝方法的流 程圖。 【主要元件符號說明】 1 01 :晶片 -15- 201138045 102 :接觸 103 :引線 104 :載片 105 :引腳 106 :接合 2 0 1 :晶片 202-1 :第 202-2 :第 203 :引線 204 :載片 205 :引腳 206-1 ：第 焊墊 框架 台 引線 一接觸焊墊 二接觸焊墊 框架 台 一接合引線 206-2 :第二接合引線BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip package structure and a package method thereof, and belongs to a semiconductor device and a method of fabricating the same. [Prior Art] In the semiconductor industry, the production of integrated circuits is mainly separable. There are three stages: the design of the integrated circuit, the fabrication of the integrated circuit, and the packaging of the integrated circuit. In the fabrication of the integrated circuit, the wafer is completed by steps of fabricating, forming an integrated circuit, and dicing the wafer. After the integrated circuit inside the wafer is completed, a plurality of pads are disposed on the wafer so that the wafers finally formed by wafer dicing can be electrically connected to a carrier via these pads. The carrier is, for example, a lead frame or a package substrate. The wafers may be bonded to the carrier by wire bonding or flip chip bonding so that the pads of the wafer can be electrically connected to the contacts of the carrier to form a chip package structure and the semiconductor package with the lead frame as the wafer carrier. For example, a quad flat semiconductor package or a quad flat unpinned semiconductor package is fabricated by attaching the semiconductor wafer to a lead frame having a carrier and a plurality of leads, and passing through a plurality of The bonding leads electrically connect the contact pads on the surface of the wafer and the plurality of pins corresponding thereto, and then coat the wafer with the encapsulant and bond the leads to form a semiconductor package. Due to the increased integration of the wafer on the package, in order to ensure the electrical quality and reduce the noise, the structure of the package must be designed to have the ground (GND) and power (IN) functions of the crystal-5-201138045. The switching signal function (LX) makes it compliant with electrical requirements. In the prior art, a grounding pin, a power pin, and a switch pin of a lead frame are respectively connected to a ground pad, a power pad, and a switch signal pad on a wafer by using a plurality of leads. Taking a package structure of a single wafer as an example, FIG. 1A is a top plan view of a conventional chip package structure including a wafer 110, a lead frame 103, and a plurality of leads. The wafer 110 is disposed on the stage 104 of the lead frame, and the plurality of leads 106 electrically connect the contact pads 102 on the wafer 101 to the corresponding external pins of the lead frame 103 across the stage 104. 105 on. Taking the chip package structure shown in FIG. 1A as an example, a set of ground pads and a set of power pads having the same potential on the wafer 101 and the switch signal pads are directly connected to the lead frame 103 through the bonding wires 106. Corresponding pin 105 on. Obviously, with such a chip package structure, the length of the ground lead is increased, that is, the lead resistance is increased, so that the power loss of the wafer 101 is increased. For some applications, since the contact pads 102 on the wafer 1 〇 1 and the leads 105 on the lead frame 103 are arranged, the bonding leads 106 inevitably cross each other, further increasing the complexity of the wiring connections. And the increase in interference between the leads is such that the reliability and stability of the wafer are degraded, and the area of the wafer required for the wafer process is also large. As shown in FIG. 1B, if it is necessary to expand the function of the wafer 1 〇1, it is necessary to re-design the circuit and lay out the layout of the contact pads 102 and the bonding leads 106 on the basis of the original wafer. Need -6- 201138045 To increase the size of the cymbals. SUMMARY OF THE INVENTION The object of the present invention is to overcome the deficiencies of the prior art, and to provide a new chip package structure and a package method thereof, which adopt different connection modes according to the type of the wafer contact pad to solve the problem of large loss of the chip and heat dissipation. Difficulties, too many bond leads and limitations of packaged die function expansion. The object of the present invention is achieved by the following technical solution, a chip package structure including a wafer having a plurality of first contact pads and a second contact pad thereon; a lead frame including a plurality of externally connected pins, and the wafer is disposed on the lead frame; a set of first bonding wires for electrically connecting the first contact pads directly to the lead frame; and a set of second bonding wires for A second contact pad is electrically connected to the plurality of leads of the lead frame. The first contact pad is a ground pad having the same potential, the set of first bond wires being a ground bond wire, the second contact pad comprising a set of potential-changing switch signal pads and a power supply having the same potential The pad, the first portion of the second bond wire connected to the switch signal pad is a switch signal bond wire, and the second portion of the second bond wire connected to the power pad is a power bond wire. The switch signal bond wires and ground bond wires are disposed on the same side of the lead frame 201138045 and the power bond wires are disposed on the opposite side of the lead frame. The signal bond wires and the ground bond wires are arranged in a staggered arrangement. The invention also includes a package for encasing the wafer and the pad, the lead frame being exposed to the exterior of the package. a wafer packaging method comprising the following steps: Step (1): providing at least one wafer to be packaged, the wafer having a first contact pad and a second contact pad; and step (2): providing a lead frame, There are a plurality of pins provided for external connection; step (3): mounting the wafer on the lead frame correspondingly; step (4): providing a set of first bonding leads to be used for the first contact pads Directly electrically connected to the lead frame; Step (5): providing a set of second bond wires to electrically connect the second contact pads directly to the plurality of pins of the lead frame. In the step (4), the first contact pad is a ground pad having the same potential, the first bonding wire is a ground bonding wire; and in the step (5), the second bonding wire is connected to the second bonding wire. The contact pad includes a set of potential-changing switch signal pads and a power pad having the same potential, and a portion of the second bond wire connected to the switch signal pad is a second bond of the signal bond wire 'connected to the power pad The leads are power bond leads. The present invention further includes: disposing the switch signal bonding wire and the ground bonding wire on the same side of the lead frame, and disposing the power supply bonding wire on the opposite side of the lead frame" -8 - 201138045 The present invention further includes The signal bond wires and the ground bond wires are arranged in a staggered arrangement. The invention further includes providing a package for encasing the wafer and the pad and exposing the lead frame to the outside of the package. The chip package structure and the packaging method according to the preferred embodiment of the present invention can be conveniently implemented: (1) the ground contact pad having the same potential is directly connected to the lead frame, and the length of the ground lead is reduced. That is, the lead resistance is reduced, thereby reducing the power loss; the ground lead of the wafer is directly connected to the lead frame, which reduces the gap between the ground lead and the stage on the lead frame, so that the heat dissipation effect is better; In this way, heat can be directly transmitted to the lead frame through the ground lead, so the thermal resistance is small, and the heat dissipation is good. For the power management type chip, the working frequency of the wafer is usually set by using an external capacitor and a resistor, and the present invention is adopted. In the package structure of the embodiment, the external capacitor can be directly connected to the grounding loop of the power supply pin and the lead frame, thereby ensuring the minimum capacitance circuit and the shortest connection line, so the wiring inductance caused by the connection is minimized, and the work of the wafer is increased. Stability and reliability, reducing the stress on the wafer and also making the ruler of the wafer A minimum. (2) The grounding lead and the switching signal leads are alternately arranged side by side so that the area of the wafer used in the wafer process is small. (3) Without the complicated lead connection, the arrangement of the pads can realize the expansion of its functions on the basis of the existing wafer, and the implementation thereof is more convenient and flexible. -9 201138045 [Embodiment] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the invention is not limited to these embodiments. The present invention encompasses any alternatives, modifications, equivalents and alternatives to the spirit and scope of the invention. The detailed description of the preferred embodiments of the invention are in the 2 is a schematic view of a wafer package structure of an embodiment of the present invention. The wafer package structure of this embodiment includes a wafer 20 1 , a lead frame 203, a first bonding wire 206-1, and a second bonding wire 206-2. The wafer 201 has a first contact pad 206-1 and a second contact pad 202-2, wherein the first contact pad 202-1 and the second contact pad 202-2 are disposed at the edge of the wafer 201 In order to facilitate the wire-making process. The lead frame 203 includes a plurality of externally connected pins 205, the first bonding wires 206_1 directly electrically connect the first contact pads 202-1 to the lead frame 203, and the second bonding wires 206-2 connect the second contact pads 202 -2 is electrically connected to a plurality of pins 2 05 of the lead frame 203. Due to the increased integration of the wafer on the package, in order to ensure the electrical quality and reduce the noise, the structure of the package must be designed to have the ground (GND) and power (IN) functions and signal switches. Function (LX), making it meet the electrical requirements. Here, the first contact pad 202-1 is the ground pad, and the second contact pad 202-2 is the power pad and the switch signal pad. The first bonding wire 206-1 of the soldering pad directly connected to the lead frame 203 -10- 201138045 is a grounding lead, and the second bonding wire 206-2 of the power supply pin of the power pad bonding frame is a power guiding switch signal pad The second connection 2 06-2 connected to the switch pin of the lead frame is the switching signal lead. The ground lead and the switch signal are routed on the same side of the lead frame 203, and are staggered in parallel. The power lead is distributed on the opposite counterpart of the lead frame 203, the ground pad on the wafer 210 and The same side of the switch signal pad is placed, and the two are arranged in a staggered arrangement, with power being applied to the opposite side of the wafer. Taking a power management type chip as an example, FIG. 3 shows a schematic diagram of the chip, including an upper switch Q1, a lower switch Q2, a power supply, and a package for the chip, which is required to have a power pin IN, a GND, and a switch. Pin LX, therefore, the package structure of the embodiment shown in FIG. 2 can be employed. That is, the power pad of the wafer is directly connected to the lead power supply pin through a lead wire, that is, the power supply lead, and the switch signal pad is directly connected to the lead frame through a set of second bonding wires, that is, wires extending through the lead frame. The switch pin pads are directly connected to the frame by a set of first bond leads, ie, ground leads. The chip package structure shown in FIG. 2 requires less grounding length, so the lead resistance generated by the leads is smaller, resulting in less power loss; the ground lead of the wafer is directly connected to the lead frame, and the ground lead and the lead frame are small. The gap between the upper stage is better. The heat effect is better. In addition, 'the heat can be directly connected to the lead, and the combined lead line is arranged on the side of the cloth. The pad position circuit is in place. Then, the ground lead of the second frame of the present invention is grounded, and the lead frame of the lead wire is grounded, so that the ground wire of the lead wire is directly transmitted to the lead frame via the -11 - 201138045, so that the heat resistance is small and the heat dissipation is good. Also, the switch lead and the ground lead are on the same side of the lead frame, and the power lead is located on the opposite side of the lead frame, wherein the switch lead and the ground lead are arranged in a staggered arrangement. For the power management type chip, the operating frequency of the power chip is usually adjusted by using an external resistor and a capacitor. In this embodiment, the external capacitor can be connected to the power supply pin of the lead frame and the ground potential of the lead frame to carry the film. The capacitor circuit is the smallest, and the lead wire is also the shortest, which also makes the overall size smaller. 0 The voltage stress is calculated by the formula (1), V = L~dt. Therefore, it can be seen that the wiring structure of the bonding lead is small by the package structure shown in the embodiment. Therefore, the voltage stress to withstand is also small. According to the prior art, if the function of the wafer needs to be expanded, as shown in FIG. 1B, the circuit design and layout need to be re-established on the basis of the original wafer, and the arrangement of the contact pads and the bonding leads is more complicated, and it is also necessary to increase the ratio. Large area of sepals. Fig. 4 is a schematic view showing a wafer package structure to be expanded on the basis of the conventional wafer by the present invention. According to the chip package structure of the embodiment of the present invention, if it is required to expand the function of the wafer 20 1 , it is only necessary to add a certain area of the cymbal in the original layout direction on the basis of the original wafer structure layout, and the corresponding bonding leads and contacts. The solder pads do not affect the original -12-201138045 leads and the arrangement of the pads, which is more convenient and flexible. For example, the chip package structure shown in FIG. 4 includes a ground, a power supply, a switching function, and a corresponding control circuit portion 206, wherein the ground, power, and switching signals function according to the wafer shown in the embodiment of the present invention. The package structure is packaged. If it is necessary to expand the new functions on the basis of the original wafers, then only a small area of the dies and the corresponding pins and pads can be added along the original wafer layout, which can affect the original leads and pads. The expansion of the wafer function is achieved on the basis of the arrangement. The other contents in Fig. 4 are the same as those shown in Fig. 2. 5 is a flow chart showing a method of wafer packaging using the present invention, comprising the steps of: S5〇1: providing a wafer to be packaged, the wafer having a first contact pad and a second contact pad; 5 02: providing a lead frame having a plurality of pins for providing external connection; S 5 〇 3: providing a set of first bonding wires to directly electrically connect the first contact pads to the lead frame; S 5 04 : providing a set of second bonding wires to electrically connect the second contact pads directly to the plurality of pins of the lead frame. 6 is a flow chart illustrating a wafer packaging method using an embodiment of the present invention by taking a wafer having a function of grounding, power, and switching signals as an example, and includes the following steps: S 601: providing a wafer to be packaged, a ground pad, a power pad, and a switch signal pad on the wafer; -13- 201138045 S 6 02: a lead frame having a plurality of leads for external connection; 5603: grounding on one side of the wafer a lead wire for directly electrically connecting the ground pad to the lead frame; 5604: providing a power lead on a side opposite to the ground lead side to directly electrically connect the power pad to the power pin of the lead frame; 6 05 : The same side as the grounding lead, and the switching signal leads are arranged in parallel to electrically connect the switch pads directly to the switch pins of the lead frame. With the chip packaging method of the present invention, the required length of the ground lead is small, so the lead resistance generated by the lead is small, so that the power loss of the wafer is small; the ground lead of the wafer is directly connected to the lead frame, and the ground lead is reduced. The gap between the stage and the stage on the lead frame makes the heat dissipation better; in addition, in this way, heat can be directly transmitted to the lead frame directly via the ground lead, so that the thermal resistance is small and the heat dissipation is good. Moreover, it is convenient to realize the expansion of the number of wafers without complicated wiring connections, arrangement of solder pads, and consideration of the positional arrangement from the respective wafers. The above specific embodiments have described the wafer package structure and the wafer package method of the present invention in detail by way of illustration and text. These examples are not intended to be exhaustive or to limit the invention to the particular embodiments. Obviously, many modifications and variations are possible in light of the above teaching. For example, the present invention is exemplified by a wafer having a ground, a power supply, and a signal pin, illustrating different types of bond leads, and the arrangement of the arrangements between the leads. -14- 201138045 However, other wafer types, as well as other wire bonding methods, etc., can be inferred in accordance with the teachings of the present invention. The present invention has been chosen and described in detail to best explain the principles of the invention and the application thereof. The modified embodiment also applies to the intended specific application. The scope of the invention is the full scope of the claims and the equivalents thereof. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a schematic view showing a monolithic chip package structure using the prior art; FIG. 1B is a schematic view showing the function expansion of the chip package structure shown in FIG. 1A: FIG. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3 is a circuit block diagram of a wafer shown in FIG. 2; FIG. 4 is a schematic diagram showing a package structure of a wafer function expansion according to an embodiment of the present invention; A flow chart of a first exemplary wafer packaging method in accordance with the present invention is shown; and Figure 6 is a flow chart of a second exemplary wafer packaging method in accordance with the present invention. [Description of main component symbols] 1 01 : Wafer-15-201138045 102 : Contact 103 : Lead 104 : Carrier 105 : Pin 106 : Bonding 2 0 1 : Wafer 202-1 : 202-2 : 203 : Lead 204 : Carrier 205 : Pin 206-1 : Lead pad frame stage lead - Contact pad 2 Contact pad frame stage 1 Bonding lead 206-2 : Second bonding lead

Claims (1)

201138045 七、申請專利範圍： 1. 一種晶片封裝結構，其特徵在於它包括： 晶片，該晶片上具有多個第一接觸焊墊和第二接觸焊 墊； 一引線框架，包括具有用於向外部連接的多個引腳， 並且該晶片配置於該引線框架上； 一組第一接合引線，用以將該第一接觸焊墊直接電連 接至該引線框架；及__ 一組第二接合引線，用以將第二接觸焊墊電連接至該 引線框架的多個引腳。 2. 根據申請專利範圍第1項所述的晶片封裝結構，其 中，該第一接觸焊墊爲具有相同電位的接地焊墊，該一組 第一接合引線爲接地接合引線，該第二接觸焊墊包括一組 電位變化的開關信號焊墊和具有相同電位的電源焊墊，與 開關信號焊墊連接的第一部分第二接合引線爲開關信號接 合引線’與電源焊墊連接的第二部分第二接合引線爲電源 接合引線。 3. 根據申請專利範圍第2項所述的晶片封裝結構，其 中，該開關信號接合引線和接地接合引線設置在該引線框 架的同一側’並將電源接合引線設置在該引線框架的相對 的另一側。 4. 根據申請專利範圍第3項所述的晶片封裝結構，其 中’該信號接合引線和接地接合引線呈交錯排列佈置。 5 _根據申請專利範圍第1至4項所述的任一晶片封裝 -17- 201138045 結構，其中，進一步包括一封裝體，用以包覆該晶片以及 焊墊’其中該引線框架暴露於該封裝體外。 6. —種晶片封裝方法，包括以下步驟： 步驟（1 ):提供~個需進行封裝的晶片，該晶片上 具有第一接觸焊塾和第二接觸焊楚； 步驟（2 ):提供一引線框架，其上具有提供向外部 連接的多個引腳； 步驟（3 ):將該晶片相應地安裝在該引線框架上； 步驟（4 ):提供一組第一接合引線，以將第一接觸 焊墊直接電連接至該引線框架；及 步驟（5 ):提供一組第二接合引線，以將第二接觸 焊墊直接電連接至該引線框的多個引腳。 7 .根據申請專利範圍第6項所述的晶片封裝方法，其 中該步驟（4)中，第一接觸焊墊爲具有相同電位的接地 焊塾，該第一接合引線爲接地接合引線，該步驟（5)中 ，與該一組第二接合引線連接的第二接觸焊墊，包括一組 電位變化的開關信號焊墊和具有相同電位的電源焊墊，與 開關信號焊墊連接的第一部分第二接合引線爲信號接合引 線，與電源焊墊連接的第二部分第二接合引線爲電源接合 引線》 8 ·根據申請專利範圍第7項所述的晶片封裝方法，其 中，進一步包括：將該開關信號接合引線和接地接合引線 設置在該引線框架的同一側，並將電源接合引線設置在該 引線框架的相對的另一側。 -18 - 201138045 9.根據申請專利範圍第7項所述的晶片封裝方法，其 中，進一步包括，將該信號接合引線和接地接合引線呈交 錯排列佈置。 1 0.根據申請專利範圍第6至9項所述的任一晶片封 裝方法，其中，進一步包括：設置一封裝體，用以包覆該 晶片以及焊墊，並將該引線框架暴露於該封裝體外。 -19-201138045 VII. Patent application scope: 1. A wafer package structure, characterized in that it comprises: a wafer having a plurality of first contact pads and second contact pads thereon; a lead frame comprising: for externally Connecting a plurality of pins, and the wafer is disposed on the lead frame; a set of first bonding wires for electrically connecting the first contact pads directly to the lead frame; and __ a set of second bonding wires The second contact pad is electrically connected to the plurality of pins of the lead frame. 2. The chip package structure of claim 1, wherein the first contact pad is a ground pad having the same potential, the set of first bond wires being a ground bond wire, the second contact pad The pad includes a set of potential-changing switch signal pads and a power pad having the same potential, and the first portion of the second bond wire connected to the switch signal pad is a switch signal bond wire 'the second portion connected to the power pad> The bond wires are power bond wires. 3. The chip package structure according to claim 2, wherein the switch signal bonding wire and the ground bonding wire are disposed on the same side of the lead frame and the power supply bonding wire is disposed on the opposite side of the lead frame One side. 4. The chip package structure of claim 3, wherein the signal bond wire and the ground bond wire are arranged in a staggered arrangement. The 177-201138045 structure according to any one of claims 1 to 4, further comprising a package for covering the wafer and a pad, wherein the lead frame is exposed to the package in vitro. 6. A wafer packaging method comprising the steps of: (1): providing a wafer to be packaged, the wafer having a first contact pad and a second contact pad; and step (2): providing a lead a frame having a plurality of pins for providing external connection; step (3): mounting the wafer on the lead frame correspondingly; and step (4): providing a set of first bonding leads to connect the first contact The pad is directly electrically connected to the lead frame; and step (5): providing a set of second bond wires to electrically connect the second contact pads directly to the plurality of pins of the lead frame. The chip packaging method according to claim 6, wherein in the step (4), the first contact pad is a ground pad having the same potential, and the first bonding wire is a ground bonding wire, the step (5) wherein the second contact pad connected to the set of second bonding wires comprises a set of switching signal pads having a potential change and a power pad having the same potential, and the first portion connected to the switch signal pad The second bonding lead is a signal bonding lead, and the second portion of the second bonding lead connected to the power supply pad is a power supply bonding lead. The chip packaging method according to claim 7 , further comprising: the switch Signal bonding leads and ground bonding leads are disposed on the same side of the lead frame, and power supply bonding leads are disposed on opposite sides of the lead frame. The chip packaging method of claim 7, wherein the signal bonding wire and the ground bonding wire are arranged in an erroneous arrangement. The method of claim 1 , wherein the method further comprises: providing a package for covering the wafer and the pad, and exposing the lead frame to the package in vitro. -19-
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI716198B (en) * 2019-10-16 2021-01-11 南亞科技股份有限公司 Chip-package device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI716198B (en) * 2019-10-16 2021-01-11 南亞科技股份有限公司 Chip-package device

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