TWI446080B - Display panel - Google Patents

Description

Display panel

The present invention relates to a display panel, and more particularly to a display panel that can avoid light leakage problems.

The display panel mainly comprises two substrates, and a display medium layer disposed between the two substrates. For example, the liquid crystal display panel includes an array substrate, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate. In order to maintain a gap between the array substrate and the color filter substrate, a spacer is disposed between the array substrate and the color filter substrate. In general, a conventional liquid crystal display panel supports a gap between an array substrate and a color filter substrate by using a photoresist spacer disposed between the array substrate and the color filter substrate and corresponding to the gate line. However, the liquid crystal display panel undergoes a press test before leaving the factory. After the press test, the photoresist spacer is often displaced to the open area due to being pressed, and causes damage to the alignment film. Damage to the alignment film affects the rotation of the liquid crystal molecules and causes light leakage problems.

One of the objects of the present invention is to provide a display panel to solve the problem of light leakage caused by the displacement of the photoresist spacer of the display panel.

A preferred embodiment of the present invention provides a display panel including a first substrate structure, a second substrate structure facing the first substrate structure, and a plurality of photoresist spacers located on the first substrate structure and the second substrate structure. And a display medium is located between the first substrate structure and the second substrate structure. The first substrate structure includes a first substrate, a plurality of sub-pixel units are disposed on the first substrate, a plurality of gate lines are disposed substantially parallel to each other on the first substrate, and the plurality of data lines are substantially parallel to each other. a first capacitor compensation electrode, a second capacitor compensation electrode, a first drain extension, and a second drain extension. Each pixel unit includes a first pixel, a second pixel, a third pixel, and a fourth pixel, and the first pixel and the second pixel are respectively located in the secondary pixel. The two diagonal elements of the unit are diagonally opposite, and the third pixel and the fourth pixel are respectively located at the other diagonally opposite corners of the sub-pixel unit. The gate line includes a first gate line disposed between the first pixel and the third pixel and between the second pixel and the fourth pixel and adjacent to the first pixel and the third pixel For driving the first pixel; a second gate line is disposed between the first pixel and the third pixel and between the second pixel and the fourth pixel and adjacent to the second pixel And a fourth pixel for driving the second pixel; a third gate line is disposed on the other side of the first pixel and the third pixel relative to the first gate line for driving a third pixel; and a fourth gate line disposed on the other side of the second pixel and the fourth pixel relative to the second gate line for driving the fourth pixel. The data line intersects the gate line, and the data line includes a first data line disposed on the other side of the first pixel and the fourth pixel relative to the second pixel and the third pixel, Driving the first pixel and the fourth pixel; and a second data line is set on the third pixel and the second pixel on the other side of the first pixel and the fourth pixel, Used to drive the third pixel and the second pixel. The first capacitance compensation electrode is coupled to the first gate line and extends along a first direction to between the first pixel and the third pixel. The second capacitance compensation electrode is coupled to the second gate line and extends in a second direction opposite to the first direction to between the second pixel and the fourth pixel. The first drain extension is located within the first pixel and partially overlaps the first capacitance compensation electrode. The second drain extension is located within the second pixel and partially overlaps the second capacitance compensation electrode. Each photoresist spacer is at least partially overlapped with one of the first capacitance compensation electrode and the second capacitance compensation electrode.

The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .

Please refer to Figure 1 and Figure 2. 1 is a schematic view showing a display panel according to a first preferred embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line A-A' of FIG. 1 for highlighting the display of the embodiment. The configuration of the panel, the first figure does not show the second substrate structure and the display medium. As shown in FIG. 1 and FIG. 2 , the display panel 1 of the present embodiment mainly includes a first substrate structure 10 , a second substrate structure 20 , a plurality of photoresist spacers 30 , and a display medium 40 . In this embodiment, the first substrate structure 10 is an array substrate structure, and the second substrate structure 20 is a color filter substrate structure, but is not limited thereto. The first substrate structure 10 includes a first substrate 12, a plurality of sub-pixel units PU, a plurality of gate lines GL, a plurality of data lines DL, a plurality of common lines CL, a plurality of thin film transistors 14, and a plurality of pixels. The electrode 16, a first capacitance compensation electrode 171, a second capacitance compensation electrode 172, a first drain extension portion 181, and a second drain extension portion 182. In this embodiment, the sub-pixel unit PU is located on the first substrate 12, wherein each pixel unit PU includes a primary pixel P1, a primary pixel P2, a primary pixel P3, and a primary pixel P4. The sub-pixel P1 and the sub-pixel P2 are respectively located at two oblique diagonals of the sub-pixel unit PU, and the sub-pixel P3 and the sub-pixel P4 are respectively located at the other two oblique angles of the sub-pixel unit PU, as shown in FIG. Shown. The sub-pixel P1, the sub-pixel P2, the sub-pixel P3 and the sub-pixel P4 of each pixel unit PU constitute a pixel array, and the pixel array includes a plurality of sub-pixel columns and a plurality of sub-pixel rows. In the primary pixel column of the pixel array, the sub-pixel P1 and the sub-pixel P3 are alternately arranged repeatedly, and in the other pixel column, the sub-pixel P4 and the sub-pixel P2 are alternately repeated. arrangement. The gate lines GL are disposed substantially parallel to each other on the first substrate 12 and extend in a column direction, and the gate lines GL include a gate line GL1, a gate line GL2, a gate line GL3, and a gate line GL4. . The gate line GL1 is disposed between the sub-pixel P1 and the sub-pixel P3 and between the sub-pixel P2 and the sub-pixel P4 and adjacent to the sub-pixel P1 and the sub-pixel P3 for driving the sub-pixel P1; the gate line GL2 is set between the sub-pixel P1 and the sub-pixel P3 and between the sub-pixel P2 and the sub-pixel P4 and adjacent to the sub-pixel P2 and the sub-pixel P4 for driving the sub-pixel P2; the gate line GL3 is set at The secondary pixel P1 and the secondary pixel P3 are opposite to the other side of the gate line GL1 for driving the sub-pixel P3; the gate line GL4 is disposed between the sub-pixel P2 and the sub-pixel P4 with respect to the gate line GL2. The other side is used to drive the sub-pixel P4. That is to say, two gate lines GL are disposed between adjacent two pixel columns. The data lines DL are disposed substantially parallel to each other on the first substrate 12, and the data lines DL intersect the gate lines GL, that is, the data lines DL extend in a row direction. The data line DL includes a data line DL1 and a data line DL2. The data line DL1 is set on the other side of the sub-pixel P1 and the sub-pixel P4 with respect to the sub-pixel P2 and the sub-pixel P3, for driving the sub-pixel P1 and the sub-pixel P4; the data line DL2 is set in the sub-picture The prime P3 and the sub-pixel P2 are opposite to the other side of the sub-pixel P1 and the sub-pixel P4, and are used to drive the sub-pixel P3 and the sub-pixel P2. That is to say, the data line DL is disposed between the partially adjacent sub-pixel lines. The common line CL and the data line DL are substantially parallel to each other and alternately arranged, that is, the common line CL is disposed between the sub-pixel P1 and the sub-pixel P4 and between the sub-pixel P2 and the sub-pixel P3, and the data line DL1 is disposed at The outer pixels P1 and the outer pixels P4 of the sub-pixel unit PU and the data line DL2 are disposed outside the sub-pixel P2 and the sub-pixel P33 of the sub-pixel unit PU. That is to say, the common line CL is disposed between the partially adjacent sub-pixel rows and alternately arranged with the data line DL. The thin film transistors 14 are respectively located in the sub-pixel P1, the sub-pixel P2, the sub-pixel P3 and the sub-pixel P4, wherein each of the thin film transistors 14 includes a gate G, a source S and a drain D. The gates G are electrically connected to the corresponding gate lines GL, respectively. The source S is electrically connected to the corresponding data line DL. The first drain extension portion 181 is located in the sub-pixel P1 and is connected to the drain D of the thin film transistor 14 in the sub-pixel P1, and the first drain extension portion 181 partially overlaps the first capacitance compensation electrode 171. This can form a compensation capacitor; the second drain extension 182 is located in the sub-pixel P2 and is connected to the drain D of the thin film transistor 14 in the sub-pixel P2, and the second drain extension 182 and the second capacitance compensation The electrodes 172 are partially overlapped, whereby a compensation capacitance can be formed. The above compensation capacitor design avoids the variation of the gate-drain capacitance (Cgd) caused by the misalignment of the gate D and the gate G due to process variation or other factors. The pixel electrodes 16 are respectively located in the sub-pixel P1, the sub-pixel P2, the sub-pixel P3 and the sub-pixel P4, wherein each pixel electrode 16 is associated with the sub-pixel P1, the sub-pixel P2, and the sub-pixel P3, respectively. The bungee D electrical connection in the sub-pixel P4. The first capacitance compensation electrode 171 is connected to the gate line GL1 and extends along a first direction D1 to between the sub-pixel P1 and the sub-pixel P3. The second capacitance compensation electrode 172 is connected to the gate line GL2 and is opposite to The second direction D2 of the first direction D1 extends between the sub-pixel P2 and the sub-pixel P4.

In this embodiment, the gate line GL, the gate G, the common line CL, the first capacitance compensation electrode 171 and the second capacitance compensation electrode 172 may be formed of the same conductive layer, for example, the first metal layer (metal 1, M1) ), but not limited to this. The data line DL, the source S, the drain D, the first drain extension 181 and the second drain extension 182 may be formed of the same conductive layer, such as a second metal layer (metal 2, M2), but not This is limited. In addition, as shown in FIG. 2, the gate G, the first capacitor compensation electrode 171 and the second capacitor compensation electrode 172 are additionally covered with a gate insulating layer 13, and the gate insulating layer 13 is provided with a semiconductor layer 15, first The drain extension 181 and the second drain extension 182 are covered with a protective layer 19, and the protective layer 19 has an opening 19A between the first drain extension 181 and the second drain extension 182.

The second substrate structure 20 is disposed to face the first substrate structure 10. The second substrate structure 20 includes a second substrate 22 , a patterned light shielding layer 24 on the surface of the second substrate 22 facing the first substrate 12 , and a color filter layer 26 on the second substrate 22 facing the first substrate 12 . The surface, and a common electrode 28 are located on the surface of the patterned light shielding layer 24 and the color filter layer 26 facing the first substrate 12. Display medium 40 is located between first substrate structure 10 and second substrate structure 20. In this embodiment, the display medium 40 can be a liquid crystal layer, but is not limited thereto. The display medium 40 can be of various types of display media such as an organic electroluminescent layer or an electrophoretic layer or the like. The photoresist spacer 30 is located between the first substrate structure 10 and the second substrate structure 20. The photoresist spacer 30 corresponds to a common corner of the sub-pixel P1, the sub-pixel P2, the sub-pixel P3 and the sub-pixel P4, and the photoresist spacer 30 is at least coupled to the first capacitance compensation electrode 171 and the second capacitor. One of the compensation electrodes 172 partially overlaps.

In this embodiment, the photoresist spacer 30 includes a main photoresist spacer 30M, wherein the main photoresist spacer 30M is in contact with the first substrate structure 10 and the second substrate structure 20, respectively, and the main photoresist spacer 30M is at least Partially overlapping one of the first drain extension 181 and the second drain extension 182. In this embodiment, the main photoresist spacer 30M partially overlaps both the first drain extension 181 and the second drain extension 182, but is not limited thereto. For example, the main photoresist spacer 30M may also partially overlap the first drain extension 181 or only partially overlap the second drain extension 182. In addition, the main photoresist spacer 30M further overlaps the corresponding gate line GL1 and the gate line GL2 and partially overlaps the gate line GL1 and the gate line GL2, and the first capacitance compensation electrode 171 and the second capacitance compensation electrode 172. The two overlap. Furthermore, the main photoresist spacer 30M of the present embodiment has a substantially rectangular horizontal cross section, as shown in FIG. 1, but is not limited thereto. Since the main photoresist spacers 30M are in contact with the first substrate structure 10 and the second substrate structure 20, respectively, the gap between the first substrate structure 10 and the second substrate structure 20 can be maintained, and the first capacitor compensation electrode 171 and the second capacitor There is a recess between the compensation electrodes 172 such that the protective layer 19 covering the first capacitance compensation electrode 171 and the second capacitance compensation electrode 172 has an undulating surface, which can increase the friction between the main photoresist spacer 30M and the protective layer 19, thus The displacement of the main photoresist spacer 30M can be avoided.

The display panel of the present invention is not limited to the above embodiment. The display panels of other preferred embodiments of the present invention will be described in order below, and in order to facilitate the comparison of the different embodiments and simplify the description, the same symbols are used to denote the same components in the following embodiments, and mainly The differences between the embodiments will be described, and the repeated portions will not be described again.

Please refer to Figure 3. FIG. 3 is a schematic view showing a display panel of a first variation of the first preferred embodiment of the present invention. As shown in Fig. 3, in the first modification, the main photoresist spacer 30M of the display panel 1' has substantially a cross-shaped horizontal cross section.

Please refer to Figure 4. 4 is a schematic view showing a display panel of a second variation of the first preferred embodiment of the present invention. As shown in FIG. 4, in the second variation, one main photoresist spacer 30M1 of the display panel 1" partially overlaps the first drain extension portion 181, and the other main photoresist spacer 30M2 is coupled to The second drain extension portion 182 partially overlaps. In another variation of this embodiment, the main photoresist spacer 30M may include only the main photoresist spacer 30M1 partially overlapping the first drain extension portion 181, but not The main photoresist spacer 30M2 partially overlapping the second drain extension 182 is included, or only the main photoresist spacer 30M2 partially overlapping the second drain extension 182 is included, and the first drain extension is not included. The portion 181 partially overlaps the main photoresist spacer 30M1.

Please refer to Figure 5 and Figure 6. Fig. 5 is a schematic view showing a display panel according to a second preferred embodiment of the present invention, and Fig. 6 is a cross-sectional view taken along line B-B' of Fig. 5. As shown in FIG. 5 and FIG. 6, unlike the first preferred embodiment, in the present embodiment, the photoresist spacer 30 of the display panel 2 includes a secondary photoresist spacer 30S, and the secondary photoresist spacer 30S spans. The corresponding gate line GL1 and the gate line GL2 partially overlap the gate line GL1 and the gate line GL2, and the secondary photoresist spacer 30S is at least one of the first capacitance compensation electrode 171 and the second capacitance compensation electrode 172. The portions partially overlap but do not overlap the first drain extension 181 and the second drain extension 182. For example, in the embodiment, the secondary photoresist spacers 30S and the first capacitor compensation electrodes 171 and the second capacitor compensation electrodes 172 partially overlap, but are not limited thereto. The sub-resistance spacer 30S may also partially overlap the first capacitance compensation electrode 171 or partially overlap the second capacitance compensation electrode 172. Further, the sub-resistance spacer 30S is in contact with the second substrate structure 20 without being in contact with the first substrate structure 10. The sub-resistance spacer 30S corresponds to the opening 19A of the protective layer 19 between the gate line GL1 and the gate line GL2, and thus is restricted in the opening 19A of the protective layer 19 without displacement during the pressing test. Therefore, damage to the alignment film (not shown) is not caused, so that light leakage does not occur. In addition, in this embodiment, the secondary photoresist spacer 30S has a substantially rectangular horizontal cross section, as shown in FIG. 5, but is not limited thereto.

Figure 7 is a schematic view showing a display panel of a variation of the second preferred embodiment of the present invention. As shown in Fig. 7, in the present modification, the sub-resistance spacer 30S of the display panel 2' has substantially a cross-shaped horizontal cross section. Similarly, the secondary photoresist spacer 30S spans the corresponding gate line GL1 and the gate line GL2 and partially overlaps the gate line GL1 and the gate line GL2, and the secondary photoresist spacer 30S is at least coupled to the first capacitor compensation electrode 171. One of the second capacitance compensation electrodes 172 partially overlaps, but does not overlap the first drain extension 181 and the second drain extension 182. For example, in the present variation, the secondary photoresist spacers 30S and the first capacitor compensation electrodes 171 and the second capacitor compensation electrodes 172 partially overlap, but are not limited thereto. The sub-resistance spacer 30S may also partially overlap the first capacitance compensation electrode 171 or partially overlap the second capacitance compensation electrode 172.

Please refer to Figure 8. Figure 8 is a schematic view showing a display panel of a third preferred embodiment of the present invention. As shown in FIG. 8, unlike the first preferred embodiment and the second preferred embodiment, in the present embodiment, the photoresist spacer 30 of the display panel 3 includes the main photoresist spacer 30M and the secondary photoresist gap. 30S. The main photoresist spacer 30M is in contact with the first substrate structure 10 and the second substrate structure 20, respectively, and the main photoresist spacer 30M partially overlaps both the first drain extension 181 and the second drain extension 182. In addition, the main photoresist spacer 30M further overlaps the corresponding gate line GL1 and the gate line GL2 and partially overlaps the gate line GL1 and the gate line GL2, and the first capacitance compensation electrode 171 and the second capacitance compensation electrode 172. The two overlap. The secondary photoresist spacer 30S spans the corresponding gate line GL1 and the gate line GL2 and partially overlaps the gate line GL1 and the gate line GL2, and the secondary photoresist spacer 30S is at least coupled to the first capacitance compensation electrode 171 and the second One of the capacitance compensation electrodes 172 partially overlaps but does not overlap the first drain extension 181 and the second drain extension 182. For example, in the embodiment, the secondary photoresist spacers 30S and the first capacitor compensation electrodes 171 and the second capacitor compensation electrodes 172 partially overlap, but are not limited thereto. The sub-resistance spacer 30S may also partially overlap the first capacitance compensation electrode 171 or partially overlap the second capacitance compensation electrode 172. Further, the sub-resistance spacer 30S is in contact with the second substrate structure 20 without being in contact with the first substrate structure 10. The sub-resistance spacer 30S corresponds to the opening 19A of the protective layer 19 between the gate line GL1 and the gate line GL2. That is to say, in the present embodiment, the photoresist spacer 30 of the display panel 3 includes both the main photoresist spacer 30M and the sub-resist spacer 30S. Main photoresist The shape and configuration of the spacer 30M can be as disclosed in the first preferred embodiment or variations thereof, and the secondary photoresist spacer 30S. The shape and configuration of the primary photoresist spacer 30M can be as disclosed in the second preferred embodiment or variations thereof.

In summary, the main photoresist spacer of the display panel of the present invention is disposed in the compensation capacitor region, and the secondary photoresist spacer is disposed between the adjacent two capacitor compensation electrodes, thereby avoiding the photoresist spacer. Displacement occurs during the press test, and the light leakage problem can be effectively solved.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

1. . . Display panel

10. . . First substrate structure

12. . . First substrate

13. . . Gate insulation

14. . . Thin film transistor

15. . . Semiconductor layer

16. . . Pixel electrode

171. . . First capacitance compensation electrode

172. . . Second capacitance compensation electrode

181. . . First bungee extension

182. . . Second bungee extension

19. . . The protective layer

19A. . . Opening

20. . . Second substrate structure

twenty two. . . Second substrate

twenty four. . . Patterned shading layer

26. . . Color filter layer

28. . . Common electrode

30. . . Resistor spacer

30M. . . Primary photoresist spacer

30M1. . . Primary photoresist spacer

30M2. . . Primary photoresist spacer

30S. . . Secondary photoresist spacer

40. . . Display medium

PU. . . Secondary pixel unit

P1. . . Subpixel

P2. . . Subpixel

P3. . . Subpixel

P4. . . Subpixel

GL. . . Gate line

GL1. . . Gate line

GL2. . . Gate line

GL3. . . Gate line

GL4. . . Gate line

DL. . . Data line

DL1. . . Data line

DL2. . . Data line

CL. . . Common line

G. . . Gate

S. . . Source

D. . . Bungee

1'. . . Display panel

1"...display panel

2. . . Display panel

2'. . . Display panel

3. . . Display panel

FIG. 1 is a schematic view showing a display panel of a first preferred embodiment of the present invention.

Fig. 2 is a schematic cross-sectional view taken along line A-A' of Fig. 1.

FIG. 3 is a schematic view showing a display panel of a first variation of the first preferred embodiment of the present invention.

4 is a schematic view showing a display panel of a second variation of the first preferred embodiment of the present invention.

Figure 5 is a schematic view showing a display panel of a second preferred embodiment of the present invention.

Fig. 6 is a schematic cross-sectional view taken along line B-B' of Fig. 5.

Figure 7 is a schematic view showing a display panel of a variation of the second preferred embodiment of the present invention.

Figure 8 is a schematic view showing a display panel of a third preferred embodiment of the present invention.

2. . . Display panel

10. . . First substrate structure

12. . . First substrate

13. . . Gate insulation

14. . . Thin film transistor

15. . . Semiconductor layer

16. . . Pixel electrode

171. . . First capacitance compensation electrode

172. . . Second capacitance compensation electrode

181. . . First bungee extension

182. . . Second bungee extension

19. . . The protective layer

19A. . . Opening

20. . . Second substrate structure

twenty two. . . Second substrate

twenty four. . . Patterned shading layer

26. . . Color filter layer

28. . . Common electrode

30. . . Resistor spacer

30S. . . Secondary photoresist spacer

40. . . Display medium

G. . . Gate

S. . . Source

D. . . Bungee

Claims (13)

A display panel includes: a first substrate structure, comprising: a first substrate; a plurality of sub-pixel units located on the first substrate, wherein each of the sub-pixel units comprises a first pixel, a first a second pixel, a third pixel, and a fourth pixel, the first pixel and the second pixel are respectively located at two oblique diagonals of the pixel unit, and the third time The pixel and the fourth pixel are respectively located at two diagonal opposite corners of the pixel unit; a plurality of gate lines are disposed on the first substrate in parallel with each other, and the gate lines include: a first gate a polar line, disposed between the first pixel and the third pixel and between the second pixel and the fourth pixel and adjacent to the first pixel and the third pixel, For driving the first pixel; a second gate line is disposed between the first pixel and the third pixel and between the second pixel and the fourth pixel The second pixel and the fourth pixel are used to drive the second pixel; a third gate line is set in the first pixel and the third pixel On the other side of the first gate line for driving the third sub-pixel; and a fourth gate line is disposed on the other side of the second pixel and the fourth pixel relative to the second gate line for driving the fourth pixel; a plurality of data lines, Parallel to each other on the first substrate, and the data lines intersect the gate lines, the data lines include: a first data line disposed on the first pixel and the fourth pixel Relative to the second pixel and the other side of the third pixel, for driving the first pixel and the fourth pixel; and a second data line, set in the third time The pixel and the second pixel are opposite to the first pixel and the other side of the fourth pixel, and are used to drive the third pixel and the second pixel; a first capacitor a compensation electrode connected to the first gate line and extending in a first direction between the first pixel and the third pixel; a second capacitance compensation electrode connected to the second gate line And extending in a second direction opposite to the first direction to between the second pixel and the fourth pixel; a first drain extension located in the first painting And partially overlapping the first capacitance compensation electrode; a second drain extension portion located in the second pixel and partially overlapping the second capacitance compensation electrode; a second substrate structure, and the first substrate a plurality of photoresist spacers are disposed between the first substrate structure and the second substrate structure, wherein each of the photoresist spacers is at least coupled to the first capacitor compensation electrode One of the second capacitance compensation electrodes partially overlaps, the photoresist spacers include a plurality of main photoresist spacers, and each of the main photoresist spacers is in contact with the first substrate structure and the second substrate structure, respectively, and At least a portion of the main photoresist spacers at least partially overlap one of the first drain extension and the second drain extension; and a display medium on the first substrate structure and the second substrate Between the structures. The display panel of claim 1, wherein each of the photoresist spacers corresponds to the first pixel, the second pixel, the third pixel, and the fourth pixel. corner. The display panel of claim 1, further comprising a plurality of thin film transistors, respectively located in the first pixel, the second pixel, the third pixel, and the fourth pixel, wherein Each of the thin film transistors includes a gate, a source and a drain, the first drain extension being connected to the drain of the thin film transistor in the first pixel, and the second turn The pole extension is connected to the drain of the thin film transistor in the second pixel. The display panel of claim 3, further comprising a plurality of pixel electrodes, respectively located in the first pixel, the second pixel, the third pixel, and the fourth pixel, wherein Each of the pixel electrodes is electrically connected to the first pixel, the second pixel, the third pixel, and the gate in the fourth pixel. The display panel of claim 1, wherein each of the photoresist spacers further spans the first gate line and the second gate line and the first gate line and the second gate line portion overlapping. The display panel of claim 1, wherein each of the main photoresist spacers partially overlaps the first drain extension and the second drain extension. The display panel of claim 1, wherein each of the main photoresist spacers at least partially overlaps one of the first drain extension and the second drain extension. The display panel of claim 1, wherein a portion of the main photoresist spacers partially overlap the first drain extension portion, and a portion of the main photoresist spacers and the second drain extension Partial overlap. The display panel of claim 1, wherein the photoresist spacers comprise a plurality of sub-resistance spacers, and the second photoresist spacers are not associated with the first drain extension and the second drain extension The first photoresist spacers are in contact with the second substrate structure and are not in contact with the first substrate structure. The display panel of claim 1, wherein the photoresist spacers comprise a plurality of secondary photoresist spacers, each of the photoresist spacers not extending with the first drain extension and the second drain extension The first photoresist spacers are in contact with the second substrate structure and are not in contact with the first substrate structure. The display panel of claim 10, wherein each of the main photoresist spacers partially overlaps the first drain extension and the second drain extension. The display panel of claim 10, wherein a portion of the main photoresist spacers partially overlap the first drain extension portion, and a portion of the main photoresist spacers and the second drain extension Partial overlap. The display panel of claim 1, wherein each of the photoresist spacers has a rectangular horizontal section or a cross-shaped horizontal section.