TWI445138B - Nonvolatile semiconductor memory - Google Patents

Description

Non-volatile semiconductor memory

This invention relates to a non-volatile semiconductor memory and, more particularly, to a NAND flash memory having a partial SOI structure.

The present application is based on and claims the benefit of priority to the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit.

Non-volatile semiconductor memories such as NAND flash memory have been used as storage units for various electronic devices.

As memory capacity and integration have grown in recent years, memory cells have been further microfabricated.

A technique for forming a memory cell in a region of a silicon oxide (SOI) region provided on a surface of a semiconductor substrate has been proposed as a microfabrication method (for example, Japanese Patent Application KOKAI Publication No. 2006-73939).

The reason why this technique is used for microfabrication is that the formation of memory cells in the SOI region makes it possible to suppress the short channel effect caused by microfabrication.

It is necessary to use a highly crystalline epitaxial layer as the SOI layer formed in the SOI region. To this end, the epitaxial layer is formed into a crystal by epitaxially growing an amorphous film covering the entire surface of the substrate in a lateral direction by using a top surface of the exposed semiconductor substrate not covered by the buried oxide film. The shaft is aligned with the crystal axis of the semiconductor substrate.

However, the epitaxial layer on the aforementioned buried oxide film inevitably contains many grain boundaries. Since the grain boundaries are randomly formed in the epitaxial layer, the memory cell characteristics vary between the memory cells having crystal grain boundaries in the channel region and the memory cells having no crystal grain boundaries.

This change becomes more important as more micro memory cells are made, which reduces the reliability of the flash memory.

According to an aspect of the present invention, a nonvolatile semiconductor memory is provided, comprising: a semiconductor substrate having an SOI region and an epitaxial region at a surface thereof; and an embedded type disposed on the SOI region An oxide film; an SOI layer disposed on the buried oxide film layer; a plurality of memory cells disposed on the SOI layer; an epitaxial layer disposed in the epitaxial region; and an epitaxial layer disposed in the epitaxial layer The gate transistor is selected, wherein the SOI layer is made of a microcrystalline layer.

According to another aspect of the present invention, a nonvolatile semiconductor memory is provided, comprising: a semiconductor substrate; a columnar semiconductor layer extending in a vertical direction toward a surface of the semiconductor substrate; a plurality of memory cells, They are disposed on the side of the semiconductor layer in the vertical direction and each of them has a charge accumulation layer and a control gate electrode, wherein the columnar semiconductor layer is made of a microcrystalline layer.

Hereinafter, embodiments of the present invention will be explained in detail with reference to the accompanying drawings.

Generalize

A non-volatile semiconductor memory in accordance with an embodiment of the present invention has a partial SOI structure. Specifically, the memory cell is disposed in the SOI region at the surface of the semiconductor substrate, and the selection gate transistor is disposed in the epitaxial region at the surface of the semiconductor substrate. The peripheral transistor is disposed at the surface of the semiconductor substrate (in the semiconductor substrate region).

In the SOI region of this embodiment, the SOI layer in which the memory cells are arranged is characterized by a microcrystalline germanium layer.

The use of the microcrystalline germanium layer as a channel for the memory cell causes the channel of each memory cell to have a structure having crystal grain boundaries in the microcrystalline germanium.

Therefore, according to this embodiment, it is possible to suppress variations in memory cell characteristics caused by the presence or absence of crystal grain boundaries in the channel region. In addition to this effect, a memory cell having a homogeneous characteristic can be provided.

In this embodiment, if the channel length of the memory cell is L and the channel width is W, the microcrystalline germanium is defined as the smaller of the crystal grain size smaller than L/2 and smaller than W/2.

2. Examples

(1) First embodiment

(a) Configuration

1 shows an example of a layout of a flash memory in accordance with a first embodiment of the present invention.

The flash memory causes the memory cell array section 100 and the column decoder circuit 110, the sense amplifier circuit 120, the control circuit 130, and other circuits disposed around the memory cell array section to be disposed on the same wafer. Hereinafter, an area in which the column decoder circuit 110, the sense amplifier circuit 120, and the control circuit 130 are provided is referred to as a peripheral circuit section.

The configuration of the memory cell array section and the peripheral circuit section will be explained by using Figs. 2 to 7. Figure 2 is a plan view of a portion of a memory cell array section. Figure 3 is a cross-sectional view taken along line III-III of Figure 2. Figure 4 is a cross-sectional view taken along line IV-IV of Figure 2 . Figure 5 is a plan view of a portion of a peripheral circuit section. Figure 6 is a cross-sectional view taken along line VI-VI of Figure 5. Figure 7 is a cross-sectional view taken along line VII-VII of Figure 5. In the first embodiment, the direction in which the line III-III and the line VI-VI extend is corresponding to the channel length direction of the MIS transistor, and the direction in which the line IV-IV and the line VII-VII extend corresponds to the MIS transistor. Channel width direction.

As shown in FIG. 2, the surface region of the memory cell array section is composed of, for example, an isolation insulating region STI having a shallow trench isolation (STI) structure and an active region AA sandwiched between the isolation insulating regions.

As shown in FIG. 3, the active area AA of the memory cell array section is composed of an SOI area SA and an epitaxial area EA (ie, two areas). The SOI region SA is composed of a buried oxide film 2 provided on the semiconductor substrate 1 and an n-type microcrystalline germanium layer 3 provided on the buried oxide film 2 and constituting the SOI layer. The n-type microcrystalline germanium layer 3 is an n ^- type semiconductor layer doped with a low concentration (for example, about 1 × 10 ¹⁸ atoms/cm ³ ) of an n-type impurity such as phosphorus (P) or arsenic (As). . The film thickness of the n-type microcrystalline germanium layer 3 is, for example, about 30 nm to 40 nm.

A plurality of memory cells MC1 to MCn are disposed on the n-type microcrystalline germanium layer 3. Each of the memory cells MC1 to MCn has a stacked gate structure composed of a floating gate electrode 7A and a control gate electrode 9A. The floating gate 7A is formed on a gate insulating film (tunnel oxide film) 6A formed at the surface of the n-type microcrystalline germanium layer 3. The floating gate electrodes 7A adjacent to each other in the channel width direction are isolated from each other by the element isolation insulating layer 16 formed in the element isolation region STI. The element isolation insulating layer 16 is formed in contact with the buried oxide film 2. As shown in FIG. 4, the control gate electrode 9A is formed to cover the top of the floating gate electrode 7A and the side surface in the channel width direction via the inter-gate insulating film 8A. The control gate electrode 9A serves as a word line. Further, the n ⁺ diffusion layer 10 formed in the n ^- -type microcrystalline germanium layer 3 serving as the SOI layer is shared as a source/drain region by two adjacent memory cells to connect the two memory cells in series.

In the first embodiment, each of the memory cells MC1 to MCn is composed of an SOI structure depletion mode transistor using the n-type microcrystalline germanium layer 3 as a channel region and using the n ⁺ diffusion layer 10 as Source/drainage area. Therefore, in the case where charges (electrons) are accumulated in the floating gate electrode 7A, the channel region is depleted, which makes it possible to alleviate the influence of the short channel effect.

The gate crystals SGD and SGS are selected to be disposed at one end (the drain side) and the other end (the source side) of the memory cells MC1 to MCn. The gate transistors SGD and SGS are selected to be disposed in the epitaxial region EA and the p ^- type semiconductor layer 5 having the crystal axis aligned with the crystal axis of the semiconductor substrate 1 is used as the channel region.

Since the gate electrodes of the gate transistors SGS and SGD are selected while forming the gate electrode of the memory cell, they have a stacked gate structure. Therefore, the gate electrode is structured such that the gate electrode 7B formed on the gate insulating film 6B at the surface of the p ^- -type semiconductor layer 5 is connected to the gate electrode 9B via the opening generated in the inter-gate insulating film 8B. .

The gate transistors SGD and SGS are selectively electrically connected to the memory cells MC1, MCn via the n ⁺ diffusion layer 10 formed in the microcrystalline germanium layer 3.

Further, the selection gate transistors SGD and SGS are electrically connected to the bit line contact BC and the source line contact SC, respectively, via the n ⁺ diffusion layer 10A formed in the epitaxial region EA. The n ⁺ diffusion layer 10A is formed in the epitaxial layer.

As described above, each of the gate transistors SGD, SGS is selected as an enhancement mode metal-insulator semiconductor (MIS) transistor in which a p ^- type semiconductor layer 5 (epitaxial layer) is used as a channel region and n ⁺ The diffusion layers 10, 10A function as a source-drain region. The channel lengths of the gate transistors SGD and SGS are selected to be larger than the channel lengths of the memory cells MC1 to MCn. This makes it possible to easily control the cutoff characteristics of the selected gate transistors SGD, SGS and to improve the cutoff characteristics.

In a first embodiment, the memory cell array section has a configuration of NAND flash memory in which a plurality of memory cells are connected in series with a select gate transistor to form their common source/drain diffusion layer.

Hereinafter, the structure of the peripheral transistor of the first embodiment will be explained by using Figs. 5 to 7. In FIGS. 5 to 7, only the n-channel MIS transistor Tr1 and the p-channel MIS transistor Tr2 are shown for the sake of convenience of explanation.

The peripheral transistors Tr1, Tr2 are disposed on the semiconductor substrate 1 and are formed while forming the memory cells MC1 to MCn and the selection gate transistors SGD, SGS. Therefore, it has a stacked gate structure. In this configuration, the gate electrode 7C on the gate insulating film 6C at the surface of the semiconductor substrate 1 is connected to the gate electrode 9C via an opening generated in the inter-gate insulating film 8C.

The gate electrodes 7C and 9C of the peripheral transistors Tr1 and Tr2 are connected to the gate wiring layer GL via the gate contact GC. The peripheral transistors Tr1 and Tr2 use the n ⁺ diffusion layer 10 and the p ⁺ diffusion layer 11 formed in the semiconductor substrate 1 as source/drain regions, respectively. Next, the metal wiring layers L1 and L2 are connected to the n ⁺ diffusion layer 10 and the p ⁺ diffusion layer 11 via the contacts C1 and C2, respectively.

Peripheral transistors Tr1, Tr2 are formed on the semiconductor substrate 1 to serve as a highly resistant piezoelectric crystal. In addition, it is also formed to function as an enhancement mode MIS transistor to facilitate threshold voltage control. The peripheral transistors Tr1, Tr2 may be disposed on the epitaxial layer formed on the semiconductor substrate 1 as the selection gate transistors SGD, SGS.

As described above, the NAND flash memory of the first embodiment has a partial SOI structure in which a memory cell array section is formed in an SOI region on the semiconductor substrate 1 and a peripheral circuit section is formed on the semiconductor substrate 1.

Each of the memory cells MC1 to MCn uses the n-type microcrystalline germanium layer 3 as a channel region. If the channel length of the memory cell is L and the channel width of the memory cell is W, the particle size r of the microcrystalline germanium constituting the n-type microcrystalline germanium layer 3 is designed to be smaller than the smaller of L/2 and W/2. .

To this end, each of the memory cells MC1 to MCn has a grain boundary in the microcrystalline crucible. Therefore, depending on the presence or absence of grain boundaries in each memory cell, the characteristics of the memory cells do not change.

Therefore, according to the first embodiment, the SOI layer made of microcrystalline germanium enables the crystal grain boundaries to be in the middle of the channel region of all the memory cells and enables the characteristics of the memory cells to be equalized.

(b) Manufacturing method

A method of manufacturing the flash memory in the first embodiment will be explained by using Figs. 8 to 17 . 8, 10, 12, 14, and 16 show the fabrication process of the cross section in the channel length direction of the memory cell array section. 9, 11, 13, 15, and 17 show the manufacturing process of the cross section in the channel length direction of the peripheral circuit section.

First, as shown in FIGS. 8 and 9, a well region is formed in the semiconductor substrate 1, and a buried oxide film 2 is formed at the surface of the semiconductor substrate 1 by a chemical vapor deposition (CVD) method (for example, Cerium oxide film). Thereafter, in the memory cell array section of FIG. 8, the ruthenium oxide film 2 is patterned to leave a ruthenium oxide film in a region where a memory cell will be formed in a subsequent process, and then, for example, by reactivity An ion etching (RIE) method is used for etching. Next, in the memory cell array section, the buried oxide film 2 is formed on the semiconductor substrate 1 in the portion which will be the SOI region in the subsequent process. The semiconductor substrate 1 is exposed in a portion which will be an epitaxial region in a subsequent process.

As shown in FIG. 9, in the peripheral circuit section, the surface of the semiconductor substrate 1 is covered by the buried oxide film 2. When the peripheral transistor is formed on the epitaxial layer, the buried oxide film 2 of the peripheral circuit section is removed.

Next, an amorphous germanium film 3A containing a low concentration (for example, about 1 × 10 ¹⁸ atoms/cm ³ ) of n-type impurities (such as phosphorus) is formed on the entire surface of the memory cell array section and the peripheral circuit section. (P) or arsenic (As)).

Next, the entire surface of the semiconductor substrate 1 is heat-treated at a substrate temperature of 600 ° C or higher by, for example, a rapid thermal annealing (RTA) method with a sharp temperature rise, thereby making the amorphous germanium film 3A short. Time to grow in the crystal. Thereafter, the surface is planarized, for example, by, for example, a chemical mechanical polishing (CMP) method.

Next, as shown in FIG. 10, the amorphous germanium deposited in contact with the surface of the semiconductor substrate 1 is epitaxially grown by the RTA method, thereby producing an epitaxial germanium in which the crystal axis is aligned with the crystal axis of the semiconductor substrate 1. Layer 4. On the other hand, the amorphous germanium deposited in contact with the surface of the buried oxide film 2 produces a microcrystalline germanium layer 3 having grain boundaries.

The reason why the above structure is obtained is that the amorphous germanium film is epitaxially grown in the epitaxial region EA on the semiconductor substrate 1, and the amorphous germanium film grows without epitaxial growth in the SOI region SA because it is embedded with The oxide film 2 (amorphous film) is in contact, and the amorphous germanium film is crystallized due to a sharp temperature change caused by the RTA method.

In the first embodiment, since the crystal of the amorphous germanium is performed by a short duration heat treatment using RTA, the crystal growth in the lateral direction (or in the direction parallel to the substrate surface) is in the longitudinal direction (or Crystal growth in a direction perpendicular to the surface of the substrate ends in a much shorter period of time. For this reason, the epitaxial layer 4 grown in the crystal form in the epitaxial region EA does not grow in the lateral direction so as to cover the entire surface of the buried oxide film 2. The substrate heating time by RTA is the time required for the amorphous germanium film in the epitaxial region EA to epitaxially grow until its top surface.

Therefore, in the memory cell array section, the microcrystalline germanium layer 3 and the epitaxial layer 4 can be separated into the SOI region and the epitaxial region in FIG. In the peripheral circuit section, when the buried oxide film 2 is not removed (as shown in FIG. 11), as in the memory cell array section, crystallites are formed on the buried oxide film 2.矽 layer 3.

Next, as shown in FIGS. 12 and 13, after the resist is applied to the semiconductor substrate, patterning is formed on the microcrystalline germanium layer 3 in the memory cell array section to expose the epitaxial region EA to serve as a selection gate. The resist pattern 14 of the polar crystal formation region. Next, in the case where the resist pattern 14 is used as a mask, the epitaxial layer in the epitaxial region EA is doped with a p-type impurity having a low concentration (for example, about 1 × 10 ¹⁸ atoms/cm ³ ). (such as boron (B)), whereby the p ^- -type semiconductor layer 5 is formed.

Thereafter, the resist pattern 14 is removed and the buried oxide film and the microcrystalline layer in the peripheral circuit section are peeled off, thereby exposing the surface of the semiconductor substrate 1, as shown in FIG. Next, as shown in FIGS. 14 and 15, for example, by a thermal oxidation method in the memory cell array of a microcrystalline silicon layer segment 3 and p ^- -type semiconductor layer 5 and the semiconductor substrate of the peripheral circuit section, A ruthenium oxide film 6 serving as a gate insulating film is formed on 1.

Next, for example, a polysilicon film 7 in which the floating gate electrode of the memory cell and the gate electrode of the peripheral transistor are continuous is formed on the gate insulating film 6 by a CVD method. Thereafter, in the memory cell array section, in order to separate the floating gate electrodes adjacent in the channel width direction, an isolation insulating layer (not shown) is formed in contact with, for example, the buried oxide film 2, This separates the active region and the isolated insulating region at the surface of the semiconductor substrate 1. At this time, an isolation insulating layer (not shown) is similarly formed in the semiconductor substrate 1 in the peripheral circuit section.

Further, on the polysilicon film 7 of, for example, the memory cell array section and the peripheral circuit section, an ONO film 8 serving as an inter-gate insulating film is formed. The inter-gate insulating film is not limited to the ONO film and may be a single-layer film of a hafnium oxide film, a tantalum nitride film, or a hafnium oxynitride film. Alternatively, the inter-gate insulating film may be a single layer film or a laminate film containing at least one of the following high dielectric materials: aluminum oxide, cerium oxide, cerium oxide, cerium oxide, and the like.

Next, an opening X reaching the polysilicon film 7 is generated in the ONO film 8 in the selection gate transistor formation region and the peripheral transistor formation region. Next, for example, a polysilicon film 9 is formed on the ONO film 8 by a CVD method, which will generate a gate electrode of the memory cell and a gate electrode of the peripheral transistor. A high melting point metal film such as tungsten (W), titanium (Ti) or molybdenum (Mo) may be further formed on the polysilicon film 9, which is deuterated by heat treatment and then formed as a gate electrode to have a polysilicon A two-layer structure of a film and a vaporized film or a single layer structure of a vaporized film. In this case, the control gate electrode can be made to have a low resistance.

Thereafter, as shown in FIG. 16 and FIG. 17, after the memory cell array section and the peripheral circuit section are patterned to obtain a transistor having a specific channel length, the polysilicon film, the ONO film, and the polysilicon film are sequentially etched by the RIE method. And a ruthenium oxide film, thereby treating the gate. As a result, the gate electrodes of the memory cells MC1 to MCn, the gate crystals SGD, SGS, and the peripheral transistors Tr1, Tr2 are formed.

Thereafter, in the case where the gate electrode is used as a mask, the n ⁺ diffusion layers 10, 10A, and p ⁺ constituting the source/drain regions are respectively formed in a self-aligned manner by, for example, an ion implantation method ^. Diffusion layer 11.

Further, as shown in FIGS. 3 and 6, the insulating layer 12 is formed on the entire surface of the memory cell array section and the peripheral circuit section. Thereafter, the bit line contact BC and the source line contact SC are electrically connected to the drain of the select gate transistor SGD and the source of the select gate transistor SGS via an opening generated in the insulating layer 12. Further, the metal wiring layer M1 is electrically connected to the bit line contact BC. The source line SL is electrically connected to the source line contact SC. At this time, in the peripheral circuit section, the metal wiring layers L1, L2 are electrically connected to the diffusion layers serving as the source/drain regions of the peripheral transistors Tr1, Tr2 via the contact portions C1, C2 formed in the insulating layer 12. 10, 11. Further, gate interconnections and gate contacts (not shown) are formed at the gate electrodes 7C, 9C of the peripheral transistors Tr1, Tr2 in the same process.

Next, after the insulating layer 13 is formed on the entire surface of the memory cell array section and the peripheral circuit section, the bit line BL is electrically connected to the metal wiring layer M1 via the via V1 formed in the insulating layer 13.

Through the above process, the flash memory of the first embodiment is completed.

The foregoing manufacturing method makes it possible to manufacture a NAND flash memory in which the SOI layer in which the memory cells MC1 to MCn are disposed is composed of the microcrystalline layer 3.

Therefore, crystal grain boundaries may be included in the channel region of each of the memory cells MC1 to MCn, which prevents the characteristics of the memory cell from changing depending on the presence or absence of crystal grain boundaries in the channel region.

Therefore, the generation of the channel region of the memory cell outside the microcrystalline layer by the above manufacturing method makes it possible to provide a memory cell having a homogeneous characteristic.

(c) Supplementary examples

A supplementary explanation of the first embodiment will be explained by using Figs. 18 and 19.

In the above manufacturing method, the amorphous germanium is epitaxially grown by RTA, which makes it possible to separately form the microcrystalline germanium layer 3 and the epitaxial layer 4 as shown in FIG.

Although the above method can suppress the lateral crystal growth of the epitaxial layer 4, it cannot completely suppress the lateral crystal growth by causing the epitaxial layer to grow only in the longitudinal direction.

Therefore, as shown in FIG. 18, the epitaxial layer 4 does not cover the entire surface of the buried oxide film 2. However, it is expected that the end of the epitaxial layer 4 will be formed at the end of the buried oxide film 2 due to a small amount of lateral crystal growth.

In this case, a grain boundary GB exists at the interface between the epitaxial layer 4 and the n-type microcrystalline germanium layer 3.

If the crystal grain boundary GB is not formed in the channel region of the memory cell, it will not cause a change in the characteristics of the memory cell depending on the presence or absence of crystal grain boundaries.

Therefore, as shown in FIG. 19, when the grain boundary GB exists in the SOI region between the adjacent memory cell and the selection gate transistor (for example, it exists in the n ⁺ diffusion layer shared by the selected gate transistor and the memory cell) In 10B), there is no problem with the homogeneity of the memory cells.

(2) Second embodiment

(a) Configuration

20 and 21 show the configuration of a flash memory in accordance with a second embodiment of the present invention. The same portions as those of the first embodiment are denoted by the same reference numerals and detailed explanation will be omitted.

In the second embodiment, the microcrystalline germanium layer constituting the SOI layer is characterized by a p-type microcrystalline germanium layer 15 doped with, for example, boron (B). The p-type microcrystalline germanium layer 15 is a p ^- type semiconductor layer doped with a low concentration (for example, about 1 × 10 ¹⁸ atoms/cm ³ ) of impurities.

Therefore, in the second embodiment, each of the memory cells MC1 to MCn is a p-channel depletion mode transistor which uses the p-type microcrystalline germanium layer 15 as a channel region and uses the p ⁺ diffusion layer 19 as a source/ Bungee area.

On the other hand, the selection gate transistors SGD and SGS disposed at the two ends of the memory cells MC1 to MCn are disposed on the epitaxial region EA in which the crystal axis is aligned with the crystal axis of the semiconductor substrate 1.

The gate transistors SGS and SGD are selected to use the n ^- type semiconductor layer 18 in which the crystal axis is aligned with the crystal axis of the semiconductor substrate 1 as the channel region, and the p ⁺ diffusion layers 19 and 19A are used as the source/drain regions. The p ⁺ diffusion layer 19 is formed in the p-type microcrystalline layer 15 and the p ⁺ diffusion layer 19A is formed in the epitaxial layer 17.

The gate transistors SGS and SGD are respectively connected to the memory cells MC1, MCn and the bit line contact BC and the source line contact SC via corresponding source/drain regions.

As described in the first embodiment, phosphorus (P), arsenic (As) or the like is used as the n-type impurity in the n-type microcrystalline germanium layer. Phosphorus (P) or arsenic (As) tends to be easily segregated at grain boundaries between crystallites.

For this reason, even if the change in the characteristics of the memory cell caused by the presence or absence of crystal grain boundaries has been suppressed by using the microcrystalline layer, the segregation of the impurities contributes to the change of the characteristics.

On the other hand, for example, boron (B) used as a p-type impurity in the second embodiment is more easily diffused than phosphorus (P) or arsenic (As). Therefore, p-type impurities are less likely to segregate at grain boundaries.

Therefore, according to the second embodiment, the use of the p-type microcrystalline layer as the SOI layer enables the characteristics of the memory cell to be more equalized.

(b) Manufacturing method

Hereinafter, a manufacturing method according to the second embodiment will be described. Explanation of the manufacturing method of the peripheral circuit section will be omitted.

As shown in FIG. 22, after the buried oxide film 2 is formed in the same process as that shown in FIG. 8 of the first embodiment, the formation is doped with a low concentration (for example, about 1 × 10 ¹⁸ atoms/cm ^{3 ).} An amorphous germanium film of, for example, boron (B) (as a p-type impurity) so as to cover the entire surface of the semiconductor substrate 1 and the buried oxide film 2.

Thereafter, the semiconductor substrate 1 is heated by RTA under the same conditions as those shown in Fig. 10 of the first embodiment. Next, the p-type amorphous germanium formed on the buried oxide film 2 is changed into the p-type microcrystalline germanium layer 15.

On the other hand, the p-type amorphous germanium formed on the semiconductor substrate 1 is epitaxially grown, whereby the p-type epitaxial layer 17 in which the crystal axis is aligned with the crystal axis of the semiconductor substrate 1 is formed.

Next, as shown in FIG. 23, channels for generating the selection gate transistors SGD, SGS are formed in the epitaxial layer 17 by, for example, an ion implantation method in the same process as that shown in FIGS. 12 to 16. The n ^- type semiconductor layer 18 of the region.

Then, after forming the gate electrodes of the memory cells MC1 to MCn and the gate transistors SGS and SGD, the source/drain electrodes serving as the memory cells and the gate transistors are formed by, for example, ion implantation. The p ⁺ diffusion layers 19, 19A of the region.

Thereafter, as shown in FIG. 20, the insulating layers 12, 13, the bit line BL, the bit line contact BC, the source line SL, the source line contact SC, and other portions are sequentially formed, which is completed in the second embodiment. Flash memory.

As described above, in the second embodiment, the SOI layer in which the memory cells MC1 to MCn are disposed is composed of a p-type microcrystalline polysilicon layer. This makes it possible to suppress variations in characteristics of the memory cells MC1 to MCn caused by crystal grain boundaries and further caused by segregation of impurities.

Therefore, according to the above manufacturing method, it is possible to suppress variations in memory cell characteristics and provide memory cells having homogeneous characteristics.

(3) Third embodiment

(a) Configuration

The third embodiment of the present invention is applicable to a flash memory in which memory cells are stacked almost vertically on the surface of the substrate. Fig. 24 is a perspective view schematically showing a main part of a NAND cell unit serving as a basic unit in the third embodiment. As shown in FIG. 24, a plurality of memory cells MC1 to MCn are disposed on the side of the columnar semiconductor layer 20 extending in a direction perpendicular to the surface of the semiconductor substrate 1. The semiconductor layer 20 is a channel region of a memory cell. The gate transistors SGS and SGD are respectively disposed on the semiconductor substrate 1 and on the side faces of the columnar semiconductor layer 20.

The use of the microcrystalline germanium layer as the channel region of the memory cells MC1 to MCn shown in Fig. 24 makes it possible to suppress variations in memory cell characteristics caused by grain boundaries as in the first embodiment and the second embodiment.

Hereinafter, the stacked structure flash memory of the third embodiment shown in Fig. 24 will be explained using Figs. 25 to 27 . In FIGS. 24 and 25 to 27, the same components are denoted by the same reference numerals. The vertical memory cell and the vertical transistor described below are MIS transistors in which the channel is formed in a direction perpendicular to the surface of the semiconductor substrate.

Figure 25 is a plan view of a NAND flash memory according to a third embodiment. Figure 26 is a cross-sectional view taken along line XXVI-XXVI of Figure 25. Figure 27 is a cross-sectional view taken along line XXVII-XXVII of Figure 25. Figure 26 shows two NAND cell units contiguous in the X direction. Figure 28 shows the structure of a peripheral transistor disposed in a peripheral circuit region. Figure 28 is a cross-sectional view taken along the length of the channel of the peripheral transistor.

In the memory cell array section, a plurality of NAND cell units are disposed in an active area AA sandwiched between the isolation regions STI disposed in the semiconductor substrate 1.

In the third embodiment, the memory cells MC1 to MCn are arranged such that they generate vertical memory cells on the side of one of the columnar n-type microcrystalline germanium layers 20 extending almost in the direction perpendicular to the surface of the semiconductor substrate 1. That is, the columnar n-type microcrystalline germanium layer 20 is a region in which the memory cells MC1 to MCn are formed. The gate electrode of the memory cells MC1 to MCn is not in contact with the insulating film 70 by the side surface formed by the n-type microcrystalline germanium layer 20, and thus the memory cell forming region has an SOI structure.

The memory cells MC1 to MCn are stacked on top of each other via the interlayer insulating layer 42, thereby forming a stacked body. The n-type microcrystalline germanium layer 20 is an n ^- type semiconductor layer doped with a low concentration (for example, about 1 × 10 ¹⁸ atoms/cm ³ ) of an n-type impurity such as phosphorus (P) or arsenic (As). . The memory cells MC1 to MCn are such that the control gates CG1 to CGn are connected to the side of the n-type microcrystalline germanium layer 20 via the gate insulating film 23. The control gate electrodes CG1 to CGn serve as word lines extending in the Y direction and are shared by memory cells adjacent in the Y direction.

In order to make the resistance lower, each of the control gate electrodes CG1 to CGn has a two-layer structure composed of, for example, a polysilicon layer and a germanide layer obtained by partially converting a polysilicon layer into a germanide. . Each of the control gate electrodes CG1 to CGn may have a single layer structure of a polysilicon layer or a germanide layer. Further, each of the control gate electrodes CG1 to CGn may have a single layer structure of a metal such as tungsten (W), aluminum (Al) or copper (Cu), which causes the control gate electrode to have a low resistance. When a metal is used as the control gate electrodes CG1 to CGn, a vaporization layer is not required.

Each of the memory cells MC1 to MCn has a MONOS structure. Therefore, the gate insulating film 23 interposed between the control gate electrodes CG1 to CGn and the n-type microcrystalline germanium layer 20 has a stacked structure in which the charge storage layer 23B is sandwiched between the first insulating film 23A and the second insulating film 23C. between.

When the charge injected from the n-type microcrystalline germanium layer 20 is accumulated in the charge storage layer 23B, or when the charge accumulated in the charge storage layer 23B is diffused into the n-type microcrystalline germanium layer 20, the second insulating film 23C Acts as a potential barrier. For example, a hafnium oxide film is used as the second insulating film 23C and has a film thickness of, for example, about 10 nm.

The charge storage layer 23B traps and accumulates charges (electrons) and acts as a data storage layer for the flash memory. For example, a tantalum nitride film is used as the charge storage film 23B and has a film thickness of, for example, about 8 nm.

The first insulating film 23A is disposed between the charge storage layer 23B and the control gate electrodes CG1 to CGn and prevents charges accumulated in the charge storage layer 23B from being diffused into the control gate electrodes CG1 to CGn. For example, a hafnium oxide film is used as the first insulating film 23A and has a film thickness of, for example, about 4 nm.

As more and more micro-fabricated memory cells in the flash memory, appropriate write/read operations can be performed without a diffusion layer acting as a source/drain region.

Therefore, in the n ^- -type semiconductor layer 20, each of the memory cells MC1 to MCn does not have a diffusion layer serving as a source/drain region, and its conductivity type is different from that of the semiconductor layer. That is, the microcrystalline germanium layer 20 (n ^- type semiconductor layer) serves as a channel region, a source region, and a drain region of the memory cell. The memory cells MC1 to MCn are almost depleted of the n-type microcrystalline germanium layer 20 just under the gate electrode based on the potential applied to the control gate electrodes CG1 to CGn, thereby achieving a closed state.

As described above, the memory cell of the third embodiment is a vertical memory cell. Therefore, the film thickness of the gate electrodes CG1 to CGn is the gate length (channel length). Let the gate length be L. Further, the film thickness of the n-type microcrystalline germanium layer 20 serving as the channel region of the memory cell MC is T.

At this time, it is necessary to make the gate length L and the film thickness T satisfy the following expression: 1 nm < T < L × 0.8.

The reason is to read the data appropriately and easily.

Specifically, in the reading operation, the inversion layer in the range of about 1 nm is formed by the interface with the gate insulating film 8 in the channel region just under the gate electrodes CG1 to CGn. Therefore, when the film thickness T becomes less than 1 nm, the carrier surface density in the inversion layer sharply drops and the bit line current decreases. As a result, it becomes difficult to read the data. On the other hand, in order to properly perform the read operation, it is necessary to make the cutoff characteristics of the memory cells good. For this reason, it is necessary to make the upper limit of the film thickness T satisfy the above expression.

Since the entire gate insulating film 23 (including the charge storage layer 23B) is an insulating material in the memory cells MC1 to MCn, the floating gate electrode as the storage layer does not need to be separated one by one as in the floating gate memory cell. That is, the gate insulating film 23 only has to be formed on the entire side surface of the n-type microcrystalline germanium layer 20, thereby eliminating the need for patterning, which makes it easy to realize a structure in which vertical memory cells are vertically stacked.

Further, the distance between the gate electrodes CG (that is, the film thickness of the interlayer insulating layer 42) is set to be equal to, for example, the thickness of the film thicknesses of the gate electrodes CG1 to CGn.

The gate transistors SGD and SGS are selected to be disposed at one end and the other end of the plurality of memory cells MC1 to MCn.

Among the selection gate transistors, a selection gate transistor (second selection gate transistor) SGD at one end (drain side) of the plurality of memory cells MC1 to MCn is located in a stacked body composed of memory cells. The highest end is formed and formed to serve as a vertical transistor having the p ^- -type semiconductor layer 21 as a channel region.

The p ^- -type semiconductor layer 21 is a microcrystalline germanium layer doped with a p-type impurity (for example, boron) of a low concentration (for example, about 1 × 10 ¹⁸ atoms/cm ³ ). Further, in the selection gate transistor SGD, the n-type microcrystalline germanium layer 20 in which the memory cell MC is disposed is used as the source region, and the n ⁺ diffusion layer 22 located at the highest end of the columnar semiconductor layer is used as the drain electrode. region. The n ⁺ diffusion layer 22 is a microcrystalline germanium layer doped with a high concentration (for example, 1 × 10 ²⁰ atoms/cm ³ ) of n-type impurities. As described above, the select gate transistor SGD acts as a p-channel enhancement mode MIS transistor.

The bit line BL is connected to the n ⁺ diffusion layer 22. The bit line BL is shared by two NAND cell units adjacent in the X direction.

Among the stacked structure gate insulating films 23 of the memory cells MC1 to MCn, the second insulating film 23C is used as the gate insulating film in the selection gate transistor SGD. Regarding the selection of the gate insulating film of the gate transistor SGD, a separately formed insulating film can be used as the gate insulating film instead of using the insulating film 23C as the gate insulating film.

Since the gate transistor SGD is selected as a vertical transistor, the film thickness of the gate electrode is the gate length.

The gate length (film thickness) of the selected gate transistor SGD is set to be larger than the gate length (film thickness) of the memory cell. The reason is that the cutoff characteristics of the selected gate transistor SGD are good. For example, if the gate length (film thickness) of the gate electrode of the memory cell is about 30 nm, the gate length (film thickness) of the selected gate transistor SGD is set to about 150 nm.

On the other hand, a selection gate transistor (first selection gate transistor) SGS at the other end (source side) of the plurality of memory cells MC1 to MCn is disposed on the semiconductor substrate 1. The gate transistor SGS and the n-type microcrystalline germanium layer 20 are selected to have a prescribed distance therebetween to ensure withstand voltage.

The gate transistor SGS is selected to have a gate electrode 31A formed on the gate insulating film 30A on the surface of the semiconductor substrate 1.

For example, in the selection of the gate transistor SGS, the n-type diffusion layers 32A, 32B formed in the semiconductor substrate 1 are used as the source/drain regions. A diffusion layer 32A serving as a drain region of the selection gate transistor SGS is connected to the columnar n-type microcrystalline layer 20. A diffusion layer 32B serving as a source region is connected to the source line SL. The source line SL and the selection gate transistor SGS have a distance therebetween to ensure withstand voltage.

The source line SL is formed in the insulating film 41. The top surface of the source line SL is set to be equal to or lower than a position closest to the lower side of the control gate electrode CG1 of the semiconductor substrate 1 among the plurality of control gate electrodes CG1 to CGn. In the case of the above configuration, the source line SL is not in the immediate vicinity of the memory cells MC1 to MCn. Therefore, it is not necessary to ensure a large distance between the memory cells MC1 to MCn and the source line SL to increase the withstand voltage between the memory cells MC1 to MCn and the source line SL. Therefore, the wafer area can be reduced.

Further, in order to reduce the wafer area, it is necessary to make the selection gate transistor SGS be located below the stacked body composed of the gate electrodes CG1 to CGn of the memory cells and the interlayer insulating film 42. Therefore, it is necessary to ensure, for example, a large thickness of the interlayer insulating film 42 to ensure a large distance between the selection gate transistor SGS and the gate electrode CG1 to prevent the transistor SGS and the electrode CG1 from affecting each other. In the third embodiment, the distance is ensured by the interlayer insulating layer 42 and the masking material 40 on the gate electrode 31A.

The peripheral transistors Tr1 and Tr2 formed in the peripheral circuit section (which are used as the source/drain regions using the n-type diffusion layer 33 and the p-type diffusion layer 34 formed in the semiconductor substrate 1) are disposed on the semiconductor substrate 1. Further, the peripheral transistors Tr1, Tr2 respectively have gate electrodes 31B, 31C formed on the gate insulating films 30B, 30C at the surface of the semiconductor substrate 1.

The selection gate transistor SGS and the peripheral transistors Tr1 and Tr2 on the source side are p-channel or n-channel enhancement mode MIS transistors whose threshold voltage is easily controlled.

Two NAND cells adjacent in the X direction are disposed on a single diffusion layer 32A formed in the semiconductor substrate 1. Via the diffusion layer 32A, two cylindrical n-type microcrystalline germanium layers 20 are electrically connected to the selective gate transistor SGS on the respective source sides.

The columnar n-type microcrystalline germanium layers 20 configured with memory cells are separated from each other in the X direction based on the NAND cell units. In order to reduce the wafer area, the distance between the two n-type microcrystalline germanium layers 20 is set to be smaller than the distance between the selective gate transistor SGS and the source line SL.

The insulating layers 70, 71, and 72 are interposed between the two n-type microcrystalline germanium layers 20, and thus the region in which the memory cells are formed has an SOI structure.

As described above, the n-type microcrystalline germanium layer 20 is used as the semiconductor layer in which the memory cells MC1 to MCn are formed, which causes the crystal grain boundaries to be in the middle of the individual channel regions of the memory cells MC1 to MCn. Therefore, according to the third embodiment, it is possible to suppress variations in memory cell characteristics caused by the presence or absence of crystal grain boundaries, which makes it possible to equalize the memory cell characteristics. In addition, the stacked NAND flash memory system is formed using vertical memory cells, which achieves high integration.

Although in the third embodiment, the state in which the memory cells are disposed in the columnar n-type microcrystalline germanium layer has been explained, a p-type microcrystalline germanium layer may be used. At this time, an n-channel enhancement mode MIS transistor using an n-type semiconductor layer as a channel region and a p-type microcrystalline germanium layer (p ^- type semiconductor layer) and a p ⁺ -type semiconductor layer as a source/drain region is used as Select the gate transistor SGS. Under this circumstance, it is possible to suppress variations in memory cell characteristics caused by the presence or absence of crystal grain boundaries and further suppress segregation of impurities into crystal grain boundaries, and to equalize the characteristics of the memory cells.

(b) Manufacturing method

Hereinafter, referring to Figures 29 to 44, a method of manufacturing the flash memory according to the third embodiment will be explained. 29, 31, 33, 35, 37, 39, 41, and 43 show the process of fabricating a memory cell array segment. 30, 32, 34, 36, 38, 40, 42 and 44 illustrate the process of fabricating peripheral circuit segments.

First, after a well region is formed in the semiconductor substrate 1, a gate insulating film such as a hafnium oxide film is formed on the semiconductor substrate 1 by a thermal oxidation method. Next, a gate electrode (such as a polysilicon film) and a mask material (such as a tantalum nitride film) are sequentially formed on the semiconductor substrate 1 by, for example, a CVD method.

Next, after patterning the tantalum nitride film, the patterned film is etched by, for example, an RIE method. Therefore, as shown in FIGS. 29 and 30, in the case where the mask material 40 is used as a mask, selective gate transistors SGS are formed on the gate insulating films 30A, 30B, 30C at the surface of the semiconductor substrate 1, respectively. The gate electrode 31A and the gate electrodes 31B and 31C of the peripheral transistors Tr1 and Tr2. Thereafter, the diffusion layers 32A, 32B, 33, 34 are formed by, for example, an ion implantation method.

Thereafter, the insulating layer 41 is formed to be aligned with the top end of the mask material 40 by, for example, CVD and CMP methods. Further, the source line SL is connected to the diffusion layer 32B serving as the source region of the selection gate transistor SGS via the opening generated in the insulating layer 41. Contact plugs connected to the source/drain diffusion layers 33, 34 of the peripheral transistor may be formed while forming the source line SL.

Next, the interlayer insulating layer 42 and the gate electrodes 51 to 5n, 60 are alternately stacked on the insulating layer 41 and the mask material 40 by, for example, a CVD method. Although in the third embodiment, the gate electrodes 51 to 5n have been made of, for example, polysilicon, they may be made of a metal such as tungsten (W), aluminum (Al) or copper (Cu).

Next, as shown in FIGS. 31 and 32, the interlayer insulating film 42 and the gate electrodes 51 to 5n, 60 are selectively etched by, for example, a photolithography technique and an RIE method, thereby thereby forming a cell array section. An opening is formed in order to expose the surface of the diffusion layer 32A. Thereafter, a first insulating film 23A (for example, a hafnium oxide film) and a charge storage layer 23B are sequentially formed on the side faces facing the openings of the interlayer insulating layer 42 and the gate electrodes 51 to 5n, 60 by, for example, a CVD method. (for example, tantalum nitride film).

Next, as shown in FIGS. 33 and 34, the charge storage layer 23B and the first insulating film 23A are selectively etched so that the side faces of the gate electrode 60 can be exposed. Next, a second insulating layer 23C is formed on the side of the charge storage layer 23B and on the side of the gate electrode 60.

Thereafter, as shown in FIGS. 35 and 36, the insulating film 23 is selectively etched by anisotropic etching, whereby the side of the first insulating film of the semiconductor substrate 1 is doped with, for example, a low concentration (for example) For example, about 1 × 10 ¹⁸ atoms/cm ³ ) of phosphorus (P) or arsenic (As) amorphous germanium film 20A.

Next, the amorphous germanium layer is selectively etched by an anisotropic etching technique, thereby separating the amorphous germanium layer in the X direction. Thereafter, the semiconductor substrate 1 is rapidly heated by, for example, RTA so that the temperature of the substrate rises to 600 ° C or higher. Next, as shown in FIGS. 37 and 38, an epitaxial layer 20B whose crystal axis is aligned with the crystal axis of the semiconductor substrate 1 is formed on the lower end side of the semiconductor substrate 1 which is in contact with the amorphous germanium film. On the other hand, in the memory cell formation region of the amorphous germanium film, the n-type microcrystalline germanium layer 20 is formed. The heating is performed by RTA in a period from the time when the amorphous germanium in the memory cell formation region is microcrystallized until the epitaxial growth on the semiconductor substrate 1 reaches the memory cell formation region.

Next, as shown in FIGS. 39 and 40, an insulating layer 70 is formed on the side of the n-type microcrystalline germanium layer 20 and on the semiconductor substrate 1 to fill the opening. The top surface of the insulating layer 70 is almost set to the same position as the lower side of the gate electrode 60. Thereafter, the exposed region above the top surface of the insulating layer 70 is doped with a p-type impurity (for example, boron) having a low concentration (for example, about 1 × 10 ¹⁸ atoms/cm ³ ). Next, a p ^- -type semiconductor layer 21 serving as a channel region of the selective gate transistor on the drain side is formed.

Next, as shown in FIGS. 41 and 42, an insulating layer 71 is formed on the insulating layer 70. At this time, the top surface of the insulating layer 71 is almost set to the same position as the top surface of the gate electrode 60. Thereafter, the exposed region above the top surface of the insulating layer 71 is doped with a high concentration (for example, about 1 × 10 ²⁰ atoms/cm ³ ) of n-type impurities. Next, an n ⁺ diffusion layer 22 serving as a drain region of the selected gate transistor is formed.

Next, as shown in FIGS. 43 and 44, an insulating layer 72 is formed on the insulating layer 71. Thereafter, a region above the source line SL is selectively etched, thereby creating an opening. The opening is filled with a high melting point metal such as tungsten (W), whereby the gate electrode composed of the polysilicon film is deuterated from the side of the opening to form the control gate electrodes CG1 to CGn. Next, after removing the remaining tungsten in the opening, a passivation film 80 is formed. Further, after removing the stacked body formed on the top surface of the insulating layer 41 of the peripheral circuit section, the insulating layer 43 is formed in the opening and on the surface of the peripheral circuit section.

Thereafter, the n-type microcrystalline germanium layer 20, the p ^- -type semiconductor layer 21, the n ⁺ diffusion layer 22, and the epitaxial layer 20B are selectively etched to produce a pillar-shaped semiconductor layer based on the NAND cell. The resulting layers were separated in the Y direction. An opening (not shown) generated by the separation in the Y direction is filled with an insulating layer (not shown). Thereafter, a bit line BL extending in the X direction is formed to be electrically connected to the n ⁺ diffusion layer 22. The process of separating the semiconductor layers to produce the columnar semiconductor layer based on the NAND cell unit is not limited to the sequence of the above manufacturing process. For example, the process can be performed simultaneously with the process of separating the amorphous germanium layer in the X direction. Through the above process, the flash memory of the third embodiment is completed.

By the above manufacturing method, a columnar semiconductor layer serving as a channel region of a memory cell in a stacked structure flash memory composed of vertical memory cells can be made of a microcrystalline germanium layer.

Therefore, according to the third embodiment, it is possible to suppress variations in the characteristics of the memory cells MC1 to MCn, and thus to provide a memory cell characterized by homogeneity. In addition, the use of a stacked structure flash memory using vertical memory cells enables high integration.

3. Other

Embodiments of the present invention enable the fabrication of memory cells having homogeneous characteristics in the SOI region.

Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive principles as defined by the appended claims.

1. . . Semiconductor substrate

2. . . Buried oxide film

3. . . Microcrystalline layer

3A. . . Amorphous germanium film

4. . . Epitaxial layer / epitaxial layer

5. . . P ^- type semiconductor layer

6A. . . Gate insulating film (tunnel oxide film)

6B. . . Gate insulating film

6C. . . Gate insulating film

7A. . . Floating gate electrode / floating gate

7B. . . Gate electrode

7C. . . Gate electrode

8. . . ONO film / gate insulating film

8A. . . Inter-gate insulating film

8B. . . Inter-gate insulating film

8C. . . Inter-gate insulating film

9. . . Polycrystalline germanium film

9A. . . Control gate electrode

9B. . . Gate electrode

9C. . . Gate electrode

10. . . n ⁺ diffusion layer

10A. . . n ⁺ diffusion layer

10B. . . n ⁺ diffusion layer

11. . . p ⁺ diffusion layer

12. . . Insulation

13. . . Insulation

14. . . Resist pattern

15. . . P-type microcrystalline layer

16. . . Component isolation insulation

17. . . Epitaxial layer

18. . . N ^- type semiconductor layer

19. . . p ⁺ diffusion layer

19A. . . p ⁺ diffusion layer

20. . . Cylindrical semiconductor layer/columnar n-type microcrystalline germanium layer

20A. . . Amorphous germanium film

20B. . . Epitaxial layer

twenty one. . . P ^- type semiconductor layer

twenty two. . . n ⁺ diffusion layer

twenty three. . . Gate insulating film

23A. . . First insulating film

23B. . . Charge storage layer

23C. . . Second insulating film

30A. . . Gate insulating film

30B. . . Gate insulating film

30C. . . Gate insulating film

31A. . . Gate electrode

31B. . . Gate electrode

31C. . . Gate electrode

32A. . . N-type diffusion layer

32B. . . N-type diffusion layer

33. . . N-type diffusion layer

34. . . P-type diffusion layer

40. . . Mask material

41. . . Insulating film / insulating layer

42. . . Interlayer insulating layer / interlayer insulating film

43. . . Insulation

51, 52, 5n. . . Gate electrode

60. . . Gate electrode

70. . . Insulating film / insulating layer

71. . . Insulation

72. . . Insulation

80. . . Passivation film

100. . . Memory cell array

110. . . Column decoder circuit

120. . . Sense amplifier circuit

130. . . Control circuit

AA. . . Action area

BC. . . Bit line contact

BL. . . Bit line

C1. . . Contact/contact part

C2. . . Contact/contact part

CG1, CG2, CGn. . . Control gate/control gate electrode

EA. . . Epitaxial region

GB. . . Grain boundaries

GC. . . Gate contact

GL. . . Gate wiring layer

L. . . Memory channel length

L1. . . Metal wiring layer

L2. . . Metal wiring layer

M1. . . Metal wiring layer

MC. . . Memory cell

MC1, MC2, MCn. . . Memory cell

SA. . . SOI area

SC. . . Source line contact

SGD. . . Select gate transistor

SGS. . . Select gate transistor

SL. . . Source line

STI. . . Isolated insulation area / component isolation area

T. . . Film thickness

Tr1. . . N-channel MIS transistor / peripheral transistor

Tr2. . . p channel MIS transistor / peripheral transistor

V1. . . path

W. . . Memory cell channel width

1 shows an example of a layout of a flash memory according to a first embodiment of the present invention;

Figure 2 is a plan view of a memory cell array section according to the first embodiment;

Figure 3 is a cross-sectional view taken along line III-III of Figure 2;

Figure 4 is a cross-sectional view taken along line IV-IV of Figure 2;

Figure 5 is a plan view of a peripheral circuit section according to the first embodiment;

Figure 6 is a cross-sectional view taken along line VI-VI of Figure 5;

Figure 7 is a cross-sectional view taken along line VII-VII of Figure 5;

Figure 8 is a cross-sectional view showing one of the manufacturing processes of the first embodiment;

Figure 9 is a cross-sectional view showing one of the manufacturing processes of the first embodiment;

Figure 10 is a cross-sectional view showing one of the manufacturing processes of the first embodiment;

Figure 11 is a cross-sectional view showing one of the manufacturing processes of the first embodiment;

Figure 12 is a cross-sectional view showing one of the manufacturing processes of the first embodiment;

Figure 13 is a cross-sectional view showing one of the manufacturing processes of the first embodiment;

Figure 14 is a cross-sectional view showing one of the manufacturing processes of the first embodiment;

Figure 15 is a cross-sectional view showing one of the manufacturing processes of the first embodiment;

Figure 16 is a cross-sectional view showing one of the manufacturing processes of the first embodiment;

Figure 17 is a cross-sectional view showing one of the manufacturing processes of the first embodiment;

Figure 18 is a cross-sectional view showing a complementary example of the first embodiment;

Figure 19 is a cross-sectional view showing a complementary example of the first embodiment;

Figure 20 is a cross-sectional view showing a memory cell array section in accordance with a second embodiment of the present invention;

Figure 21 is a cross-sectional view showing a peripheral circuit section of the second embodiment;

Figure 22 is a cross-sectional view showing one of the manufacturing processes of the second embodiment;

Figure 23 is a cross-sectional view showing one of the manufacturing processes of the second embodiment;

Figure 24 is a perspective view of a NAND cell unit in accordance with a third embodiment of the present invention;

Figure 25 is a plan view showing a memory cell array section according to a third embodiment;

Figure 26 is a cross-sectional view taken along line XXVI-XXVI of Figure 25;

Figure 27 is a cross-sectional view taken along line XXVII-XXVII of Figure 25;

Figure 28 is a cross-sectional view taken along the length of the channel of the peripheral transistor;

Figure 29 is a cross-sectional view showing one of the manufacturing processes of the third embodiment;

Figure 30 is a cross-sectional view showing one of the manufacturing processes of the third embodiment;

Figure 31 is a cross-sectional view showing one of the manufacturing processes of the third embodiment;

Figure 32 is a cross-sectional view showing one of the manufacturing processes of the third embodiment;

Figure 33 is a cross-sectional view showing one of the manufacturing processes of the third embodiment;

Figure 34 is a cross-sectional view showing one of the manufacturing processes of the third embodiment;

Figure 35 is a cross-sectional view showing one of the manufacturing processes of the third embodiment;

Figure 36 is a cross-sectional view showing one of the manufacturing processes of the third embodiment;

Figure 37 is a cross-sectional view showing one of the manufacturing processes of the third embodiment;

Figure 38 is a cross-sectional view showing one of the manufacturing processes of the third embodiment;

Figure 39 is a cross-sectional view showing one of the manufacturing processes of the third embodiment;

Figure 40 is a cross-sectional view showing one of the manufacturing processes of the third embodiment;

Figure 41 is a cross-sectional view showing one of the manufacturing processes of the third embodiment;

Figure 42 is a cross-sectional view showing one of the manufacturing processes of the third embodiment;

Figure 43 is a cross-sectional view showing one of the manufacturing processes of the third embodiment; and

Figure 44 is a cross-sectional view showing one of the manufacturing processes of the third embodiment.

1. . . Semiconductor substrate

2. . . Buried oxide film

3. . . Microcrystalline layer

4. . . Epitaxial layer / epitaxial layer

5. . . P ^- type semiconductor layer

6A. . . Gate insulating film (tunnel oxide film)

6B. . . Gate insulating film

7A. . . Floating gate electrode / floating gate

7B. . . Gate electrode

8A. . . Inter-gate insulating film

8B. . . Inter-gate insulating film

9A. . . Control gate electrode

9B. . . Gate electrode

10. . . n ⁺ diffusion layer

10A. . . n ⁺ diffusion layer

12. . . Insulation

13. . . Insulation

BC. . . Bit line contact

BL. . . Bit line

EA. . . Epitaxial region

M1. . . Metal wiring layer

MC1, MC2, MCn. . . Memory cell

SA. . . SOI area

SC. . . Source line contact

SGD. . . Select gate transistor

SGS. . . Select gate transistor

SL. . . Source line

V1. . . path

Claims (12)

A non-volatile semiconductor memory comprising: a semiconductor substrate; a pillar-shaped semiconductor layer extending in a vertical direction toward a surface of the semiconductor substrate; a plurality of memory cells disposed in the vertical direction Each of the sides of the semiconductor layer has a charge storage layer and a control gate electrode, wherein the pillar semiconductor layer is made of a microcrystalline layer. The non-volatile semiconductor memory of claim 1, further comprising: a first select gate transistor disposed on the semiconductor and disposed at an end of the plurality of memory cells on the side of the semiconductor substrate, and Connected to the semiconductor layer via a diffusion layer; and a second select gate transistor disposed on the side of the semiconductor layer and disposed on the opposite side of the semiconductor substrate side At the end. The non-volatile semiconductor memory of claim 1, wherein the crystallites constituting the microcrystalline layer have a particle diameter smaller than a half of a channel length and a channel width of the memory cell. The non-volatile semiconductor memory of claim 2, wherein the gate electrode of the first select gate transistor is under the control gate electrode of the memory cell via an interlayer insulating film. The non-volatile semiconductor memory of claim 2, further comprising a source line connected to the first select gate transistor, wherein a top surface of the source line is at a lower than the closest to the plurality of memories The position of the memory cell of the cell on the semiconductor substrate side that controls the lower side of the gate electrode. The non-volatile semiconductor memory of claim 1, wherein the memory cells are depletion mode MONOS structure transistors, and the transistors do not have a diffusion layer serving as a source/drain region in the semiconductor layer, and the conduction thereof The properties are different from the conductivity of the semiconductor layer. The non-volatile semiconductor memory of claim 2, wherein the first select gate transistor and the second select gate transistor are enhancement mode MIS transistors. The non-volatile semiconductor memory of claim 1, wherein each of the memory cells further has a first insulating film disposed between the control gate electrode and the charge storage layer and a charge disposed on the charge a second insulating layer between the storage layer and the semiconductor layer. The non-volatile semiconductor memory of claim 8, wherein the second insulating film is disposed between the gate electrode of the second select gate transistor and the semiconductor layer. The non-volatile semiconductor memory of claim 2, wherein a gate length of the second select gate transistor is greater than a control gate length of the memory cells. The non-volatile semiconductor memory of claim 1, wherein if the film thickness of the semiconductor layer is T, and the gate length of the memory cells is L, T is greater than 1 nm and less than L×0.8. The non-volatile semiconductor memory of claim 1, further comprising a peripheral transistor disposed on the semiconductor substrate, wherein the peripheral transistor is an enhancement mode MIS transistor.