TWI434398B - Esd protection circuit for high voltage chip - Google Patents

Description

Electrostatic discharge protection circuit for ultra high voltage wafer

The present invention relates to an electrostatic discharge protection circuit, and more particularly to an electrostatic discharge protection circuit for an ultrahigh voltage wafer.

In general, Electrostatic Discharge (ESD) current is one of the main problems in the connection process of electronic products. In addition to the human body's touch may cause the discharge of static electricity, the electronic product itself will accumulate static electricity. An electrostatic discharge current is generated.

With the advancement of electronic products, consumers not only pay attention to the functions of electronic products themselves, but if electronic products can be connected to various electronic devices, it will help to increase consumers' willingness to purchase. For example, multi-functionality and miniaturization have become the trend of current handheld electronic product design. In order to enable handheld electronic products to integrate peripheral electronic devices, the transmission interface (such as I/O埠) is usually increased. However, in practice, if the transmission interface is more, it is often easier for the electrostatic discharge current to enter the electronic product through the transmission interface, thereby interfering with or damaging the integrated circuit inside the electronic product.

In particular, when part of the integrated circuit inside the electronic product is operated in an ultra-high voltage environment, if the electrostatic discharge current in an ultra-high voltage environment is directly guided to a circuit of a general voltage, it will easily cause an electronic product. Many circuit or electronic parts fail (such as receiving excessive current or overheating), causing many losses to electronics manufacturers. Therefore, the industry is eager to solve the problem of electrostatic discharge current in ultra-high voltage wafers in order to improve the yield and reliability of electronic products.

The invention provides an electrostatic discharge protection circuit for an ultra-high voltage wafer, which can actively detect whether an electrostatic discharge current is generated and provide an appropriate current transmission path to discharge an electrostatic discharge current. When an electrostatic discharge current is detected, the electrostatic discharge protection circuit turns on a power semiconductor component inside, and opens a current transmission path from a power line of the high voltage isolation well region to the potential conversion circuit to avoid operation of a general voltage. The circuit is damaged.

Embodiments of the present invention provide an ESD protection circuit for an ultra-high voltage wafer. The ESD protection circuit is coupled to a potential conversion circuit and coupled to a ground through a potential conversion circuit. The ESD protection circuit includes a power clamping module and at least one switch module. The power clamping module is coupled between the first high voltage end and the first low voltage end for detecting an electrostatic discharge current from the first high voltage end or the first low voltage end, thereby generating a control signal. The switch module includes a first resistor and a first power semiconductor component, the first resistor is coupled between the first high voltage terminal and the potential conversion circuit, the first power semiconductor component is coupled in parallel with the first resistor, and the first power semiconductor component is Controlling the control signal to selectively turn on the first current transmission path, so that the first high voltage end is electrically connected to the potential conversion circuit through the first current transmission path, wherein a potential difference between the first low voltage end and the ground end is greater than a first voltage threshold value.

In an exemplary embodiment of the invention, the ESD protection circuit and the potential conversion circuit are formed in the same ultrahigh voltage wafer via the same semiconductor process. In addition, the control electrode of the first power semiconductor component can be coupled to the power clamping module to receive the control signal, the first electrode of the first power semiconductor component can be coupled to the first high voltage end, and the second electrode of the first power semiconductor component can be The potential conversion circuit is coupled. In addition, the power clamping module includes at least one second resistor and a first capacitor, the second resistor and the first capacitor are coupled between the first high voltage end and the first low voltage end, and the second resistor is coupled in series through the first node. Connected to the first capacitor, the power clamping module detects the amount of potential change on the first node to generate a control signal.

In summary, the present invention provides an electrostatic discharge protection circuit for an ultra-high voltage wafer. When the power supply clamp module determines that an electrostatic discharge current is generated, an appropriate current transmission path can be provided immediately to discharge the electrostatic discharge current. In other words, when the power clamping module detects the electrostatic discharge current, the electrostatic discharge protection circuit turns on a power semiconductor component in the internal switch module, and opens the power line from the high voltage isolation well region to the potential conversion. The current transmission path of the circuit prevents the circuit operating from the normal voltage from being damaged.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

[Embodiment of Electrostatic Discharge Protection Circuit]

Please refer to FIG. 1. FIG. 1 is a schematic circuit diagram of an electrostatic discharge protection circuit according to an embodiment of the invention. As shown in FIG. 1, the ESD protection circuit 1a of the present embodiment has a power supply clamping module 10, a switch module 12a, a switch module 12b, a power semiconductor component 14a, a power semiconductor component 14b, a diode 16a, and a diode. 16b, and the ESD protection circuit 1a is coupled to the gate driver 18 and the potential conversion circuit 3, respectively. Since the gate driver 18 is mainly used to push an electric device requiring a higher voltage such as a motor or a coil, and the electrostatic discharge protection circuit 1a and the gate driver 18 operate in a high voltage environment, static electricity is considered from the viewpoint of circuit layout. The discharge protection circuit 1a and the gate driver 18 are located in the high voltage isolation well region H. Further, the potential conversion circuit 3 is not particularly distinguished from other general circuits.

In practice, the potential conversion circuit 3 can control the two high voltage resistant power transistors 32a, 32b by the potential conversion controller 30 to raise the voltage level of the high voltage isolation well region H, so that the high voltage isolation well The base voltage level of the zone H (the voltage of the first low voltage terminal V _S ) has a voltage threshold between the basic voltage level of the general circuit (the voltage of the ground terminal V _SS ). In addition, the electrical device (not shown) that the gate driver 18 is to push is connected to the transmission interface 20a, the transmission interface 20b, and the transmission interface 20c, and the electrical equipment is often pre-configured to be optimal for operation. In the working voltage interval, in order to make the output voltage of the gate driver 18 be within the preset operating voltage range of the electrical device, the high voltage isolation well region H needs to raise the voltage of the first low voltage terminal V _S to make the first low voltage end The voltage of V _S corresponds to the lower limit of the operating voltage range of the electrical device. That is to say, the voltage threshold value of the embodiment is actually determined by referring to the operating voltage interval of the electrical device.

For example, if the electrical device needs to operate in the range of 325V to 342V, the first high voltage terminal V _{B of} the high voltage isolation well region H can be designed to have a voltage of about 342V, and the high voltage isolation well region. The first low voltage terminal V _{S of} H can be designed to have a voltage level of about 325V. Relative to the voltage level (0V) of the general circuit ground terminal V _SS , the high voltage isolation well region H can be raised by a voltage level of a voltage threshold (ie, 325V), so that the gate driver 18 can be used for output. Meet the voltage required by the electrical equipment.

In other words, since the voltage variation in the high voltage isolation well region H is limited, the circuit components in the high voltage isolation well region H need only meet the withstand voltage requirement of about 30V. On the other hand, since the potential conversion circuit 3 of the present embodiment withstands a voltage difference of 300 V or more, the potential conversion circuit 3 requires a relatively higher withstand voltage requirement at the time of design (for example, a device with a withstand voltage of about 700 V can be designed. ). Further, the electrostatic discharge protection circuit 1a, the gate driver 18, and the potential conversion circuit 3 are formed in the same ultrahigh voltage wafer through the same semiconductor process. Hereinafter, each component of the electrostatic discharge protection circuit 1a and other matching circuits will be described in detail. .

Clamping power module 10 is coupled between the first high voltage terminal and the first low voltage terminal V _B V _S, from the first to the high voltage terminal V _B V _S or the first low side current detecting electrostatic discharge, according to generate a control signal. Here, the power supply clamping module 10 includes a resistor R ₁ , a capacitor C ₁ , an inverter 102 and a transistor 104 , wherein the resistor R ₁ , the capacitor C ₁ and the inverter 102 can be regarded as an ESD transient detecting unit. The transistor 104 is coupled in parallel to the ESD transient detecting unit. In addition, the gate of the transistor 104 in the power clamping module 10 is coupled to the output of the inverter 102 (node B), and the input of the inverter 102 is connected between the resistor R ₁ and the capacitor C ₁ . Node A.

In practice, the power clamping module 10 detects the amount of potential change on the node A, and then the detection result is inverted by the inverter 102, and the control signal is obtained from the node B. In addition, the capacitor C ₁ may be composed of an NMOS power MOS transistor, and the inverter 102 may be composed of a PMOS power MOS transistor and an NMOS power MOS transistor, which has general knowledge in the technical field. The design can be freely changed depending on the situation, and the invention is not limited thereto.

Switch module 12a includes a resistor R _2a to the power semiconductor element Q _1a, R _2a resistor coupled between the first 3 and the high voltage terminal V _B voltage conversion circuit, the power semiconductor element Q _1a R _2a resistor coupled in parallel, and the power The semiconductor element Q _{1a is} controlled by a control signal to selectively electrically connect the first high voltage terminal V _B to the potential conversion circuit 3. In detail, the power semiconductor device Q _{1a of the} present embodiment may be an NMOS power MOS transistor, and the control electrode (gate) of the power semiconductor device Q _1a is coupled to the node B of the power clamping module 10, and the power is The first electrode (drain) of the semiconductor device Q _1a is coupled to the first high voltage terminal V _B , and the second electrode (source) of the power semiconductor device Q _1a is coupled to the potential conversion circuit 3 .

Whereby, when the control signal for driving the power semiconductor element on the source Node B Q _1a is turned on, the internal power semiconductor element Q _1a can be provided a high-voltage terminal by a first potential V _B to a current transmission path conversion circuit 3, The electrostatic discharge current is prevented from flowing into the ultrahigh voltage wafer by entering the resistor R _2a . Of course, in addition to the switch module 12a, there may be another switch module 12b. The number of switch modules may be changed by a person skilled in the art, and the present invention is not limited thereto.

Referring to FIG. 1 , the power semiconductor component 14a may be an NMOS power MOS transistor, and the gate (gate) of the power semiconductor component 14a is coupled to the first low voltage terminal V _S , and the power semiconductor component 14 a The first electrode (drain) is coupled to the first high voltage terminal V _B , and the second electrode (source ) of the power semiconductor device 14 a is coupled to the second electrode (source) of the power semiconductor device Q ₁ a and the potential conversion circuit 3 Between the nodes. Here, in addition to the power semiconductor component 14a, there may actually be another set of power semiconductor components 14b, and the connection relationship between the power semiconductor component 14b and the switch module 12b is the same as that of the power semiconductor component 14a and the switch module 12a. The connection relationship between the embodiments is not described herein.

The diode 16a and the diode 16b are coupled in series between the first high voltage terminal V _B and the first low voltage terminal V _S to provide a unidirectional current from the first low voltage terminal V _S to the first high voltage terminal V _B . Transmission path. In practice, the gate driver 18 needs to push the motor, the coil, etc., so the gate driver 18 exemplifies three transmission interfaces (for example, corresponding to the three-phase voltage required by the back-end device), that is, The output of the gate driver 18 is a transmission interface 20a, a transmission interface 20b, and a transmission interface 20c. Here, the voltages carried by the transmission interface 20a, the transmission interface 20b, and the transmission interface 20c are not necessarily the same. For example, the transmission interface 20a and the transmission interface 20c have a voltage difference of about 17V, and the voltage difference between the transmission interface 20a and the transmission interface 20b should be Less than 17V.

As can be seen from FIG. 1, the diode 16a is coupled between the transmission interface 20a and the transmission interface 20b, and the diode 16b is coupled between the transmission interface 20b and the transmission interface 20c. The function of the diode 16a and the diode 16b of the present embodiment is that the electrostatic discharge current can be transmitted from the transmission interface 20b or the transmission interface 20c through the diode 16a and the diode 16b of the embodiment. The electrostatic discharge current is directed to the first high voltage terminal V _B . Of course, if the electrostatic discharge current is fed from the transmission interface 20a, since the electrostatic discharge current is already on the first high voltage terminal V _B , the diode 16a and the diode 16b do not operate at this time. In other words, the diode 16a and the diode 16b are used to guide the electrostatic discharge current fed by the respective transmission interfaces to the first high voltage terminal V _B , which can be used by those skilled in the art in practice. Different numbers of diodes or variations design a circuit for guiding the electrostatic discharge current, and the invention is not limited thereto.

From the actual operation mode of the circuit of the embodiment, for example, when the electrostatic discharge current is fed from the transmission interface 20c, the electrostatic discharge current is first concentrated from the current transmission path formed by the diode 16a and the diode 16b. On the first high voltage end V _B . Further, in the steady state, the capacitor C ₁ is in a state of being fully charged, and the voltage of the node A is almost equal to the voltage of the first high voltage terminal V _B . The occurrence of the electrostatic discharge current will instantaneously pull the voltage of the node A low (close to the voltage of the first low voltage terminal V _S ), and since the amount of voltage change on the node B and the voltage change on the node A are inversely related to each other, The voltage at node B is raised in an instant. The voltage that is raised at this moment is a control signal, thereby turning on the transistor 104, the power semiconductor element Q _1a, and the power semiconductor element Q _1b .

It can be seen from the above that when the rate semiconductor element Q _{1a is} turned on, the inside of the power semiconductor element Q _1a can provide the current transmission path of the first high voltage terminal V _B to the potential conversion circuit 3, so that the electrostatic discharge current can be from the ground terminal V _SS Discharge. Of course, the electrostatic discharge current can be transmitted through the power clamp module 40a, 40b or the power supply diode clamp module 42 from the second or the third high-voltage terminal V _CC discharging the high voltage terminal V _DD, wherein the diode 40b may be coupled at its Between the high voltage terminal V _CC and the third high voltage terminal V _DD . That is to say, after the electrostatic discharge protection circuit 1a of the present invention directs the electrostatic discharge current to the potential conversion circuit 3, it can be combined with the electrostatic discharge mechanism of the general circuit to discharge the electrostatic discharge current from the power of the general circuit or from the ground. (ground) discharge.

It should be noted that the control signal described in this embodiment does not have to be obtained from the node B. In the case that the other components in the electrostatic discharge protection circuit 1a have a matching design, those having ordinary knowledge in the technical field may of course take The detection result on the node A is used as a control signal. Herein, although the present invention has been described as a few embodiments, the present invention is not limited thereto.

[Another Embodiment of Electrostatic Discharge Protection Circuit]

Referring to FIG. 2, FIG. 2 is a schematic circuit diagram of an ESD protection circuit according to another embodiment of the present invention. 2 is the same as FIG. 1 in that the electrostatic discharge protection circuit 1b of FIG. 2 also uses the power supply clamping module 10 to detect the electrostatic discharge current, thereby controlling the switch module 12c and the switch module 12d to generate the first high voltage end. V _B to the current transfer path of the potential conversion circuit 3. However, FIG. 2 differs from FIG. 1 in that the power semiconductor device Q _1a of FIG. 1 is an NMOS power MOS transistor, and the power semiconductor device Q _1a of FIG. 2 is an npn bipolar transistor (BJT). .

Here, the base of the npn bipolar transistor (BJT) and the gate of the NMOS power MOS transistor drive the npn bipolar transistor and the NMOS power oxy-oxide respectively when receiving a high level voltage. The semi-transistor is turned on so that the npn bipolar transistor can also provide a current transmission path from the first high voltage terminal V _B to the potential conversion circuit 3. In addition, the operation of the power supply clamping module 10 is the same as that of the electrostatic discharge protection circuit 1a of FIG. 1, and no additional design is required.

[Another embodiment of the electrostatic discharge protection circuit]

Referring to FIG. 3, FIG. 3 is a schematic circuit diagram of an ESD protection circuit according to still another embodiment of the present invention. 3 is the same as FIG. 2 in that the switching module of the ESD protection circuit 1c of FIG. 3 also uses an npn bipolar transistor (BJT), and generates a first high voltage terminal V _B to the potential conversion circuit 3 according to the control signal. Current transfer path. However, FIG. 3 differs from FIG. 2 in that the power supply clamping module 10a of FIG. 3 does not have an inverter. That is to say, with respect to the power supply clamping module 10 of the previous embodiment, the power supply clamping module 10a of FIG. 3 has a reduced component, and of course the manufacturing cost is also reduced.

Here, the power supply clamping module 10a changes the series sequence of the resistor R ₁ and the capacitor C ₁ such that at steady state, since the capacitor C ₁ is fully charged, the voltage of the node A is almost equal to the voltage of the first low voltage terminal V _S . . When an electrostatic discharge current occurs, the voltage at node A is momentarily pulled high (close to the voltage at the first high voltage terminal V _B ). The moment the voltage is raised is the control signal, whereby access to electricity conducting crystal 104, the power semiconductor element of the power semiconductor element Q _1a and Q _1b, Q _1a so that the power semiconductor element and the power semiconductor element Q _1b (npn bipolar The transistor) can provide a current transmission path from the first high voltage terminal V _B to the potential conversion circuit 3.

[Another embodiment of the electrostatic discharge protection circuit]

Referring to FIG. 4, FIG. 4 is a schematic circuit diagram of an ESD protection circuit according to still another embodiment of the present invention. 4 is the same as FIG. 1 in that the electrostatic discharge protection circuit 1d of FIG. 4 also uses the power supply clamp module to detect the electrostatic discharge current, and then controls the switch module to generate the first high voltage terminal V _B to the potential conversion circuit 3 . Current transfer path. However, FIG. 4 differs from FIG. 1 in that the power semiconductor device Q _1a of FIG. 1 is an NMOS power MOS transistor, and the power semiconductor device Q _1a of FIG. 4 is a pnp bipolar transistor (BJT). And Figure 4 draws control signals from node A.

In steady state, the capacitor C ₁ is in a fully charged state, the voltage of the node A is almost equal to the voltage of the first high voltage terminal V _B , and the occurrence of the electrostatic discharge current instantaneously lowers the voltage of the node A (close to the first The voltage of a low voltage terminal V _S ). Here, since the base of the pnp bipolar transistor is turned on by the low level voltage, the voltage variation on the node A can be regarded as the control signal, so the node A of FIG. 4 can be directly coupled. To the base of the pnp bipolar transistor.

[Another embodiment of the electrostatic discharge protection circuit]

Referring to FIG. 5, FIG. 5 is a schematic circuit diagram of an ESD protection circuit according to still another embodiment of the present invention. 5 is the same as FIG. 4 in that the switch modules 12e and 12f of the ESD protection circuit 1e of FIG. 5 also use a power semiconductor element Q _{1a which} is a pnp bipolar transistor (BJT) for providing a first high voltage. The current transfer path from the terminal V _B to the potential conversion circuit 3. However, FIG. 5 differs from FIG. 4 in that the power supply clamping module 10c of FIG. 5 does not have an inverter, and the transistor 104a is a PMOS power MOS transistor.

It should be understood by those skilled in the art that since the voltage of the node A is pulled down instantaneously due to the occurrence of the electrostatic discharge current, the sudden voltage drop on the node A of FIG. 5 can simultaneously drive the power clamp module 10c. The transistor 104a is electrically connected to the pnp bipolar transistor in the switch module 12e and the switch module 12f.

[Another embodiment of the electrostatic discharge protection circuit]

Referring to FIG. 6, FIG. 6 is a schematic circuit diagram of an electrostatic discharge protection circuit according to still another embodiment of the present invention. 6 is the same as FIG. 1 in that the electrostatic discharge protection circuit 1f of FIG. 6 also uses the power supply clamping module 10 to detect the electrostatic discharge current, thereby controlling the switch module 12g and the switch module 12h to generate the first high voltage end. V _B to the current transfer path of the potential conversion circuit 3. However, FIG. 6 differs from FIG. 1 in that the power semiconductor element Q _1a of FIG. 6 is a gated rectifier (SCR).

Here, when the gate of the step-controlled rectifier receives the high level voltage, it respectively drives the step-controlled rectifier to be turned on, so that the step-controlled rectifier can also provide the current transmission path of the first high-voltage terminal V _B to the potential conversion circuit 3. In addition, the operation of the power supply clamping module 10 is the same as that of the electrostatic discharge protection circuit 1a of FIG. 1, and no additional design is required.

[Another embodiment of the electrostatic discharge protection circuit]

Referring to FIG. 7, FIG. 7 is a schematic circuit diagram of an ESD protection circuit according to still another embodiment of the present invention. 7 is the same as FIG. 6 in that the switching module of the ESD protection circuit 1g of FIG. 7 also selects a current-controlled rectifier to generate a current transmission path from the first high-voltage terminal V _B to the potential conversion circuit 3 according to the control signal. However, FIG. 7 differs from FIG. 6 in that the power supply clamping module 10a of FIG. 7 does not have an inverter. That is to say, with respect to the power supply clamping module 10 of the previous embodiment, the power supply clamping module 10a of FIG. 7 has a reduced component, and of course the manufacturing cost is also reduced.

Here, the power supply clamping module 10a changes the series sequence of the resistor R ₁ and the capacitor C ₁ such that at steady state, since the capacitor C ₁ is fully charged, the voltage of the node A is almost equal to the voltage of the first low voltage terminal V _S . . When an electrostatic discharge current occurs, the voltage at node A is momentarily pulled high (close to the voltage at the first high voltage terminal V _B ). The voltage that is raised at this moment is the control signal, thereby turning on the transistor 104 and the step-controlled rectifier in the switch modules 12g, 12h, so that the step-controlled rectifier can provide the first high-voltage terminal V _B to the potential conversion circuit. 3 current transmission path.

[Another embodiment of the electrostatic discharge protection circuit]

Referring to FIG. 8, FIG. 8 is a schematic circuit diagram of an ESD protection circuit according to still another embodiment of the present invention. 8 is the same as FIG. 4 in that the electrostatic discharge protection circuit 1h of FIG. 8 similarly detects the electrostatic discharge current by the power supply clamping module 10b, and draws a control signal from the node A. 8 is different from FIG. 4 in that the switch modules 12j and 12k of FIG. 8 are selected from PMOS power MOS transistors.

In steady state, the capacitor C ₁ is in a fully charged state, the voltage of the node A is almost equal to the voltage of the first high voltage terminal V _B , and the occurrence of the electrostatic discharge current instantaneously lowers the voltage of the node A (close to the first The voltage of a low voltage terminal V _S ). Here, since the gate of the PMOS power MOS transistor is turned on by the low level voltage, the voltage variation on the node A can be regarded as the control signal, so the node A of FIG. 8 can be directly coupled. Connected to the gate of the PMOS power MOS transistor.

[Another embodiment of the electrostatic discharge protection circuit]

Referring to FIG. 9, FIG. 9 is a schematic circuit diagram of an ESD protection circuit according to still another embodiment of the present invention. 9 is the same as FIG. 5 in that the electrostatic discharge protection circuit 1i of FIG. 9 similarly detects the electrostatic discharge current by the power supply clamping module 10c, and draws a control signal from the node A. 9 is different from FIG. 6 in that the switch modules 12j and 12k of FIG. 9 are selected from PMOS power MOS transistors.

It should be understood by those skilled in the art that since the voltage of the node A is pulled down instantaneously due to the occurrence of the electrostatic discharge current, the sudden voltage drop on the node A of FIG. 9 can simultaneously drive the power clamp module 10c. The transistor 104a is electrically connected to the PMOS power MOS transistor in the switch module 12j and the switch module 12k.

In summary, the ESD protection circuit for the ultra-high voltage chip provided by the embodiment of the present invention can be connected between the first high voltage end and the first low voltage end by the power clamping module to detect the first high voltage end. Or whether an electrostatic discharge current is generated on the first low voltage end. When the power clamping module determines that the electrostatic discharge current is generated, an appropriate current transmission path can be provided immediately to discharge the electrostatic discharge current. In other words, when the power clamping module detects the electrostatic discharge current, the electrostatic discharge protection circuit turns on a power semiconductor component in the internal switch module, and opens the power line from the high voltage isolation well region to the potential conversion. The current transmission path of the circuit prevents the circuit operating from the normal voltage from being damaged.

The above description is only an embodiment of the present invention, and is not intended to limit the scope of the invention.

1a~1i. . . Electrostatic discharge protection circuit

10, 10a~10c. . . Power clamp module

102. . . inverter

104, 104a. . . Transistor

12a~12k. . . Switch module

14a~14b. . . Power semiconductor component

16a~16b. . . Dipole

18. . . Gate driver

20a~20c. . . Transmission interface

3. . . Potential conversion circuit

30. . . Potential conversion controller

32a, 32b. . . High voltage resistant power transistor

40a. . . Power clamp module

40b. . . Dipole

42. . . Power clamp module

V _B . . . First high end

V _S . . . First low end

V _SS . . . Ground terminal

V _CC . . . Second low end

V _DD . . . Third high end

H. . . High voltage isolation well region

A, B. . . node

R ₁ , R _2a , R _2b . . . resistance

C ₁ . . . capacitance

Q _1a , Q _1b . . . Power semiconductor component

FIG. 1 is a schematic circuit diagram of an electrostatic discharge protection circuit according to an embodiment of the invention.

2 is a circuit diagram of an electrostatic discharge protection circuit according to another embodiment of the present invention.

3 is a circuit diagram showing an electrostatic discharge protection circuit according to still another embodiment of the present invention.

4 is a circuit diagram showing an electrostatic discharge protection circuit according to still another embodiment of the present invention.

FIG. 5 is a schematic circuit diagram of an electrostatic discharge protection circuit according to still another embodiment of the present invention.

6 is a circuit diagram of an electrostatic discharge protection circuit according to still another embodiment of the present invention.

FIG. 7 is a schematic circuit diagram of an ESD protection circuit according to still another embodiment of the present invention.

FIG. 8 is a schematic circuit diagram of an ESD protection circuit according to still another embodiment of the present invention.

FIG. 9 is a schematic circuit diagram of an ESD protection circuit according to still another embodiment of the present invention.

1a. . . Electrostatic discharge protection circuit

10. . . Power clamp module

102. . . inverter

104, 104a. . . Transistor

12a~12b. . . Switch module

14a~14b. . . Power semiconductor component

16a~16b. . . Dipole

18. . . Gate driver

20a~20c. . . Transmission interface

3. . . Potential conversion circuit

30. . . Potential conversion controller

32a, 32b. . . High voltage resistant power transistor

40a. . . Power clamp module

40b. . . Dipole

42. . . Power clamp module

V _B . . . First high end

V _S . . . First low end

V _SS . . . Ground terminal

V _CC . . . Second low end

V _DD . . . Third high end

H. . . High voltage isolation well region

A, B. . . node

R ₁ , R _2a , R _2b . . . resistance

C ₁ . . . capacitance

Q _1a , Q _1b . . . Power semiconductor component

Claims (10)

An ESD protection circuit for an ultra-high voltage wafer is coupled to a potential conversion circuit and coupled to a ground through the potential conversion circuit. The ESD protection circuit includes: a power clamping module coupled to the first Between the high voltage end and a first low voltage end, for detecting an electrostatic discharge current from the first high voltage end or the first low voltage end, thereby generating a control signal; and at least one switch module, the switch module The first resistor is coupled between the first high voltage terminal and the potential conversion circuit; and a first power semiconductor component coupled in parallel with the first resistor, controlled by the control signal to selectively conduct a first current transmission path, the first high voltage end is electrically connected to the potential conversion circuit through the first current transmission path; wherein a potential difference between the first low voltage end and the ground end is greater than a first voltage threshold. The electrostatic discharge protection circuit of claim 1, wherein the electrostatic discharge protection circuit and the potential conversion circuit are formed in the same ultrahigh voltage wafer via the same semiconductor process. The ESD protection circuit of claim 2, wherein the UHV chip further comprises a gate driver, and the gate driver and the ESD protection circuit are located in the same high voltage isolation well region, and The gate driver is coupled between the first high voltage end and the first low voltage end. The electrostatic discharge protection circuit of claim 3, further comprising: at least one diode coupled between the first high voltage end and the first low voltage end for providing the first low voltage end to a second current transmission path of the first high voltage end; wherein the gate driver has a plurality of transmission interfaces, at least one of the transmission interfaces is coupled to the first high voltage end, and at least one of the transmission interfaces is transmitted The interface is coupled to the first low voltage end. The electrostatic discharge protection circuit of claim 4, wherein the transmission interfaces are respectively coupled to an electrical device, the gate driver drives the electrical device through the transmission interfaces, and the electrical device operates at an operating voltage In the interval, the first voltage threshold is a lower limit of the operating voltage interval. The electrostatic discharge protection circuit of claim 1, wherein the control electrode of the first power semiconductor component is coupled to the power supply clamping module to receive the control signal, and the first electrode of the first power semiconductor component is coupled The first high voltage end, and the second electrode of the first power semiconductor component is coupled to the potential conversion circuit. The electrostatic discharge protection circuit of claim 6, wherein the first power semiconductor component is a power MOS transistor, a bipolar transistor or a 矽-controlled rectifier. The ESD protection circuit of claim 6, wherein the power supply clamping module includes at least a second resistor and a first capacitor, and the second resistor and the first capacitor are coupled to the first high voltage end. Between the first low voltage terminal and the second resistor coupled to the first capacitor through a first node, the power clamping module detects a potential change on the first node, thereby generating the control signal. The electrostatic discharge protection circuit of claim 1, further comprising: at least one second power semiconductor component, wherein a control electrode of the second power semiconductor component is coupled to the first low voltage terminal, and the second power semiconductor component The first electrode is coupled to the first high voltage end, and the second electrode of the second power semiconductor component is coupled to the potential conversion circuit. The electrostatic discharge protection circuit of claim 1, wherein a voltage difference between the first high voltage end and the first low voltage end is less than 30 volts.