TWI434361B - Process monitor circuit element for monitoring manufacturing process - Google Patents

Process monitor circuit element for monitoring manufacturing process Download PDF

Info

Publication number
TWI434361B
TWI434361B TW100121013A TW100121013A TWI434361B TW I434361 B TWI434361 B TW I434361B TW 100121013 A TW100121013 A TW 100121013A TW 100121013 A TW100121013 A TW 100121013A TW I434361 B TWI434361 B TW I434361B
Authority
TW
Taiwan
Prior art keywords
hole chain
end point
hole
chain
metal piece
Prior art date
Application number
TW100121013A
Other languages
Chinese (zh)
Other versions
TW201301418A (en
Inventor
陳冠宇
方柏翔
蔡明汎
李信宏
Original Assignee
矽品精密工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW100121013A priority Critical patent/TWI434361B/en
Priority to CN201110186548.6A priority patent/CN102832202B/en
Publication of TW201301418A publication Critical patent/TW201301418A/en
Application granted granted Critical
Publication of TWI434361B publication Critical patent/TWI434361B/en

Links

Description

用於製程監控之電路元件結構Circuit component structure for process monitoring

本發明係有關於積體電路製程及積體電路測試結構,更具體而言,係關於應用於先進半導體製程中作為測試電路及製程監控之電路元件結構。The present invention relates to an integrated circuit process and an integrated circuit test structure, and more particularly to a circuit component structure for use in an advanced semiconductor process as a test circuit and process monitoring.

由於通訊、網路、及電腦等各式可攜式(Portable)電子產品及其周邊產品輕薄短小之趨勢的日益重要,且該等電子產品係朝多功能及高性能的方向發展,半導體製程上則不斷朝向積體化更高的製程演進,且高密度的構裝結構係為業者追求的目標。如此一來,所製造具有更高密度的半導體晶片的可靠度測試也越形重要。Due to the increasing importance of the variety of portable electronic products and their peripheral products such as communication, networking, and computers, and the development of these electronic products in the direction of versatility and high performance, semiconductor manufacturing processes It is constantly evolving toward a higher process evolution, and the high-density structure is the goal pursued by the industry. As a result, reliability testing of semiconductor wafers with higher density is becoming more important.

為了達到測試半導體晶片可靠度的目的,通常必須於晶片上設置測試電路,以判斷可能導致半導體電路發生缺陷的製程參數或變數。基於測試半導體晶片可靠度所設置的測試電路,可稱為製程監控(PCM-Process Control Monitor),典型上,可藉由於晶圓周圍或角落設置孔鏈(via chain)作為用於製程監控之測試電路。In order to achieve the reliability of testing semiconductor wafers, it is often necessary to place test circuits on the wafer to determine process parameters or variables that may cause defects in the semiconductor circuit. The test circuit based on the reliability of the test semiconductor wafer can be called a PCM-Process Control Monitor. Typically, a via chain is placed around the wafer or at a corner as a test for process monitoring. Circuit.

於習知技術中,孔鏈係經設計成如第1圖所示之矩形外觀,主要用於在直流測試(DC testing)中檢查電阻值變異。但是對於先進的半導體製造技術而言,此類孔鏈拓僕將明顯受到尖端放電效應及射頻耦合或串音效應的影響。舉例而言,第1圖所示之矩形孔鏈具有節省尺寸面積的優點,但是對於高頻信號測試(如交流或射頻信號測試)而言,此類設計存在有如第1圖所示的兩種非理想效應:亦即,若高頻信號通過該直角R,則該高頻信號將放射於空氣中,造成該信號不會通過該等孔鏈;其次,於兩段孔鏈或者傳輸線之間,可能存在有例如寄生電容Cp,造成高頻信號將通過寄生電容Cp,而不會通過該等孔鏈。In the prior art, the pore chain is designed to have a rectangular appearance as shown in Fig. 1, and is mainly used for checking resistance value variation in DC testing. But for advanced semiconductor manufacturing technologies, such a chain of slabs will be significantly affected by tip discharge effects and RF coupling or crosstalk effects. For example, the rectangular hole chain shown in Figure 1 has the advantage of saving size, but for high-frequency signal testing (such as AC or RF signal testing), there are two such designs as shown in Figure 1. Non-ideal effect: that is, if the high-frequency signal passes through the right angle R, the high-frequency signal will be radiated into the air, causing the signal not to pass through the holes; secondly, between the two-stage chain or transmission line, there may be For example, the parasitic capacitance Cp causes the high frequency signal to pass through the parasitic capacitance Cp without passing through the holes.

具體而言,當進行上述交流或射頻測試時,信號將經由該直角R放射至空氣中或者通過該等寄生電容Cp,進而使得對通孔電阻值(via resistance)的評估發生錯誤。Specifically, when the above-described alternating current or radio frequency test is performed, the signal will be radiated into the air via the right angle R or through the parasitic capacitance Cp, thereby causing an error in the evaluation of the via resistance.

因此,如何提出一種可應用於直流測試中,同時能夠於交流或射頻測試中達到降低尖端放電效應及射頻耦合或串音效應所造成之影響,以避免上述種種缺失的電路元件結構,實為目前各界亟欲解決之技術問題。Therefore, how to propose a circuit component structure that can be applied to DC test and can reduce the effect of tip discharge and RF coupling or crosstalk in AC or RF test to avoid the above-mentioned missing circuit component structure. The technical problems that all walks of life want to solve.

鑒於上述習知技術之缺點,本發明提供一種用於製程監控之電路元件結構,包括:具有第一前端點及第一尾端點之第一孔鏈;具有第二前端點及第二尾端點,且與該第一孔鏈之間間隔一第一間隙的第二孔鏈,且該第一前端點與第二前端點相鄰,第一尾端點與第二尾端點相鄰;第一浮動金屬層,係形成於該第一孔鏈與該第二孔鏈之間的該第一間隙中,且並未與該第一孔鏈及該第二孔鏈接觸;以及繞過該第一浮動金屬層連接該第一前端點與第二前端點之第一弧形連接部。In view of the above disadvantages of the prior art, the present invention provides a circuit component structure for process monitoring, comprising: a first hole chain having a first front end point and a first end point; having a second front end point and a second end end And a second hole chain spaced apart from the first hole chain by a first gap, and the first front end point is adjacent to the second front end point, and the first end point is adjacent to the second end point; a first floating metal layer formed in the first gap between the first hole chain and the second hole chain, and not in contact with the first hole chain and the second hole chain; and bypassing the The first floating metal layer connects the first curved connection portion of the first front end point and the second front end point.

於本發明之其他實施形態中,該用於製程監控之電路元件結構復包括第三孔鏈、第二浮動金屬層、以及第二弧形連接部,其中,第三孔鏈具有第三前端點及第三尾端點,且與該第二孔鏈之間間隔一第二間隙,使該第二孔鏈介於該第一孔鏈與第三孔鏈之間,且該第二前端點與第三前端點相鄰,第二尾端點與第三尾端點相鄰;第二浮動金屬層形成於該第二孔鏈與該第三孔鏈之間的該第二間隙中,且並未與該第二孔鏈及該第三孔鏈接觸;且第二弧形連接部繞過該第二浮動金屬層連接該第二尾端點與第三尾端點。In another embodiment of the present invention, the circuit component structure for process monitoring further includes a third hole chain, a second floating metal layer, and a second curved connection portion, wherein the third hole chain has a third front end point And a third end point, and a second gap is spaced from the second hole chain, such that the second hole chain is between the first hole chain and the third hole chain, and the second front end point is a third front end point adjacent to the second end point adjacent to the third end point; a second floating metal layer formed in the second gap between the second hole chain and the third hole chain, and Not contacting the second chain of holes and the chain of third holes; and the second arcuate connection connects the second and third tail ends around the second floating metal layer.

於本發明之又一實施形態中,該第一間隙的寬度等於該第二間隙。而該第一間隙的寬度亦可大於或小於該第二間隙。In still another embodiment of the present invention, the width of the first gap is equal to the second gap. The width of the first gap may also be greater or smaller than the second gap.

相較於習知技術,本發明不但能夠有效地避免或降低孔鏈之間所產生的邊緣寄生電容Cp,避免高頻信號通過寄生電容Cp,同時亦可降低尖端放電及射頻耦合或串音效應所帶來的負面效應,避免信號經由尖端放電而放射至空氣中,提升對通孔電阻值的正確評估,顯著改善對於半導體製程測試之可靠度。Compared with the prior art, the invention can not only effectively avoid or reduce the edge parasitic capacitance Cp generated between the hole chains, avoid the high frequency signal passing through the parasitic capacitance Cp, and also reduce the tip discharge and the radio frequency coupling or crosstalk effect. The negative effect is to prevent the signal from being radiated into the air through the tip discharge, which improves the correct evaluation of the via resistance value and significantly improves the reliability of the semiconductor process test.

以下係藉由特定的具體實施形態說明本發明之技術內容,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點與功效。本發明亦可藉由其他不同的具體實施形態加以施行或應用,本說明書中的各項細節亦可基於不同觀點與應用,在未悖離本發明之精神下進行各種修飾與變更。The other technical advantages of the present invention will be readily understood by those skilled in the art from this disclosure. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes may be made without departing from the spirit and scope of the invention.

須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“第一”、“第二”、“第三”、“第四”、“上方”、“前”、“尾”及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. At the same time, the terms “first”, “second”, “third”, “fourth”, “above”, “before”, “tail” and “one” quoted in this specification are only For the sake of brevity, and not to limit the scope of the invention, the relative relationship changes or adjustments are considered to be within the scope of the invention.

請參照第2圖,係本發明之一例示性實施例之用於製程監控之電路元件結構200之上視圖。如圖所示,該電路元件結構200可包含:第一、第二、第三、第四孔鏈202,204,206,208;第一、第二、第三弧形連接部203,205,207;以及第一、第二、第三浮動金屬層203a,205a,207a。Referring to Figure 2, there is shown a top view of a circuit component structure 200 for process monitoring in accordance with an exemplary embodiment of the present invention. As shown, the circuit component structure 200 can include: first, second, third, and fourth hole chains 202, 204, 206, 208; first, second, and third arcuate connections 203, 205, 207; and first, second, and Three floating metal layers 203a, 205a, 207a.

該第一、第二、第三、第四孔鏈202,204,206,208係彼此平行,例如,該第二孔鏈204在一直線方向上平行於該第一孔鏈202;該第三孔鏈206在一直線方向上平行於該第二孔鏈204;該第四孔鏈208在一直線方向上平行於該第三孔鏈206。The first, second, third, and fourth hole chains 202, 204, 206, 208 are parallel to each other. For example, the second hole chain 204 is parallel to the first hole chain 202 in a linear direction; the third hole chain 206 is in a straight line direction. Parallel to the second hole chain 204; the fourth hole chain 208 is parallel to the third hole chain 206 in a linear direction.

此外,如圖所示,該第一孔鏈202具有第一前端點202a及第一尾端點202b,該第二孔鏈204具有第二前端點204a及第二尾端點204b,且該第二孔鏈204與該第一孔鏈202之間間隔一第一間隙211,且該第一前端點202a與第二前端點204a相鄰,第一尾端點202b與第二尾端點204b相鄰;該第三孔鏈206具有第三前端點206a及第三尾端點206b,且該第三孔鏈206與該第二孔鏈204之間間隔一第二間隙212,使該第二孔鏈204介於該第一孔鏈202與第三孔鏈206之間,且該第二前端點204a與第三前端點206a相鄰,第二尾端點204b與第三尾端點206b相鄰;該第四孔鏈208具有第四前端點208a及第四尾端點208b,且該第四孔鏈208與該第三孔鏈206之間間隔一第三間隙213,使該第三孔鏈206介於該第二孔鏈204與第四孔鏈208之間,且該第三前端點206a與第四前端點208a相鄰,第三尾端點206b與第四尾端點208b相鄰。In addition, as shown, the first hole chain 202 has a first front end point 202a and a first tail end point 202b, and the second hole chain 204 has a second front end point 204a and a second tail end point 204b, and the first A first gap 211 is defined between the two-hole chain 204 and the first hole chain 202, and the first front end point 202a is adjacent to the second front end point 204a, and the first tail end point 202b is opposite to the second tail end point 204b. The third hole chain 206 has a third front end point 206a and a third end end point 206b, and a second gap 212 is spaced between the third hole chain 206 and the second hole chain 204 to make the second hole The chain 204 is interposed between the first hole chain 202 and the third hole chain 206, and the second front end point 204a is adjacent to the third front end point 206a, and the second tail end point 204b is adjacent to the third tail end point 206b. The fourth hole chain 208 has a fourth front end point 208a and a fourth end end point 208b, and the fourth hole chain 208 and the third hole chain 206 are separated by a third gap 213, so that the third hole chain 206 is between the second hole chain 204 and the fourth hole chain 208, and the third front end point 206a is adjacent to the fourth front end point 208a, and the third end end point 206b is adjacent to the fourth tail end point 208b.

本發明用於製程監控之電路元件結構包括之第一浮動金屬層203a係形成於該第一間隙211中,亦即,可形成於該第一孔鏈202與該第二孔鏈204之間,且並未與該第一孔鏈202及該第二孔鏈204相接觸。The circuit component structure for the process monitoring includes a first floating metal layer 203a formed in the first gap 211, that is, between the first hole chain 202 and the second hole chain 204, And not in contact with the first hole chain 202 and the second hole chain 204.

該第一弧形連接部203係由圓弧形金屬構成,用以將該第一孔鏈202的第一前端點202a電性連接至該第二孔鏈204的第二前端點204a,並且繞過該第一浮動金屬層203a。同樣地,如圖所示,該等第二、第三及第四孔鏈204,206,208彼此之間亦可間隔以適當的間隙,且兩個相鄰的孔鏈之間的間隙無須等於其他兩個相鄰孔鏈之間的間隙的必要。The first curved connecting portion 203 is formed of a circular arc metal for electrically connecting the first front end point 202a of the first hole chain 202 to the second front end point 204a of the second hole chain 204, and is wound around The first floating metal layer 203a passes. Similarly, as shown, the second, third, and fourth hole chains 204, 206, 208 may be spaced apart from each other by a suitable gap, and the gap between two adjacent hole chains need not be equal to the other two phases. Necessary for the gap between adjacent hole chains.

舉例而言,該第二孔鏈204與該第三孔鏈206之間亦可間隔一第二間隙212,且該第二孔鏈204與該第三孔鏈206之間的第二間隙212可能不同於該第一孔鏈202與該第二孔鏈204之間的第一間隙211。該第二浮動金屬層205a係形成於該第二間隙212中,亦即,可形成於該第二孔鏈204與該第三孔鏈206之間,且並未與該第二孔鏈204與該第三孔鏈206之間相接觸。該第二弧形連接部205同樣係由圓弧形金屬構成,其形狀可不同於該第一弧形連接部203,用以將該第二孔鏈204的第二尾端點204b電性連接至該第三孔鏈206的第三尾端點206b,並且繞過該第二浮動金屬層205a。For example, a second gap 212 may be spaced between the second hole chain 204 and the third hole chain 206, and a second gap 212 between the second hole chain 204 and the third hole chain 206 may be Different from the first gap 211 between the first hole chain 202 and the second hole chain 204. The second floating metal layer 205a is formed in the second gap 212, that is, between the second hole chain 204 and the third hole chain 206, and is not associated with the second hole chain 204. The third chain of holes 206 are in contact with each other. The second curved connecting portion 205 is also formed of a circular arc metal, and the shape thereof may be different from the first curved connecting portion 203 for electrically connecting the second end point 204b of the second hole chain 204. To the third tail end 206b of the third hole chain 206, and bypassing the second floating metal layer 205a.

同樣地,該第三弧形連接部207可用以將該第三孔鏈206的第三前端點206a電性連接至該第四孔鏈208的第四前端點208a,並且繞過該第三浮動金屬層207a。Similarly, the third curved connecting portion 207 can be used to electrically connect the third front end point 206a of the third hole chain 206 to the fourth front end point 208a of the fourth hole chain 208, and bypass the third floating Metal layer 207a.

本實施例所欲強調的是,該等弧形連接部的形狀並不限定,僅需成型為具有圓弧形的邊緣,主要目的在於避免或降低在進行交流或射頻測試時,信號經由太過尖銳的邊緣(如第1圖之直角R)放射至空氣中。It should be emphasized in this embodiment that the shape of the arcuate connecting portions is not limited, and only needs to be formed into a circular arc-shaped edge, and the main purpose is to avoid or reduce the signal passing through when conducting AC or RF testing. Sharp edges (such as the right angle R of Figure 1) are radiated into the air.

此外,於本發明之實施態樣中,可進一步包含輸入接地墊片201及輸出接地墊片209,其係分別用以作為射頻(RF)測試輸入信號的接地端及作為射頻(RF)測試輸出信號的接地端。該第一孔鏈202的第一尾端點202b可用以作為射頻(RF)測試輸入信號的輸入端,而該第四孔鏈208具有第四尾端點208b則用以作為射頻(RF)測試輸出信號的輸出端。In addition, in the embodiment of the present invention, the input ground pad 201 and the output ground pad 209 may be further included as a ground end of the radio frequency (RF) test input signal and as a radio frequency (RF) test output. The ground of the signal. The first tail end 202b of the first hole chain 202 can be used as an input of a radio frequency (RF) test input signal, and the fourth hole chain 208 has a fourth tail end point 208b for use as a radio frequency (RF) test. The output of the output signal.

復請參閱第3圖,係以孔鏈之剖視圖說明本發明之孔鏈組成和結構。以第一孔鏈202舉例說明之,該第一孔鏈202包括複數第一上層金屬片2020、第一下層金屬片2021及第一通孔2022,其中,各該第一上層金屬片2020與第一下層金屬片2021彼此錯位,並藉由各該第一通孔2022電性連接該第一上層金屬片2020與第一下層金屬片2021,以構成串聯結構。如圖所示,該第一下層金屬片2021及第一通孔2022係形成於介電層221中,該第一下層金屬片2021可在形成導電線路的同時藉由電鍍法形成,該第一通孔2022則可透過圖案化製程、以及如電鍍或濺渡的方式製作。當然,上述之浮動金屬層和弧形連接部亦可依該習知技術形成。Referring to Figure 3, the composition and structure of the pore chain of the present invention will be described in a cross-sectional view of the pore chain. Illustrated by the first hole chain 202, the first hole chain 202 includes a plurality of first upper metal pieces 2020, a first lower metal piece 2021, and a first through hole 2022, wherein each of the first upper metal pieces 2020 and The first lower metal sheets 2021 are offset from each other, and the first upper metal sheet 2020 and the first lower metal sheet 2021 are electrically connected to each other through the first through holes 2022 to form a series structure. As shown in the figure, the first lower metal piece 2021 and the first through hole 2022 are formed in the dielectric layer 221, and the first lower metal piece 2021 can be formed by electroplating while forming a conductive line. The first via 2022 can be fabricated through a patterning process, such as electroplating or sputtering. Of course, the floating metal layer and the curved connecting portion described above can also be formed according to the prior art.

同樣地,該第二孔鏈包括複數第二上層金屬片、第二下層金屬片及第二通孔,其中,各該第二上層金屬片與第二下層金屬片彼此錯位,並藉由各該第二通孔電性連接該第二上層金屬片與第二下層金屬片,以構成串聯結構。該第三孔鏈包括複數第三上層金屬片、第三下層金屬片及第三通孔,其中,各該第三上層金屬片與第三下層金屬片彼此錯位,並藉由各該第三通孔電性連接該第三上層金屬片與第三下層金屬片,以構成串聯結構(未圖示)。應可瞭解的是,各該孔鏈之上層金屬片可同時形成、通孔亦可同時形成以及下層金屬片亦可同時形成。Similarly, the second hole chain includes a plurality of second upper metal pieces, a second lower metal piece, and a second through hole, wherein each of the second upper metal piece and the second lower metal piece are misaligned with each other The second through hole is electrically connected to the second upper metal piece and the second lower metal piece to form a series structure. The third hole chain includes a plurality of third upper metal pieces, a third lower metal piece, and a third through hole, wherein each of the third upper metal piece and the third lower metal piece are misaligned with each other, and each of the third through The hole electrically connects the third upper metal piece and the third lower metal piece to form a series structure (not shown). It should be understood that the metal sheets on the upper layer of each of the pore chains may be simultaneously formed, the through holes may be simultaneously formed, and the lower metal sheets may be simultaneously formed.

請參閱第4A及4B圖,係示意地描繪本發明實施例之電路元件結構200沿著第2圖剖面線2--2之剖面圖。Referring to Figures 4A and 4B, a cross-sectional view of the circuit component structure 200 of the embodiment of the present invention taken along line 2-2 of Figure 2 is schematically depicted.

如第4A圖所示,該第一、第二、第三、第四孔鏈202,204,206,208皆形成於基板220(如矽基板或印刷電路板等)上,且分別係藉由通孔電性連接上下層金屬片。例如,該第一孔鏈202係由第一通孔2022電性連接該第一上層金屬片2020與第一下層金屬片2021,以構成串聯結構。該第二孔鏈204係由第二通孔2042電性連接第二上層金屬片2040與第二下層金屬片2041,該第三孔鏈206係由第三通孔2062電性連接第三上層金屬片2060與第三下層金屬片2061,及該第四孔鏈208係由第四通孔2082電性連接第四上層金屬片2080與第四下層金屬片2081。As shown in FIG. 4A, the first, second, third, and fourth hole chains 202, 204, 206, and 208 are formed on the substrate 220 (such as a germanium substrate or a printed circuit board), and are electrically connected through the through holes respectively. Lower metal sheet. For example, the first hole chain 202 is electrically connected to the first upper metal piece 2020 and the first lower metal piece 2021 by the first through hole 2022 to form a series structure. The second via link 204 is electrically connected to the second upper metal piece 2040 and the second lower metal piece 2041 by the second through hole 2042. The third hole chain 206 is electrically connected to the third upper layer metal by the third through hole 2062. The sheet 2060 and the third lower metal piece 2061 and the fourth hole chain 208 are electrically connected to the fourth upper metal piece 2080 and the fourth lower metal piece 2081 by the fourth through hole 2082.

該第一孔鏈202與該第二孔鏈204之間、該第二孔鏈204與該第三孔鏈206之間、及該第三孔鏈206與該第四孔鏈208之間皆存在間隙,各個間隙的大小不一定相同,依據製程或使用者需求而定。Between the first hole chain 202 and the second hole chain 204, between the second hole chain 204 and the third hole chain 206, and between the third hole chain 206 and the fourth hole chain 208 The gap, the size of each gap is not necessarily the same, depending on the process or user needs.

此外,該第一孔鏈202與該第二孔鏈204之間設置有第一浮動金屬層203a,且並未與該第一孔鏈202及該第二孔鏈204相接觸。同樣地,該第二孔鏈204與該第三孔鏈206之間、該第三孔鏈206與該第四孔鏈208之間亦可分別設置有第二浮動金屬層205a及第三浮動金屬層207a。In addition, a first floating metal layer 203a is disposed between the first hole chain 202 and the second hole chain 204, and is not in contact with the first hole chain 202 and the second hole chain 204. Similarly, a second floating metal layer 205a and a third floating metal may be disposed between the second hole chain 204 and the third hole chain 206, and between the third hole chain 206 and the fourth hole chain 208, respectively. Layer 207a.

更具體而言,於第4A圖所示之架構中,第一浮動金屬層203a係設置於該第一下層金屬片2021和第二下層金屬片2041之間。同樣地,第二浮動金屬層205a亦係設置於該第二下層金屬片2041和第三下層金屬片2061之間,其他情況可據此類推。More specifically, in the structure shown in FIG. 4A, the first floating metal layer 203a is disposed between the first lower metal piece 2021 and the second lower metal piece 2041. Similarly, the second floating metal layer 205a is also disposed between the second lower metal piece 2041 and the third lower metal piece 2061, and other conditions may be derived therefrom.

或者如第4B圖,第一浮動金屬層203a係設置於該第一上層金屬片2020和第二上層金屬片2040之間。同樣地,第二浮動金屬層205a亦係設置於該第二上層金屬片2040和第三上層金屬片2060之間。Or as shown in FIG. 4B, the first floating metal layer 203a is disposed between the first upper metal piece 2020 and the second upper metal piece 2040. Similarly, the second floating metal layer 205a is also disposed between the second upper metal piece 2040 and the third upper metal piece 2060.

本實施例所欲強調的是,該等浮動金屬層的設置位置並不限定,僅需設置於相鄰的兩個孔鏈之間,主要目的在於避免或降低相鄰的兩個孔鏈之間的邊緣寄生電容Cp於交流或射頻測試中降低射頻耦合及造成串音效應。It is emphasized in this embodiment that the arrangement positions of the floating metal layers are not limited, and only need to be disposed between two adjacent hole chains, and the main purpose is to avoid or reduce the relationship between the adjacent two hole chains. The edge parasitic capacitance Cp reduces RF coupling and causes crosstalk effects in AC or RF tests.

此外,應留意到,本發明上述實施態樣中僅僅以上下兩層作為說明範例,然而,本發明並不限定於此,亦即,本發明上述各實施形態皆可類推並應用至具有複數層之情況。In addition, it should be noted that in the foregoing embodiments of the present invention, only the above two layers are used as an illustrative example. However, the present invention is not limited thereto, that is, the above embodiments of the present invention can be analogized and applied to have multiple layers. The situation.

綜上所述,本發明之用於製程監控之電路元件結構能夠於交流或射頻測試中降低尖端放電及射頻耦合或串音效應,藉由避免高頻信號通過寄生電容Cp,及避免信號經由尖端放電而放射至空氣中,提升對通孔電阻值的正確評估,同時避免發生串音。再者,相較於習知的矩形電路元件結構,本發明之用於製程監控之電路元件結構能夠使得於交流或射頻測試中對通孔電阻值的評估更加正確,俾供使用者判斷可能導致半導體電路發生缺陷的製程參數或變數,同時提升半導體裝置及製程的可靠度。In summary, the circuit component structure for process monitoring of the present invention can reduce tip discharge and RF coupling or crosstalk effects in AC or RF testing by avoiding high frequency signals passing through parasitic capacitance Cp and avoiding signals passing through the tip. Discharge and radiate into the air to improve the correct evaluation of the through-hole resistance value while avoiding crosstalk. Moreover, compared with the conventional rectangular circuit component structure, the circuit component structure for process monitoring of the present invention can make the evaluation of the via resistance value more correct in the AC or RF test, which may be caused by the user's judgment. A process parameter or variable in which a semiconductor circuit is defective, while improving the reliability of the semiconductor device and the process.

上述實施形態僅例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施形態進行修飾與改變。因此,本發明之權利保護範圍,應如後述之申請專利範圍所列。The above embodiments are merely illustrative of the principles and effects of the invention and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the claims described below.

200...電路元件結構200. . . Circuit component structure

201...輸入接地墊片201. . . Input grounding gasket

202...第一孔鏈202. . . First hole chain

202a...第一前端點202a. . . First front end point

202b...第一尾端點202b. . . First end

203...第一弧形連接部203. . . First curved joint

203a...第一浮動金屬層203a. . . First floating metal layer

204...第二孔鏈204. . . Second chain

204a...第二前端點204a. . . Second front end point

204b...第二尾端點204b. . . Second tail endpoint

205...第二弧形連接部205. . . Second curved joint

205a...第二浮動金屬層205a. . . Second floating metal layer

206...第三孔鏈206. . . Third hole chain

206a...第三前端點206a. . . Third front end point

206b...第三尾端點206b. . . Third end

207...第三弧形連接部207. . . Third curved joint

207a...第三浮動金屬層207a. . . Third floating metal layer

208...第四孔鏈208. . . Fourth hole chain

208a...第四前端點208a. . . Fourth front end point

208b...第四尾端點208b. . . Fourth tail

209...輸出接地墊片209. . . Output grounding gasket

211...第一間隙211. . . First gap

212...第二間隙212. . . Second gap

213...第三間隙213. . . Third gap

220...基板220. . . Substrate

221...介電層221. . . Dielectric layer

2020...第一上層金屬片2020. . . First upper metal sheet

2021...第一下層金屬片2021. . . First lower metal sheet

2022...第一通孔2022. . . First through hole

2040...第二上層金屬片2040. . . Second upper metal sheet

2041...第二下層金屬片2041. . . Second lower metal sheet

2042...第二通孔2042. . . Second through hole

2060...第三上層金屬片2060. . . Third upper metal sheet

2061...第三下層金屬片2061. . . Third underlying metal sheet

2062...第三通孔2062. . . Third through hole

2080...第四上層金屬片2080. . . Fourth upper metal sheet

2081...第四下層金屬片2081. . . Fourth lower metal sheet

2082...第四通孔2082. . . Fourth through hole

2--2...剖面線2--2. . . Section line

R...直角R. . . Right angle

Cp...寄生電容Cp. . . Parasitic capacitance

第1圖係示意地描繪習知半導體製程中作為測試電路之矩形孔鏈之上視圖;1 is a schematic view of a top view of a rectangular chain of holes as a test circuit in a conventional semiconductor process;

第2圖係示意地描繪本發明實施例之用於製程監控之電路元件結構之上視圖;2 is a top view schematically showing the structure of a circuit component for process monitoring according to an embodiment of the present invention;

第3圖係說明本發明之孔鏈組成和結構之剖視圖;以及Figure 3 is a cross-sectional view showing the composition and structure of the pore chain of the present invention;

第4A及4B圖係示意地描繪本發明實施例之用於製程監控之電路元件結構沿著剖面線2--2之剖面圖。4A and 4B are schematic cross-sectional views showing the structure of a circuit component for process monitoring according to an embodiment of the present invention taken along line 2-2.

200...電路元件結構200. . . Circuit component structure

201...輸入接地墊片201. . . Input grounding gasket

202...第一孔鏈202. . . First hole chain

202a...第一前端點202a. . . First front end point

202b...第一尾端點202b. . . First end

203...第一弧形連接部203. . . First curved joint

203a...第一浮動金屬層203a. . . First floating metal layer

204...第二孔鏈204. . . Second chain

204a...第二前端點204a. . . Second front end point

204b...第二尾端點204b. . . Second tail endpoint

205...第二弧形連接部205. . . Second curved joint

205a...第二浮動金屬層205a. . . Second floating metal layer

206...第三孔鏈206. . . Third hole chain

206a...第三前端點206a. . . Third front end point

206b...第三尾端點206b. . . Third end

207...第三弧形連接部207. . . Third curved joint

207a...第三浮動金屬層207a. . . Third floating metal layer

208...第四孔鏈208. . . Fourth hole chain

208a...第四前端點208a. . . Fourth front end point

208b...第四尾端點208b. . . Fourth tail

209...輸出接地墊片209. . . Output grounding gasket

211...第一間隙211. . . First gap

212...第二間隙212. . . Second gap

213...第三間隙213. . . Third gap

2--2...剖面線2--2. . . Section line

Claims (11)

一種用於製程監控之電路元件結構,包括:第一孔鏈,係具有第一前端點及第一尾端點;第二孔鏈,係具有第二前端點及第二尾端點,且與該第一孔鏈之間間隔一第一間隙,且該第一前端點與第二前端點相鄰,第一尾端點與第二尾端點相鄰;第一浮動金屬層,係形成於該第一孔鏈與該第二孔鏈之間的該第一間隙中,且並未與該第一孔鏈及該第二孔鏈接觸;以及第一弧形連接部,係繞過該第一浮動金屬層連接該第一前端點與第二前端點。A circuit component structure for process monitoring, comprising: a first hole chain having a first front end point and a first tail end point; and a second hole chain having a second front end point and a second end point, and The first hole chain is separated by a first gap, and the first front end point is adjacent to the second front end point, and the first tail end point is adjacent to the second tail end point; the first floating metal layer is formed on the first floating metal layer The first gap between the first hole chain and the second hole chain is not in contact with the first hole chain and the second hole chain; and the first curved connection portion bypasses the first A floating metal layer connects the first front end point and the second front end point. 如申請專利範圍第1項所述之用於製程監控之電路元件結構,其中,該第二孔鏈平行於該第一孔鏈。The circuit component structure for process monitoring according to claim 1, wherein the second hole chain is parallel to the first hole chain. 如申請專利範圍第2項所述之用於製程監控之電路元件結構,其中,該第二孔鏈在一直線方向上平行於該第一孔鏈。The circuit component structure for process monitoring according to claim 2, wherein the second hole chain is parallel to the first hole chain in a linear direction. 如申請專利範圍第1項所述之用於製程監控之電路元件結構,其中,該第一孔鏈包括複數第一上層金屬片、第一下層金屬片及第一通孔,其中,各該第一上層金屬片與第一下層金屬片彼此錯位,並藉由各該第一通孔電性連接該第一上層金屬片與第一下層金屬片,以構成串聯結構。The circuit component structure for process monitoring according to claim 1, wherein the first hole chain comprises a plurality of first upper metal pieces, a first lower metal piece and a first through hole, wherein each of the holes The first upper metal piece and the first lower metal piece are offset from each other, and the first upper metal piece and the first lower metal piece are electrically connected by the first through holes to form a series structure. 如申請專利範圍第1項所述之用於製程監控之電路元件結構,其中,該第二孔鏈包括複數第二上層金屬片、第二下層金屬片及第二通孔,其中,各該第二上層金屬片與第二下層金屬片彼此錯位,並藉由各該第二通孔電性連接該第二上層金屬片與第二下層金屬片,以構成串聯結構。The circuit component structure for process monitoring according to claim 1, wherein the second hole chain comprises a plurality of second upper metal pieces, a second lower metal piece and a second through hole, wherein each of the The second upper metal piece and the second lower metal piece are offset from each other, and the second upper metal piece and the second lower metal piece are electrically connected by the second through holes to form a series structure. 如申請專利範圍第1項所述之用於製程監控之電路元件結構,復包括:第三孔鏈,係具有第三前端點及第三尾端點,且與該第二孔鏈之間間隔一第二間隙,使該第二孔鏈介於該第一孔鏈與第三孔鏈之間,且該第二前端點與第三前端點相鄰,第二尾端點與第三尾端點相鄰;第二浮動金屬層,係形成於該第二孔鏈與該第三孔鏈之間的該第二間隙中,且並未與該第二孔鏈及該第三孔鏈接觸;以及第二弧形連接部,係繞過該第二浮動金屬層連接該第二尾端點與第三尾端點。The circuit component structure for process monitoring according to claim 1, wherein the third hole chain has a third front end point and a third end end point, and is spaced from the second hole chain. a second gap, the second hole chain is between the first hole chain and the third hole chain, and the second front end point is adjacent to the third front end point, the second end point and the third end end a second floating metal layer is formed in the second gap between the second hole chain and the third hole chain, and is not in contact with the second hole chain and the third hole chain; And a second curved connecting portion connecting the second tail metal layer and the third tail end point by bypassing the second floating metal layer. 如申請專利範圍第6項所述之用於製程監控之電路元件結構,其中,該第三孔鏈平行於該第二孔鏈。The circuit component structure for process monitoring according to claim 6, wherein the third hole chain is parallel to the second hole chain. 如申請專利範圍第7項所述之用於製程監控之電路元件結構,其中,該第三孔鏈在一直線方向上平行於該第二孔鏈。The circuit component structure for process monitoring according to claim 7, wherein the third hole chain is parallel to the second hole chain in a linear direction. 如申請專利範圍第6項所述之用於製程監控之電路元件結構,其中,該第三孔鏈包括複數第三上層金屬片、第三下層金屬片及第三通孔,其中,各該第三上層金屬片與第三下層金屬片彼此錯位,並藉由各該第三通孔電性連接該第三上層金屬片與第三下層金屬片,以構成串聯結構。The circuit component structure for process monitoring according to claim 6, wherein the third hole chain comprises a plurality of third upper metal pieces, a third lower metal piece and a third through hole, wherein each of the The third upper metal piece and the third lower metal piece are misaligned with each other, and the third upper metal piece and the third lower metal piece are electrically connected by the third through holes to form a series structure. 如申請專利範圍第6項所述之用於製程監控之電路元件結構,其中,該第一間隙的寬度等於該第二間隙。The circuit component structure for process monitoring according to claim 6, wherein the width of the first gap is equal to the second gap. 如申請專利範圍第6項所述之用於製程監控之電路元件結構,其中,該第一間隙的寬度大於或小於該第二間隙。The circuit component structure for process monitoring according to claim 6, wherein the width of the first gap is greater or smaller than the second gap.
TW100121013A 2011-06-16 2011-06-16 Process monitor circuit element for monitoring manufacturing process TWI434361B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW100121013A TWI434361B (en) 2011-06-16 2011-06-16 Process monitor circuit element for monitoring manufacturing process
CN201110186548.6A CN102832202B (en) 2011-06-16 2011-06-30 Circuit assembly structure for process monitoring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW100121013A TWI434361B (en) 2011-06-16 2011-06-16 Process monitor circuit element for monitoring manufacturing process

Publications (2)

Publication Number Publication Date
TW201301418A TW201301418A (en) 2013-01-01
TWI434361B true TWI434361B (en) 2014-04-11

Family

ID=47335266

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100121013A TWI434361B (en) 2011-06-16 2011-06-16 Process monitor circuit element for monitoring manufacturing process

Country Status (2)

Country Link
CN (1) CN102832202B (en)
TW (1) TWI434361B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113224035B (en) * 2021-01-26 2024-03-15 上海华力微电子有限公司 Semiconductor test structure and test method

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6566885B1 (en) * 1999-12-14 2003-05-20 Kla-Tencor Multiple directional scans of test structures on semiconductor integrated circuits
US6362634B1 (en) * 2000-01-14 2002-03-26 Advanced Micro Devices, Inc. Integrated defect monitor structures for conductive features on a semiconductor topography and method of use
US7317203B2 (en) * 2005-07-25 2008-01-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method and monitor structure for detecting and locating IC wiring defects
CN201017877Y (en) * 2007-03-06 2008-02-06 中芯国际集成电路制造(上海)有限公司 Staged thru hole chain structure easy to test reliability

Also Published As

Publication number Publication date
CN102832202A (en) 2012-12-19
TW201301418A (en) 2013-01-01
CN102832202B (en) 2016-02-24

Similar Documents

Publication Publication Date Title
JP5199071B2 (en) Via structure with impedance adjustment
US8586873B2 (en) Test point design for a high speed bus
JP2007013109A (en) Communication circuit module
TWI415560B (en) Structure and method for reducing em radiation, and electric object and manufacture method thereof
TWI423753B (en) Multilayer wiring board
TWI375499B (en) Improvement method for ebg structures and multi-layer board applying the same
US8237055B2 (en) Circuit board
JP2008271421A5 (en)
TWI434361B (en) Process monitor circuit element for monitoring manufacturing process
US9756721B2 (en) Multilayer laminated substrate structure
US10129974B2 (en) Multi-layer circuit structure
US20090071702A1 (en) Circuit board
TWI399138B (en) Printed circuit board
TWI447887B (en) Circuit element via chain structure and layout method thereof
JP5228925B2 (en) High frequency contactor
US9526165B2 (en) Multilayer circuit substrate
TWI484693B (en) Digital electronic device
CN107222970A (en) multilayer circuit structure
TWI489922B (en) Multilayer circuit boards
TWI361028B (en)
TW200727760A (en) Circuit substrate and method of fabricating the same
TW202004205A (en) Circuit board for transmitting high speed signal and for said signal to be detected
TWI650559B (en) Circuit structure of adjusting power signal impedance and semiconductor test interface system thereof
US11191152B2 (en) Printed circuit board signal layer testing
CN206775819U (en) A kind of printed circuit board (PCB)