TWI434162B - Voltage regulation system and method - Google Patents

Description

Voltage adjustment system and method

Various specific embodiments are directed to electronic systems.

Electronic systems (e.g., microprocessors) that can use digital and/or analog circuits typically operate when powered at a supply voltage. Many electronic systems are designed to operate from a regulated supply voltage to provide a voltage within a voltage range suitable for the circuit.

The voltage regulator can typically include a device having an input coupled to a power supply and an output coupled to a load. In operation, the voltage regulator can extract energy from the power source and deliver the energy to the load with a regulated voltage. Typically, the voltage of the power supply and the voltage of the load may be substantially independent, and the voltages may be substantially different. In normal operation, the voltage regulator operates at a voltage within a rated voltage operating range to supply current to the load. Some voltage regulators may be specified to adjust the voltage supplied to the load to within a tolerance of, for example, 1%, 5%, or 10% of the rated voltage.

The rated voltage supplied by the regulator to the load may depend on the type of load being supplied. In some digital systems, the voltage regulator can supply a nominal voltage of, for example, 3.3 volts or 5 volts. In some analog systems, the voltage regulator can supply a nominal voltage of, for example, -5 volts, 2.5 volts, 5 volts, or 12 volts. Many other permissible values and/or voltage ratings are still possible.

The voltage regulator can have a variety of designs. For example, some switched DC converters can generate an adjusted output voltage by quickly storing and releasing energy into an energy storage component (such as an inductor, capacitor). Some examples of switched voltage regulator topologies include charge pump, boost, buck, step-down, flyback, SEPIC (single-ended primary inductor converter), Cuk (Cook) and forward converter. Another type of voltage regulator is a linear regulator. Examples of linear regulators can include series bypass and shunt regulators.

The method and apparatus of the present invention can be provided for multiple input voltage adjustments, wherein when the difference between the input voltages falls within a voltage range, the current supplied to an output node is shunted according to its respective input voltage to a plurality of voltage regulators. between. When the difference in input voltage falls outside of this voltage range, then the current flowing to the output node is substantially supplied through the voltage regulator having the highest input voltage. In some embodiments, the voltage range can be (at least in part) determined by a transistor gate to source threshold voltage characteristic. In one example, a dual input voltage regulator system in a combined smart card supplies current from a contact and/or non-contact (eg, inductively coupled) power supply based on a relative voltage between the respective input voltages.

Some embodiments may provide one or several advantages. For example, some embodiments may substantially mitigate potential operational errors that may result from transient power conditions. In this way, robust performance can be maintained during the relative intensity transfer of the available power source. In some embodiments, smoothing of current shunting between regulators of individual independent power inputs can substantially reduce or prevent, for example, data errors or other faults. A single transistor voltage drop architecture provides low dropout regulation capability without substantially increasing the transistor volume. Some embodiments may substantially prevent reverse current from passing through a regulator connected to the inactive power input. In addition, low power operation can be achieved over a wide range of operating conditions by substantially reducing or preventing reverse (e.g., feedback) current through regulator transistors that are not selected or coupled to the active power source. In some embodiments, performance can be enhanced by selectively extracting power from the highest available power source.

The details of one or more specific embodiments are set forth in the accompanying drawings and the description below. Other functions, objectives, and advantages will be apparent from the description and illustration and claims.

1 shows an example system 100 that includes a dual input voltage regulator (DIVR) 105 configured to receive power from multiple (eg, independent) power sources. The DIVR 105 receives the input voltages V1, V2 from the input nodes 110, 115, respectively, and supplies an output current Iout to a device (e.g., processing system 120) at an output voltage 125 at an adjustment voltage Vout. In one embodiment, when V1 and V2 are within respective circuit dependent windows, DIVR 105 extracts current from both input nodes 110, 115 to supply Iout. When the difference between V1 and V2 falls outside the window, the DIVR 105 extracts current from the input node 110 or 105 having the highest voltage input V1 or V2, respectively, to supply Iout. As such, when, for example, the input voltages V1, V2 are independently changed (eg, turned on, off, boosted, attenuated), the DIVR 105 can supply an output voltage Vout at the output node 125 and substantially reduce or eliminate transient effects.

In some embodiments, DIVR 105 can include a transistor that operates to substantially block reverse current from one of output node 125 to one of input nodes 110, 115. For example, when the difference between V1 and V2 falls outside the circuit dependent window, the reverse current flowing to the input nodes 110, 115 having the lowest voltage inputs V1, V2 can be substantially blocked.

System 100 receives power from external sources 130, 135 coupled to system 100 through transmission interfaces 140, 145, respectively. In the depicted example, system 100 receives power and/or data from sources 130, 135. In some embodiments, one or both of the interfaces 140, 145 can convert the received data signals into power signals to supply operational power to the processing system 120. In some examples, any of the interfaces 140, 145 can include separate and integrated power and data to be coupled to the corresponding sources 130, 135.

In the depicted example, source 130 includes a power source 150 and a data interface 155, and source 135 includes a power source 160 and a data interface 165. Power sources 150, 160 can transmit power to system 100 through interfaces 140, 145, respectively. The data interfaces 155, 165 can communicate with the system 100 by transmitting and/or receiving data through the interfaces 140, 145, respectively.

In various embodiments, the interfaces 140, 145 can be configured to receive wired signals and/or wireless signals.

In some examples, system 100 can receive power and data from a cable interface, such as via a universal serial bus (USB) interface. In some examples, processing system 120 can communicate with either or both of sources 130, 135 through corresponding interfaces 140, 145.

Some specific embodiments can be integrated into a smart card. In some embodiments, the smart card transmits and/or receives data by communicating with a suitable card reader system. Some cards, commonly referred to as contact cards, communicate with the card reader system as they are directly electronically connected to the card reader system. The data signals communicated through such direct contact interfaces may conform to specific communication protocols, such as ISO/IEC 7816 or ISO/IEC 7810 (ISO refers to the International Organization for Standardization; IEC refers to the International Electrotechnical Commission). Other cards are called contactless cards and can communicate wirelessly with the card reader system using RF (radio frequency) signals. The RF data signals used for contactless cards can conform to specific communication protocols such as ISO/SEC 14443 or ISO/IEC 15693.

Various types of power supplies are available to operate the electronic power of the circuits in the integrated circuit card. For example, some cards are powered by integrated power storage devices such as batteries or large value capacitors. The power supply can be powered by direct electronic contact of the contact card with a terminal connected to a power source, such as a power supply integrated into the card reader system. The contactless smart card can be powered by capturing and storing radio frequency (RF) energy transmitted by the card reader system.

Hybrid smart cards (sometimes referred to as combo cards) can exchange data either by direct electronic contact or by RF coupling to a card reader system.

In an exemplary embodiment, interface 140 can be a contact interface and interface 145 can be a wireless interface. The contact interface 140 can receive power from a primary battery, primary battery, and/or public power. The wireless interface 145 can receive power by, for example, rectifying the received radio frequency (RF) signal to enable energy to be stored in the battery or capacitor.

The voltages provided by the power supplies 150, 160 can be varied independently. For example, V1 may be supplied by a relatively fixed voltage source in one of the contact card reader devices, and V1 may appear to be on when contacting interface 140 and off when interrupting contact interface 140. V2 can be supplied by electromagnetic coupling to a contactless card reader device. In this example, the V2 visible antenna is oriented relative to the magnetic field, the distance from the emitter, the presence or absence of a magnetically distorted object (such as a metal and/or a distorted medium object), signal reflection, humidity, and the like. Change. Thus, V2 can vary between less than, substantially close to, or greater than V1.

Thus, the difference between V1 and V2 can sometimes be within the circuit dependent window (eg 0.2 V, 0.3 V, 0.4 V, 0.5 V, 0.6 V, 0.7 V, 0.8 V, 0.9 V, 1 V, etc.). Sometimes the difference between V1 and V2 can be outside the circuit dependent window. In one embodiment, DIVR 105 draws power from both power sources 150, 160 when V1 and V2 are within the window. When V1 and V2 are outside the window, the DIVR 105 substantially extracts power from the power source 150 or 160 that supplies the highest voltage V1 or V2, respectively.

In an illustrative example, interface 140 receives battery power and interface 145 receives RF power. V1 is initially invariant and V2 is initially unpowered, leaving (V1-V2) outside the circuit dependent window. The DIVR 105 essentially draws current from the input node 110 to supply Iout. Moreover, substantially no current passes through the input node 115. As the RF field strength increases (as when the interface 145 is substantially moved closer to the RF source 135), V2 increases and (V1-V2) decreases accordingly. When (V1-V2) is within the window, DIVR 105 uses current supply Iout from both input nodes 110, 115. In some embodiments, the amount of current drawn from the input nodes 110, 115 is directly associated with V1, V2. As the RF magnetic field strength continues to increase, V2 can become greater than V1 leaving (V1-V2) outside the window. When (V1-V2) is outside the window and V2 > V1, DIVR 105 essentially draws current from input node 151. A current conversion example relating to the difference between V1 and V2 is explained with reference to FIG.

2 illustrates an example of a DIVR 105 that is configured to shift the current it supplies when the relative voltages of the power supplies 150, 160 change. The DIVR 105 includes a transistor 205 for adjusting the voltage supplied by the input node 110, and a transistor 210 for adjusting the voltage supplied by the input node 115. The DIVR 105 produces a regulator output voltage Vout at the drain terminals of the transistors 205, 210 coupled to the output node 125. As shown in FIG. 2, the output current Iout is supplied from either or both of the current paths indicated by the currents I1, I2 of the transistors 205, 210. Currents I1, I2 are controlled by the gate to source voltage (Vgs) of transistors 205, 210. The supplied gate voltage is controlled such that Iout is continuously supplied by I1 and/or I2 during operation.

The DIVR 105 includes gate bias circuits 215, 220 for controlling the gate voltages of the transistor 205 and the transistor 210, respectively. The gate bias circuits 215, 220 can adjust Vout by controlling the gate voltage. In the depicted example, the transistors 205, 210 are p-channel enhanced metal oxide semiconductor field effect transistors (PMOS). When Vgs is greater than the circuit dependent voltage threshold (Vt), the PMOS transistors 205, 210 can be turned off and the current can be substantially non-conducting. When Vgs is less than Vt, the PMOS transistors 205, 210 can be turned on and a current can be conducted from the source to the drain. In various embodiments, the Vt visible transistor is dictated by the type of other circuit components. The Vt range of the PMOS transistor can typically range from, for example, about -4 V to about 0 V.

The gate bias circuits 215, 220 control the supplied gate voltage to allow for a transition (e.g., smooth transition) between the power supplies 150, 160. The gate bias circuit 215 is supplied by the voltage V1, and the gate bias circuit 220 is supplied by the voltage V2. In some cases, such as when V1 is approximately equal to V2, the gate bias circuits 215, 220 can supply substantially the same gate voltage to the transistors 205, 210.

The gate bias circuits 215, 220 can control I1 and I2 based on the relative difference between V1 and V2. During operation, when either voltage V1 or V2 is too low relative to the gate voltage system to meet the threshold voltage condition (eg, Vgs > Vt), the corresponding current path is turned off.

When both V1 and V2 are higher than the supplied gate voltage, the operation of DIVR 105 depends on the relative difference between V1 and V2. For example, when voltages V1 and V2 are within the window, since Vgs is lower than Vt, transistors 205, 210 may allow currents I1, I2 to flow through transistors 205, 210 to supply Iout. The amount of currents I1 and I2 varies based on V1 and V2. For example, when V1 is greater than V2, I1 is greater than I2. When voltages V1 and V2 are outside the window, Vgs can be controlled such that Iout is essentially supplied by source 150 or 160 having the highest input voltages V1, V2. For example, when V1 > V2, and V1 and V2 are outside the window, Iout is essentially supplied by source 150.

The gate bias circuits 215, 220 generate gate voltages based on the voltages V1, V2 and one of the control signals Vbias received from the operational amplifier 225, respectively. Operational amplifier 225 receives a reference input and a feedback input at node 230. The transistors 205, 210, the gate bias circuits 215, 220 and the operational amplifier 225 combine to form a feedback circuit for adjusting Vout and controlling the currents I1, I2 in the current path. In some embodiments, the feedback circuit operates to control the Vgs of the transistors 205, 210 such that when the V1 and V2 are within the window, the DIVR 105 draws current from the input nodes 110, 115 depending on Vout. Based on V1, V2, and Vout, the feedback circuit generates a gate bias voltage for the transistors 205, 210 to adjust Vout and smoothly transform the current through the transistors 205, 210 as the voltages of the power supplies 150, 160 change. When V1 and V2 are outside the voltage window, the feedback circuit can control the Vgs of the transistors 205, 210 such that substantially all of the Iout flows through the transistors coupled to the highest available input voltages V1, V2.

3 is a diagram 300 showing an example of current transformation (e.g., smooth) when the voltage difference (V2-V1 = ΔV) changes in a range. The graph 300 includes a horizontal axis 305 representing the amount of ΔV, and a vertical axis 310 representing I1, I2 passing through the transistors 205, 210 of FIG.

In chart 300, lines 315, 320 plot the characteristics of I1, I2 within a range of ΔV. In DIVR 105, Iout = I1 + I2. In the example shown, I1 and I2 change smoothly and continuously over the range of ΔV. For example, there are no sudden discontinuities in the plots 315, 320. As such, the Iout is continuously supplied by at least one power supply. Thus, in some examples, the DIVR 105 can advantageously supply the output current Iout and substantially reduce the fault. In particular, it responds to the transformation in the input voltages V1, V2. For example, when power supply 160 is suddenly removed from system 100, forcing DIVR 105 to supply current from power supply 160 to supply current from power supply 150, the transformation can occur smoothly and substantially reduce the failure.

As shown in Figure 3, chart 300 shows three regions of operation. The DIVR 105 operates in Region 1 when ΔV is within the circuit dependent window between -Vd1 and Vd2 (including -Vd1 and Vd2). When ΔV is less than -Vd1, the DIVR 105 operates in the area 2a. When ΔV is greater than Vd2, DIVR 110 can operate in region 2b.

When DIVR 105 operates in zone 1, power supplies 150, 160 can simultaneously supply Iout. As shown in graph 300, DIVR 105 extracts current I1 and/or I2 to supply Iout. At ΔV=-Vd1, the DIVR 105 can essentially extract only I1 to supply Iout, leaving I1 substantially equal to Iout. When ΔV increases, I2 increases and I1 decreases, causing approximately I1+I2=Iout. At ΔV = Vd2, DIVR 105 may extract only I2 to supply Iout substantially, leaving I2 substantially equal to Iout. The window width is in the range from -Vd1 to Vd2. In some examples, Vd1 and Vd2 may be the same (eg, |Vd1|=|Vd2|=0.4 V). In other examples, the thresholds Vd1, Vd2 of the power supplies 150, 160 may not be symmetrical. For example, Vd1 can be about 0.6 V and Vd2 can be about 0.4 V. Vd1 and Vd2 are tied and can be determined based on circuit dependent characteristics (e.g., gate to source thresholds of transistors 205, 210). In an illustrative example, a change in processing parameters can cause a change in Vt (e.g., about +/- 100 mV). Various other factors can also cause variations in the width of the window. In some examples, Vt may increase as the temperature drops and/or as the source to drain voltage of a PMOS device increases. In addition, matching devices can cause variations in window width.

When DIVR 105 is operating in region 2a, power supply 105 supplies substantially all of Iout, while the current path coupled to power supply 160 supplies little or no current. In the depicted example, I2 is substantially zero in region 2a, but remains at a non-negative number. When DIVR 105 is operating in region 2b, power supply 160 provides substantially all of Iout, while the current path coupled to power supply 150 supplies little or no current. In the depicted example, I1 is substantially zero in region 2b, but remains at a non-negative number.

As an illustrative example, assume that DIVR 105 adjusts output node 125 to 2.5 V and supplies a load current of approximately 1.7 mA. It is assumed that the power supply 150 supplies V1 to a substantially constant voltage of 3.7 V, and V2 jumps from 0 V to 6 V. The DIVR 105 initially operates in the area 2a. When V2 jumps from 0 V to approximately (3.7-Vd1)V, DIVR 105 continues to operate in region 2a, while all Iout is essentially supplied from I1 (eg, I1 is substantially 1.7 mA, and I2 is substantially zero And non-negative numbers). When V2 and V1 are within the window (eg, V2 is greater than (3.7-Vd1)V but less than (3.7+Vd2)V), DIVR 105 operates in Region 1, and Iout is supplied from both I1 and I2. In the example of region 1 shown, as V2 increases, the current of I1 decreases and the current of I2 increases. In various embodiments, when ΔV is in operation region 1, the sum of I1 and I2 is substantially equal to Iout. As shown, when V2 jumps, the current of I1 decreases smoothly (e.g., monotonically) and the current of I2 increases smoothly (e.g., monotonically). In some embodiments, such as when V1 is substantially equal to V2, the power supplies 150, 160 share the load current substantially evenly (eg, I1 = I2 = 850 [mu]A). When V2 is greater than (3.7 + Vd2) V, DIVR 105 operates in region 2b, and all Iout is substantially supplied from I2 (eg, I2 is substantially 1.7 mA, while I1 is substantially zero and non-negative).

4 shows an overview of an example circuit 400, the specific implementation of which is described with reference to FIG. Circuit 400 shows additional details of bias circuits 215, 220 and operational amplifier 225. In some embodiments, the circuit 400 can be embodied using discrete components and/or integrated components, or any combination thereof.

As described with respect to FIG. 2, DIVR 105 adjusts output voltage Vout at output node 125 and supplies current Iout, and DIVR 105 extracts currents I1, I2 from input nodes 110, 115, respectively. The transistors 205, 210 can control the currents I1, I2 in the first and second current paths, respectively, based on the gate voltages of the transistors 205, 210 supplied by the gate bias circuits 215, 220.

In some cases, the gate bias circuits 215, 220 can supply substantially similar gate voltages to the gates of the transistors 205, 210. The gate circuits 215, 220 are supplied by voltages V1, V2, respectively. As such, the gate biases supplied by the respective gate bias circuits 215, 220 may depend on the respective supply voltages V1, V2. In the depicted example, gate bias circuits 215, 220 are responsive to control signal Vbias from operational amplifier 225. In this example, gate bias circuits 215, 220 may be responsive to Vbias to generate gate voltages to transistors 205, 210, respectively, within limits associated with supply voltages V1, V2.

When the difference between V1 and V2 is within the window (e.g., voltage region 1 in FIG. 3), the gate bias circuits 215, 220 are configured to allow I1 to be combined with I2 to supply Iout. When the difference between V1 and V2 is outside the window (e.g., voltage regions 2a and 2b in FIG. 3), gate bias circuits 215, 220 are configured such that substantially all of the Iout system is coupled through its source. The higher voltage transistors 205, 210 between V1 and V2 are supplied.

The gate bias circuits 215, 220 can also use Vbias to adjust the output voltage Vout. To generate Vbias, operational amplifier 225 uses a received feedback voltage and an input Vref. The received feedback voltage is directly related to Vout. Based on Vref and the feedback voltage, operational amplifier 225 outputs a voltage Vbias to gate bias circuits 215, 220. Based on Vbias, V1 and V2, the gate bias circuits 215, 220 allow the currents I1, I2 to supply Iout, or only one current path can supply Iout and substantially block the reverse current.

When only one of V1, V2 is below a (eg, circuit dependent) threshold, operational amplifier 225 can control gate bias circuits 215, 220 to substantially block current flow through transistor 205 or 210. Factors that may affect the circuit dependent threshold include, but are not limited to, the characteristics of the transistor (eg, the threshold voltage) used to implement the gate bias circuits 215, 220 and the control voltage output by the operational amplifier 225. In an illustrative example, it is assumed that the transistor 205 is off. Circuit 400 can substantially prevent reverse current from flowing from output node 125 to input node 110 by turning off transistor 205. Thus, the output current Iout is substantially supported by the current I2, and I2 does not supply a feedback current through the transistor 205.

When both V1 and V2 are above the circuit dependent threshold, the gate bias circuits 215, 220 can use the Vbias generated by the operational amplifier 225 to control the currents I1 and I2 flowing through the transistors 205, 210. The currents I1, I2 can be determined, for example, by the difference between V1 and V2 within or outside the window.

If the difference between V1 and V2 is within the window, operational amplifier 225 can control gate bias circuits 215, 220 to enable both current paths to conduct currents I1, I2 via transistors 205, 210. If the difference between V1 and V2 is outside the window, operational amplifier 225 can control gate bias circuits 215, 220 to enable the current path with the highest voltage to substantially supply current Iout. The relative amplitudes of the currents I1, I2 can be directly related to the relative voltages V1 and V2. In some examples, for a particular differential voltage, the associated current shunt between the current paths may remain substantially constant as the load current changes. The ratio of currents I1, I2 can vary over a range of voltage differences between V1 and V2, as shown in graph 300.

Circuit 400 also includes a voltage selection module 450 that selects a maximum voltage between supply voltages V1 and V2. Voltage selection module 450 receives the supply voltage and generates an output voltage at node Vselect. In the depicted example, the output voltage is supplied to the body terminals of the PMOS transistors of the bias circuits 215, 220.

When V1 and V2 change, the output voltage of Vselect can provide the highest supply voltage that is substantially available from the two supply voltages V1, V2. Vselect can provide substantially the highest available voltage to the body terminal of the PMOS transistor. For example, a substrate that supplies the highest available voltage to the PMOS device can, for example, substantially reduce or prevent accidental forward biasing of the internal junction of the PMOS transistor. Moreover, Vselect may, in some embodiments, facilitate reducing and/or preventing reverse current, such as between a source and a source of a non-use output PMOS device. Some examples of voltage selection module 450 are described in further detail with respect to Figures 5A-B.

5A-B show example circuits 500, 550 that implement voltage selection module 450. As shown in FIG. 5A, circuit 500 includes two NMOS transistors 505, 510 that are coupled to voltage supplies V1 and V2, respectively. Circuit 500 can supply the higher of V1 and V2 to an output node Vselect. As in the example illustrated with reference to FIG. 4, the Vselect voltage can be supplied to substrates (e.g., body connections) and/or transistors 205, 210 of various PMOS transistors, such as in bias circuits 215, 220. In some embodiments, supplying the highest available voltage to the PMOS substrate substantially prevents accidental forward biasing of the PMOS transistor internal junction.

In some embodiments, NMOS transistors 505, 510 can have a Vt that is substantially zero. In some embodiments, NMOS transistors 505, 510 can have a positive threshold voltage (eg, Vt up to at least about 1 V). In some examples, the Vds of the NMOS transistors 505, 510 can be directly associated with Vt. A small Vt across the NMOS transistors 505, 510 can lead to, for example, a small voltage drop (Vds) across the drain terminal and the source terminal.

In operation, voltage selection module 450 can select a highest voltage between V1 and V2 at Vselect. For example, assume that Vt is essentially 0 V. When V1 > V2, the voltage of Vselect may be approximately V1, and the NMOS transistor 510 may be turned off because the Vds of NMOS transistor 510 (which is Vselect-V2) is less than Vt (which is substantially 0 V). When V2 > V1, the voltage of Vselect may be approximately V2, and NMOS transistor 505 may be turned off because the Vds of NMOS transistor 505 (which is Vselect-V1) is less than Vt (which is substantially 0 V).

As shown in FIG. 5B, circuit 550 includes PMOS transistors 555, 560. Circuit 550 can provide several advantages, such as additional reverse current protection when using an NMOS device such as Vt having a voltage of about zero. In various embodiments, the PMOS device can help achieve a reduced voltage drop and/or reduced volume.

Another option is other specific embodiments in which the voltage selection module 450 can be used. For example, a voltage selection module can be implemented to select a minimum input voltage as an output using a PMOS having a Vt of substantially zero.

Although examples of systems (which may be portable) have been described with reference to the above illustrations, other specific embodiments may be employed in other applications, such as other circuit applications, computing applications, network applications, and the like.

In some embodiments, system 100 can obtain power from more than two power sources. For example, a DIVR 105 using the same technology can use three or more power supplies to adjust Vout. By controlling the gate voltage of each PMOS transistor that adjusts the input voltage, the DIVR 105 can control the current shunt between the various power supplies. When the input voltage is outside the voltage range, the output power is supplied by the power supply with the highest input voltage. Furthermore, by appropriately applying a bias voltage to the corresponding transistor, the reverse current of each of the multiple sources can be substantially prevented.

In a particular embodiment with more than two voltage regulators, various modes of operation can be used. For example, DIVR 105 can receive current from two or more input nodes (eg, three or more voltage inputs). Each input can be controlled by a gate bias circuit responsive to the Vbias signal generated by operational amplifier 225. When more than one voltage is above a circuit dependent threshold, for example, a gate bias circuit can control the amount of current flowing through each current path based on a relative voltage difference between the input voltages.

In some other embodiments, the current regulator can be substituted for the voltage regulator, such as by replacing the operational amplifier circuit 225 (see FIG. 2) with a current comparator and comparing a reference current to the delivered load current.

In some embodiments, DIVR 105 can be configured to use a voltage supply that is negative for a circuit reference voltage (eg, ground). For example, DIVR 105 can use an N-channel MOS transistor for such a negative voltage. When the DIVR 105 is supplied with a negative voltage, the gate bias circuits 215, 220 can select one from the input node 110, 115 having the lowest (eg, most negative) voltage when the difference between the input voltages is outside the window. Current is used. When the difference between the input voltages is within the window, the gate bias circuits 215, 220 can allow multiple (eg, both) current paths to simultaneously support the output current. In some embodiments, the linearity may be sufficient to substantially avoid chattering when operating in or near the edge of the window. In some embodiments, a select window function can be selectively implemented to temporarily lock one of the adjusters in their current state (eg, to supply all load currents Iout). Such a particular embodiment may be advantageous, for example, if the V1 source provides limited stability or poor interference cancellation near the operating point where V2 may operate.

Although some specific features of an architecture have been described, other features can be combined to improve performance. For example, other hardware and software may be provided to perform operations, such as networking or other communication using one or more protocols, wireless (eg, infrared) communication, stored operational energy and power supplies (eg, batteries), switches, and / or linear power supply circuit, software maintenance (such as self-test, upgrade). One or more communication interfaces can be provided to support data storage and related operations.

Some systems may be embodied as a computer system that can be used with embodiments of the present invention. For example, different embodiments may include digital and/or analog circuits, computer hardware, firmware, software, or combinations thereof.

In various embodiments, system 100 can communicate using suitable communication methods, devices, and techniques. For example, system 100 can use point-to-point communication to communicate with compatible devices (eg, capable of transferring data to and/or transferring data from system 100), wherein the messages are linked through a proprietary entity (eg, fiber optic links, point-to-point wiring, daisies) The chain is transmitted directly from the source to the receiver. The components of the system can exchange information via any form or medium of analog or digital data communication, including packet-based messages on the communication network. Examples of communication networks include, for example, LAN (Regional Network), WAN (Wide Area Network), MAN (Metro Network), wireless and/or fiber optic networks, and computers and networks that form the Internet. Other embodiments may transmit messages by broadcasting to all or substantially all of the devices that are coupled together by a communication network (e.g., by using a one-way radio frequency (RF) signal). Still other embodiments may use an oriented (i.e., narrow beam) antenna or infrared signal that is selectively usable with the focusing optics to convey a message characterized by high directivity, such as the transmitted RF signal. Still other embodiments are possible, using appropriate interfaces and protocols such as, by way of example and not limitation, USB 2.0, Firewire, ATA/IDE, RS-232, RS-422, RS-485, 802.11a /b/g, Wi-Fi, Ethernet, IrDA, FDDI (Fiber Distributed Data Interface), token ring network or multiplex technology based on frequency division, time division or code division. Some embodiments may selectively incorporate several functions, such as error checking and correction (ECC) for data integrity, or security measures such as encryption (eg, WEP) and password protection.

Several specific embodiments of the invention have been described. However, it will be appreciated that various modifications may be made without departing from the spirit and scope of the invention. For example, if the steps of the disclosed technology are carried out in a different order, if the components of the disclosed system are combined in different ways, or if the components are replaced or supplemented with other components, an advantageous result can be achieved. The functions and procedures (including algorithms) may be implemented in hardware, software, or a combination thereof, and some embodiments may be practiced on a different module or hardware than the ones described. Accordingly, other specific embodiments are within the scope of the following claims.

100. . . system

105. . . Dual Input Voltage Regulator (DIVR)

110. . . Input node

115. . . Input node

120. . . Processing system

125. . . Output node

130. . . source

135. . . source

140. . . interface

145. . . interface

150. . . power supply

155. . . Data interface

160. . . power supply

165. . . Data interface

205. . . Transistor

210. . . Transistor

215. . . Gate bias circuit

220. . . Gate bias circuit

225. . . Operational Amplifier

230. . . node

300. . . chart

305. . . horizontal axis

310. . . Vertical axis

315. . . Line/drawing

320. . . Line/drawing

400. . . Circuit

450. . . Voltage selection module

500. . . Circuit

505. . . NMOS transistor

510. . . NMOS transistor

550. . . Circuit

555. . . PMOS transistor

560. . . PMOS transistor

1 shows an example system that includes a dual input voltage regulator configured to receive power from multiple power sources.

2 illustrates an example of a dual input voltage regulator configured to convert between multiple power supplies.

Fig. 3 is a graph showing an example of current conversion when the voltage of one power source is changed with respect to the other power source.

4 shows an overview of an example circuit that implements a dual input voltage regulator using PMOS and NMOS transistors.

5A-B show an exemplary embodiment of a voltage selection module.

The same reference symbols in the various drawings are the same elements.

100. . . system

105. . . Dual Input Voltage Regulator (DIVR)

110. . . Input node

115. . . Input node

120. . . Processing system

125. . . Output node

130. . . source

135. . . source

140. . . interface

145. . . interface

150. . . power supply

155. . . Data interface

160. . . power supply

165. . . Data interface

Claims (22)

A voltage regulation system includes: a first current path providing a first current I ₁ between a first supply node and an output node; a second current path at a second supply node and the output Providing a second current I ₂ between the nodes; and a control circuit for adjusting a voltage of the output node by supplying a control signal to each current path, the control circuit being operable to be at the first supply node When the difference between the voltage and the voltage of the second supply node falls within a voltage range, a current is shunted along the current paths for supply to the output nodes, and the shunt characteristic defined by a function is characterized by The three regions limited by the two threshold voltage levels include a first, second and third region, wherein: in the first region I ₁ >I ₂ , in the second region I ₁ =I ₂ , In the third region, I ₁ <I ₂ , and conversely, substantially all of the output current is supplied from a supply node having a higher voltage. The system of claim 1, wherein the current supplied to the output node substantially smoothly transitions from the first current path to the second current path when the voltage of the second supply node increases within the voltage range. The system of claim 1, wherein when a voltage of the first supply node increases within the voltage range, a current supplied to the output node changes substantially smoothly from the second current path to the first current path. The system of claim 1, wherein the control circuit shunts the current by applying the control signal to apply a transistor biased to one of the current paths. The system of claim 4, wherein the first current path comprises a first PMOS transistor having a source terminal coupled to the first supply node. The system of claim 5, wherein the second current path comprises a second PMOS transistor having a source terminal coupled to the second supply node. The system of claim 6, wherein the output node is connected to a drain terminal of the first PMOS transistor in the first current path, and a drain of the second PMOS transistor in the second current path terminal. The system of claim 7, wherein the control circuit provides a bias signal to modulate the first and second PMOS transistors. The system of claim 6, further comprising a plurality of gate bias circuits for supplying substantially the same voltage to the gate terminal of the first PMOS transistor and the first portion when the difference is in the second region The gate terminal of the two PMOS transistors. The system of claim 1, further comprising a smart card comprising a first current path, a second current path and a controller. A system as claimed in claim 1, wherein the voltage range extends up to about 1 volt. The system of claim 1 wherein the voltage range extends between about 0.2 volts and about 0.8 volts. The system of claim 1, wherein the first current path and the second current path each comprise a junction field effect transistor. The system of claim 1, wherein the first current path and the second current path each comprise a dual carrier junction transistor. A voltage adjustment method includes: receiving a first voltage of a first input of a voltage regulator; receiving a second voltage of the second input of the voltage regulator; and adjusting a voltage output by one of the voltage regulators; And when the difference between the first voltage and the second voltage falls outside a voltage range, the input current is only input from one of the substantially higher input voltages to the output, and when the first voltage is When the difference between the second voltages falls within the voltage range, a current is supplied to the output such that a current supplied from each of the first and second inputs is shunted according to a voltage of its respective input. The method of claim 15 wherein the voltage range is substantially dependent on a gate to source threshold voltage of a transistor. The method of claim 15, wherein the voltage range comprises a voltage difference between a first flip-flop and a second flip-flop, wherein each flip-flop defines a transition threshold, the transition threshold being from only An input supply current is converted to at least a portion of the current from the first and second inputs, the difference being selected from the group consisting of: about 0.1, about 0.2, about 0.3, about 0.4, about 0.5 , about 0.6, about 0.7, about 0.8, about 0.9, and about 1.0 volt. The method of claim 15, further comprising supplying power to the first input by contacting a connector entity. The method of claim 15, further comprising supplying power to the second input through a wireless interface. The method of claim 15 further comprising transferring the data through an interface operable to receive the first voltage. The method of claim 20, further comprising transferring the data through an interface operable to receive the second voltage. The method of claim 15 further comprising selecting a highest available voltage at the first and second inputs to apply a substrate biased to one of the voltage regulators.