TWI433246B - Smart defect review for semiconductor integrated - Google Patents

Description

Semiconductor integrated circuit defect review device

The present invention relates to a defect review sampling, a defect review method, and a defect classification method applied in a semiconductor integrated circuit manufacturing process, and a device designed based on the method. The apparatus and method can be used to inspect defects on a semiconductor wafer or defects on a printed reticle of an integrated circuit.

As the line width and structure design of the semiconductor integrated circuit shrinks, the 300 mm wafer becomes a commonly used size, and the process control window becomes smaller, the result is that the number of defects detected by the inspection machine increases. Especially for those components that are in the early stages of development or just entering the mass production stage, the number of defects is very high.

Defects are usually detected by instruments such as the so-called defect inspection machine. 1 is a simplified diagram of a typical defect review apparatus 100. The defect to be reviewed and the previously detected defect file are loaded from the loading unit 102, and then the positioning of the wafer, the coordinates of the die, and the offset of the relative position of the defect are all calibrated in the image capturing unit 104. The image capture condition 106 and the review sample plan 108 are provided by the host computer 110. The defective image captured by the image capturing unit 104 is compared with the reference image of the same position in the defect locating unit 112, and the actual coordinate of each position of the defective image can be analyzed in the defect locating unit 112. Then, the position information is fed back to the image capturing unit 104 to obtain the high resolution and high magnification defect images of the position, and then the defect image is provided to the defect classification and data output unit 114 for defect classification. Finally, the previously detected defect file name is replaced with the defect classification code, and sent to the database 116 for storage together with the high resolution and high magnification defect image.

As shown in Figure 1, a typical automatic defect review procedure includes the following steps: (1) loading the wafer to be reviewed and the previous inspection result file (the defect data is obtained by the inspection machine); (2) calibrating the wafer and desire Review the grain coordinates; (3) Deviation correction of the defect relative position of the grain; (4) Setting of the electron beam detection condition; (5) Setting the sampling standard for reviewing the defect; (6) Automatically finding the method of the defect address; 7) setting review image retrieval conditions; (8) defect classification, which can be fully automatic, semi-automatic, or manual classification; (9) setting data output; and (10) unloading wafers.

It is quite time consuming to review all the defects selected by the inspection machine one by one, and most of them are unnecessary. Regarding step 5, the most common practice in semiconductor production line monitoring is to review 50 or 100 defects randomly from one test result. More sophisticated sampling methods may include random selection of defects such as percentage, defect size, defect classification (rough bin), and cluster defects. A common problem with the above sampling methods is that the machine user cannot avoid reviewing defects located in "non-critical areas or locations where the non-line monitors are concerned." Examining non-critical defects that are not important wastes valuable machine time.

The above method can only locate randomly occurring defects and it is difficult to define systemic defects (such as repetitive defects: such as mask defects), because adjacent grains that are used as a reference may also contain the same or similar defects, so it is difficult to The image of the examined die is compared with the image of the reference die, and repetitive defects are found, so the information of the original design database is used. Furthermore, defect review machines, especially electron beam (e-beam) defect review machines, are expensive (each typically exceeds $2 million). Therefore, the processing speed of the automatic defect review machine is becoming higher and higher. Therefore, the intelligent defect review method becomes more and more necessary, and the present invention can assist in achieving the above requirements.

[Reciprocal Reference of Related Applications]

The present application claims the priority of US Provisional Patent Application No. 60/887,901, entitled "Smart Defect Review For Semiconductor Integrated Circuit", filed on February 2, 2007, to The content is incorporated into this case for reference.

It is an object of the present invention to provide an automatic defect review sampling and defect classification method in a semiconductor integrated circuit manufacturing process, and a device designed based on the method. The apparatus and method can be used to inspect defects on a semiconductor wafer or defects on a printed reticle of an integrated circuit. The above and other objects are achieved by comparing the image of the defect with the reference image of the defect location picked up by the smart sampling filter.

In one embodiment, the present invention discloses a cluster computer system that provides a data cache based on a high speed network and saves computation time and memory. In another embodiment, the present invention discloses an intelligent review sampling filter that automatically searches for a "sensitive area" and selects a possible defect location near the "sensitive area" as a review sample. This information can also help to classify defects.

The purpose, technical contents, features, and effects achieved by the present invention will become more apparent from the detailed description of the appended claims.

This will be described in detail in accordance with the specific embodiments of the invention. Examples of these embodiments are illustrated by the accompanying drawings. It is to be understood that the invention is not intended to limit the scope of the invention Rather, the alternatives, modifications, and equivalents may be included within the spirit and scope of the invention as defined by the appended claims. In the following description, numerous specific details are set forth in order to provide a thorough understanding. The invention may be practiced in the absence of some or all of the above details. On the other hand, the conventional steps are not described in detail to avoid unnecessary misinterpretation of the present invention.

The present invention assists in improving the performance of step 5 (set review defect sampling criteria), step 6 (method of automatically finding defective addresses), and step 8 (defect classification) with the assistance of an integrated circuit design database.

One embodiment of the present invention is a smart review sampling filter 200 (Fig. 2). 2 is a simplified diagram showing an intelligent review sampling filter 200 in accordance with an embodiment. The component coordinates can be retrieved from the integrated circuit design database 202 by the location extract processor 204, and a "sensitive area" susceptible to defects is automatically created. This "sensitive area" can also be manually established after initially viewing the image of the wafer. In conjunction with the "sensitive area" and the defect distribution information in the previous inspection results, a component review location plan 206 can be generated and transmitted to the review sampling unit 208 in the host computer.

Defects found by all previous inspection results are obtained by the location extract processor 204. After analysis by the smart review sampling filter 200, the sampling position of the defect to be reviewed can be determined. Both the smart review sampling filter 200 and the defect review position plan are established when the inspection procedure is established. The following items can be achieved by establishing a smart review sampling filter 200:

(1) Machine users can avoid wasting valuable time reviewing defects in unimportant areas, such as defects on the cutting line (space between the grains). By setting the review sampling conditions, the user can only review the defects defined as sensitive areas (for example, areas with high aspect ratio (HAR) contact holes).

(2) The distribution of defects on a particular component (such as the distribution of defects on a Static Random Access Memory (SRAM)) can be displayed to assist the user in evaluating the integrated circuit process on the wafer.

(3) It is possible to provide defect density in a specific area or component, such as defect density on SRAM.

(4) Defects that may impact subsequent circuit layers, will be flagged and may be sampled for review.

When the design line width is as low as 32 nm or less, the wafer integrated circuit design database becomes very large, and sometimes it can reach more than 200G. One embodiment of the present invention is a high speed data cacher based on a cluster computer architecture. As shown in Figure 3, the integrated circuit design database will be stored in separate computers, and then connected to the host computer by a high-speed network 304 (such as Infiniband).

Please refer to FIG. 3 in succession. FIG. 3 is an integrated circuit design database 300 of a cluster computer. The integrated circuit design database 300 can be stored in separate computers 302a-302n according to location coordinates, and each of the individual computers 302a-302n is connected by a high speed network 304. The position information of the defect is input to the relevant computer 302a-n according to the coordinates to reflect the position of the defect, and the design configuration data of the integrated circuit is output according to the coordinate. Based on the above structure, we can process the original design database of the integrated circuit of any memory capacity very quickly. Each individual computer 302a-n only needs to process design information for a small area.

Based on the reviewed defect coordinate information, each computer only caches the integrated circuit design data around the defect location, and does not need to load all the integrated circuit design database into the arithmetic memory.

With regard to step 6, Figure 4 shows the most common application of the current review machine. 4 is a simplified diagram of a typical automatic defect locating unit 400 in a defect review machine. The defect image 402 and its reference image 404 taken from the same position in the reference die are image-aligned by the image alignment and defect locating unit 406 to determine whether the defect is an incomplete configuration pattern or a foreign object. The reference crystal grain is a standard crystal grain or one or two crystal grains adjacent to the defect crystal grain. This alignment program obtains the coordinates of the exact defect locations in the defective image. This coordinate information is fed back to the microscope 408 to obtain a higher magnification image of the coordinate for detailed defect classification and research leading to the cause of the defect.

The most common difficulty when using the program shown in Figure 4 for automatic defect location (ADL) is that the alignment process takes too much time. In order to view a defect, it is usually necessary to move the sample stage twice (to view the same position of the defect and its reference die) ‧ and take three images (low-rate reference image, low-magnification defect image, high-magnification defect image) .

Another element of the present invention is general defect locating (GDL), which not only locates defects without regularity, but also automatically locates defects with regularity. FIG. 5 shows a method for locating a GDL, which is characterized by comparing a defect image with an integrated circuit design configuration image from a database to locate a corrected coordinate position of the defect. FIG. 5 is a simplified diagram of a general defect coordinate positioning unit 500. The image that is aligned in the automated general defect review tool 502 may be an image taken at the same location as the conventional defect image 504 and other dies (standard dies or adjacent dies). In this case, the image converter 508 and the image converter 510 can be skipped.

However, when the defect image to be reviewed belongs to a complicated component combination line configuration, and the original integrated circuit design database has no existing configuration image at the same position, the image converter can be used to design the database. Part of the image of the die or component is extracted separately to form a comparative reference image of the complex circuit configuration to be tested, and then the relative position coordinates of the defect are compared. On the other hand, the real image of the defect can be adjusted to become the existing configuration image in the design database, and then the relative position coordinates of the defect are compared.

Therefore, if the compared image is an image processed/converted defect image and an image processed/converted image at the same position in the database; the image converter 508 is used to integrate the integrated circuit design database. The data 506 is converted into an image, and the image converter 510 is used to convert the real image taken by the microscope into an image that can be compared with the integrated circuit design database image.

By means of this comparison method, the problems common to the two current defect review machines can be overcome.

(1) According to the method proposed by the present invention, the sample stage can be moved a small number of times when the defect is reviewed, and therefore, the processing speed can be increased by using the method.

(2) The image converted from the original design database of the integrated circuit does not change the correctness of the comparison result due to the slight variation of the process or the occurrence of repeated defects (such as mask defects) during manufacturing. The review system and method designed in accordance with the present invention provide a direct comparison of the die and the integrated circuit database to construct a defect file for review.

With regard to step 8, as shown in FIG. 6, the smart review sampling filter provides the user with the option to automatically classify defects based on the location of the defect. Figure 6 is a simplified diagram of an automated general defect review tool 600 in accordance with the present invention. Similar to the general defect review device, the wafer to be inspected and the previously detected defect file are loaded from the loading unit 102; then, the calibration wafer, the crystal origin coordinates, and the relative position of the defect are completed in the image capturing unit 104. Offset correction. The automatic general defect inspection machine 600 has the following major differences compared to the standard defect review machine 100 (shown in Figure 1):

(1) The previous test result is first transmitted to the smart review sampling filter 200 (shown in FIG. 2) to filter out all defects not located in the "sensitive area". All defects found by previous inspections are followed by coordinate information of the relative position of the components after processing by the smart review sampling filter 200.

(2) Another difference is the image matching mode 406 when the defect is positioned. The comparison is performed in an automatic general defect inspection machine 600, and the aligned image may be an image of a conventional defect image and other crystal grains (standard crystal or adjacent crystal grains) at the same position; or The image processed/converted defect image and the image processed/converted image at the same position in the database 202.

(3) As previously described in (1), all the defects found by the inspection are processed by the smart review sampling filter 200 with coordinate information of the relative position of the components, and this information can be used not only for sample selection at the time of review, It can also be used to automatically classify defects.

For example, if a SRAM area with a review range of 50% is defined, that is, 50% of the defects in the SRAM area will be randomly selected and reviewed. The SRAM area can be defined by the smart review sampling filter 200 from the wafer integrated circuit design database 202.

The inventive device can also be used for defect inspection, where the smart review sampling filter 200 can be used to define a test sensitive area which will make the test procedure more efficient and accurate.

To further illustrate, in the defect inspection, the inspection parameter is 50% SRAM area, X=80%, Y=90%, which means that every other SRAM area is defined as the inspection sensitive area, and the inspection coverage is each SRAM area. The x-axis is 80% of the actual length extracted from the integrated circuit design database, and the y-axis of each SRAM area is 90% of the actual length extracted from the integrated circuit design database.

Another example is the application of defect inspection. There are usually two kinds of contact boring patterns in the crystal grains of integrated circuit components: conventional contact boring type and high aspect ratio (HAR) contact boring type. state. The smart review sampling filter 200 according to an embodiment of the present invention can determine whether the defect is an over-etch conventional contact hole or an under-etched HAR contact hole. Because these two defects represent different meanings for the semiconductor process.

When the review sampling filter detects a defect in a critical component, or if a defect is found during the comparison of the automatic defect repositioning in the review sampling filter, the position coordinates of the defect are automatically marked and the Internet is used. Send a warning signal to the relevant personnel. The imaging range of each key component in different sensitive areas can be pre-defined and provided to the intelligent review sampling filter 200, which is selected when setting up the defect review plan.

While the present invention has been described in terms of the embodiments shown and described, it will be understood that Also, various modifications may be made by those skilled in the art without departing from the spirit and scope of the appended claims.

100. . . Defect review machine

102. . . Loading unit

104. . . Image capture unit

106. . . Image capture condition

108. . . Review sampling

110. . . Host

112. . . Defect location unit

114. . . Defect classification and data output unit

116. . . database

200. . . Smart review sampling filter

202. . . Integrated circuit design database

204. . . Location extract processor

206. . . Review location plan

208. . . Review sampling unit

300. . . Integrated circuit design database

302a, 302b~302n. . . computer

304. . . High speed network

400. . . Automatic defect locating unit

402. . . Defect image

404. . . Reference image

406. . . Image alignment defect locating unit

408. . . microscope

500. . . Universal defect positioning unit

502. . . Universal defect inspection machine

504. . . Defect image

506. . . Information retrieved from the design database

508. . . Image converter

510. . . Image converter two

600. . . Automatic general defect inspection machine

602. . . Loading unit

604. . . Image converter

606. . . Image converter two

Figure 1 is a simplified diagram of a standard defect inspection device.

2 is a smart review sampling filter according to an embodiment of the present invention.

Figure 3 shows a library of integrated circuit design built into a cluster computer.

Figure 4 is a simplified diagram of a typical automatic defect locating unit in a defect inspection machine.

FIG. 5 is a schematic diagram of a general defect locating unit according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of an automatic general defect inspection machine according to an embodiment of the present invention.

600. . . Automatic general defect inspection equipment

602. . . Wafer loading unit

604. . . Image converter

606. . . Image converter two

Claims (15)

An apparatus for automatically reviewing defects of a semiconductor integrated circuit, comprising: an image capturing unit for obtaining a component image to be reviewed, and a reference control image of the component image; and a smart review sampling filter capable of The component information retrieved from the integrated circuit design database to define the range to be reviewed; a storage unit for storing the integrated circuit design database in the wafer; and a defect repositioning unit based on the previous inspection machine The defect location data obtained by the station is repositioned on the wafer to be reviewed and the integrated circuit pattern configuration image of the component is obtained, and the image is compared with the integrated circuit pattern image of a reference component, and the position coordinates of the defect are generated. Marked on the reference pattern, the reference pattern is selected from the component image adjacent to the defect or from the integrated circuit design database, and the integrated circuit configuration image of the component captured in the pre-designated area; a classification unit, For classifying the component location information and defect characteristics obtained from the integrated circuit design database; and an output unit for The video after the investigation, the reference output image and output monitoring classification results to the client database. The apparatus for automatically reviewing defects of a semiconductor integrated circuit as described in claim 1, wherein a computer system can be a special cluster computer system built on a high speed network, between the independent computers and between the independent computers and the host computer. High speed internet connection. The apparatus for automatically reviewing a semiconductor integrated circuit defect according to claim 1, wherein the integrated circuit design database is a high-efficiency data temporary storage structure, and the related integrated body can be preloaded based on the defect position coordinate information. Design information for circuit components. The apparatus for automatically reviewing a semiconductor integrated circuit defect according to claim 1, wherein the defect repositioning unit performs a defect positioning alignment process on the wafer by comparing a defect of the integrated circuit on the wafer The image is converted from an image converted from the same position on the integrated circuit design database, or an integrated circuit image at the same position on the standard die, or a product selected from the same position of any die on the wafer. The body circuit images are compared to obtain the coordinates of the defect location. The apparatus for automatically reviewing defects of a semiconductor integrated circuit according to claim 1, wherein the image of the defect realignment unit is compared with a reference image, which can be separately obtained from different components, wherein the component coordinate information system Provided by the integrated circuit design database. The apparatus for automatically reviewing defects of a semiconductor integrated circuit as described in claim 1, wherein the integrated circuit pattern to be reviewed can be automatically defined by using the integrated circuit design database. The apparatus for automatically reviewing defects of a semiconductor integrated circuit as described in claim 1 can also be used as an integrated circuit pattern inspection device. The integrated circuit pattern inspection device of claim 7, wherein the manner in which the sensitive area of the test is defined is derived from the method of defining the review range, which can be obtained by multiplying a constant in the x or y direction. The integrated circuit pattern inspection device of claim 7, wherein the sensitive area of the inspection is manually settable from the image taking unit. The integrated circuit pattern checking device according to claim 7, wherein the parameter of the alignment matching defined by the component density is controlled, and the component density is pre-specified according to the integrated circuit design database. The apparatus for automatically reviewing defects of a semiconductor integrated circuit as claimed in claim 1, wherein an abnormal pattern or defect determined by an automatic defect repositioning program is automatically performed according to a component position coordinate captured by the integrated circuit design database. classification. The integrated circuit pattern inspection device of claim 7, wherein the detected abnormal pattern or defect is automatically classified according to the component position coordinates captured by the integrated circuit design database. The integrated circuit pattern checking device according to claim 7, wherein the relative position of the defect area which is easy to generate in the design configuration or the defect area in the process is pre-defined in the integrated circuit design database, and is detected. Automatically marked at the time. The apparatus for automatically reviewing defects of a semiconductor integrated circuit as described in claim 1, wherein the image capturing conditions used in the image capturing unit are pre-specified according to different key positions. The integrated circuit pattern checking device according to claim 7, wherein the image capturing conditions used in the image capturing unit are pre-specified according to different key positions.