TWI433129B - Liquid crystal display and driving circuit thereof - Google Patents

Description

Liquid crystal display and its driving circuit

The present invention relates to a liquid crystal display (LCD), and more particularly to a driving circuit for driving the liquid crystal display.

The liquid crystal display is a thin electronic display device that utilizes the light adjustment function of the liquid crystal material. The liquid crystal material itself does not emit light. The display of the image is done by controlling the transmission of the liquid crystal material.

For each liquid crystal pixel, the penetration of light is determined by the amount of voltage applied to it. In order to prevent the liquid crystal material from being polarized, the voltage applied to the same pixel in the continuous video picture needs to be of opposite polarity. A variety of polarity inversion techniques have been developed, including line inversion, dot inversion, and column inversion.

Polarity inversion techniques typically require reference to a common voltage. If the potential applied to the pixel is higher than the common mode potential, it is called positive polarity development. If the potential applied to the pixel is lower than the common mode potential, it is called negative polarity development. Taking the dot inversion technique (refer to Figure 1A) or the row inversion technique (refer to Figure 1B) as an example, the polarity of each pixel must be inverted every time it switches to the next screen. In addition, the same column and adjacent rows The adjacent two pixels (for example, the first pixel P1 and the second pixel P2) must be opposite to each other. Since pixels such as the first and second pixels P1 and P2 in the same column may share the same common mode potential source, the common mode potential must be fixed at a fixed value, which is commonly referred to as a fixed-value common mode potential (DC VCOM). ). However, this constant value of the common mode potential may cause unnecessary power consumption of the driving circuit of the liquid crystal display. The embodiments listed in the following summary are discussing this energy consumption and revealing techniques for eliminating the energy consumption.

A liquid crystal display and a driving circuit therefor are disclosed below.

The driving circuit is a liquid crystal pixel array for driving the liquid crystal display. The driving circuit includes at least a source driver, a common mode potential driver (VCOM driver), and a timing controller.

The source driver includes a first source operational amplifier. A first pixel that supplies a first developing capacitor in the liquid crystal pixel array is scanned for positive polarity development, and a positive display potential is coupled to a first end of the first developing capacitor When allowed, the first source operational amplifier is coupled to the positive display potential to the first terminal of the first display capacitor.

The common mode potential driver includes a common mode potential operational amplifier, a first switch, and a second switch. The common mode potential operational amplifier outputs a certain value of the common mode potential. The first switch is coupled to a second end of the first display capacitor to a ground point when turned on. The second switch is designed to be coupled to the constant-valued common mode potential (the output of the common mode operational amplifier) to the second end of the first display capacitor when turned on.

The timing controller is designed to reduce energy consumption. The timing controller determines when the positive development potential is allowed to couple the first end of the first development capacitor, and further controls the states of the first and the second switches.

In one embodiment, when the positive polarity development potential is coupled to the first end of the first development capacitor, the timing controller turns on the first switch and does not turn on the second switch. The disclosed structure maintains the conductive state of the first switch and the non-conducting state of the second switch until the connection between the positive developing potential and the first end of the first developing capacitor is broken. In some embodiments, the timing controller further discharges the first imaging capacitor to a zero potential by turning on the first switch and not turning on the second switch.

In order to couple the positive display potential to the first end of the first development capacitor, the first source operational amplifier can be driven by a positive supply potential and a power supply ground. To output the fixed-value common mode potential, the common mode operational amplifier can be driven by the power supply terminal and a negative supply potential.

The above described objects, features, and advantages of the invention will be apparent from the description and appended claims appended claims

The following description discloses various embodiments of the invention, and is intended to be in the scope of the invention. The scope of the invention should be referred to the scope of the patent application.

2 is a block diagram illustrating a liquid crystal display 200 implemented in accordance with an embodiment of the present invention. The liquid crystal display 200 includes a liquid crystal pixel array 202 and a driving circuit 204. The driving circuit 204 includes a gate driver 206, a source driver 208, a common mode potential driver 210, and a timing controller 212. The gate driver 206 is controlled by the timing controller 212 to scan the liquid crystal pixel array 202 column by column. The source driver 208 is controlled by the timing controller 212 to provide a display potential to the pixel being scanned. The common mode potential driver 210 is controlled by the timing controller to supply a common mode potential to the liquid crystal pixel array 202. In the present invention, the circuitry of the common mode potential driver 210 and the control scheme provided by the timing controller 212 are specifically designed to reduce energy consumption.

For convenience of explanation, the driving circuit discussed herein focuses on two adjacent pixels (in the same column, adjacent rows) on the liquid crystal pixel array 202. However, such a simplified description is not intended to limit the invention. The disclosed structure can be extended in accordance with techniques well known in the art for controlling the entire liquid crystal pixel array.

FIG. 3A illustrates two adjacent pixels on the liquid crystal pixel array 202. The two pixels are respectively named as a first pixel P1 and a second pixel P2, and are located in two rows on the same column of the liquid crystal pixel array 202. In the previous screen, the first pixel P1 is negative polarity and the second pixel P2 is positive polarity. After switching to the new screen (current screen), the first pixel P1 is switched to the positive polarity and the second pixel P2 is switched to the negative polarity. In order to drive the first pixel P1 for positive polarity development and drive the second pixel P2 for negative polarity development, FIG. 3B discloses a driving circuit that consumes much less energy than conventional techniques.

Referring to FIG. 3B, the first developing capacitor C1 and the second developing capacitor C2 respectively represent the first pixel P1 and the second pixel P2 of FIG. 3A. The first developing capacitor C1 can be a liquid crystal capacitor provided by the first pixel P1. The second developing capacitor C2 can be a liquid crystal capacitor provided by the second pixel P2. The first end of the first developing capacitor C1 is labeled Source1, the first end of the second developing capacitor C2 is labeled Source2, and the second end of the first developing capacitor C1 and the second end of the second developing capacitor C2 Linked together to a common mode endpoint VCOM.

In addition to the first and second developing capacitors C1 and C2, FIG. 3B further shows a first source operational amplifier 302, a second source operational amplifier 304, a common mode potential operational amplifier 306, a first switch SW1, and A second switch SW2.

The first and second source operational amplifiers 302 and 304 are supplied from the second source driver 208. In order to drive the first pixel P1 of the first development capacitor C1 with a positive polarity, the first source operational amplifier 302 can be powered by the positive supply potential VDDA and the power supply ground VSSA, and a positive development potential Data1 is transmitted to The first source operational amplifier 302. When the first pixel P1 is scanned and the coupling of the positive display potential Data1 to the first end Source1 of the first development capacitor C1 is allowed, the positive development potential Data1 is calculated by the first source. The amplifier 302 is coupled to the first end Source1 of the first developing capacitor C1 to charge the first developing capacitor C1 to provide positive polarity development. In order to drive the second pixel P2 of the second developing capacitor C2 with a negative polarity, the second source operational amplifier 304 can be powered by the power ground terminal VSSA and the negative value power supply potential nVDDA, and a negative polarity developing potential Data2 is It is transmitted to the second source operational amplifier 304. When the second pixel P2 is scanned and the coupling of the negative display potential Data2 to the first end Source2 of the second development capacitor C2 is allowed, the second source operational amplifier 304 displays the negative polarity The potential Data2 is coupled to the first end Source2 of the second developing capacitor C2 to discharge the second developing capacitor C2 to achieve negative polarity development.

The common mode potential operational amplifier 306, the first switch SW1, and the second switch SW2 shown in FIG. 3B are supplied from the common mode potential driver 210 shown in FIG. Referring to FIG. 3B, the operation of the common mode potential operational amplifier 306, the first switch SW1, and the second switch SW2 will be discussed below. The common mode potential operational amplifier 306 can be powered by the power supply ground VSSA and the negative power supply potential nVDDA for outputting a certain value common mode potential DCVCOM. When the first switch SW1 is turned on, the second ends of the first and second developing capacitors C1 and C2 (also referred to as common mode end points, VCOM) are grounded to GND. The second switch SW2 is coupled to the constant-value common-mode potential DCVCOM supplied by the common-mode potential operational amplifier 306 to the second terminal VCOM of the first and second developing capacitors C1 and C2.

By arranging the positive polarity imaging potential Data1 to be coupled to the first end Source1 of the first developing capacitor C1, the negative imaging potential Data2 is coupled to the first end Source2 of the second developing capacitor C2. At the time point of the connection, and the state of controlling the first and the second switches SW1 and SW2, the energy consumption of the overall driving circuit can be greatly reduced. The timing control provided by the timing controller 212 of FIG. 2 is used to control the coupling between Data1 and Source1, the coupling between Data2 and Source2, and the switching of switches SW1 and SW2.

Referring to FIG. 3B, FIG. 4 illustrates the potentials of the endpoints Source1, Source2, and VCOM, the states of the first and second switches SW1 and SW2, the positive polarity charging timing of the first pixel P1, and the second pixel in a waveform diagram. The negative discharge timing of P2.

As shown, the first switch SW1 is non-conducting most of the time, the second switch SW2 is turned on most of the time, and the potential of the common mode terminal VCOM is fixed to the constant value supplied by the common mode operational amplifier 306 most of the time. Total Mode potential DCVCOM. When switching from the previous screen to the new screen, the conduction of the first switch SW1 and the non-conduction of the second switch SW2 can adjust the common mode terminal VCOM to the ground potential GND. The contents are detailed below.

In the previous picture, the first terminal Source1 of the first developing capacitor C1 is negative (the potential is lower than the potential of the common mode terminal VCOM), and the potential of the first terminal Source2 of the second developing capacitor C2 is positive. (The potential is higher than the potential of the common mode terminal VCOM). Before displaying a new picture, the first ends Source1 and Source2 of the first and second developing capacitors C1 and C2 may be grounded to discharge the first and second developing capacitors C1 and C2 to cope with the reverse polarity Transfer program. At the same time, the first switch SW1 can be turned on and the second switch SW2 can be switched to be non-conducting, so that the second ends of the first and second developing capacitors C1 and C2 (the common mode end point, the label VCOM) are grounded (adjusted to GND), the first and second developing capacitors C1 and C2 can thus be discharged to zero potential.

After the endpoints Source1, Source2, and VCOM are all adjusted to the ground potential GND, the first and second pixels P1 and P2 supplying the first and second developing capacitors C1 and C2 are scanned to develop a new one. Picture. When the first pixel P1 is scanned and the charging of the first developing capacitor C1 is enabled according to the positive imaging potential Data1, the positive display potential Data1 and the first end of the first developing capacitor C1 are enabled. The coupling relationship of Source1 is established via the first source operational amplifier 302. As shown, the first developing capacitor C1 is charged, and the potential of the first terminal Source1 of the first developing capacitor C1 is boosted for positive polarity development. When the array scan proceeds to the next column, the positive display potential Data1 and the first end Source1 of the first development capacitor C1 are turned off, and the potential of the end point Source1 may stop rising. Further, in some embodiments, At this point, the connection formed by the first switch SW1 can be disconnected and the second switch SW2 can be turned on to adjust the common mode end point VCOM back to the constant value common mode potential DCVCOM.

This section discusses the timing of coupling the negative imaging potential Data2 to the first terminal Source2 of the second developing capacitor C2 to discharge the second developing capacitor C2 according to the negative developing potential Data2. Referring to the waveform at the bottom of FIG. 4, the coupling relationship between the negative imaging potential Data2 and the second developing capacitor C2 can be coupled to the first terminal Source1 of the first developing capacitor C1 at the positive developing potential Data1. After the array, it is established by the second source operational amplifier 304. As shown, the potential of the endpoint Source2 is pulled down for negative polarity display. In summary, when the first and second developing capacitors C1 and C2 are scanned to develop a new picture, the timing of establishing the coupling relationship between the positive imaging potential Data1 and the end point Source1 may be earlier than the negative polarity imaging. The coupling action between the potential Data2 and the endpoint Source2.

The following paragraphs discuss why the control scheme described in Figure 4 can significantly reduce energy consumption. Hereinafter, the charging path of the first developing capacitor C1 of the first pixel P1 will be briefly described as an example.

If the positive display potential Data1 is coupled to the first terminal Source1 of the first development capacitor C1, the conduction of the first switch SW1 and the non-conduction of the second switch SW2 form a charging path of the first development capacitor C1 as shown in FIG. 5A. And the non-conduction of the first switch SW1 and the conduction of the second switch SW2 form a charging path of the first developing capacitor C1 as shown in FIG. 5B.

Referring to FIG. 5A, according to the time interval T1 of FIG. 4, the charging current flows from the positive supply potential VDDA of the first source operational amplifier 302 to the first developing capacitor C1, and finally to the ground potential GND. As a result, when the endpoint Source1 is charged from the ground potential GND to the positive polarity level, the current path does not involve the common mode operational amplifier 306. Therefore, the potential change experienced on the charging path is (VDDA-GND), which is much smaller than the potential variation experienced by conventional techniques (VDDA-nVDDA). Energy consumption is thus reduced.

In the example of FIG. 5B, with respect to the time interval T2 of FIG. 4, the charging path flows from the first source operational amplifier 302 positive supply potential VDDA to the first development capacitor C1, and finally to the common mode potential operational amplifier 306. Negative supply potential nVDDA. Fortunately, although there is a considerable potential change in such a current path (from the positive supply potential VDDA of the first source operational amplifier 302 to the negative supply potential nVDDA of the common mode potential operational amplifier 306), the capacitive charging path is still not Excessive energy consumption. The reason is that the common mode end point VCOM only needs a small amount of potential adjustment at this time (adjusted from the ground potential GND to the fixed value common mode potential DCVCOM). Therefore, the energy consumption is greatly improved compared to the conventional technology.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

200. . . LCD Monitor

202. . . Liquid crystal pixel array

204. . . Drive circuit

206. . . Gate driver

208. . . Source driver

210. . . Common mode potential driver

212. . . Timing controller

302, 304. . . First and second source operational amplifiers

306. . . Common mode potential operational amplifier

C1, C2. . . First and second developing capacitors

Data1, Data2. . . Positive and negative imaging potential

DCVCOM. . . Fixed common mode potential

GND. . . Ground

nVDDA. . . Negative supply potential

P1, P2. . . First and second pixels

Source1, Source2. . . First ends of the first and second developing capacitors C1 and C2

SW1, SW2. . . First and second switches

T1, T2. . . Time interval

VCOM. . . Common mode endpoint

VDDA. . . Positive supply potential

VSSA. . . Power ground

Figure 1A illustrates a point inversion technique;

Figure 1B illustrates a one-line inversion technique;

Figure 2 is a block diagram illustrating a liquid crystal display 200 implemented in accordance with an embodiment of the present invention;

FIG. 3A illustrates two adjacent pixels on the liquid crystal pixel array 202 in the same column and adjacent rows;

FIG. 3B illustrates two adjacent pixels P1 and P2 of FIG. 3A using two developing capacitors C1 and C2, and illustrates a basic driving circuit of the two adjacent pixels;

4 is a waveform diagram illustrating the potentials of the endpoints Source1, Source2, VCOM, the states of the first switch SW1 and the second switch SW2, the positive charging timing of the first pixel P1, and the negative charging timing of the second pixel P2;

5A illustrates a charging path of the first developing capacitor C1, wherein the first switch SW1 is turned on and the second switch SW2 is not turned on, and a coupling state between the positive developing potential Data1 and the end point Source1 is established;

FIG. 5B illustrates a charging path of the first developing capacitor C1, in which the first switch SW1 is not turned on and the second switch SW2 is turned on, and the coupling state between the positive developing potential Data1 and the end point Source1 is established.

302, 304. . . First and second source operational amplifiers

306. . . Common mode potential operational amplifier

C1, C2. . . First and second developing capacitors

Data1, Data2. . . Positive and negative imaging potential

DCVCOM. . . Fixed common mode potential

GND. . . Ground

nVDDA. . . Negative supply potential

Source1, Source2. . . First ends of the first and second developing capacitors C1 and C2

SW1, SW2. . . First and second switches

VCOM. . . Common mode endpoint

VDDA. . . Positive supply potential

VSSA. . . Power ground

Claims (8)

A driving circuit for driving a liquid crystal pixel array, comprising: a source driver comprising a first source operational amplifier and a second source operational amplifier, wherein a first display is provided in the liquid crystal pixel array The first source operational amplifier is coupled when a first pixel of the capacitor is scanned for positive polarity development and a positive display potential and a first end of the first display capacitor are coupled. The positive display potential is to the first end of the first developing capacitor, and a second pixel that supplies a second developing capacitor in the liquid crystal pixel array is scanned for negative polarity display and a negative polarity display The second source operational amplifier is coupled to the negative imaging potential to the first end of the second developing capacitor when the coupling of the potential and the first terminal of the second developing capacitor is allowed; The mode potential driver includes: a common mode potential operational amplifier that outputs a certain value of a common mode potential; a first switch that couples a second end of the first display capacitor to the ground when turned on; and a second switch , when the conduction is turned on The common mode potential is coupled to the second end of the first display capacitor, wherein the common mode potential driver further comprises the second end of the first developing capacitor and the second developing capacitor An electrical connection between the two ends is coupled to the second end of the second developing capacitor; and a timing controller that determines when the positive developing potential and the first developing capacitor are allowed to be the first end Coupling relationship, more decide when to allow the negative A coupling between the polarity developing potential and the first end of the second developing capacitor, and controlling states of the first and second switches to reduce energy consumption of the driving circuit. The driving circuit of claim 1, wherein the timing controller turns on the first switch when the positive display potential and the coupling relationship of the first terminal of the first developing capacitor are established. The second switch is not turned on; and the timing controller maintains the first switch to be on and maintains the second switch to be non-conducting until the positive display potential and the first end of the first display capacitor are coupled disconnect. The driving circuit of claim 2, wherein the timing controller discharges the first developing capacitor to a zero potential by turning on the first switch and not turning on the second switch. The driving circuit of claim 1, wherein: the first source operational amplifier is powered by a positive power supply potential and a power supply ground; and the common mode operational amplifier is terminated by the power supply terminal and a negative value Power supply potential supply. The driving circuit of claim 2, wherein the timing controller allows the coupling relationship between the positive display potential and the first end of the first developing capacitor to be disconnected a coupling relationship between the negative imaging potential and the first end of the second developing capacitor. The driving circuit of claim 5, wherein the timing controller further discharges the first and second developing capacitors to a zero level by turning on the first switch and not turning on the second switch. . The driving circuit of claim 4, wherein the second source operational amplifier is powered by the power supply ground and the negative power supply potential to couple the negative potential to the second display Like the first end of the capacitor. A liquid crystal display comprising: the driving circuit according to claim 1; and the liquid crystal pixel array driven by the driving circuit.