TWI433129B - Liquid crystal display and driving circuit thereof - Google Patents
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Description
本發明係有關於液晶顯示器(LCD),且特別有關於驅動該液晶顯示器的驅動電路。The present invention relates to a liquid crystal display (LCD), and more particularly to a driving circuit for driving the liquid crystal display.
液晶顯示器為薄型電子顯像裝置,利用的是液晶物質的光調適功能。液晶物質本身並不會發射光線。影像的顯示是藉控制液晶物質的穿透性(transmission)完成。The liquid crystal display is a thin electronic display device that utilizes the light adjustment function of the liquid crystal material. The liquid crystal material itself does not emit light. The display of the image is done by controlling the transmission of the liquid crystal material.
對每一個液晶像素,光線的穿透性是由施加於其上的電壓大小決定。為了防止液晶物質被偏極化(polarization),連續視訊畫面中,作用於同一像素的電壓需為相反極性。目前已發展有多種極性反轉技術,包括線反轉(line inversion)、點反轉(dot inversion)以及行反轉(column inversion)。For each liquid crystal pixel, the penetration of light is determined by the amount of voltage applied to it. In order to prevent the liquid crystal material from being polarized, the voltage applied to the same pixel in the continuous video picture needs to be of opposite polarity. A variety of polarity inversion techniques have been developed, including line inversion, dot inversion, and column inversion.
極性反轉技術通常需要參考一共模電位(common voltage)。若施加於像素上的電位高於該共模電位,則稱之為正極性顯像。若施加於像素上的電位低於該共模電位,則稱之為負極性顯像。以點反轉技術(參考第1A圖)、或行反轉技術(參考第1B圖)為例,每切換到下一個畫面,各個像素的極性就必須反轉,此外,同一列且相鄰行的相鄰兩個像素(例如第一像素P1以及第二像素P2)必須彼此為相反極性。由於如第一與第二像素P1與P2這樣位於同一列的像素可能會共用同樣的共模電位來源,此共模電位必須被固定在固定值,通常稱之為定值共模電位(DC VCOM)。然而,此定值共模電位可能使液晶顯示器的驅動電路產生無謂的能量消耗。以下發明內容所列舉的實施方式即是在討論此能量消耗,並且揭露消除所述能量消耗的技術。Polarity inversion techniques typically require reference to a common voltage. If the potential applied to the pixel is higher than the common mode potential, it is called positive polarity development. If the potential applied to the pixel is lower than the common mode potential, it is called negative polarity development. Taking the dot inversion technique (refer to Figure 1A) or the row inversion technique (refer to Figure 1B) as an example, the polarity of each pixel must be inverted every time it switches to the next screen. In addition, the same column and adjacent rows The adjacent two pixels (for example, the first pixel P1 and the second pixel P2) must be opposite to each other. Since pixels such as the first and second pixels P1 and P2 in the same column may share the same common mode potential source, the common mode potential must be fixed at a fixed value, which is commonly referred to as a fixed-value common mode potential (DC VCOM). ). However, this constant value of the common mode potential may cause unnecessary power consumption of the driving circuit of the liquid crystal display. The embodiments listed in the following summary are discussing this energy consumption and revealing techniques for eliminating the energy consumption.
以下揭露一種液晶顯示器以及其中驅動電路。A liquid crystal display and a driving circuit therefor are disclosed below.
所述驅動電路是用於驅動所述液晶顯示器的一液晶像素陣列。該驅動電路至少包括一源極驅動器(source driver)、一共模電位驅動器(VCOM driver)以及一時序控制器(timing controller)。The driving circuit is a liquid crystal pixel array for driving the liquid crystal display. The driving circuit includes at least a source driver, a common mode potential driver (VCOM driver), and a timing controller.
所述源極驅動器包括一第一源極運算放大器。當該液晶像素陣列內供應一第一顯像電容的一第一像素被掃描作正極性顯像、且一正極性顯像電位與該第一顯像電容的一第一端點之耦接被允許時,該第一源極運算放大器耦接該正極性顯像電位給該第一顯像電容的該第一端點。The source driver includes a first source operational amplifier. A first pixel that supplies a first developing capacitor in the liquid crystal pixel array is scanned for positive polarity development, and a positive display potential is coupled to a first end of the first developing capacitor When allowed, the first source operational amplifier is coupled to the positive display potential to the first terminal of the first display capacitor.
該共模電位驅動器包括一共模電位運算放大器、一第一開關以及一第二開關。該共模電位運算放大器輸出一定值共模電位。該第一開關於導通時耦接該第一顯像電容的一第二端點至一接地點。至於該第二開關,則是設計來於導通時耦接該定值共模電位(該共模運算放大器之輸出端)至該第一顯像電容的該第二端點。The common mode potential driver includes a common mode potential operational amplifier, a first switch, and a second switch. The common mode potential operational amplifier outputs a certain value of the common mode potential. The first switch is coupled to a second end of the first display capacitor to a ground point when turned on. The second switch is designed to be coupled to the constant-valued common mode potential (the output of the common mode operational amplifier) to the second end of the first display capacitor when turned on.
該時序控制器之是設計將降低能量消耗。該時序控制器會判斷何時允許該正極性顯像電位耦接該第一顯像電容的該第一端,且更控制該第一以及該第二開關的狀態。The timing controller is designed to reduce energy consumption. The timing controller determines when the positive development potential is allowed to couple the first end of the first development capacitor, and further controls the states of the first and the second switches.
在一種實施方式中,當該正極性顯像電位與該第一顯像電容的該第一端之耦接建立時,該時序控制器導通該第一開關且不導通該第二開關。所揭露之結構會維持該第一開關之導通狀態以及該第二開關之不導通狀態直至該正極性顯像電位與該第一顯像電容的該第一端之間的連結被斷開。在一些實施方式中,該時序控制器更藉由導通該第一開關且不導通該第二開關放電該第一顯像電容至零電位。In one embodiment, when the positive polarity development potential is coupled to the first end of the first development capacitor, the timing controller turns on the first switch and does not turn on the second switch. The disclosed structure maintains the conductive state of the first switch and the non-conducting state of the second switch until the connection between the positive developing potential and the first end of the first developing capacitor is broken. In some embodiments, the timing controller further discharges the first imaging capacitor to a zero potential by turning on the first switch and not turning on the second switch.
為了耦接該正極性顯像電位至該第一顯像電容的該第一端,該第一源極運算放大器可由一正值供電電位以及一電源地端驅動。為了輸出該定值共模電位,該共模運算放大器可由該電源地端以及一負值供電電位驅動。In order to couple the positive display potential to the first end of the first development capacitor, the first source operational amplifier can be driven by a positive supply potential and a power supply ground. To output the fixed-value common mode potential, the common mode operational amplifier can be driven by the power supply terminal and a negative supply potential.
為使本發明之上述目的、特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖示,詳細說明如下。The above described objects, features, and advantages of the invention will be apparent from the description and appended claims appended claims
以下說明揭露本發明多種實施方式,內容是關於本發明的主要精神,並非意圖限定本發明的範圍。本發明的範疇應當要參考申請專利範圍的內容。The following description discloses various embodiments of the invention, and is intended to be in the scope of the invention. The scope of the invention should be referred to the scope of the patent application.
第2圖以一方塊圖圖解根據本發明一種實施方式所實現的一液晶顯示器200。該液晶顯示器200包括一液晶像素陣列202以及一驅動電路204。該驅動電路204包括一閘極驅動器206、一源極驅動器208、一共模電位驅動器210以及一時序控制器212。閘極驅動器206是由該時序控制器212控制,以逐列掃描該液晶像素陣列202。該源極驅動器208由該時序控制器212控制,以提供顯像電位給正被掃描的像素。共模電位驅動器210是由該時序控制器控制,以供應共模電位給該液晶像素陣列202。在本發明中,共模電位驅動器210的電路以及時序控制器212所提供的控制方案是特別設計來降低能量消耗。2 is a block diagram illustrating a liquid crystal display 200 implemented in accordance with an embodiment of the present invention. The liquid crystal display 200 includes a liquid crystal pixel array 202 and a driving circuit 204. The driving circuit 204 includes a gate driver 206, a source driver 208, a common mode potential driver 210, and a timing controller 212. The gate driver 206 is controlled by the timing controller 212 to scan the liquid crystal pixel array 202 column by column. The source driver 208 is controlled by the timing controller 212 to provide a display potential to the pixel being scanned. The common mode potential driver 210 is controlled by the timing controller to supply a common mode potential to the liquid crystal pixel array 202. In the present invention, the circuitry of the common mode potential driver 210 and the control scheme provided by the timing controller 212 are specifically designed to reduce energy consumption.
為了方便說明,此處所討論的驅動電路著重於液晶像素陣列202上相鄰的兩個像素(在同一列、相鄰行)。然而,這樣的簡化說明並不是意圖限定發明內容。所揭露的結構可依照本技術領域所熟知技術擴展,以用於控制整個液晶像素陣列。For convenience of explanation, the driving circuit discussed herein focuses on two adjacent pixels (in the same column, adjacent rows) on the liquid crystal pixel array 202. However, such a simplified description is not intended to limit the invention. The disclosed structure can be extended in accordance with techniques well known in the art for controlling the entire liquid crystal pixel array.
第3A圖圖解液晶像素陣列202上兩個相鄰的像素。所述兩個像素分別命名為一第一像素P1以及一第二像素P2,且位在該液晶像素陣列202同一列上相鄰兩行。在前一個畫面中,第一像素P1為負極性且第二像素P2為正極性。切換至新的畫面(目前畫面)後,第一像素P1切換為正極性且第二像素P2切換為負極性。為了驅動該第一像素P1作正極性顯像、且驅動該第二像素P2作負極性顯像,第3B圖揭露一驅動電路,其所消耗的能量遠低於傳統技術。FIG. 3A illustrates two adjacent pixels on the liquid crystal pixel array 202. The two pixels are respectively named as a first pixel P1 and a second pixel P2, and are located in two rows on the same column of the liquid crystal pixel array 202. In the previous screen, the first pixel P1 is negative polarity and the second pixel P2 is positive polarity. After switching to the new screen (current screen), the first pixel P1 is switched to the positive polarity and the second pixel P2 is switched to the negative polarity. In order to drive the first pixel P1 for positive polarity development and drive the second pixel P2 for negative polarity development, FIG. 3B discloses a driving circuit that consumes much less energy than conventional techniques.
參閱第3B圖,第一顯像電容C1以及第二顯像電容C2分別代表第3A圖的第一像素P1以及第二像素P2。第一顯像電容C1可為第一像素P1所提供的一液晶電容。第二顯像電容C2可為第二像素P2所提供的一液晶電容。第一顯像電容C1的第一端標號為Source1,第二顯像電容C2的第一端標號為Source2,且第一顯像電容C1的第二端以及第二顯像電容C2的第二端一同連結至一共模端點VCOM。Referring to FIG. 3B, the first developing capacitor C1 and the second developing capacitor C2 respectively represent the first pixel P1 and the second pixel P2 of FIG. 3A. The first developing capacitor C1 can be a liquid crystal capacitor provided by the first pixel P1. The second developing capacitor C2 can be a liquid crystal capacitor provided by the second pixel P2. The first end of the first developing capacitor C1 is labeled Source1, the first end of the second developing capacitor C2 is labeled Source2, and the second end of the first developing capacitor C1 and the second end of the second developing capacitor C2 Linked together to a common mode endpoint VCOM.
除了上述第一以及第二顯像電容C1以及C2,第3B圖更顯示一第一源極運算放大器302、一第二源極運算放大器304、一共模電位運算放大器306、一第一開關SW1以及一第二開關SW2。In addition to the first and second developing capacitors C1 and C2, FIG. 3B further shows a first source operational amplifier 302, a second source operational amplifier 304, a common mode potential operational amplifier 306, a first switch SW1, and A second switch SW2.
上述第一以及第二源極運算放大器302以及304是由第2圖源極驅動器208供應。為了以正極性驅動供應該第一顯像電容C1的第一像素P1,第一源極運算放大器302可由正值供電電位VDDA以及電源地端VSSA供電,且一正極性顯像電位Data1被傳送給該第一源極運算放大器302。當掃描該第一像素P1、且該正極性顯像電位Data1至該第一顯像電容C1之第一端Source1的耦接被允許時,正極性顯像電位Data1會經該第一源極運算放大器302耦接到第一顯像電容C1的第一端Source1,以充電該第一顯像電容C1提供正極性顯像。為了以負極性驅動供應該第二顯像電容C2的該第二像素P2,,第二源極運算放大器304可由電源地端VSSA以及負值供電電位nVDDA供電,且一負極性顯像電位Data2被傳送給該第二源極運算放大器304。當掃描該第二像素P2、且該負極性顯像電位Data2至該第二顯像電容C2之第一端Source2的耦接被允許時,該第二源極運算放大器304將該負極性顯像電位Data2耦接到第二顯像電容C2的第一端Source2,以放電該第二顯像電容C2實現負極性顯像。The first and second source operational amplifiers 302 and 304 are supplied from the second source driver 208. In order to drive the first pixel P1 of the first development capacitor C1 with a positive polarity, the first source operational amplifier 302 can be powered by the positive supply potential VDDA and the power supply ground VSSA, and a positive development potential Data1 is transmitted to The first source operational amplifier 302. When the first pixel P1 is scanned and the coupling of the positive display potential Data1 to the first end Source1 of the first development capacitor C1 is allowed, the positive development potential Data1 is calculated by the first source. The amplifier 302 is coupled to the first end Source1 of the first developing capacitor C1 to charge the first developing capacitor C1 to provide positive polarity development. In order to drive the second pixel P2 of the second developing capacitor C2 with a negative polarity, the second source operational amplifier 304 can be powered by the power ground terminal VSSA and the negative value power supply potential nVDDA, and a negative polarity developing potential Data2 is It is transmitted to the second source operational amplifier 304. When the second pixel P2 is scanned and the coupling of the negative display potential Data2 to the first end Source2 of the second development capacitor C2 is allowed, the second source operational amplifier 304 displays the negative polarity The potential Data2 is coupled to the first end Source2 of the second developing capacitor C2 to discharge the second developing capacitor C2 to achieve negative polarity development.
第3B圖所示的共模電位運算放大器306、第一開關SW1以及第二開關SW2是由第2圖所示之共模電位驅動器210所供應。參考第3B圖,以下討論共模電位運算放大器306、第一開關SW1以及第二開關SW2的操作。共模電位運算放大器306可由電源地端VSSA以及負值供電電位nVDDA供電,用以輸出一定值共模電位DCVCOM。該第一開關SW1於導通時將該第一以及該第二顯像電容C1以及C2的第二端(又稱共模端點,標號VCOM)接地GND。第二開關SW2於導通時耦接該共模電位運算放大器306所供應的該定值共模電位DCVCOM至該第一以及該第二顯像電容C1以及C2的第二端VCOM。The common mode potential operational amplifier 306, the first switch SW1, and the second switch SW2 shown in FIG. 3B are supplied from the common mode potential driver 210 shown in FIG. Referring to FIG. 3B, the operation of the common mode potential operational amplifier 306, the first switch SW1, and the second switch SW2 will be discussed below. The common mode potential operational amplifier 306 can be powered by the power supply ground VSSA and the negative power supply potential nVDDA for outputting a certain value common mode potential DCVCOM. When the first switch SW1 is turned on, the second ends of the first and second developing capacitors C1 and C2 (also referred to as common mode end points, VCOM) are grounded to GND. The second switch SW2 is coupled to the constant-value common-mode potential DCVCOM supplied by the common-mode potential operational amplifier 306 to the second terminal VCOM of the first and second developing capacitors C1 and C2.
藉由安排該正極性顯像電位Data1與該第一顯像電容C1之第一端Source1耦接的時間點、該負極性顯像電位Data2與該第二顯像電容C2之第一端Source2耦接的時間點、以及控制該第一以及該第二開關SW1以及SW2之狀態,整體驅動電路的能量消耗可被大幅降低。第2圖的時序控制器212所提供的時序控制即是用來控制Data1以及Source1之間的耦接、Data2以及Source2之間的耦接、以及開關SW1以及SW2之切換。By arranging the positive polarity imaging potential Data1 to be coupled to the first end Source1 of the first developing capacitor C1, the negative imaging potential Data2 is coupled to the first end Source2 of the second developing capacitor C2. At the time point of the connection, and the state of controlling the first and the second switches SW1 and SW2, the energy consumption of the overall driving circuit can be greatly reduced. The timing control provided by the timing controller 212 of FIG. 2 is used to control the coupling between Data1 and Source1, the coupling between Data2 and Source2, and the switching of switches SW1 and SW2.
參考第3B圖,第4圖以波形圖說明端點Source1、Source2以及VCOM的電位、該第一以及該第二開關SW1與SW2之狀態、第一像素P1之正極性充電時序、以及第二像素P2之負極性放電時序。Referring to FIG. 3B, FIG. 4 illustrates the potentials of the endpoints Source1, Source2, and VCOM, the states of the first and second switches SW1 and SW2, the positive polarity charging timing of the first pixel P1, and the second pixel in a waveform diagram. The negative discharge timing of P2.
如圖所示,第一開關SW1大多數時間是不導通,第二開關SW2大多數時間是導通,且共模端點VCOM之電位大多數時候是固定在共模運算放大器306所供應的定值共 模電位DCVCOM。由前一個畫面切換到新的畫面時,第一開關SW1的導通以及第二開關SW2的不導通可將共模端點VCOM調適至地端電位GND。以下詳述其內容。As shown, the first switch SW1 is non-conducting most of the time, the second switch SW2 is turned on most of the time, and the potential of the common mode terminal VCOM is fixed to the constant value supplied by the common mode operational amplifier 306 most of the time. Total Mode potential DCVCOM. When switching from the previous screen to the new screen, the conduction of the first switch SW1 and the non-conduction of the second switch SW2 can adjust the common mode terminal VCOM to the ground potential GND. The contents are detailed below.
在前一個畫面中,第一顯像電容C1的第一端Source1為負極性(電位低於共模端點VCOM之電位),且第二顯像電容C2的第一端Source2之電位為正極性(電位高於共模端點VCOM之電位)。在顯示新的一個畫面前,第一以及第二顯像電容C1以及C2之第一端Source1以及Source2可被接地以放電該第一以及該第二顯像電容C1以及C2,應付接續的極性反轉程序。同時,第一開關SW1可被導通且第二開關SW2可切換為不導通,以使第一以及第二顯像電容C1以及C2之第二端(共模端點,標號VCOM)接地(調整到GND),第一以及第二顯像電容C1與C2因而可放電至零電位。In the previous picture, the first terminal Source1 of the first developing capacitor C1 is negative (the potential is lower than the potential of the common mode terminal VCOM), and the potential of the first terminal Source2 of the second developing capacitor C2 is positive. (The potential is higher than the potential of the common mode terminal VCOM). Before displaying a new picture, the first ends Source1 and Source2 of the first and second developing capacitors C1 and C2 may be grounded to discharge the first and second developing capacitors C1 and C2 to cope with the reverse polarity Transfer program. At the same time, the first switch SW1 can be turned on and the second switch SW2 can be switched to be non-conducting, so that the second ends of the first and second developing capacitors C1 and C2 (the common mode end point, the label VCOM) are grounded (adjusted to GND), the first and second developing capacitors C1 and C2 can thus be discharged to zero potential.
在端點Source1、Source2以及VCOM全被調整到地端電位GND後,供應該第一以及該第二顯像電容C1以及C2的第一以及第二像素P1以及P2被掃描,以顯像新的畫面。當該第一像素P1被掃描、且根據該正極性顯像電位Data1充電該第一顯像電容C1的動作被致能時,正極性顯像電位Data1以及第一顯像電容C1之第一端Source1之耦接關係經由該第一源極運算放大器302建立。如圖所示,第一顯像電容C1被充電,且第一顯像電容C1之第一端Source1之電位被提升以作正極性顯像。當所述陣列掃描進行到下一列時,正極性顯像電位Data1以及第一顯像電容C1之第一端Source1斷開,端點Source1的電位可停止上升,此外,在某些實施方式中,此刻可用來斷開第一開關SW1所形成的連結且導通第二開關SW2,以調整該共模端點VCOM回到該定值共模電位DCVCOM。After the endpoints Source1, Source2, and VCOM are all adjusted to the ground potential GND, the first and second pixels P1 and P2 supplying the first and second developing capacitors C1 and C2 are scanned to develop a new one. Picture. When the first pixel P1 is scanned and the charging of the first developing capacitor C1 is enabled according to the positive imaging potential Data1, the positive display potential Data1 and the first end of the first developing capacitor C1 are enabled. The coupling relationship of Source1 is established via the first source operational amplifier 302. As shown, the first developing capacitor C1 is charged, and the potential of the first terminal Source1 of the first developing capacitor C1 is boosted for positive polarity development. When the array scan proceeds to the next column, the positive display potential Data1 and the first end Source1 of the first development capacitor C1 are turned off, and the potential of the end point Source1 may stop rising. Further, in some embodiments, At this point, the connection formed by the first switch SW1 can be disconnected and the second switch SW2 can be turned on to adjust the common mode end point VCOM back to the constant value common mode potential DCVCOM.
此段討論耦接該負極性顯像電位Data2至該第二顯像電容C2的第一端Source2之時機,以根據該負極性顯像電位Data2放電該第二顯像電容C2。參閱第4圖最下方的波形,負極性顯像電位Data2以及第二顯像電容C2的耦接關係可在該正極性顯像電位Data1耦接該第一顯像電容C1之第一端Source1一陣子後,由該第二源極運算放大器304建立。如圖所示,端點Source2的電位被下拉以作負極性顯示。總結之,當第一以及第二顯像電容C1以及C2被掃描以顯像新的畫面時,正極性顯像電位Data1與端點Source1之間耦接關係的建立時機可早於負極性顯像電位Data2與端點Source2之間的耦接動作。This section discusses the timing of coupling the negative imaging potential Data2 to the first terminal Source2 of the second developing capacitor C2 to discharge the second developing capacitor C2 according to the negative developing potential Data2. Referring to the waveform at the bottom of FIG. 4, the coupling relationship between the negative imaging potential Data2 and the second developing capacitor C2 can be coupled to the first terminal Source1 of the first developing capacitor C1 at the positive developing potential Data1. After the array, it is established by the second source operational amplifier 304. As shown, the potential of the endpoint Source2 is pulled down for negative polarity display. In summary, when the first and second developing capacitors C1 and C2 are scanned to develop a new picture, the timing of establishing the coupling relationship between the positive imaging potential Data1 and the end point Source1 may be earlier than the negative polarity imaging. The coupling action between the potential Data2 and the endpoint Source2.
以下段落討論為何第4圖所介紹的控制方案可顯著降低能量耗損。以下以第一像素P1的第一顯像電容C1之充電路徑為例,簡單說明之。The following paragraphs discuss why the control scheme described in Figure 4 can significantly reduce energy consumption. Hereinafter, the charging path of the first developing capacitor C1 of the first pixel P1 will be briefly described as an example.
若正極性顯像電位Data1耦接第一顯像電容C1的第一端Source1,第一開關SW1之導通以及第二開關SW2的不導通會如第5A圖形成第一顯像電容C1的充電路徑,且第一開關SW1的不導通以及第二開關SW2的導通會如第5B圖形成第一顯像電容C1的充電路徑。If the positive display potential Data1 is coupled to the first terminal Source1 of the first development capacitor C1, the conduction of the first switch SW1 and the non-conduction of the second switch SW2 form a charging path of the first development capacitor C1 as shown in FIG. 5A. And the non-conduction of the first switch SW1 and the conduction of the second switch SW2 form a charging path of the first developing capacitor C1 as shown in FIG. 5B.
參考第5A圖,根據第4圖之時間區間T1,充電電流自第一源極運算放大器302之正值供電電位VDDA流向第一顯像電容C1,且最終流向地端電位GND。如此一來,端點Source1自地端電位GND充電至正極性準位時,電流路徑不涉及共模運算放大器306。因此,充電路徑上所經歷的電位變化為(VDDA-GND),遠小於傳統技術所歷經的電位變化(VDDA-nVDDA)。能量耗損因而降低。Referring to FIG. 5A, according to the time interval T1 of FIG. 4, the charging current flows from the positive supply potential VDDA of the first source operational amplifier 302 to the first developing capacitor C1, and finally to the ground potential GND. As a result, when the endpoint Source1 is charged from the ground potential GND to the positive polarity level, the current path does not involve the common mode operational amplifier 306. Therefore, the potential change experienced on the charging path is (VDDA-GND), which is much smaller than the potential variation experienced by conventional techniques (VDDA-nVDDA). Energy consumption is thus reduced.
在第5B圖的例子中,關於第4圖之時間區間T2,充電路徑自第一源極運算放大器302正值供電電位VDDA流向第一顯像電容C1,且最終流向共模電位運算放大器306至負值供電電位nVDDA。所幸,雖然這樣的電流路徑存在相當大的電位變化(自第一源極運算放大器302的正值供電電位VDDA流向共模電位運算放大器306的負值供電電位nVDDA),此電容充電路徑仍然不至於消耗過多能量。原因是共模端點VCOM此時僅需要一小量的電位調整(自地端電位GND調整至定值共模電位DCVCOM)。因此,相較於傳統技術,能量消耗被大幅改善。In the example of FIG. 5B, with respect to the time interval T2 of FIG. 4, the charging path flows from the first source operational amplifier 302 positive supply potential VDDA to the first development capacitor C1, and finally to the common mode potential operational amplifier 306. Negative supply potential nVDDA. Fortunately, although there is a considerable potential change in such a current path (from the positive supply potential VDDA of the first source operational amplifier 302 to the negative supply potential nVDDA of the common mode potential operational amplifier 306), the capacitive charging path is still not Excessive energy consumption. The reason is that the common mode end point VCOM only needs a small amount of potential adjustment at this time (adjusted from the ground potential GND to the fixed value common mode potential DCVCOM). Therefore, the energy consumption is greatly improved compared to the conventional technology.
雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何熟悉此項技藝者,在不脫離本發明之精神和範圍內,當可做些許更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.
200...液晶顯示器200. . . LCD Monitor
202...液晶像素陣列202. . . Liquid crystal pixel array
204...驅動電路204. . . Drive circuit
206...閘極驅動器206. . . Gate driver
208...源極驅動器208. . . Source driver
210...共模電位驅動器210. . . Common mode potential driver
212...時序控制器212. . . Timing controller
302、304...第一、第二源極運算放大器302, 304. . . First and second source operational amplifiers
306...共模電位運算放大器306. . . Common mode potential operational amplifier
C1、C2...第一、第二顯像電容C1, C2. . . First and second developing capacitors
Data1、Data2...正、負極性顯像電位Data1, Data2. . . Positive and negative imaging potential
DCVCOM...定值共模電位DCVCOM. . . Fixed common mode potential
GND...接地GND. . . Ground
nVDDA...負值供電電位nVDDA. . . Negative supply potential
P1、P2...第一、第二像素P1, P2. . . First and second pixels
Source1、Source2...第一、第二顯像電容C1、C2各自的第一端Source1, Source2. . . First ends of the first and second developing capacitors C1 and C2
SW1、SW2...第一、第二開關SW1, SW2. . . First and second switches
T1、T2...時間區間T1, T2. . . Time interval
VCOM...共模端點VCOM. . . Common mode endpoint
VDDA...正值供電電位VDDA. . . Positive supply potential
VSSA...電源地端VSSA. . . Power ground
第1A圖說明一點反轉技術;Figure 1A illustrates a point inversion technique;
第1B圖說明一行反轉技術;Figure 1B illustrates a one-line inversion technique;
第2圖為一方塊圖,圖解根據本發明一種實施方式所實現的一液晶顯示器200;Figure 2 is a block diagram illustrating a liquid crystal display 200 implemented in accordance with an embodiment of the present invention;
第3A圖圖解液晶像素陣列202上兩個相鄰像素,位於同一列且相鄰行;FIG. 3A illustrates two adjacent pixels on the liquid crystal pixel array 202 in the same column and adjacent rows;
第3B圖採用兩個顯像電容C1以及C2代表第3A圖的兩個相鄰像素P1以及P2,且圖解此二相鄰像素的基本驅動電路;FIG. 3B illustrates two adjacent pixels P1 and P2 of FIG. 3A using two developing capacitors C1 and C2, and illustrates a basic driving circuit of the two adjacent pixels;
第4圖以波形圖圖解端點Source1、Source2、VCOM之電位、第一開關SW1與第二開關SW2之狀態、第一像素P1之正極性充電時序、以及第二像素P2之負極性充電時序;4 is a waveform diagram illustrating the potentials of the endpoints Source1, Source2, VCOM, the states of the first switch SW1 and the second switch SW2, the positive charging timing of the first pixel P1, and the negative charging timing of the second pixel P2;
第5A圖圖解第一顯像電容C1的充電路徑,其中第一開關SW1導通且第二開關SW2不導通、且正極性顯像電位Data1與端點Source1之間的耦接狀態成立;且5A illustrates a charging path of the first developing capacitor C1, wherein the first switch SW1 is turned on and the second switch SW2 is not turned on, and a coupling state between the positive developing potential Data1 and the end point Source1 is established;
第5B圖圖解第一顯像電容C1的充電路徑,其中第一開關SW1不導通且第二開關SW2導通、且正極性顯像電位Data1與端點Source1之間的耦接狀態成立。FIG. 5B illustrates a charging path of the first developing capacitor C1, in which the first switch SW1 is not turned on and the second switch SW2 is turned on, and the coupling state between the positive developing potential Data1 and the end point Source1 is established.
302、304...第一、第二源極運算放大器302, 304. . . First and second source operational amplifiers
306...共模電位運算放大器306. . . Common mode potential operational amplifier
C1、C2...第一、第二顯像電容C1, C2. . . First and second developing capacitors
Data1、Data2...正、負極性顯像電位Data1, Data2. . . Positive and negative imaging potential
DCVCOM...定值共模電位DCVCOM. . . Fixed common mode potential
GND...接地GND. . . Ground
nVDDA...負值供電電位nVDDA. . . Negative supply potential
Source1、Source2...第一、第二顯像電容C1、C2各自的第一端Source1, Source2. . . First ends of the first and second developing capacitors C1 and C2
SW1、SW2...第一、第二開關SW1, SW2. . . First and second switches
VCOM...共模端點VCOM. . . Common mode endpoint
VDDA...正值供電電位VDDA. . . Positive supply potential
VSSA...電源地端VSSA. . . Power ground
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