TW201225053A - Liquid crystal display and driving circuit thereof - Google Patents

Abstract

A driving circuit and a liquid crystal display using the same. In the driving circuit, a first switch and a second switch are provided in a VCOM driver thereof. The first switch is designed to be turned on to ground a VCOM terminal of a display capacitor, and the second switch is designed to be turned on to couple a constant voltage level DC VCOM to the VCOM terminal of the display capacitor. In addition, a timing controller of the driving circuit is designed for reducing power consumption, which controls the statuses of the first and second switches and determines when to allow a positive polarity voltage to be coupled to the display capacitor to charge the display capacitor for positive polarity display.

Description

201225053 VI. Description of the Invention: [Technical Field] The present invention relates to a liquid crystal display (LCD), and more particularly to a driving circuit for driving the liquid crystal display. [Prior Art] A liquid crystal display is a thin electronic display device that utilizes a light-adjusting function of a liquid crystal material. The liquid crystal material itself does not emit light. The display of the image is done by controlling the transmission of the liquid crystal material. For each liquid crystal pixel, the penetration of light is determined by the amount of voltage applied to it. In order to prevent the liquid crystal material from being polarized, the voltage applied to the same pixel in the continuous video plane needs to be opposite in polarity. A variety of polarity inversion techniques have been developed, including line inversion, dot inversion, and column inversion. The polarity inversion technique typically requires reference to a common voltage. If the potential applied to the pixel is higher than the common mode potential, it is referred to as positive polarity development. If the potential applied to the pixel is lower than the common mode potential, it is called negative polarity development. Taking the dot inversion technique (refer to Figure 1A) or the row inversion technique (refer to Figure 1B) as an example, the polarity of each pixel must be inverted every time it is switched to the next facet. In addition, the same column and adjacent The adjacent two pixels of the row (for example, the first pixel P1 and the second pixel P2) must be of opposite polarities to each other. Since the pixels in the same column as the first and second pixels P1 and P2 may share the same common mode potential source, the common mode potential must be fixed at 201225053 at a fixed value 'commonly referred to as a fixed common mode potential ( DC vc〇M). Iron, this fixed-value common-mode potential may cause the (four) circuit of the liquid crystal display to generate energy. The embodiment cited in the following is a technique for predicting the energy miscellaneous and exposing the technique. SUMMARY OF THE INVENTION The following discloses a liquid crystal display and a driving circuit therefor. The drive circuit is a liquid crystal array for driving the liquid crystal display. The driving circuit includes at least a source driver (s_driver) and a common mode potential driver (-one). The source driver includes a first source operational amplifier. When the pixel-array array supplies the first-pixel two-image, and the positive-positive imaging potential and the first-image imaging I: a positive electrode IS:::: the source operational amplifier _ The potential is at the first end of the first-developing capacitance. = Common mode potential driver includes - common mode potential operational amplifier, value = and - second switch. The common mode potential operation is amplified by 11 rounds-set value f. The first switch is turned on _1 display = capacity: : second end point to - ground point. As for the second switch, it is :::: the first time, the value of the common mode electrical common mode operational amplifier 2) to the second end of the younger-developing capacitor. <Transmission" The design of the timing controller is to reduce the energy consumption. In order to determine when the component is controlled, the m-polar imaging potential _ the first image capacitor 201225053 of the first end, and more control - Kind, the state of the younger brother and the younger brother. The post-lei-μ^工申, when the positive-side imaging potential of the first side of the fish-switches and the timing controller does not turn on the conduction state of the switch and the The non-conducting of the two switches is straight = the monochromatic developing potential is turned on with the first terminal of the first developing capacitor. In some embodiments, the timing junction is broken... the first switch discharges the first - The developing capacitor is at zero potential. For the _ red 姊 developing potential to the first - developing power = the first: the source operational amplifier can be driven by a positive supply potential with 2 冤 source. In order to output the fixed value common mode The above-mentioned objects, features and advantages of the present invention can be more clearly understood from the power supply ground and a negative power supply potential, as will be described below with reference to the accompanying drawings. The details are as follows. [Embodiment] The following description discloses the present disclosure. The invention is not intended to limit the scope of the invention. The scope of the invention should be referred to the scope of the patent application. FIG. 2 is a block diagram illustrating an embodiment of the invention. A liquid crystal display 200 is realized. The liquid crystal display 2 includes a liquid crystal pixel array 202 and a driving circuit 2〇4. The driving circuit 204 includes a gate driving H 206, a source driver 2〇8, and a common mode. The potential driver 210 and a timing controller 212. The gate driver 206 is controlled by the timing control 201225053 to scan the liquid crystal pixel array 202 column by column. The source driver 208 is controlled by the timing controller, 212. To provide a developing potential to the pixel being scanned, the common mode potential driver 21 is controlled by the timing controller to supply a common mode potential to the liquid crystal pixel array 2 〇 2. In the present invention, the common mode potential driver 21 The circuit and the control scheme provided by the timing controller 2丨2 are specially designed to reduce energy consumption. For the convenience of 5, the discussion here The moving circuit focuses on two adjacent pixels on the liquid crystal array 202 (in the same column, adjacent rows, however, a simplified description is not intended to limit the invention. The disclosed junctions are expanded as is well known in the art. For the pixel array. The two adjacent pixels on the 3A ® graphic liquid crystal pixel array 2〇2 are named as -th-pixel pi and -second image two P2' and In the liquid crystal pixel array moving the same - two adjacent rows on the column

In the f:, the first pixel P1 is negative and the second pixel P2 is positive: after the knife 2 to the new face (current face), the first pixel P1 is switched to the polarity and the second pixel P2 is switched to the negative Sex. , for positive polarity development, and drive the second pixel? = Figure reveals - the drive circuit, the energy consumed is far lower = technical division 2 K 3 map 'first development capacitor C1 and second development capacitor C2 The first pixel ρι and the second pixel of the 3A 戈 戈 — 像 像 像 can be the first pixel ρι provided by a liquid crystal capacitor _,,, the page image capacitance C2 can be the second pixel? The first end of the second liquid crystal capacitor is labeled s_el, the second end of the second display 201225053 is labeled Source2, and the second end of the first developing capacitor C1 and the second developing capacitor C2 are second. The ends are linked together to a common mode endpoint VCOM. In addition to the first and second developing capacitors C1 and C2, FIG. 3B further shows a first source operational amplifier 302, a second source operational amplifier 304, a common mode potential operational amplifier 306, a first switch SW1, and A second switch SW2. The first and second source operational amplifiers 302 and 304 are supplied from the source driver 208 of FIG. In order to drive the first pixel P1 of the first development capacitor C1 with a positive polarity, the first source operational amplifier 302 can be powered by the positive supply potential VDDA and the power supply ground VSSA, and a positive development potential Data1 is transmitted to The first source operational amplifier 302. When the first pixel P1 is scanned and the positive display potential Data1 is coupled to the first end Source 1 of the first development capacitor C1, the positive display potential Data1 passes through the first source. The operational amplifier 302 is coupled to the first end Source1 of the first developing capacitor C1 to charge the first developing capacitor C1 to provide positive polarity development. In order to drive the second pixel P2 of the second developing capacitor C2 with a negative polarity, the second source operational amplifier 304 can be powered by the power ground terminal VSSA and the negative value power supply potential nVDDA, and a negative polarity developing potential Data2 is It is transmitted to the second source operational amplifier 304. When the second pixel P2 is scanned and the coupling of the negative display potential Data2 to the first end Source2 of the second development capacitor C2 is allowed, the second source operational amplifier 304 images the negative polarity The potential Data2 is coupled to the first end Source2 of the second developing capacitor C2 to discharge the second developing capacitor C2 to achieve negative polarity development. The common mode potential operational amplifier 306, the first switch 201225053 SW1, and the second switch SW2 shown in Fig. 3B are supplied by the common mode potential driving cry 210 shown in Fig. 2. Referring to FIG. 3B, the operation of the common mode potential operation amplification = 306~, the first open_SW1, and the second switch display will be discussed below. The common mode potential shift amplifier 306 can be powered by the power supply ground VSSA and the negative power supply potential nVDDA for outputting a certain value common mode potential DCVC〇M. When the first switch swi is turned on, the first and second developing capacitors ei and the second end of C2 (also referred to as the common mode end point, vc 〇 M) are grounded to qnd.

The second switch SW2 is coupled to the constant-value common-mode potential DCVCOM supplied from the common-mode potential operational amplifier 3〇6 to the second terminals VCOM of the first and second display capacitors C1 and C2. By arranging the positive polarity imaging potential Data1 to be coupled to the first end S〇urcel of the first developing capacitor C1, the negative imaging potential Data2 and the second imaging f-C2 At the time point of the terminal (Μ) and the state of controlling the first and the second switches SW1 and (10), the energy consumption of the overall driving circuit can be greatly reduced.帛2 graph time

The timing control provided by the sequence controller 212 is used to control the coupling between the dca and the sourcel, and between the s〇_2 and the switch SW1 and the switch. (4) Referring to FIG. 3B, FIG. 4 is a waveform diagram illustrating the potentials of the terminals S〇urce:1, Wce2, and VC0M, the state of the first and the second switches SW1 and SW2, and the positive charging timing of the first pixel ρι. The negative discharge timing of one pixel P2. As shown in the figure, the 6W1 is not turned off most of the time. "&quot;W2 is turned on most of the time, and the common mode end point is fixed at the constant value of the common mode operational amplifier. 201225053 The potential DCVCOM, when switching from the previous kneading surface to the new kneading surface, the conduction of the first switch SW1 and the non-conduction of the second switch SW2 can adjust the common mode end point VCOM to the ground potential GND. In the previous picture, 'the first end of the first developing capacitor C1, Soucel, is negative (the potential is lower than the potential of the common mode end point VCOM), and the potential of the first end S〇urce2 of the second developing capacitor C2 is Positive polarity (potential is higher than the potential of the common mode end point VCOM). In front of displaying a new one, the first and the first end of the poison image C1 and C2, Source1 and Souce2, can be grounded to discharge the first And the second developing capacitors C1 and C2, φ should be connected to the polarity reversal procedure. Meanwhile, the first switch SW1 can be turned on and the second switch SW2 can be switched to be non-conducting, so that the first and second images are The second end of capacitor C1 and C2 (common mode end point, label VC m) ground (adjusted to GND) 'the first and second imaging capacitor C2 ci and thus discharged to zero potential.

After the endpoints Source1, Source2, and VCOM are all adjusted to the ground potential GND, 'the first and second developing capacitors C1 are supplied and the first and second pixels P1 and P2 are scanned to display a new picture. The T pixel P1 is scanned, and according to the positive display potential, when the operation of the first image developing capacitor C1 is enabled, the positive display power and the first end of the first developing capacitor C1 So relays the relay:: It is established by the source operational amplifier 3〇2. As shown in the figure == is charged, and the first image capacitor C1 is at the end-end 8. _ is boosted for positive development. The array scan is performed until _: polarity development potential Datai and the first development capacitor 彳1 wcel disconnects the end, the potential of the point s〇urcel can stop rising, in addition 10 201225053 in some embodiments, now available The connection formed by the first switch SW1 is turned off and the second switch SW2 is turned on to adjust the common mode end point VCOM to return to the constant value common mode potential DCVCOM. This paragraph discusses coupling the negative polarity development potential Data2 to the The timing of the first terminal Source2 of the second developing capacitor C2 is based on the negative polarity developing potential Data2 Discharging the second developing capacitor C2. Referring to the waveform at the bottom of FIG. 4, the coupling relationship between the negative developing potential Data2 and the second developing capacitor C2 can be coupled to the first display at the positive developing potential Data1. Like the first terminal Source1 of the capacitor C1, it is established by the second source operational amplifier 304. As shown, the potential of the terminal Source2 is pulled down for negative polarity display. In summary, when the first and the first When the two developing capacitors C1 and C2 are scanned to develop a new surface, the timing of establishing the connection between the positive imaging potential Data1 and the end point Source 1 may be earlier than the negative imaging potential Data2 and the end point Source2. The following paragraphs discuss why the control scheme described in Figure 4 can significantly reduce the energy consumption. The following is a brief description of the charging path of the first developing capacitor C1 of the first pixel P1. If the positive development potential Data1 is coupled to the first terminal Source1 of the first development capacitor C1, the conduction of the first switch SW1 and the non-conduction of the second switch SW2 form a charging path of the first development capacitor C1 as shown in FIG. 5A. And the first switch SW1 does not The conduction and the conduction of the second switch SW2 form a charging path of the first developing capacitor C1 as shown in Fig. 5B. Referring to Fig. 5A, according to the time interval T1 of Fig. 4, the charging current is positive from the first source operational amplifier 302. The value supply potential VDDA flows to the first developing capacitor C1 and finally flows to the ground potential GND. Thus, when the 201225053 terminal Source1 is charged from the ground potential GND to the positive polarity, the current path does not involve the common mode operational amplifier 306. . Therefore, the potential change experienced by the charger after the charging path is (VDDA-GND)' much smaller than the potential change (VDDA-nVDDA) experienced by the conventional technology. Energy consumption is thus reduced. In the example of FIG. 5B, with respect to the time interval T2 of FIG. 4, the charging path flows from the first source operational amplifier 302 positive supply potential VDDA to the first development capacitor ci, and finally to the common mode potential operational amplifier 3〇. 6 to negative supply potential nVDDA. Fortunately, although there is a considerable potential change in such a current path (from the positive supply potential VDDA of the first source operational amplifier 3〇2 to the negative supply potential nVDDA of the common mode potential operational amplifier 3〇6), this capacitor is charged. The path still does not consume too much energy. The reason is that the common mode endpoint VCQM only needs a small amount of potential adjustment (from the ground potential GND to the fixed value common mode potential DCVC 〇 M). Therefore, the energy consumption is greatly improved compared to the conventional technology. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. 201225053 [Simplified Schematic Description] FIG. 1A illustrates a dot inversion technique; FIG. 1B illustrates a row inversion technique; and FIG. 2 is a block diagram illustrating a liquid crystal display 200 according to an embodiment of the present invention. Figure 3A illustrates two adjacent pixels on the liquid crystal pixel array 2〇2, in the same column and adjacent rows; ”, Lu

Figure 3B uses two development capacitors C1 and c2 to represent the motion of the third diagram: adjacent pixels P1 and p2, and illustrates the basic drive of the two adjacent pixels.

^ * 4 ® Sourcel ^ Source2 ^ VC0M a ® switch s W1 and second switch S W2 state, first image ^1; positive charge timing, and second pixel Μ negative charge step diagram diagram network豕电谷^ SW1 is turned on and the second switch SW2 is not turned on, and the surface connection state between the positive polarity image electric atal and the end point Wcel is established; and the switch diagram illustrates the charging path of the first image developing capacitor C1, wherein The first bit D t 1 ^ is turned on and the second switch is turned on, and the positive polarity display is aa. The facet state between the endpoints S〇urcel is established. [Main component symbol description] 200 ~ liquid crystal display; 202 ~ liquid crystal pixel array; 201225053 204 ~ drive circuit; 206 ~ gate driver; 208 ~ source driver; 210 ~ common mode potential driver; 212 ~ timing controller; 304~first and second source operational amplifiers; 306~ common mode potential operational amplifiers;

Cl, C2~ first and second developing capacitors;

Datal, Data2~ positive and negative development potential; 瘫 DCVCOM~ fixed value common mode potential; GND~ground; nVDDA~ negative value supply potential; PI, P2~ first and second pixels;

Sourcel, Source2~ first and second developing capacitors C1, C2 respective first ends; SW1, SW2~ first and second switches; Ή, T2~ time interval; φ VC0M~ common mode end; VDDΑ~正Value supply potential; VSSA ~ power ground. 14

Claims (1)

c 201225053 VII. Patent application scope: 1)-type drive circuit for driving-liquid crystal pixel array, wherein a source driver, including a -th source operational amplifier, is supplied in the liquid crystal pixel array. The first of the developing capacitors is positively developed, and the positive developing potential is in frequency; when the capacitive-first end is allowed to be connected, the first source is coupled to the positive developing potential To the first end of the first-developing capacitor; - common mode potential driving 'includes: a dragon potential operational amplifier' outputs a 1-value common mode potential; a brother-one switch that couples the first-phase to ground when conducting And the valley - Zhuo Er Duan - Xian first: pass: r fixed common mode (10) connected to the first - when to allow the positive display potential and the brother" like electric excitement, Hai Di - force And _ connection, and control the state of the first switch 'to reduce the energy consumption of the drive circuit. 2. If you apply for a patent scope! The driving circuit described in the item. When the positive polarity developing potential and the _th imaging capacitance are established, the timing control can close the second switch; and] is off and does not conduct ^ timing (4) H It should be turned on and off: until the positive display potential and the first display; = the coupling relationship of the first end is disconnected., 5, 15 C, 1C, 1201225053 3. If applying The driving circuit of claim 2, wherein the timing controller discharges the first developing capacitor to a zero potential by turning on the first switch and not turning on the second switch. The driving circuit of the first aspect of the patent, wherein: the first source operational amplifier is powered by a positive power supply potential and a ground terminal; and the 共's hai common mode operational amplifier is powered by the ground terminal and a negative The driving circuit of the first aspect of the invention, wherein: the source driver further comprises a second source operational amplifier, wherein the liquid crystal pixel array is supplied with a second developing capacitor - the second pixel is swept = as the negative The second source operational amplifier is connected to the negative polarity imaging potential to the second when the coupling of the first development of the negative development potential and the second development image f is enabled. The first terminal of the image forming capacitor; the common mode potential driver is further coupled to the first developing capacitor by an electrical connection between a second end of the image capacitor of the first developing capacitor a second end; and the timing control further determines when the pure imaging potential is allowed to be connected to the second end of the first-developing capacitor. The driving according to claim 5 is claimed. a circuit, wherein: the positive display potential and the first display capacitor of the first end of the gate are connected to the second and the order control #通_1 is off and the non-conductive = sequence control II maintains the first switch is turned on And maintaining the second switch to be non-conductive until the positive display potential is disconnected from the coupling of the first 16201225053 terminal of the first development capacitor. 7. If the patent application scope is the first positive electrode potential material/characteristic circuit, wherein, after the connection is disconnected, the timing control; like: the second imaging capacitor coupled between the first ends of the valley The second end of the second working point: the coupling relationship between the negative polarity developing potential and the music. 8. If the order controller according to claim 7 of the patent application scope is further controlled by 兮筮-s /, zhong 嗲 嗲 first, and 筮 quot quot 第 且 且 且 且 且 且 且 且 且The 苐 and _ two imaging capacitors are discharged to zero level. 9. The driving circuit of claim 5, wherein: the first-source operational amplifier is powered by a positive supply potential and a source ground terminal to simplify the positive display potential to the first a first terminal of the developing capacitor; the second source operational amplifier is powered by the power ground terminal and the negative power supply potential to lightly connect the negative polarity developing potential to the second developing capacitor a first terminal; and the common mode potential operational amplifier is powered by the power supply ground and the negative value to output the fixed common mode potential. A liquid crystal display comprising: the driving circuit according to claim 1; and the liquid crystal pixel array driven by the driving circuit.