TWI428984B - 具有控制界面之鑭系元素介電質 - Google Patents

具有控制界面之鑭系元素介電質 Download PDF

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Publication number
TWI428984B
TWI428984B TW097135817A TW97135817A TWI428984B TW I428984 B TWI428984 B TW I428984B TW 097135817 A TW097135817 A TW 097135817A TW 97135817 A TW97135817 A TW 97135817A TW I428984 B TWI428984 B TW I428984B
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Taiwan
Prior art keywords
lanthanide
layer
passivation layer
substrate
dielectric
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TW097135817A
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English (en)
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TW200926293A (en
Inventor
Arup Bhattacharyya
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Micron Technology Inc
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    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
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    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
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Description

具有控制界面之鑭系元素介電質
本揭示案大體係關於半導體設備及設備製造，且更特定言之，係關於介電質層及其製造方法。
起氧化皮(Scaling)介電質層(包括超過2nm之二氧化矽(SiO2 ))歸因於直接穿隧而導致大洩漏電流。因而，已提出替代之高k介電質。通常，"高K"指代大於SiO2 之介電常數(K約為3.9)的介電常數。於本文中使用時，"高K"將指代大於15之介電常數，而"中K"將指代在約4至15之間的介電常數。
一般方法涉及具有較高介電常數之非晶材料，諸如鉿或鋯氧化物(K約為20至25)及其矽酸鹽(K約為10至14)。前一群(氧化物)展示不良熱穩定性且在適度溫度(>800℃)下經歷再絕緣化(reinsulatorlization)。後者(矽酸鹽)以較低介電常數為代價達成較高熱穩定性。通常，兩個群在被用作直接在矽基板上之閘極介電質時顯示高界面狀態密度且因此導致場效電晶體(FET)設備之嚴重遷移率降級。另外，氧空位誘發之缺陷引起高密度之淺陷阱，從而引入臨限不穩定性及可靠性問題。
本發明提供用於具有控制界面之高k介電質的方法及設備。一種方法實施例包括在一基板上形成一鈍化層，其中該鈍化層含有矽、氧及氮之組合物。該方法亦包括在該鈍化層上形成一鑭系元素介電質膜，及在該鑭系元素介電質膜上形成一封裝層。
在本揭示案之以下[實施方式]中，對隨附圖式進行參考，隨附圖式形成本揭示案之一部分，且其中藉由說明而展示如何實踐本揭示案之一或多個實施例。以足以使一般熟習此項技術者能夠實踐本揭示案之實施例的細節來描述此等實施例，且應理解，可利用其他實施例，且可在不脫離本揭示案之範疇的情況下進行過程、電及/或結構改變。
圖1A說明根據本揭示案之一或多個實施例的包括一具有控制界面103及107之鑭系元素絕緣體膜106的高k介電質(在100處)。鈍化層104經展示為形成於半導體基板102晶圓(例如，矽)上。鑭系元素介電質膜106經展示為形成於鈍化層104上。封裝層107經展示為形成於鑭系元素介電質層106上。界面103經說明為在鈍化層104與基板102之間的界面。下文將描述鈍化層104控制界面103之方式。界面107經展示為在鑭系元素介電質層106與任一額外層之間的如由封裝層108所控制之界面，可在介電質上使用該任一額外層(例如，諸如圖2中之214的閘電極)。下文將描述封裝層108控制界面107之方式。
在一或多個實施例中，如一般熟習此項技術者所理解，半導體基板102可為一矽晶圓。下文將結合圖1B更詳細地描述鈍化層104。一或多個實施例可適用於包括反應性金屬氧化物、矽酸鹽、鋁酸鹽、氮氧化物、複合物及層壓物(其可易於與矽及金屬反應)之其他高k絕緣體。於本文中使用時，術語"鑭系元素"指代元素鑭及其他稀土金屬，例如，鐠、釹、釤、釓、鏑及鉺。實施例不限於鑭系元素之給定實例。於本文中使用時，術語"鑭系元素介電質"指代鑭系元素族金屬的成員與額外元素之化合物(combination)，例如，鑭系元素氧化物、鑭系元素矽化物及鑭系元素鋁化物。實施例不限於上文列舉的鑭系元素介電質之給定實例。
在一或多個實施例中，鑭系元素介電質膜106可充當半導體之介電質。在一些先前方法中，將二氧化矽用作介電質層。然而，超過2nm之起氧化皮SiO2 可歸因於介電質與基板之間的直接穿隧而導致大洩漏電流。在一些先前方法中，已提出以具有較高介電常數之非晶材料(諸如，鉿或鋯氧化物及其矽酸鹽)作為SiO2 之替代。前述氧化物具有在約20至25之間的介電常數，但可展示不良熱穩定性且在小於800℃之溫度下經歷再結晶。前述矽酸鹽具有較低介電常數(10至14)。此外，氧化物與矽酸鹽兩者在被用作直接在矽基板(例如，102)上之介電質時可顯示高界面狀態密度及固定電荷，因此引起場效電晶體(FET)設備之嚴重遷移率降級及臨限移位。另外，氧空位誘發之缺陷可引起高密度之淺陷阱，從而引入臨限不穩定性及可靠性問題。
鑭系元素絕緣體膜106可為鑭系元素氧化物，例如，La2 O3 、Pr2 O3 、Nd2 O3 、Sm2 O3 、Gd2 O3 、Dy2 O3 及Er2 O3 ，其可顯示大帶隙(通常大於5ev)，其中導帶關於矽偏移大於2ev。與ZrO2 或HfO2 相比，該等氧化物亦可在矽基板(例如，102)上顯示較大熱穩定性。鑭系元素氧化物在針對給定洩漏電流密度而正規化時亦可具有較高有效介電常數，且可具有與矽匹配之晶格參數，此有助於磊晶氧化物(epi-oxide)生長，從而得到更高的介電常數值。另外，鑭系元素氧化物顯示出眾之洩漏特性。鑭系元素介電質膜106亦可形成為穩定鑭系元素矽化物及鋁酸鹽。
鑭系元素介電質之一些先前處理機制可導致在基板界面103處不需要之SiO2 、矽酸鹽(Six My Oz )及鋁酸鹽(Alx My Oz )的不可控之形成，此可降低膜之有效介電常數，且可引起不需要之較高固定電荷密度。此外，一些先前處理機制可導致大於1E12/cm2 之界面密度及負固定電荷密度，從而導致歸因於減少之載子遷移率的不良FET設備特性。根據本揭示案之一或多個實施例，如下文結合圖6及圖7所描述的，至少包括以下所列之手段可用於形成鑭系元素介電質膜106：液體注入金屬有機化學氣相沈積(MOCVD)、熱壁減壓液體注入原子層沈積(ALD)、使用電子束蒸鍍之超高真空分子束磊晶法(MBE)及高真空濺鍍。
"等效氧化物厚度"(EOT)量測(有時簡稱為"氧化物等效")為給定厚度之任何介電質層之相對電容相對於若SiO2 介電質層用於任何給定應用中則可需要之厚度的方便量測。介電質層之EOT係藉由將該層之實體厚度除以關於二氧化矽之介電常數的其介電常數來計算。二氧化矽之介電常數為約4。在本揭示案之一或多個實施例中，鑭系元素介電質膜106可經形成至一具有約1nm至2nm之EOT的約5nm至10nm的厚度。
鑭系元素氧化物可易於吸收濕氣。氧及不需要之污染物可易於在適當溫度下經由該等膜而擴散。為確保後形成處理之完整性及為控制介電質與額外層(諸如，閘電極)之間的界面107，封裝層108可形成於鑭系元素介電質膜106之上。在一或多個實施例中，封裝層108可藉由在界面107處形成諸如矽酸鹽、氮氧化物或鋁酸鹽之穩定化合物及藉由防止鑭系元素介電質膜106與水反應而有助於控制界面107。封裝層108可經形成至一厚度(例如，在介電質上之0.5nm至2.0nm)。在一或多個實施例中，封裝層108可為(例如)氮化矽(SiN)、未摻雜之多晶矽、氮化鈦(TiN)、氮化鉭(TaN)、氮化鎢(WN)或PrTix Oy 。可使用包括快速熱退火(RTA)或自複合物源原位沈積之手段藉由電子束、濺鍍、ALD或MOCVD形成封裝層108。
圖1B說明圖1A之一部分的擴展圖。圖1B說明鈍化層104之擴展圖。鑭系元素介電質膜(例如，106)可與氧、-OH離子及氫反應。該等膜亦可甚至在超高真空條件下在室溫下形成矽酸鹽層。此外，氧與矽兩者皆可在鑭系元素介電質膜(例如，106)中互相擴散。雖然界面狀態之高密度可歸因於界面103處之不飽和鍵，但固定電荷及陷阱之高密度可與非化學計量之矽酸鹽或矽化物形成及相關聯之缺陷相關聯。藉由併入鈍化層104，使界面103穩定且最小化如上文描述之缺陷形成。
需要在界面103處的適當氧濃度及Si-O鍵形成以克服上述缺陷，而在改良界面103穩定性的同時不形成較弱Si-H鍵以抑制界面狀態。同時，在或靠近界面103處所建立之足夠的Si-N鍵可大體上使與氧、-OH及氫之反應鈍化。
如圖1B中所說明之實施例中所示，鈍化層104可包括形成於矽、氧及氮之組合物"SiON"110之上的氮化物112。在一或多個實施例中，SiON層110可包括約40原子百分比之氧、20原子百分比之氮及40原子百分比之矽的混合物。可使用諸如液體注入MOCVD、液體注入ALD或熱壁減壓液體注入ALD之手段將SiON層110形成至0.5nm至2.0nm之厚度。下文將結合圖6及圖7更詳細地描述形成方法。
在一或多個實施例中，鈍化層104可經形成為兩層，例如，一形成於基板102上之底層110及一形成於底層110上之頂層112。在一或多個實施例中，頂層112可經形成為氮化物或富氮氮氧化物。實施例不限於兩層鈍化層104。在包括僅一層鈍化層104之實施例中，可大體上如對於底層110(例如，SiON)所描述而形成鈍化層。具有兩個分層之封裝層108的實施例可包括一經形成至約1.0nm至1.5nm的底層及一經形成至約0.5nm至1.0nm的頂層。
圖2說明根據本揭示案之一或多個實施例的具有一具有控制界面203及207之鑭系元素介電質膜206的電晶體200。在一或多個實施例中，電晶體200可為一場效電晶體(FET)。如一般熟習此項技術者將瞭解，電晶體200可用作邏輯電路(諸如微處理器)之基礎高效能設備以及半導體記憶體單元中(例如，如結合圖4A及圖4B所描述之DRAM，或如結合圖5A及圖5B所描述之非揮發性記憶體單元中)的基礎高效能裝置。
擴散區域216(例如，源極區域及汲極區域)可形成於基板(例如，矽半導體基板晶圓)202中。鈍化層204可形成於基板202上。鑭系元素介電質膜206可形成於鈍化層204上。封裝層208可形成於鑭系元素介電質膜206上。閘電極214可形成於封裝層208上。
鈍化層204、鑭系元素介電質膜206及封裝層208可經形成且可大體上起如結合圖1A、1B、圖6及圖7所描述的作用。此外，控制界面203及207大體上類似於如結合圖1A所描述之控制界面103及107。閘電極214可用於將電壓施加至電晶體200，以便在基板202中於擴散區域216之間建立一導電通道。電晶體200可為金屬氧化物半導體(MOS)電晶體。
在一或多個實施例中，鑭系元素介電質膜206可形成為(例如)鑭系元素矽化物、鑭系元素鋁化物、穩定多晶鑭系元素氧化物、非晶鑭系元素氧化物、穩定單晶氧化物，或非晶或穩定單晶鋁酸鹽。鑭系元素介電質層206之介電常數可大於20。電晶體200之EOT可為大約1.0nm至1.5nm。根據本揭示案之一或多個實施例，電晶體之有效電子遷移率可大於500cm2 /V-秒。在一或多個實施例中，電晶體可具有約80mV/dec之次Vt斜率及約0.5V之Vth，如結合圖9更詳細地描述。電晶體200提供用於諸如可用於高效能微處理器中的高效能下一代邏輯電路之建構區塊。
圖3說明根據本揭示案之一或多個實施例的具有一具有控制界面305之鑭系元素介電質膜306的電容器300。在一或多個實施例中，電容器300可形成於基板302上。如一般熟習此項技術者將瞭解，電容器300可用於半導體記憶體單元中，例如，如結合圖4A及圖4B所描述之DRAM中。或者，電容器300亦可用作邏輯及RF電路中之離散電容器元件。電容器300包括導電電極層318，其可由諸如金屬、多晶矽或摻雜之多晶矽的導電材料形成。
如圖3中所說明之實施例中所示，電容器300包括在導電層318之間且鄰近導電層318的鈍化層309。在一或多個實施例中，鈍化層可形成為TiN、TaN或WN。亦如圖3中所說明之實施例中所示，電容器300包括一在封裝層之間的鑭系元素介電質膜306。鑭系元素介電質膜306亦可形成為上文結合圖1A所描述之材料。在一或多個實施例中，鑭系元素介電質膜306可形成為包括PrTiOx 之一層及PrSiOx 之一層的兩層介電質。在一或多個實施例中，PrTiOx 及PrSiOx 之層的相對位置可顛倒。該等層之置放次序視設備之特定製造過程及該等層關於電極材料區段的相對位置以及整合需要而定。
與使用Al2 O3 、HfO2 ，或ZrO2 介電質層所形成之電容器相比，根據本揭示案之一或多個實施例所形成的電容器300可提供差不多雙倍的電容器儲存容量。電容器300可達成對於包括鈍化層-鑭系元素介電質膜-鈍化層(309-306-309)結構的22或更大之介電常數，諸如包括TiN-PrSiOx -TiN、TiN-PrTiOx -TiN、TiN-PrTiOx /PrSiOx -TiN、TaN-PrTiOx /PrSiOx -TaN及WN-PrTiOx /PrSiOx -WN以及鑭族介電質之其他類似組合的結構。根據本揭示案之一或多個實施例所形成的電容器300可達成對於包括作為鑭系元素介電質膜306之單一介電質Pr2 O3 的結構的30之介電常數。
圖4A說明根據本揭示案之一或多個實施例的具有一具有控制界面403、405及407之鑭系元素介電質膜406的內埋式電容器型DRAM記憶體單元400-A。圖4B說明根據本揭示案之一或多個實施例的具有一具有控制界面403及407之鑭系元素絕緣膜406的溝槽式電容器型DRAM記憶體單元400-B。控制界面403及407之細節大體上與上文結合圖1A對於界面103及197所描述的相同。圖4A及圖4B中所說明之該一或多個實施例可用於DRAM記憶體單元中。
圖4A及圖4B包括包括儲存電極432及平板電極434之電容器430。儲存電極432及平板電極434可由如圖3中之導電層318所表示的任何導電材料或半導電材料製成。在一或多個實施例中，儲存電極432及平板電極434係由多晶矽或晶體矽、耐熔金屬(諸如，W、Mo、Ta、Ti或Cr)或其組合(諸如，WSi2 、MoSi2 、TaSi2 或TiSi2 )製成。將瞭解，在不脫離本揭示案之範疇的情況下，電極432及434可由其他材料製成。在一或多個實施例中，儲存電極432及平板電極434由具有控制界面405(例如，圖3中之305)的鈍化層409(例如，圖3中之309)及鑭系元素介電質膜406(例如，圖3中之306)隔開。
電容器430用於儲存表示資料之電荷。經由選擇線(例如，字元線)422及感測線(例如，位元線)424對電容器430進行存取。選擇線422為電晶體420之閘電極(例如，圖2中之214)，閘電極用於在將足夠電壓施加至選擇線422時在擴散區域(例如，源極/汲極區域)416(例如，圖2中之216)之間形成一導電通道。在本揭示案之一或多個實施例中，選擇線422位於封裝層408上。如上文結合圖1A所描述，封裝層408(例如，圖1A中之108)可形成為氮化矽(SiN)、未摻雜之多晶矽、氮化鈦(TiN)、氮化鉭(TaN)、氮化鎢(WN)或PrTix Oy 。
在圖4A及圖4B中所說明之一或多個實施例中，封裝層408位於鑭系元素介電質膜406之上。如上文結合圖1A所描述，鑭系元素介電質膜406(例如，圖1A中之106)可形成為鑭系元素矽化物、鑭系元素鋁化物、穩定多晶鑭系元素氧化物、非晶鑭系元素氧化物、穩定單介電線氧化物，及穩定非晶或單晶鋁酸鹽。對於特定DRAM設備而言，用作電晶體420及電容器430的介電質之鑭系元素介電質膜可由相同或不同材料製成。
亦如圖4A及圖4B中所說明之該一或多個實施例中所說明，鑭系元素介電質膜406位於鈍化層404之上，鈍化層404位於基板402之上。如上文結合圖1所描述，鈍化層404(例如，圖1A中之104)可形成為矽、氧及氮之組合物。在一或多個實施例中，該組合物可包括40原子百分比之氧、20原子百分比之氮及40原子百分比之矽。亦如上文結合圖1B所描述，在一或多個實施例中，鈍化層404可形成為SiON層及氮化物或富氮氮氧化物之層，例如，分別為圖1B中之層110及112。下文結合圖6及圖7更詳細地描述圖4A及圖4B中所說明的各種層之形成過程。
圖5A說明根據本揭示案之一或多個實施例的具有一具有控制界面之鑭系元素介電質膜的浮動閘極型記憶體單元500。電晶體500包括具有擴散區域516(例如，源極及汲極)的基板502(例如，基於矽之基板)。在一或多個實施例中，基板502可為植入有n型擴散區域516之p型矽基板。在一或多個實施例中，基板502可為植入有p型擴散區域516之n型矽基板。
位於基板503之上的為一包括穿隧介電質548、浮動閘極(FG)544、電荷阻擋介電質546、控制閘極(CG)542及選擇線(例如，字線)接觸540之堆疊。浮動閘極544可用於儲存表示資料之電荷。儘管圖5A中未展示，但連接至選擇線接觸540之選擇線繼續連接其他記憶體單元(例如，在頁中及/或在頁外延伸的選擇線上之電晶體)之控制閘極中之每一者，如圖5A中所說明。介電質層548與546兩者可為如圖5B中所說明之高k鑭系元素介電質膜。
圖5B說明圖5A中所說明之高k介電質的擴展圖548。圖5B包括一鈍化層504、一鑭系元素介電質膜506、一封裝層508及控制界面503及507。鈍化層504形成於基板502上，如圖5A中所說明。圖5A中之浮動閘極544形成於封裝層508之上，如圖5B中所說明。圖5B之元件可大體上如上文結合圖1A及圖1B所描述及如下文結合圖6及圖7所描述而形成。
如一般熟習此項技術者將瞭解，圖5A中之電荷阻擋介電質546亦可包括鈍化層(例如，圖5B中之504)及/或封裝層(例如，圖5B中之508)。圖5A及圖5B中所說明之電晶體500可為一(諸如)通常用於NAND或NOR快閃陣列中之非揮發性記憶體單元。
圖6說明可根據本揭示案之一或多個實施例使用之MOCVD/ALD反應器600。所描繪之元件允許本揭示案之論述，使得熟習此項技術者可在無不適當試驗的情況下實踐本發明。在圖6中，目標656(例如，基板)可位於MOCVD/ALD反應器600之反應室684內部。亦位於反應室684內的可為一加熱旋轉台654，其可熱耦合至目標656以控制目標溫度。蒸發器658可將前驅物引入至目標656。每一前驅物可來源於源660，包括源662、664及666，其流動可由質量流控制器680來控制。源660可藉由提供一液體材料以在蒸發器658中形成選定前驅物氣體而提供前驅物。
亦包括於MOCVD/ALD反應器600中的可為包括672及674之清洗氣體源670。此外，額外清洗氣體源可建構於MOCVD/ALD反應器600中，例如，對於每一種前驅物氣體一清洗氣體源。對於使用相同清洗氣體用於多個前驅物氣體之過程而言，需要較少清洗氣體源用於MOCVD/ALD系統600。對於ALD模式操作，MOCVD/ALD反應器600亦可包括氣體源676、678及679以用於在不需要於658處蒸發的情況下引入至反應室684。反應室684亦可在熱電耦650後耦接至真空泵(或排氣泵)652以在清洗序列末端處自反應室684中移除過多前驅物氣體、清洗氣體及副產物氣體。
為方便起見，如熟習此項技術者所知的控制顯示器、安裝裝置、溫度感測設備、基板控制裝置及必要的電連接未展示於圖6中。儘管MOCVD/ALD反應器600非常適於實踐本發明，但可使用市售之其他MOCVD/ALD系統。
一般熟習半導體製造技術者理解用於膜之沈積的反應室的使用、結構及基本操作。本發明可在無不適當試驗情況下在各種該等反應室上實踐。此外，一般熟習此項技術者在閱讀本揭示案後將瞭解半導體製造技術中的必要偵測、量測及控制技術。
MOCVD/ALD反應器600可由電腦來控制。為聚焦於MOCVD/ALD反應器600在本發明之各種實施例中的使用，未展示電腦。熟習此項技術者可瞭解，諸如MOCVD/ALD系統600中之壓力控制、溫度控制及氣體流動的個別元件可在電腦控制之下。
MOCVD/ALD反應器600可用於形成如上文結合圖1A及圖1B所描述之鈍化層(例如)104。鈍化層(例如，鈍化層104，包括40原子百分比之氧、20原子百分比之氮及40原子百分比之矽，具有約1.6之折射率)可於矽基板(例如，目標656)上沈積至約1nm至2nm的厚度。在一或多個實施例中，可在一些預先步驟後執行形成。舉例而言，反應室684之適當高溫脫氣(例如，在超高純氮環境中在450℃下之預先烘焙)有助於在SiON沈積之前提供氫及濕氣自矽表面的完全解吸附及一無污染矽表面。此外，可在形成之前執行基板(例如，目標656)之預先清潔、界面(例如，圖1A中之界面103)氧化及天然氧化物自矽基板(例如，目標656)之表面的原位氣相移除。
SiON鈍化層(例如，圖1A及圖1B中之104)可在約650℃至750℃下使用在氮載體中經適當稀釋的反應物SiCl4 、NH3 、N2 O或臭氧在MOCVD模式中而沈積。亦可以約400℃至450℃下之SiCl4 或約650℃至700℃下之NH3 -O3 -N2 的循環於ALD模式中形成該層，同時保持SiCl4 、NH3 及N2 O之適當氣體壓力以在一小於0.1nm/秒的慢沈積速率下達成所要膜組合物。
如上文結合圖1B所描述，鈍化層亦可由SiON之底層(例如，圖1B中之110)及氮化物或富氮SiON之頂層(例如，圖1B中之112)形成。在利用兩層鈍化層之一或多個實施例中，如結合圖1B所描述，氮化物之層可形成至一約0.5nm至1.0nm之厚度。富氮SiON之層(具有約1.8之折射率)可藉由適當控制N2 O含量而形成。氮化物之層(具有約2.0之折射率)可藉由在氮化物層之沈積期間完全消除N2 O而形成。
晶體學上，膜組合物及品質以及鑭系元素介電質之電特性對於基板(例如，圖1A中之102)製備及界面(例如，圖1A中之103)鈍化非常敏感。鑭系元素介電質之形成亦非常依賴於源材料組合物及製備、沈積之溫度及環境條件。通常，當使用源材料之四甲基庚二酸鹽(tetramethylheptanedionate)[(tmhd)3]及甲氧基甲基丙酸鹽(methoxymethlypropanolate)[(mmp)3]前驅物族時，由ALD或MOCVD在低於650℃之基板溫度下生長的氧化膜為具有或不具有非晶矽酸鹽間層之聚介電質線(polydielectricline)(例如，六邊形的及富氧的)。此等膜具有特徵紋理且顯示較不良之電特性並在高於800℃下退火時經歷結構變化。在較高溫度下生長之膜在惰性環境(Ar或N2 )中退火時相對更穩定且矽酸鹽間層可經歷在氧環境中之介電質化。相比之下，當使用矽烷基醯胺前驅物源時，即使在由ALD或MOCVD方式在介於約250℃至550℃之間的溫度下沈積於基板(例如，目標656)時矽酸鹽仍更穩定且保持非晶形。
在如上文描述形成鈍化層(例如，圖1A之104)後，可使用MOCVD/ALD反應器600來形成鑭系元素介電質膜(例如，圖1A中之106)。可於MOCVD模式中在具有為穩定化而添加之四乙二醇二甲醚(tetraglyme)的甲苯中使用源材料[Ln{n(SiMe3)2}3](鑭系元素三烷基矽烷基醯胺)來形成鑭系元素矽化物，且使用由氬+N2 O或氮+N2 O組成之載氣將鑭系元素矽化物保持於約170℃。基板溫度可保持在400℃至600℃左右且反應器壓力可保持在約1毫巴。併入N2 O可藉由形成揮發性CO2 而有助於確保碳自膜中移除同時保持適於矽酸鹽膜形成的氧之部分壓力。生長速率可為約5nm/min至7nm/min。可在具有約1nm至2nm之EOT的約5nm至10nm之範圍內沈積鑭系元素矽化物。使用上述條件，所形成之特定鑭系元素可包括La、Pr或Gd。
可在ALD模式中藉由除以下變化外保持反應器600及上述源不變而形成鑭系元素矽化物。載氣可為氬+O3 或氮+O3 。基板溫度可保持在200℃至400℃左右同時前驅物脈衝長度可為約0.5秒至1.0秒。在一或多個實施例中，水蒸汽與臭氧之混合物連同氮或氬一起被用於控制沈積速率。可採用每循環約20μL至40μL之前驅物體積。
可在大體上如上文所描述之MOCVD或ALD模式中但藉由結合Me3 Al使用包括鑭系元素脒化物(lanthanide amidinates)[Ln(R-NCHN-R)3]之前驅物而形成鑭系元素鋁化物。
為了有助於減少鑭系元素氧化物多晶結構源於使用前驅物之Ln(mmp)3及Ln(mthd)3族的MOCVD/ALD反應的較不良結構穩定性及電特性，可在沈積期間併入過多矽以驅動表面反應朝向在晶粒邊界周圍形成矽酸鹽(silicate formation)。此可藉由在基板處大體上同時併入SiCl4 及{Ln(mmp)3或Ln(mthd)3或矽烷基醯胺}前驅物而達成。此可導致一可增強熱穩定性及電特性的混合氧化物/矽酸鹽非晶膜。使用一在沒有氧之情況下在大於450℃之溫度下沈積於矽基板之上的Gd(mmp)3前驅物可導致單晶穩定Gd2 O3 膜。在較低溫度下及在存在氧之情況下，膜可為非晶的。
封裝層(例如，圖1A中之108)可形成於鑭系元素介電質層(例如，圖1A中之106)上。封裝層可有助於鈍化界面(圖1A中之107)處之膜，且使整個整合過程免受後處理污染物之影響。約0.5nm至2.0nm厚度SiN膜之原位沈積可有助於在有效介電常數僅些微減少之情況下封裝介電質層。封裝層之其他選項包括未摻雜多晶矽、TiN、TaN或WN。該層可藉由標準原位CVD及其他技術而沈積。可由一般熟習此項技術者來選擇給定介電質層之最佳封裝層。舉例而言，TiN可為防止矽酸鹽形成及作為介電質膜之Pr2 O3 與水反應的有效界面層。
圖7說明可根據本揭示案之一或多個實施例使用之電子束蒸鍍容器700。電子束蒸鍍容器700可位於基礎底板(base plate)781上。基板(例如，目標756)可包括SiON及/或(富氮)氮化物的先前沈積之鈍化層。基板(例如，目標756)可固持於一具有面對擋閘786之目標表面之基板支撐設備788中，擋閘786控制基板表面曝露至蒸發之鑭系元素源706之束。該束可由來自設置於擋閘786下方之腔室底部中的電子槍790之轟擊而發射。
基板(例如，目標756)之溫度及腔室環境可由一可包括接近於基板(例如，目標756)之可選反射器789的加熱器787總成來控制。氧分布環783可位於擋閘786下方。氧分布環可為一在約1E-7托之壓力下在基板(例如，目標756)之表面四周分布氧的歧管。電子束蒸鍍容器700可經組態有一用於將腔室排空至約10E-6托或更小之壓力的真空泵752。腔室中之氧壓力可藉由氧控制調節器780來調節。腔室中需要少量氧以確保鑭系元素膜之沈積層完全被氧化，因為電子束蒸鍍之過程趨於使鑭系元素材料706之氧化化學計量降級。可選偵測器或監視器可包括於容器700之內部或外部上，諸如一用於偵測層之厚度的內部設置之偵測器791及用於顯示層之厚度的外部設置之監視器792。鑭系元素介電質層可藉由控制電子束蒸鍍之持續時間而形成至一具有約1nm至2nm之EOT的約5nm至10nm的適當厚度。
使用上文描述之處理機制，可在約600℃下在用於在矽基板上之Pr2 O3 單介電質形成的超高真空條件下形成約2nm厚度的穩定之矽酸鹽界面層。視情況，亦可在較低基板溫度下沈積穩定Pr矽酸鹽(PrSix Oy )非晶膜，此可達成約22之介電常數。
可使用來自706處之Pr6 O11 晶體之固體單晶體托盤的電子束蒸鍍將穩定單晶Pr2 O3 沈積於矽基板(例如，目標756)上。如上文所描述，在鈍化層(例如，圖1A中之104)形成後，可沈積單晶體Pr2 O3 膜而無矽酸鹽界面層。約100nm厚之未摻雜多晶矽層可經原位沈積以在隨後處理之前消除濕氣吸附。如一般熟習此項技術者將理解，對於其他鑭系元素氧化物介電質膜，可採用一使用其他LnOx 材料作為源的類似方法。或者，對於單晶體鋁酸鹽膜，單晶體LnAlO3 可用作目標且可在約1E-7托下在約650℃至700℃之基板溫度下採用雷射濺鍍沈積技術。
圖8說明根據本揭示案之一或多個實施例的藉由液體注入金屬有機化學氣相沈積形成包括一具有控制界面之鑭系元素介電質膜的半導體設備之方法之實施例的要素的流程圖800。要素810、820、830、840、850及860指示形成半導體設備的方法之一般要素。要素反映一般要素之子要素，子要素來自一般要素。舉例而言，811、813、815及817提供關於一般要素810之更多細節。
在810處，矽基板(例如，圖1A中之102)可經預先清潔，表面可經氧化及退火。要素810包括RCA清潔及5%HF浸漬以在811處自基板移除氫氧化物。在813處，低溫臭氧氧化可用於在600℃下形成保護氧化物。在815處，可執行原位HF蒸汽清潔以達成無氧化物之清潔矽表面。在817處，基板可經UV烘焙以有助於確保一清潔矽基板表面並自界面(例如，圖1A中之界面103)移除氫。
在820處，如參看圖1A、圖1B及圖6更詳細地描述，SiON鈍化層可經沈積至一約0.5nm至1.0nm之厚度。要素820可包括在821處在700℃下使用前驅物SiCl4 、NH3 、N2 O及N2 。在823處，N2 O流之程式化減少可用於將整個鈍化層之頂層轉換成氮化物或富氮氮化物(例如，圖1B中之112)。如結合圖1A及1B所描述，鈍化層104可包括SiON之單一層，或包括SiON之底層110及氮化物或富氮氮化物之頂層112的兩層。
在830處，鑭系元素介電質膜(例如，圖1A中之106，例如，Ln矽酸鹽)可經原位沈積至約4nm至5nm之厚度。要素830可包括在831處在1毫巴壓力下以約5nm/min之生長速率在約500℃至550℃之溫度下使用前驅物SiCl3 、Pr三烷基矽烷基醯胺、臭氧及(N2 或Ar)。參看圖6及圖7更詳細地描述此層之形成。
在840處，封裝層(例如，圖1A中之108，例如，SiN)經原位沈積至約0.5nm至1.0nm的厚度。要素840可包括在841處在約700℃下使用前驅物SiCl4 、NH3 及N2 。參看圖6及圖7更詳細地描述此層之形成。
在850處，可在900℃下於N2 中對基板(例如，圖1A中之102)執行外部RTA退火。此處，基板可包括鈍化層、鑭系元素介電質膜及封裝層。如一般熟習此項技術者將瞭解，為易於處理，可在一控制環境中在過程中間不移除基板的情況下執行要素815至850。在860處，如一般熟習此項技術者將理解，可發生標準後處理。
圖9說明根據本揭示案之一或多個實施例形成的電晶體之轉移特性。x軸為以伏特為單位所量測之閘極電壓之線性表示。y軸為以安培/μm為單位所量測之汲極電流關於通道寬度之對數表示。在圖9中所說明之實施例中，可形成包括鑭系元素介電質膜(例如，圖1A中之106，例如，包括作為鑭系元素介電質之Pr2 O3 )的電晶體。對於圖9中所說明之實例，通道寬度可為約100μm。
要素900-1表示根據一些先前方法(例如，在無界面控制之情況下)所形成之設備的轉移特性。要素900-1說明145mV/decade的次臨限Vt移位。要素900-2表示根據本揭示案之一或多個實施例使用界面控制所形成之設備的轉移特性。要素900-2說明80mV/decade的次臨限Vt移位。在無界面控制之情況下，在900-1處所說明的顯著較高之次臨限Vt移位可指示設備接通，例如，歸因於不良界面特性回應於所施加閘極電勢而緩慢導電。在如900-2處所說明之界面控制情況下達成具有出眾速度及洩漏的接近理想之設備特性。
結論
提供用於具有控制界面之介電質的方法及設備。一種方法實施例包括在基板上形成鈍化層，其中鈍化層含有矽、氧及氮之組合物。該方法亦包括在鈍化層上形成一鑭系元素介電質膜，及在鑭系元素介電質膜上形成封裝層。
儘管本文已說明並描述特定實施例，但是一般熟習此項技術者將瞭解，經計算以達成相同結果之配置可替代所示之特定實施例。本揭示案意欲涵蓋本揭示案之各種實施例的調適或變化。應理解，以說明性方式(且並未為限制性方式)進行上文描述。熟習此項技術者在審閱上文描述後，上文實施例及本文未特定描述之其他實施例之組合將顯而易見。本揭示案之各種實施例的範疇包括使用上文結構及方法的其他應用。因此，應關於隨附申請專利範圍以及該等申請專利範圍所授權的均等物之完整範圍來判定本揭示案之各種實施例的範疇。
在前述[實施方式]中，為流線化本揭示案之目的，將各種特徵共同分組在單一實施例中。不應將此揭示方法解釋為反映本揭示案之揭示實施例必須使用比每一申請專利範圍中所明確陳述的更多之特徵的意圖。而是，根據以下申請專利範圍反映，發明標的物在小於單一揭示實施例的所有特徵中。因而，以下申請專利範圍據此併入於[實施方式]中，其中每一請求項自身作為獨立實施例。
100．．．高k介電質
102．．．半導體基板/基板
103．．．控制界面
104．．．鈍化層
106．．．鑭系元素介電質膜
107．．．控制界面
108．．．封裝層
110．．．SiON層/底層
112．．．氮化物或富氮SiON之頂層/頂層
200．．．半導體電晶體
202．．．基板
203．．．控制界面
204．．．鈍化層
206．．．鑭系元素介電質層/鑭系元素介電質膜
207．．．控制界面
208．．．封裝層
214．．．閘電極
216．．．擴散區域
300．．．電容器
302．．．基板
305．．．控制界面
306．．．鑭系元素介電質膜/介電質層
309．．．鈍化層
318．．．導電層
400-A．．．內埋式電容器型DRAM記憶體單元
400-B．．．溝槽式電容器型DRAM記憶體單元
402．．．基板
403．．．控制界面
404．．．鈍化層
405．．．控制界面
406．．．鑭系元素介電質膜
407．．．控制界面
408．．．封裝層
409．．．鈍化層
416．．．源極/汲極區域
420．．．電晶體
422．．．選擇線
424．．．感測線
430．．．電容器
432．．．儲存電極
434．．．平板電極
500．．．浮動閘極型記憶體單元/電晶體
502．．．基板
503．．．控制界面
504．．．鈍化層
506．．．鑭系元素介電質膜
507．．．控制界面
508．．．封裝層
516．．．擴散區域
540．．．選擇線接觸
542．．．控制閘極(CG)
544．．．浮動閘極(FG)
546．．．介電質層/電荷阻擋介電質
548．．．介電質層
600．．．MOCVD/ALD反應器/MOCVD/ALD系統
650．．．熱電耦
652．．．真空泵(或排氣泵)
654．．．加熱旋轉台
656．．．目標
658．．．蒸發器
660．．．源
662．．．源
664．．．源
666．．．源
670．．．清洗氣體源
672．．．清洗氣體源
674．．．清洗氣體源
676．．．氣體源
678．．．氣體源
679．．．氣體源
680．．．質量流控制器
684．．．反應室
700．．．電子束蒸鍍容器
706．．．鑭系元素源/鑭系元素材料
752．．．真空泵
756．．．目標
780．．．氧控制調節器
781．．．基礎底板
783．．．氧分布環
786．．．擋閘
787．．．加熱器
788．．．基板支撐設備
789．．．可選反射器
790．．．電子槍
791．．．內部設置之偵測器
792．．．外部設置之監視器
900-1．．．要素
900-2．．．要素
圖1A說明根據本揭示案之一或多個實施例的包括一具有控制界面之鑭系元素絕緣體膜的高k介電質。
圖1B說明圖1A之一部分的擴展圖。
圖2說明根據本揭示案之一或多個實施例的具有一具有控制界面之鑭系元素膜的電晶體。
圖3說明根據本揭示案之一或多個實施例的具有一具有控制界面之鑭系元素介電質膜的電容器。
圖4A說明根據本揭示案之一或多個實施例的具有一具有控制界面之鑭系元素介電質膜的內埋式電容器型DRAM記憶體單元。
圖4B說明根據本揭示案之一或多個實施例的具有一具有控制界面之鑭系元素絕緣體膜的溝槽式電容器型DRAM記憶體單元。
圖5A說明根據本揭示案之一或多個實施例的具有一具有控制界面之鑭系元素絕緣體膜的浮動閘極型記憶體單元。
圖5B說明圖5A中所說明之高k介電質的擴展圖。
圖6說明可根據本揭示案之一或多個實施例使用之MOCVD/ALD反應器。
圖7說明可根據本揭示案之一或多個實施例使用之電子束(e-beam)蒸鍍容器。
圖8說明根據本揭示案之一或多個實施例的藉由液體注入金屬有機化學氣相沈積形成包括一具有控制界面之鑭系元素絕緣體膜之半導體設備的方法之實施例之要素的流程圖。
圖9說明根據本揭示案之一或多個實施例形成的電晶體之轉移特性。
100．．．高k介電質
102．．．半導體基板/基板
103．．．控制界面
104．．．鈍化層
106．．．鑭系元素介電質膜
107．．．控制界面
108．．．封裝層

Claims (24)

  1. 一種形成一具有控制界面(103、107)之高k介電質的方法，其包含：在一基板(102)上形成一鈍化層(104)，其中該鈍化層(104)含有約40原子百分比之矽、40原子百分比之氧及20原子百分比之氮之一組合物；在該鈍化層(104)上形成一鑭系元素介電質膜(106)；及在該鑭系元素介電質膜(106)上形成一封裝層(108)。
  2. 如請求項1之方法，其中該方法包括在該基板(102)上形成該鈍化層(104)至一約0.5nm至2.0nm之厚度。
  3. 如請求項1或2之方法，其中形成該鈍化層(104)包括：在該基板(102)上形成一底層(110)，其中該底層(110)包括約40原子百分比之氧、20原子百分比之氮及40原子百分比之矽；及在該底層(110)上形成一頂層(112)，其中該頂層(112)係自包括以下各物之群中選擇：富氮氮化物；及氮化物。
  4. 如請求項1之方法，其中形成該鑭系元素介電質膜(106)包括一自包括以下各物之群中所選擇之鑭系元素介電質：鑭系元素矽化物；鑭系元素鋁化物；穩定多晶鑭系元素氧化物； 非晶鑭系元素氧化物；穩定單晶氧化物；及穩定單晶鋁酸鹽。
  5. 如請求項1或4之方法，其中該方法包括將該鑭系元素介電質膜(106)形成至一具有一約1nm至2nm之有效氧化物厚度(EOT)的約5nm至10nm之厚度。
  6. 如請求項1之方法，其中該方法包括形成自包括以下各物之群中所選擇之該封裝層(108)：氮化矽(SiN)；氮化鈦(TiN)；氮化鉭(TaN)；氮化鎢(WN)；未摻雜之多晶矽；及PrTix Oy 。
  7. 一種形成一具有控制界面(103、107)之高k介電質的方法，其包含：預先清潔一基板(102)；在一高於450℃之溫度下於一氮環境中預先烘焙該基板(102)；在該基板(102)上形成一鈍化層(104)，其中該鈍化層(104)包括約40原子百分比之氧、20原子百分比之氮及40原子百分比之矽；在該鈍化層(104)上形成一鑭系元素介電質膜(106)；及在該鑭系元素介電質膜(106)上形成一封裝層(108)。
  8. 如請求項7之方法，其中該方法包括使用化學氣相沈積(CVD)以藉由在約650℃至700℃下在一氮載體中使SiCl4 、NH3 及N2 O反應而形成該鈍化層(104)。
  9. 如請求項7之方法，其中該方法包括使用原子層沈積(ALD)以藉由在約400℃至450℃下循環SiCl4 及在約650℃至700℃下循環NH3 -N2 O-N2 而形成該鈍化層(104)。
  10. 如請求項7至9中之任一項之方法，其中該方法包括使用金屬有機化學氣相沈積(MOCVD)以形成該鑭系元素介電質膜(106)，且其中使用MOCVD包括：將該基板保持在約400℃至600℃；及使用一自包括以下各物之群中所選擇的載氣：氬+N2 O；及氮+N2 O。
  11. 如請求項10之方法，其中形成該鑭系元素介電質膜(106)包括藉由在具有四乙二醇二甲醚之甲苯中注入鑭系元素三烷基矽烷基醯胺[Ln{n(SiMe3)2}3]而形成鑭系元素矽化物。
  12. 如請求項10之方法，其中形成該鑭系元素介電質膜(106)包括藉由注入鑭系元素脒化物[Ln(R-NCHN-R)3]及Me3 Al而形成鑭系元素鋁化物。
  13. 如請求項7至9中之任一項之方法，其中該方法包括使用原子層沈積(ALD)以形成該鑭系元素介電質膜(106)，且其中使用ALD包括：將該基板保持於約200℃至400℃； 使用一約0.5秒至1.0秒之前驅物脈衝長度；使用每循環約20μL至40μL之一前驅物體積；及使用一自包括以下各物之群中所選擇的載氣：氬+臭氧；及氮+臭氧。
  14. 如請求項7至9中之任一項的方法，其中形成該鑭系元素介電質膜(106)包括使用金屬有機化學氣相沈積(MOCVD)以藉由注入SiCl4 及一自包括以下各物之群中所選擇的額外前驅物來形成一非晶鑭系元素混合氧化物/矽酸鹽膜：鑭甲氧基甲基丙醇化物[Ln(mmp)3]；鑭甲氧基四乙基庚二醇化物[Ln(mthd)3]；及矽烷基醯胺。
  15. 如請求項7至9中之任一項的方法，其中形成該鑭系元素介電質膜(106)包括藉由在沒有氧之情況下及在一高於450℃之溫度下在該基板上沈積SiCl4 及Gd(mmp)3前驅物而形成一穩定單介電質線Gd2 O3 膜。
  16. 一種半導體電晶體(200)，其包含：一基板(202)；一源極區域(216)及一汲極區域(216)；一在該基板(202)上之鈍化層(204)，其橋接該源極區域(216)及該汲極區域(216)；一在該鈍化層(204)上之鑭系元素介電質層(206)；一在該鑭系元素介電質層(206)上之封裝層(208)；及 一在該封裝層(208)上之閘電極(214)；其中該鑭系元素介電質層(206)之一介電常數(K)大於20；及其中該鈍化層(204)含有約40原子百分比之氧、20原子百分比之氮及40原子百分比之矽一之組合物。
  17. 如請求項16之電晶體(200)，其中該鈍化層(204)起鈍化作用以防止：界面狀態產生；固定電荷產生；及在一在該基板與該鑭系元素介電質之間的界面(203)處之SiO2 及矽化物形成。
  18. 如請求項16之電晶體(200)，其中該電晶體(200)之一有效氧化物厚度(EOT)為約1.5nm。
  19. 如請求項16之電晶體(200)，其中該電晶體(200)之一有效電子遷移率大於500cm2 /V-秒。
  20. 如請求項16之電晶體(200)，其中該電晶體(200)之一次Vt斜率為約80mV/dec。
  21. 如請求項16之電晶體(200)，其中該電晶體(200)之Vth為約0.5V。
  22. 一種半導體電容器(300)，其包含：一第一導電層(318)；一在該第一導電層(318)上之第一鈍化層(309)；一在該第一鈍化層(309)上之介電質層(306)，其包括一鑭系元素介電質膜(306)； 一在該鑭系元素介電質膜(306)上之第二鈍化層(309)；一在該第二鈍化層(309)上之第二導電層(318)；且其中，該鑭系元素介電質層(306)之一介電常數(K)大於20；及其中該第一鈍化層(309)及該第二鈍化層(309)係自包括以下各物之群中選擇：氮化鈦(TiN)；氮化鉭(TaN)；及氮化鎢(WN)。
  23. 如請求項22之電容器(300)，其中該鑭系元素介電質膜(306)係自包括以下各物之群中選擇：Pr2 O3 ；PrSiOx ；及PrTiOx 。
  24. 如請求項22之電容器(300)，其中該鑭系元素介電質膜(306)包括PrTiOx 之一層及PrSiOx 之一層。
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