TWI427775B - Semiconductor integrated circuit device and method of manufacturing a semiconductor integrated circuit device - Google Patents

Description

Semiconductor integrated circuit device and method of manufacturing same

The present invention relates to a process for forming an integrated circuit device, and more particularly to a process for forming an integrated circuit device having a memory array.

In the semiconductor industry, the trend today is to continuously increase the density of the device. In order to achieve high density, there is an ongoing effort to reduce the size of these devices to sub-micron levels on semiconductor wafers. However, many problems arise due to such circuit miniaturization.

The semiconductor process includes a front-end process that includes a process of forming a transistor in a wafer. For example, the front stage process can include a process of forming a vertical channel. Many different processes can successfully reduce the pitch of such structures, allowing for the miniaturization of the structures formed in the front-end process.

The semiconductor process also includes a post-process of wafer fabrication. The latter stage process is also commonly referred to as the back end of the line (BEOL) and typically involves the creation of metal interconnects between the transistors formed in the front stage process. The subsequent process also includes forming an insulating structure between the metal interconnects.

Although many different processes can successfully shrink the structure formed in the front-end process, such a process cannot shrink the structure formed in the back-end process. For example, although many different processes are known to successfully shrink the spacing between vertical channels formed in the front-end process, such processes cannot successfully contact the contact windows and metal interconnects in the back-end process. The spacing between them is reduced. Therefore, the miniaturization of the structure formed in the back-end process cannot limit the miniaturization capability of the entire bulk circuit device.

Accordingly, it is desirable to provide a new approach to fabricating integrated circuits to allow for the desired miniature size, particularly for the contact windows and metal structures formed in the back end process.

SUMMARY OF THE INVENTION The present invention is directed to a system, arrangement and method for fabricating a semiconductor integrated circuit that can improve the required shrinkage in many different back end process structures, such as contact windows and other metal interconnect structures. The completed structure includes at least one germanide film, such as tungsten germanium (WSi _x ) and a self-aligned germanide film, such as cobalt telluride (CoSi _x ) and nickel telluride (NiSi _x ), over a buried diffusion layer. Such a structure allows for many improvements in semiconductor devices such as semiconductor memory devices. For example, the systems and methods disclosed herein reduce the sheet resistance of a bit line structure in a semiconductor memory device without the need for a contact window continuous take-off method used in the prior art to avoid bit line load problems. Rather, the contact window is directly connected to one end of the bit line, and the relaxation of the back-end process spacing and the smaller memory array area can be achieved.

According to some embodiments of the present invention, a semiconductor integrated circuit device includes a semiconductor substrate, a first buried diffusion region over the semiconductor substrate, and a first contact layer over the first buried diffusion region. The first contact layer comprises at least one of a telluride material and a self-aligned telluride material. The semiconductor integrated circuit device also includes a memory gate structure over at least a portion of the first contact layer.

In certain embodiments, the first contact layer comprises a germanide material, and wherein the germanide material comprises tungsten.

In certain embodiments, the first contact layer comprises an auto-alignment telluride material, and wherein the auto-alignment telluride material comprises at least one of nickel and cobalt.

In some embodiments, the semiconductor integrated circuit device further includes a charge storage layer, for example, a tantalum oxide-tantalum nitride-anthracene oxide (ONO) layer is formed on at least a portion of the first contact layer .

In some embodiments, the first contact layer is connected to the one bit line via a vertical contact structure.

In some embodiments, the semiconductor integrated circuit device further includes a second buried diffusion region and a charge storage layer, wherein the charge storage layer extends between the first buried diffusion region and the second buried diffusion region . In some such embodiments, the semiconductor integrated circuit device further includes a second contact layer over the second buried diffusion region. In some such embodiments, the charge storage layer extends between the first contact layer and the second contact layer. Additionally, the second contact layer comprises an auto-alignment telluride material comprising at least one of, for example, nickel and cobalt.

According to another aspect of the present invention, a method of fabricating a semiconductor integrated circuit device includes forming a first buried diffusion region over a semiconductor substrate; forming a first contact layer in the first buried diffusion region Above, the first contact layer comprises at least one of a telluride material and a self-aligned telluride material; and a memory gate structure is formed over at least a portion of the first contact layer.

In certain embodiments, the first contact layer comprises a germanide material, and wherein the germanide material comprises tungsten.

In certain embodiments, the first contact layer comprises an auto-alignment telluride material, and wherein the auto-alignment telluride material comprises at least one of nickel and cobalt.

In some embodiments, the method further includes forming a charge storage layer, for example, comprising a tantalum oxide-tantalum nitride-anthracene oxide (ONO) layer formed over at least a portion of the first contact layer.

In some embodiments, the method further includes forming a vertical contact structure to connect the first contact layer to the one bit line.

In some embodiments, the method further includes forming a second buried diffusion region and a charge storage layer, wherein the charge storage layer extends between the first buried diffusion region and the second buried diffusion region. In some such embodiments, the method further includes forming a second contact layer over the second buried diffusion region. In some such embodiments, the charge storage layer extends between the first contact layer and the second contact layer. Additionally, the second contact layer comprises an auto-alignment telluride material comprising at least one of, for example, nickel and cobalt.

According to still another object of the present invention, a layout of a semiconductor memory device is provided, the layout comprising a first plurality of bit lines extending in a first direction; a second plurality of bit lines being substantially associated with the first Extending in a direction parallel to the direction, the second plurality of bit lines includes bit lines disposed between the first plurality of bit lines; a first plurality of buried diffusion regions are substantially parallel to the first direction Extending in a direction; a first plurality of contact layers are disposed on the respective first plurality of buried diffusion regions, and the contact layer in the first plurality of contact layers comprises at least one of a telluride material and a self-aligned telluride material And a plurality of memory gate structures extending in a second direction substantially perpendicular to the first direction, the plurality of memory gate structures being formed on at least a portion of the contact layer of the first plurality of contact layers.

In some embodiments, the contact layer in the first plurality of contact layers comprises a germanide material, and wherein the germanide material comprises tungsten.

In some embodiments, the contact layer in the first plurality of contact layers comprises an auto-alignment telluride material, and wherein the auto-alignment telluride material comprises at least one of nickel and cobalt.

In some embodiments, the layout further includes a charge storage layer, including, for example, a tantalum oxide-tantalum nitride-anthracene oxide (ONO) layer formed in at least a portion of the contact layer of the first plurality of contact layers Above.

In some embodiments, the contact layers of the first plurality of contact layers are connected to respective ones of the first plurality of bit lines via respective vertical contact structures.

In some embodiments, the layout further includes a second plurality of buried diffusion regions extending in a direction substantially parallel to the first direction; and a plurality of charge storage layers. The charge storage layer extends between each of the first buried diffusion regions of the first plurality of buried diffusion regions and the second buried diffusion region of the second plurality of buried diffusion regions.

In some embodiments, the layout further includes a second plurality of contact layers over respective second buried diffusion regions of the second plurality of buried diffusion regions. In some such embodiments, the charge storage layer of the plurality of charge storage layers extends between a respective first contact layer of the first plurality of contact layers and a second of the second plurality of contact layers Between the contact layers. Additionally, the contact layer in the second plurality of contact layers comprises a self-aligned telluride material, and wherein the auto-aligned telluride material comprises at least one of nickel and cobalt.

The objects, features, and embodiments of the present invention will be described in the accompanying drawings.

Referring to Fig. 1, there is shown a top view of a layout for achieving a back-segment relaxation using a telluride scheme in accordance with a first embodiment of the present invention. 1 is a top plan view showing a portion of an exemplary nitride read-only memory memory array 100 including a first plurality of bit lines 102 extending to respective complex top bit line transistors (top BLT), and The second plurality of bit lines 104 extend to respective complex bottom bit line transistors (bottom BLT). The first plurality of bit lines 102 extend in parallel and are located above the plurality of buried diffusion implant regions 106. The second plurality of bit lines 104 extend in parallel and are located above a plurality of buried buried implant regions 108. A first plurality of contact windows 110, which constitute an exemplary vertical contact structure, extend vertically between respective first plurality of bit lines 102 and a plurality of upper buried diffusion implant regions 106. A second plurality of contact windows 112, which also form an exemplary vertical contact structure, extend vertically between respective second plurality of bit lines 104 and a plurality of lower buried diffusion implant regions 108. The contact windows 110, 112 may be formed of a metallic material, for example, comprising tungsten or copper. Moreover, although not shown in FIG. 1, it can be seen from the description of Figures 2 through 9 below that the telluride contact window 118 can also extend over and be parallel to the respective upper buried diffusion implanted regions 106. A plurality of gate structures 115 including respective polysilicon gate structures 114 and word lines 117 extending through the bit lines 102 and 104 in the memory array 100 and burying the diffusion implant regions 106 and 108 above and below and at least substantially vertical.

Fig. 2 is a cross-sectional view showing the memory array 100 taken along the line II-II of Fig. 1, and Fig. 3 is a cross-sectional view showing the memory array 100 taken along the line III-III of Fig. 1. 2 and 3 show a substrate 116 having an upper buried diffusion implant region 106 and a lower buried diffusion implant region 108 formed therein. A telluride contact window 118 is formed over the buried diffusion implanted region 106. The upper buried diffusion implant regions 106 are connected to the respective contact windows 110 via respective germanide contact windows 118, and the lower buried diffusion implant regions 108 are connected to the respective contact windows 112. An interlayer dielectric (ILD) region 120 is formed between each of the contact windows 110 and the contact window 112. The niobium oxide-tantalum nitride-anthracene oxide (ONO) structure 122 extends between the upper and lower buried diffusion implant regions 106 and 108 along the sidewalls of the vertical channels of the substrate 116. The yttria-tantalum nitride-anthracene oxide (ONO) structure 122 can serve as a charge storage layer for a memory cell in the memory array 100.

A process embodiment for fabricating the memory array structure shown in Figures 1 through 3 will be described in conjunction with Figures 4 through 10. 4 to 9 show the intermediate structure forming the memory array 100, and Fig. 10 shows a process flow chart for forming the memory array 100. It must be noted that the intermediate structures in Figures 4 through 6 are identical to the final structures in Figures 7 through 9, except that the profiles are taken in different directions.

Referring to FIG. 4, a layer for forming the upper buried diffusion implant region 106 is formed over the substrate 116.

4 shows that a layer for forming the upper buried diffusion implant region 106 is formed over the substrate 116. Although not shown, the semiconductor device and other layers may be formed on or in the substrate 116. For example, a logic transistor can be formed in the substrate 116 using conventional methods. Patterning of different structures can be accomplished using known lithography processes, such as optical lithography processes.

The diffusion implant layer 106 is buried on top of it, and a portion thereof then becomes an upper buried diffusion implant region 106, which can be formed by, for example, ion implantation techniques. Thereafter, a germanide layer 118, a portion of which later becomes a germanide contact window 118 formed over the buried diffusion implant layer 106, may be used, for example, according to known processes, such as chemical vapor deposition (CVD). , physical vapor deposition (PVD), thermal growth, or a combination thereof, depositing a telluride tungsten germanium (WSi _x ) material. A hard mask layer 124 is then formed over the vapor layer 118. For example, the hard mask layer can be an oxidized material formed using deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), thermal growth, or combinations thereof.

Referring to FIG. 5, once the hard mask layer 124 is formed, a lithography process can be used to pattern and form the vertical vias 126. This process of forming vertical channels 126 can include a series of one or more etching processes. For example, in some embodiments, a bottom anti-reflective layer (BARC) can be formed and matched with a selective etch process, thus allowing one or more auto-alignment structures to be formed. As shown in FIG. 5, this etching includes etching through the hard mask monolayer 124 and up to the substrate 116, thus forming a vertical via 126.

Thereafter, referring to FIG. 6, a region in which the buried diffusion implant region 108 is exposed on the substrate 116 outside the vertical channel 126 is formed. This underlying buried diffusion implant region 108 can be formed using, for example, ion implantation techniques. Prior to the formation of the buried diffusion implanted region 108 below, an oxide layer 128 is formed which protects the vertical vias 126 by, for example, involving a neutral radical oxidation process.

Next, please refer to Fig. 7, which is a cross-sectional view taken along the line VII-VII of Fig. 1. In contrast to the cross-section in FIG. 6, in FIG. 7, the ONO structure 122 and the gate structure 115 including the polysilicon gate structure 114 and the word line 117 are formed first. First, excess oxidizing material, such as hard mask layer 124 and oxide layer 128, is removed using an oxide cleaning process. This ONO structure 122 is then formed over the germanide contact window 118, the sidewalls of the vertical channel 126, and the buried diffusion implant region 108 below. The ONO structure 122 can be formed by a known process including an underlying hafnium oxide layer 122A, a tantalum nitride layer 122B is formed on the lower hafnium oxide layer 122A, and an upper hafnium oxide layer 122C is formed on the tantalum nitride layer 122B. on. A thermal oxidation process can be used to form the lower hafnium oxide layer 122A and the upper hafnium oxide layer 122C, and a deposition process, such as a chemical vapor deposition (CVD), can be used to form the tantalum nitride layer 122B.

In addition, the gate structure 115 including the polysilicon gate structure 114 shown in FIG. 7 is formed over the ONO structure 122, and a word line 117 is formed over the polysilicon gate structure 114. The polysilicon gate structure 114 includes a polysilicon material, and the word line 117 includes a metal material such as tungsten germanium (WSi _x ). As shown in FIG. 10, in the process of forming the gate structure 115 including the polysilicon gate structure 114 and the word line 117, a series of deposition and lithography processes may be included, for example, deposition of tetraethoxy groups. The decane (TEOS) and the deposited polysilicon hard mask are used as a definition and lithography/etching process for forming the polysilicon gate structure 114 and the word line 117.

Thereafter, the interlayer dielectric layer (ILD) region 120, the contact windows 110, 112, and the bit lines 102, 104 may be formed to achieve the structures as shown in Figures 8 and 9, respectively, in Figures 2 and 3, respectively. The cross-sectional views shown correspond. It will be appreciated that the arrangement of the desired interlayer dielectric (ILD) region 120, contact windows 110, 112, and bit lines 102, 104 can be achieved using one or more lithography processes. For example, a lithography and etching process can be used to remove a portion of the interlayer dielectric (ILD) region 120 and the ONO structure 122 to allow the germanide contact window 118 to be directly connected to the contact window 110, and also to allow the contact window 112 to directly The buried diffusion implanted area 108 is connected below.

Figures 8 and 9 respectively show cross-sectional views of the completed structure along the II-II and III-III directions of the first drawing. The metallization process can be used to form interlayer dielectric (ILD) regions 120, contact windows 110, 112, and bit lines 102, 104 to achieve the desired memory array 100 structure, such as shown in Figures 1-3.

Figure 10 shows a process summary flow diagram for forming such a memory array 100 in accordance with an embodiment, which may form the memory array 100 structure as shown in Figures 1-9. Block 152 shows an exemplary process flow that can be used to form the structure as shown in FIGS. 4-5, including forming an upper buried diffusion implant region 106, a telluride contact window 118, and a vertical channel 126. Block 154 shows an exemplary process flow that can be used to form the structure as shown in FIG. 6 and some of the structures shown in FIG. 7, including forming a buried buried implant region 108 and an ONO structure 122. Block 156 shows an exemplary process flow that can be used to form the structure as shown in FIG. 7, including forming a gate structure 115 including a polysilicon gate structure 114 and a word line 117. After the process of block 156, the metallization process can be formed as indicated by block 158 to complete the structure shown in Figures 1-3. Other alternative processes may also be used, including, for example, alternative embodiments involving other types of memory devices.

Referring to Fig. 11, there is shown a top view of a layout for achieving a rear-span spacing relaxation using a telluride scheme in accordance with a second embodiment of the present invention. 11 is a top plan view showing a portion of a memory array 200 including a first plurality of bit lines 202 extending to respective complex top bit line transistors (top BLT), and a second plurality of bit lines 204 extends to respective complex bottom bit line transistors (bottom BLT). The first plurality of bit lines 202 extend in parallel and are located above the plurality of buried diffusion implant regions 206. The second plurality of bit lines 204 extend in parallel and are located above a plurality of buried buried implant regions 208. A first plurality of contact windows 120, which constitute an exemplary vertical contact structure, extend vertically between respective first plurality of bit lines 202 and a plurality of upper buried diffusion implant regions 206. A second plurality of contact windows 212, which also form an exemplary vertical contact structure, extend vertically between respective second plurality of bit lines 204 and a plurality of lower buried diffusion implant regions 208. The contact windows 210, 212 may be formed of a metallic material, for example, comprising tungsten or copper. Moreover, although not shown in FIG. 11, it can be seen from the description of Figures 12 through 21 below that the telluride contact window 218 can also extend over and be parallel to the respective upper buried diffusion implanted regions 206. A plurality of gate structures 215 including respective polysilicon gate structures 214 and word lines 217 extending through the bit lines 202 and 204 in the memory array 200 and buried diffusion implant regions 206 and 208 above and below and at least substantially vertical.

Fig. 12 is a cross-sectional view showing the memory array 200 taken along the line XII-XII of Fig. 11, and Fig. 13 is a cross-sectional view showing the memory array 200 taken along the line XIII-XIII of Fig. 11. 112 and 3 show a substrate 216 having an upper buried diffusion implant region 206 and a lower buried diffusion implant region 208 formed therein. The telluride contact window 218 is formed over the upper buried diffusion implant region 206 and also above the buried diffusion implant region 208. The upper buried diffusion implant regions 206 are connected to the respective contact windows 210 via respective germanium contact windows 218, and the lower buried diffusion implant regions 208 are connected to the respective contact windows 212 via respective germanium contact windows 218. An interlayer dielectric (ILD) region 120 is formed between each of the contact windows 210 and between each of the contact windows 212. The niobium oxide-tantalum nitride-anthracene oxide (ONO) structure 222 extends between the upper and lower buried diffusion implant regions 206 and 208 along the sidewalls of the vertical channels of the substrate 216. The yttria-tantalum nitride-on-oxide (ONO) structure 222 can serve as a memory gate structure, more specifically an ONO gate dielectric layer stack of a memory cell in the memory array 200.

A process embodiment for fabricating the memory array structure shown in Figures 11 through 13 will be described with reference to Figures 14 through 22. 14 through 21 show the intermediate structure forming the memory array 200, and Fig. 22 shows a process flow chart for forming the memory array 200. It must be noted that the intermediate structure in Figs. 14 to 18 is the same as the final structure in Figs. 19 to 21 except that the cross section is taken in different directions.

Referring to FIG. 14, a hard mask layer 224 is formed over the substrate 216. For example, the hard mask layer 224 can be an oxidized material formed using deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), thermal growth, or combinations thereof. Once the hard mask layer 224 is formed, a lithography process can be used to pattern and form the vertical channels 226. This process of forming vertical channels 226 can include a series of one or more etching processes. For example, in some embodiments, a bottom anti-reflective layer (BARC) can be formed and matched with a selective etch process, thus allowing one or more auto-alignment structures to be formed.

Thereafter, as shown in FIG. 15, an oxide layer 228 is formed prior to forming the upper buried diffusion implant region 206 and the lower buried diffusion implant region 208, which utilizes, for example, a method involving a neutral radical oxidation process. The vertical channel 226 is protected. The excess hard mask layer 224 can be removed using, for example, an oxide cleaning process prior to forming the upper buried diffusion implant region 206 and the lower buried diffusion implant region 208, and the oxide layer 228. An oxide layer 228 is formed, and then an upper buried diffusion implant region 206 and a lower buried diffusion implant region 208 are formed.

Figure 16 shows the results of an etch process using a buried diffusion implant region 206 from above and a buried diffusion implant region 208 to remove a portion of the oxide layer 228. A portion of the oxide layer 228 remains maintained along the sidewalls of the vertical channel 226.

Thereafter, as shown in FIG. 17, a metal layer 218', a portion of which later becomes an auto-alignment telluride contact window 218, is formed below the buried diffusion implant layer 208, the oxide layer 228 on the sidewall of the vertical via 226, and above. Buried over the implanted area 206. The metal layer 218' can be formed using a known deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), thermal growth, or combinations thereof to deposit a telluride precursor material (eg, nickel or cobalt).

Figure 18 shows the results after removing a portion of the metal layer 218', which may include a rapid thermal process. The portion of the metal layer 218' adjacent to the buried diffusion implant layer 208 and the buried diffusion implant region 206 above will react with the germanium in the buried diffusion implant layers 206 and 208, thereby resulting in the formation of a self-aligned germanide contact window 218. The diffusion implant layer 208 is buried below and the buried diffusion implanted region 206 is above.

Thereafter, please refer to Fig. 19, which is a cross-sectional view taken along the line XIX-XIX of Fig. 11 . In contrast to the cross-sectional view of Fig. 18, in Fig. 19, the ONO structure 222 and the gate structure 215 including the polysilicon gate structure 214 and the word line 217 are formed first. First, the excess oxide layer 228 material is removed using an oxide cleaning (CLN) process. The ONO structure 222 is then formed on the telluride contact window 218 (on both the buried diffusion implant layer 208 and the buried buried spread implant region 206) and along the sidewalls of the vertical via 226. The ONO structure 222 can be formed by a known process including an underlying hafnium oxide layer 222A, a tantalum nitride layer 222B is formed over the lower hafnium oxide layer 222A, and an upper hafnium oxide layer 222C is formed on the tantalum nitride layer 222B. on. A thermal oxidation process can be used to form the lower hafnium oxide layer 222A and the upper hafnium oxide layer 222C, and a deposition process, such as a chemical vapor deposition (CVD), can be used to form the tantalum nitride layer 222B.

In addition, the gate structure 215 including the polysilicon gate structure 214 shown in FIG. 19 is formed over the ONO structure 222, and a word line 217 is formed over the polysilicon gate structure 214. The polysilicon gate structure 214 includes a polysilicon material, and the word line 217 includes a metal material such as tungsten germanium (WSi _x ). As shown in FIG. 22, in the process of forming the gate structure 215 including the polysilicon gate structure 214 and the word line 217, a series of deposition and lithography processes may be included, for example, deposition of tetraethoxy groups. The decane (TEOS) and the deposited polysilicon hard mask are used as a definition and lithography/etching process for forming the polysilicon gate structure 214 and the word line 217.

Thereafter, the interlayer dielectric layer (ILD) region 220, the contact windows 210, 212, and the bit lines 202, 204 may be formed to achieve the structure as shown in FIGS. 20 and 21, respectively, in FIGS. 12 and 13 The cross-sectional views shown correspond. It will be appreciated that the arrangement of the desired interlayer dielectric (ILD) region 220, contact windows 210, 212, and bit lines 202, 204 can be achieved using one or more lithography processes. For example, the lithography and etching process can be used to remove a portion of the interlayer dielectric (ILD) region 220 and the ONO structure 222 to allow the germanium contact window 218 to be directly connected to the contact window 210, and also to allow the contact window 212 to directly The buried diffusion implanted region 208 is connected below.

Figures 20 and 21 respectively show cross-sectional views of the completed structure along the XII-XII direction and the XIII-XIII direction of the eleventh figure. The metallization process can be used to form interlayer dielectric (ILD) regions 220, contact windows 210, 212, and bit lines 202, 204 to achieve the desired memory array 200 structure, such as shown in Figures 11-13.

Figure 22 shows a process summary flow for forming such a memory array 200 in accordance with an embodiment which can form the memory array 200 structure as shown in Figures 11-21. Block 252 shows an exemplary process flow that can be used to form the structure as shown in Figures 14-16, including forming an upper buried diffusion implant region 206, a buried buried diffusion implant layer 208, and a vertical channel 226. Block 254 shows an exemplary process flow that can be used to form the structures as shown in FIGS. 17 and 18 and some of the structures shown in FIG. 19, including the formation of the telluride contact window 218 and the ONO structure 222. Block 256 shows an exemplary process flow that can be used to form the structure as shown in FIG. 19, including forming a polysilicon gate structure 214. After the process of block 256, the metallization process can be formed as indicated by block 258 to complete the structure shown in Figures 11-13. Other alternative processes may also be used, including, for example, alternative embodiments involving other types of memory devices.

Accordingly, the present invention is directed to a semiconductor integrated circuit device and method of fabricating the same that allows for the provision of a number of improved miniature back-end structures that may include contact windows and other metal interconnect structures. The completed structure includes at least one germanide film, such as tungsten germanium (WSi _x ) and a self-aligned germanide film, such as cobalt telluride (CoSi _x ) and nickel telluride (NiSi _x ), over a buried diffusion layer. Although the embodiments disclosed herein are illustrated with a nitride read-only memory memory device, alternative embodiments may include memory devices that involve other types. For example, embodiments of the present invention may also be used in a buried diffusion memory device. For example, an alternative embodiment can include a buried diffusion type memory device that includes N-bit memory cells having planar channels, vertical channels, and/or vertical channels with solid isolation structures. In addition, an alternative embodiment may include a band gap engineered yttrium-yttria-yttria-yttria-yttrium oxide-BE-SONOS or a nanocrystalline layer in place of the ONO structure 222.

Although the present invention has been described with reference to the embodiments, the present invention is not limited by the detailed description thereof. Alternatives and modifications are suggested in the foregoing description, and other alternatives and modifications will be apparent to those skilled in the art. In particular, all combinations of components that are substantially identical to the invention can achieve substantially the same results as the present invention without departing from the spirit of the invention. Therefore, all such equivalents and modifications are intended to be within the scope of the invention as defined by the appended claims and their equivalents.

100, 200. . . Memory array

102, 104, 202, 204. . . Bit line

106, 206. . . Buried diffused planting area

108, 208. . . Buried diffusion implant (LDF) area below

110, 112, 210, 212. . . Contact window

114,214. . . Polycrystalline germanium

116,216. . . Substrate

118. . . Telluride contact window

120, 220. . . Interlayer dielectric layer

122, 222. . . ONO structure

124, 224. . . Hard curtain single layer

126, 226. . . Vertical channel

128, 228. . . Oxide layer

218'. . . Metal layer

218. . . Automatic alignment of the telluride contact window

The invention is defined by the scope of the patent application. These and other objects, features, and embodiments are described in the following sections of the accompanying drawings, in which:

Figure 1 is a top plan view showing a portion of an exemplary nitride read only memory (NROM) memory array.

Fig. 2 is a cross-sectional view showing the memory array along the line II-II of Fig. 1.

Fig. 3 is a cross-sectional view showing the memory array along the line III-III of Fig. 1;

4 to 9 are cross-sectional views showing the intermediate structure of the memory array in Figs. 1 to 3.

Fig. 10 is a flow chart showing the process of forming the memory array according to the embodiment of Figs. 1 to 9.

Figure 11 is a top plan view showing a portion of another exemplary nitride read only memory (NROM) memory array.

Figure 12 is a cross-sectional view showing the memory array along the line XII-XII of Figure 11;

Figure 13 is a cross-sectional view showing the memory array along the line XIII-XIII of Figure 11;

Figs. 14 to 21 show cross-sectional views showing the intermediate structure of the memory array in Figs. 11 to 13.

Fig. 22 is a flow chart showing the process of forming the memory array according to the embodiment of Figs. 14 to 21.

102, 104. . . Bit line

106. . . Buried diffused planting area

108. . . Buried diffusion implant (LDF) area below

110, 112. . . Contact window

116. . . Substrate

118. . . Telluride contact window

120. . . Interlayer dielectric layer

122. . . ONO structure

Claims (27)

A semiconductor integrated circuit device comprising: a semiconductor substrate; a first buried diffusion region over the semiconductor substrate; a first contact layer over the first buried diffusion region, the first contact layer comprising a germanide material And automatically aligning at least one of the mash material; a memory gate structure over at least a portion of the first contact layer; and a second buried diffusion region and a charge storage layer, wherein the charge storage layer extends between The first buried diffusion region is between the second buried diffusion region. The semiconductor integrated circuit device of claim 1, wherein the first contact layer comprises a vaporized material, and wherein the germanide material comprises tungsten. The semiconductor integrated circuit device of claim 1, wherein the first contact layer comprises an auto-alignment telluride material, and wherein the auto-alignment telluride material comprises at least one of nickel and cobalt. The semiconductor integrated circuit device of claim 1, wherein the first contact layer is connected to the one-dimensional line via a vertical contact structure. The semiconductor integrated circuit device of claim 1, wherein the charge storage layer is located on a sidewall of a vertical channel. The semiconductor integrated circuit device of claim 1, further comprising a second contact layer over the second buried diffusion region. The semiconductor integrated circuit device of claim 5, wherein the charge storage layer extends between the first contact layer and the second contact layer. The semiconductor integrated circuit device of claim 6, wherein the second contact layer comprises an auto-alignment telluride material. The semiconductor integrated circuit device of claim 8, wherein the self-aligned telluride material comprises at least one of nickel and cobalt. A method of fabricating a semiconductor integrated circuit device, the method comprising: forming a first buried diffusion region over a semiconductor substrate; forming a first contact layer over the first buried diffusion region, the first contact layer Forming at least one of a telluride material and a self-aligned telluride material; forming a memory gate structure over at least a portion of the first contact layer; and forming a second buried diffusion region and a charge storage layer, wherein the The charge storage layer extends between the first buried diffusion region and the second buried diffusion region. The method of claim 10, wherein the first contact layer comprises a vaporized material, and wherein the vaporized material comprises tungsten. The method of claim 10, wherein the first contact layer comprises an autoalignment telluride material, and wherein the autoalignment telluride material comprises at least one of nickel and cobalt. The method of claim 10, further comprising: forming a vertical contact structure connected to the first contact layer; Forming a one-dimensional line is connected to the first contact layer via the vertical contact structure. The method of claim 11, wherein the charge storage layer is located on a sidewall of a vertical channel. The method of claim 11, further comprising forming a second contact layer over the second buried diffusion region. The method of claim 15, wherein the charge storage layer extends between the first contact layer and the second contact layer. The method of claim 15, wherein the second contact layer comprises a self-aligning telluride material. The method of claim 17, wherein the self-aligning telluride material comprises at least one of nickel and cobalt. A layout of a semiconductor memory device includes: a first plurality of bit lines extending in a first direction; a second plurality of bit lines extending in a direction substantially parallel to the first direction, the second plurality The bit line includes a bit line disposed between the first plurality of bit lines; a first plurality of buried diffusion regions extending in a direction substantially parallel to the first direction; a first plurality of contacts And a layer of the first plurality of buried diffusion regions, wherein the contact layer of the first plurality of contact layers comprises at least one of a telluride material and a self-aligned telluride material; a plurality of memory gate structures extending in a second direction substantially perpendicular to the first direction, a plurality of memory gate structures being formed over at least a portion of the first plurality of contact layers; a second plurality a buried diffusion region extending in a direction substantially parallel to the first direction; and a plurality of charge storage layers; wherein the charge storage layer extends between each of the first plurality of buried diffusion regions and the first buried diffusion region Between each of the second plurality of buried diffusion regions in the second buried diffusion region. The layout of the semiconductor memory device of claim 19, wherein the contact layer of the first plurality of contact layers comprises a germanide material, and wherein the germanide material comprises tungsten. The semiconductor memory device of claim 19, wherein the contact layer of the first plurality of contact layers comprises a self-aligned germanide material, and wherein the self-aligned germanide material comprises at least nickel and cobalt One. The layout of the semiconductor memory device of claim 19, wherein the contact layers of the first plurality of contact layers and the respective bit lines of the first plurality of bit lines are via respective vertical contact structures connection. The layout of the semiconductor memory device of claim 19, wherein the charge storage layer is located on a respective sidewall of the respective vertical channel. The layout of the semiconductor memory device of claim 19, further comprising a second plurality of contact layers over respective second buried diffusion regions of the second plurality of buried diffusion regions. The layout of the semiconductor memory device of claim 24, wherein the charge storage layer of the plurality of charge storage layers extends between the first contact layer and the second plurality of the first plurality of contact layers Between the respective second contact layers in the contact layers. The layout of the semiconductor memory device of claim 24, wherein the contact layer of the second plurality of contact layers comprises a self-aligned telluride material. The layout of the semiconductor memory device of claim 26, wherein the self-aligned telluride material comprises at least one of nickel and cobalt.