TWI427301B - Dc-to-dc converter having test circuit - Google Patents

Description

DC converter with test circuit

The present disclosure relates to a test circuit, and more particularly to a test circuit for a DC converter and a test method therefor.

DC converters have a wide range of applications in many circuit designs. For example, a light-emitting diode circuit often uses a DC converter to drive the light-emitting diodes for illumination. The inductor is an essential component in the DC converter to couple the power supply to the DC converter's power MOS transistor so that the power MOS transistor can draw current from the supply voltage through the inductor. The capacitor in the middle is charged to cause the light emitting diode to conduct and emit light. Therefore, it is necessary to test whether the overcurrent protection mechanism of the inductor is activated when the current of the inductor reaches the upper limit of the current to ensure that the inductor and the power MOS transistor are protected when an overcurrent occurs. However, probes that measure current are often unable to withstand large currents. Therefore, in the conventional design, it is quite difficult to directly test whether the overcurrent mechanism is activated.

Therefore, how to design a new DC converter with test circuit to overcome the above problems is an urgent problem to be solved in the industry.

Accordingly, one aspect of the present disclosure is to provide a test circuit for a dc-to-dc converter, wherein the DC converter includes an inductor, a capacitor, a load, and a power MOS transistor. The MOS transistor is used to conduct the drive current from the inductor, and further charges the capacitor to drive the load. The test circuit includes a current mirror and an overcurrent detector. The current mirror includes an input branch, an operational branch, and a test branch that generate an input current based on the drive current. The overcurrent detector is connected to the operating branch and the test branch. In the operational mode, the operational branch is enabled and the test branch is disabled so that the overcurrent detector receives the operating voltage from the operational branch and is generated from the operating current obtained by the mirroring of the input current, Determine if an overcurrent condition has occurred. In the test mode, the test branch is enabled and the operating branch is disabled so that the overcurrent detector receives the test voltage from the test branch and is generated from the test current obtained by the mirroring of the input current, A determination is made as to whether an overcurrent condition is generated, wherein the drive current in the test mode sufficient to trigger an overcurrent condition is less than the drive current in the operational mode sufficient to trigger an overcurrent condition.

According to an embodiment of the present disclosure, the test branch includes a test switch, and the operation branch includes an operation switch for receiving the mode selection signal, so that when the mode selection signal starts the operation mode in the first state, the test branch is borrowed By the test switch, the operation branch is enabled by the operation switch, and when the mode selection signal is activated in the second state, the operation branch is activated by the operation switch, and the test branch is tested by The switch is enabled.

According to another embodiment of the present disclosure, the test branch further includes a test load in series with the test switch, so that the test voltage is generated according to the test current and the test load, and the operation branch further includes the operation One of the switches in series operates the load such that the operating voltage is generated based on the operating current and the operational load.

According to still another embodiment of the present disclosure, the magnitudes of the operating current and the test current are the same.

According to still another embodiment of the present disclosure, the overcurrent detector further determines whether an overcurrent condition is generated by determining whether the test voltage or the operating voltage is greater than a reference voltage. The overcurrent detector is a comparator, and the comparator includes a first input end, a second input end, and an output end, the first input end is configured to receive a test voltage or an operating voltage, and the second input end is configured to receive a reference voltage and output The end is used to generate a comparison result.

In accordance with an embodiment of the present disclosure, in the test mode, the drive current is measured by the probe.

Another aspect of the present disclosure is to provide a DC converter. The DC converter consists of an inductor, a capacitor, a load, a power MOS transistor, and a test circuit. The power MOS transistor is connected from the connection terminal to the inductor, the capacitor and the load, and is used to conduct the drive current from the inductor to further charge the capacitor to drive the load. The test circuit includes: a current mirror and an overcurrent detector. The current mirror includes an input branch, an operational branch, and a test branch that generate an input current based on the drive current. The overcurrent detector is connected to the operating branch and the test branch. In the operational mode, the operational branch is enabled and the test branch is disabled so that the overcurrent detector receives the operating voltage from the operational branch and is generated from the operating current obtained by the mirroring of the input current, Determine if an overcurrent condition has occurred. In the test mode, the test branch is enabled and the operating branch is disabled so that the overcurrent detector receives the test voltage from the test branch and is generated from the test current obtained by the mirroring of the input current, A determination is made as to whether an overcurrent condition is generated, wherein the drive current in the test mode sufficient to trigger an overcurrent condition is less than the drive current in the operational mode sufficient to trigger an overcurrent condition.

According to an embodiment of the present disclosure, the test branch includes a test switch, and the operation branch includes an operation switch for receiving the mode selection signal, so that when the mode selection signal starts the operation mode in the first state, the test branch is borrowed By the test switch, the operation branch is enabled by the operation switch, and when the mode selection signal is activated in the second state, the operation branch is activated by the operation switch, and the test branch is tested by The switch is enabled.

According to another embodiment of the present disclosure, the test branch further includes a test load in series with the test switch, so that the test voltage is generated according to the test current and the test load, and the operation branch further includes the operation One of the switches in series operates the load such that the operating voltage is generated based on the operating current and the operational load.

According to still another embodiment of the present disclosure, the magnitudes of the operating current and the test current are the same.

According to still another embodiment of the present disclosure, the overcurrent detector further determines whether an overcurrent condition is generated by determining whether the test voltage or the operating voltage is greater than a reference voltage. The overcurrent detector is a comparator, and the comparator includes a first input end, a second input end, and an output end, the first input end is configured to receive a test voltage or an operating voltage, and the second input end is configured to receive a reference voltage and output The end is used to generate a comparison result.

In accordance with an embodiment of the present disclosure, in the test mode, the drive current is measured by the probe.

According to still another embodiment of the present disclosure, the DC converter further includes a control module for connecting the gate of the power amplifier to control whether the power amplifier is turned on or not. In the operation mode, when the overcurrent detector determines that an overcurrent condition occurs, the power amplifier is turned off by the control module.

The advantage of applying the present disclosure is that the overcurrent condition can be measured by the method of triggering an overcurrent condition with a small driving current in the test mode, and the above object can be easily achieved.

Please refer to Figure 1. FIG. 1 is a circuit diagram of a DC converter 1 in an embodiment of the disclosure. The DC converter 1 includes an inductor 10, a capacitor 12, a load 14, a power MOS transistor 16, a control module 18, and a test circuit 2.

The power MOS transistor 16 is connected to the inductor 10, the capacitor 12, and the load 14 via a connection terminal P. The power MOS transistor 16 is used to switch to further charge and discharge the capacitor 12 to drive the load 14. In one embodiment, the load 14 includes a plurality of light emitting diodes (not shown) to cause the light emitting diodes to conduct and emit light when the power MOS transistors 16 are turned on. When the power MOS transistor 16 is turned off, the capacitor 12 will discharge to turn off the light-emitting diode.

In one embodiment, the power MOS transistor 16 is an N-type MOS transistor, wherein the drain of the power MOS transistor 16 is connected to the connection terminal P. In an embodiment, in the operation mode, the supply voltage Vss is connected to the connection terminal P through the inductor 10 such that the voltage of the supply voltage Vss is coupled to the connection terminal P through the inductor 10. Therefore, when the power MOS transistor 16 is turned on, the driving current Id can be drawn from the supply voltage Vss through the inductor 10 to charge the capacitor 12 to drive the load 14.

The control module 18 is connected to the power MOS transistor 16. The control module 18 can include an error amplifier, an oscillator, and a bandwidth modulator (not shown) to control the gate of the power MOS transistor 16 based on the reference voltage Vr and the feedback voltage FB. In the operation mode, the control module 18 can control the gate of the power MOS transistor 16 according to the comparison result between the reference voltage Vr and the feedback voltage FB to control the turn-on and turn-off of the power MOS transistor 16. In one embodiment, the feedback voltage FB is a voltage associated with an output voltage (not shown) of the load 14.

The current limit of the inductor 10 is an important parameter to determine the maximum amount of current that the inductor 10 can withstand. Therefore, when the upper limit of the current of the inductor 10 arrives, whether the overcurrent protection mechanism can be accurately activated to protect the inductor and the power MOS transistor is one of the items that must be tested in the circuit.

However, probes that measure current are often unable to withstand large currents. Therefore, in the conventional design, it is quite difficult to directly test whether the overcurrent mechanism is activated.

Therefore, please refer to Figure 2 at the same time. FIG. 2 is a schematic diagram of the test circuit 2 in an embodiment of the disclosure. The test circuit 2 includes a current mirror 20 and an overcurrent detector 22. Current mirror 20 includes an input branch 24, an operational branch 26, and a test branch 28. It should be noted that in FIG. 2, the inductor 10 and the power MOS transistor 16 are also shown.

The input branch 24 in this embodiment includes an input switch 240. Input switch 240 and power MOS transistor 16 are controlled in this embodiment by control signal 11 also from control module 18. Therefore, the input current Ic in the input branch 24 will be simultaneously generated based on the drive current Id of the power MOS transistor 16. In one embodiment, the drive current Id is a multiple of the input current Ic.

In the present embodiment, test branch 28 includes test switch 280 and test load 282 in series. The operational branch 26 includes an operational switch 260 and an operational load 262 that are connected in series. The test switch 280 and the operation switch 260 are respectively configured to receive the mode selection signal 21, so that when the mode selection signal 21 starts the operation mode in the first state, the test branch 28 is disabled by the test switch 280, and the branch 26 is operated. It is enabled by operating switch 260. When the mode selection signal 21 starts the test mode in the second state, the operation branch 26 is disabled by the operation switch 260, and the test branch 28 is enabled by the test switch 280. In this embodiment, the test mode is started when the mode selection signal 21 is high, and the high state is directly transmitted to the test switch 280 to enable the test branch 28, and the high state is turned to the low state via the inverter. It is passed to the operation switch 260 to inhibit the operation of the branch 26. When the mode selection signal 21 is in a low state, the opposite operation mode is omitted, and details are not described herein again.

In this embodiment, the input switch 240, the test switch 280, and the operation switch 260 are all N-type MOS transistors, and are designed to have the same component size so that when the operation branch 26 is enabled, the input current Ic is mirrored. The operating current Io and the test current It mirrored by the input current Ic are both the same as the input current Ic.

Due to the test current It and the test load 282, the test branch 28 can generate the test voltage Vt in the test mode, and the operating branch 26 can generate the operating voltage Vo during the operating mode due to the operating current Io and the operating load 262. In the present embodiment, the operational load 262 has a resistance R1 and the test load 282 has a resistance R2.

Therefore, when the power MOS transistor 16 is turned on to generate the drive current Id, the input current Ic will become Id/α. The operating voltage Vo generated in the operating mode will be (Id/α)*R1. The test voltage Vt generated in the test mode will be (Id/α)*R2.

In one embodiment, the resistance of the test load 282 can be designed to be β times the resistance of the operational load 262. In other words, R2 = β * R1. Therefore, the test voltage Vt will be expressed as (Id/α)*β*R1. The drive current Ido in the operation mode can be expressed as (Vo*R1)*α, and the drive current Idt in the test mode can be expressed as (Vt*R1)*(α/β).

The operational branch 26 and the test branch 28 are further connected to the overcurrent detector 22. In this embodiment, the overcurrent detector 22 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is configured to receive the test voltage Vt or the operating voltage Vo, and the second input terminal is configured to receive the test voltage Vt or the operating voltage Vo. The reference voltage Vref is received, and the output is used to generate a comparison result Vocp_out. The reference voltage Vref and the reference voltage Vr in the control module 18 can be different voltage values as previously described. When the test voltage Vt or the operating voltage Vo is greater than the value of the reference voltage Vref, the overcurrent detector 22 will determine that an overcurrent condition is generated. In the operational mode, the overcurrent detector 22 will output the comparison result Vocp_out to the control module 18 such that when an overcurrent condition occurs, the control module 18 can thereby disable the power MOS transistor 16. The power MOS transistor 16 or the inductor 10 is protected from damage.

In an embodiment, β can be designed to a value greater than one. Since the voltage value for triggering the overcurrent condition is equivalent to the reference voltage Vref, in the operation mode, the drive current Ido that can trigger the overcurrent condition is (Vref/R1)*α. In the test mode, the drive current Idt that can trigger the overcurrent condition is (Vref/R1)*(α/β). Therefore, since β is a value greater than 1, the drive current Idt required to trigger the overcurrent condition in the test mode is smaller than the drive current Ido in the operation mode.

For example, if β is 24 and the drive current Ido required to trigger an overcurrent condition in the operating mode is 4.8 amps, the drive current Idt required to trigger an overcurrent condition in the test mode is only 200 milliamps.

It should be noted that in other embodiments, the test branch and the operational branch in the current mirror may have other forms of design. However, the test branch must be designed to generate a test voltage sufficient to trigger an overcurrent condition with a small drive current in the operating mode in the test mode so that the probe can thus measure this smaller drive current in the test mode. .

The advantage of applying the present disclosure is that the overcurrent condition can be measured by triggering an overcurrent condition with a small drive current in the test mode.

The present disclosure has been disclosed in the above embodiments, but it is not intended to limit the disclosure, and any person skilled in the art can make various changes and refinements without departing from the spirit and scope of the disclosure. The scope of protection of the disclosure is subject to the definition of the scope of the patent application.

1. . . DC converter

10. . . inductance

12. . . capacitance

14. . . load

16. . . Power MOS semi-transistor

18. . . Control module

2. . . Test circuit

20. . . Current mirror

twenty one. . . Mode selection signal

twenty two. . . Over current detector

twenty four. . . Input branch

240. . . Input switch

26. . . Operational branch

260. . . Operating switch

262. . . Operating load

28. . . Test branch

280. . . Test switch

282. . . Test load

The above and other objects, features, advantages and embodiments of the present disclosure will become more apparent and understood.

1 is a circuit diagram of a DC converter in an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a test circuit in an embodiment of the disclosure.

10. . . inductance

11. . . Control signal

2. . . Test circuit

20. . . Current mirror

twenty one. . . Mode selection signal

twenty two. . . Over current detector

twenty four. . . Input branch

240. . . Input switch

26. . . Operational branch

260. . . Operating switch

262. . . Operating load

28. . . Test branch

280. . . Test switch

282. . . Test load

Claims (16)

A test circuit is applied to a dc-to-dc converter, wherein the DC converter comprises an inductor, a capacitor, a load, and a power MOS transistor, the power MOS transistor Is used to conduct a driving current from the inductor, and further charge the capacitor to drive the load. The test circuit includes: a current mirror, including an input branch for generating an input current according to the driving current, and a An operating branch and a test branch; and an overcurrent detector coupled to the operational branch and the test branch; wherein in an operational mode, the operational branch is enabled and the test branch is Suppressing, so that the overcurrent detector receives an operating voltage from the operating branch and generates an operating current according to a mirrored current of the input current, and determines whether an overcurrent condition is generated; and wherein In a test mode, the test branch is enabled and the operational branch is disabled such that the overcurrent detector receives from the test branch and is mirrored by the input current The test current generates one of the test voltages, 俾 determining whether an overcurrent condition is generated, wherein the drive current in the test mode sufficient to trigger the overcurrent condition is less than the drive current sufficient to trigger the overcurrent condition in the operational mode . The test circuit of claim 1, wherein the test branch includes a test switch, the operation branch includes an operation switch for receiving a mode selection signal, so that when the mode selection signal is activated in a first state In the mode of operation, the test branch is disabled by the test switch, and The operation branch is enabled by the operation switch, and when the mode selection signal activates the test mode in a second state, the operation branch is disabled by the operation switch, and the test branch is enabled by The test switch is enabled. The test circuit of claim 2, wherein the test branch further comprises a test load in series with the test switch, so that the test voltage is generated according to the test current and the test load, and the operation branch further includes The operational switch is connected in series to operate the load such that the operating voltage is generated based on the operating current and the operational load. The test circuit of claim 1, wherein the operating current and the magnitude of the test current are the same. The test circuit of claim 1, wherein the overcurrent detector further determines whether the overcurrent condition is generated by determining whether the test voltage or the operating voltage is greater than a reference voltage. The test circuit of claim 5, wherein the overcurrent detector is a comparator, the comparator includes a first input terminal, a second input terminal, and an output terminal, the first input terminal is configured to receive The test voltage or the operating voltage, the second input is used to receive the reference voltage, and the output is used to generate a comparison result. The test circuit of claim 1, wherein the test mode is In the formula, the driving current is measured by a probe. A DC converter comprising: an inductor connected to a supply voltage; a capacitor; a load; a power MOS semi-transistor connected to the inductor, the capacitor and the load by a connection, the power oxy-half The transistor is used to conduct, to draw a driving current from the supply voltage from the inductor, further charging the capacitor to drive the load; a test circuit comprising: a current mirror, comprising: generating an input according to the driving current a current input branch, an operational branch, and a test branch; and an overcurrent detector coupled to the operational branch and the test branch; wherein in an operational mode, the operational branch is Enabled and the test branch is disabled, such that the overcurrent detector receives an operating voltage from the operating branch and generates an operating current according to a mirrored current of the input current, and determines an overcurrent Whether the situation is generated; and wherein in a test mode, the test branch is enabled and the operational branch is disabled such that the overcurrent detector receives the test branch and is based on The input current of one of the mirrored test current is generated to give one test voltage, determining whether to serve an overcurrent condition is generated, wherein in the test mode is sufficient to trigger the current through the drive train is smaller than the case where the current operating mode The drive current is sufficient to trigger the overcurrent condition. The DC converter of claim 8, wherein the test branch includes a test switch, the operation branch includes an operation switch for receiving a mode selection signal, so that when the mode selection signal is in a first state When the operation mode is activated, the test branch is enabled by the test switch, and the operation branch is enabled by the operation switch, and when the mode selection signal is activated in a second state to start the test mode, The operational branch is disabled by the operational switch and the test branch is enabled by the test switch. The DC converter of claim 9, wherein the test branch further comprises a test load in series with the test switch, so that the test voltage is generated according to the test current and the test load, and the operation branch further includes The operational switch operates in series with one of the loads such that the operating voltage is generated based on the operating current and the operational load. The DC converter of claim 8, wherein the operating current and the magnitude of the test current are the same. The DC converter of claim 8, wherein the overcurrent detector further determines whether the overcurrent condition is generated by determining whether the test voltage or the operating voltage is greater than a reference voltage. The DC converter of claim 12, wherein the overcurrent detection The comparator is a comparator, the comparator includes a first input terminal, a second input terminal, and an output terminal, the first input terminal is configured to receive the test voltage or the operating voltage, and the second input terminal is configured to receive the test voltage or the operating voltage. The reference voltage is received, and the output is used to generate a comparison result. A DC converter as claimed in claim 8 wherein, in the test mode, the drive current is measured by a probe. The DC converter of claim 8, further comprising a control module connected to the gate of the power MOS transistor to control whether the power amplifier is turned on or not. The DC converter of claim 15, wherein in the operation mode, when the overcurrent detector determines that the overcurrent condition occurs, the power MOS transistor is turned off by the control module.