TWI426572B - Structure and process for microelectromechanical system-based sensor - Google Patents
Structure and process for microelectromechanical system-based sensor Download PDFInfo
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
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- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
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Description
本發明係有關於一種微機電感測裝置及其製造方法，特別是有關於一種微機電感測裝置的導線配置及其製造方法。The invention relates to a microcomputer inductance measuring device and a manufacturing method thereof, in particular to a wire arrangement of a microcomputer inductance measuring device and a manufacturing method thereof.
微機電感測元件已積極地整合於人類之日常生活產業中，如導航裝置、遊戲娛樂、手持式通訊、汽機車電子等產業；另一方面由全球產業市場資訊來看，未來無論是在感測元件或感測系統模組之產值上，在未來皆呈現可預期之高度成長趨勢。Microcomputer inductance measuring components have been actively integrated into the daily life industry of human beings, such as navigation devices, game entertainment, handheld communication, automobile and motorcycle electronics, etc. On the other hand, from the perspective of global industrial market information, the future is in the sense The output value of the measuring component or the sensing system module will have a predictable high growth trend in the future.
然而，習知的微機電感測元件係設置於玻璃基材上，因而仍具有許多缺點。舉例來說，玻璃基材厚度因受限玻璃研磨加工基礎產業之不足，所以整體元件厚度無法完整薄化。另外，設置於玻璃基材和固定構件之間的導線薄細，需覆蓋一額外保護氧化層以避免導線變形移位。再者，為了保證固定構件(anchor)與導線和玻璃基材接觸品質，固定構件上需額外設置一金屬接觸層以供固定構件與導線之物理嵌合製程進行，接合面積難以提升。此外，習知技術利用蝕刻加工製程來形成構件，因而構件厚度變異範圍係難以控制。However, conventional microcomputer inductance measuring components are disposed on a glass substrate and thus still have many disadvantages. For example, the thickness of the glass substrate is insufficient for the basic industry of the limited glass grinding process, so the overall component thickness cannot be completely thinned. In addition, the wire disposed between the glass substrate and the fixing member is thin and needs to be covered with an additional protective oxide layer to avoid deformation and displacement of the wire. Furthermore, in order to ensure the contact quality between the anchor and the wire and the glass substrate, a metal contact layer is additionally provided on the fixing member for the physical fitting process of the fixing member and the wire, and the joint area is difficult to be improved. In addition, conventional techniques utilize an etching process to form a member, and thus the range of variation in the thickness of the member is difficult to control.
因此，有必要尋求一種具有可極度薄化、低元件成本、高元件特性穩定度、與高元件可靠性微機電感測裝置及其製造方法，其能夠改善或避免上述的問題。Therefore, it is necessary to find a microcomputer inductance measuring device which can be extremely thinned, low component cost, high component characteristic stability, and high component reliability, and a manufacturing method thereof, which can improve or avoid the above problems.
有鑑於此，本發明實施例提供一種微機電感測裝置及其製造方法。本發明一實施例之微機電感測裝置包括一基材晶片；一第一絕緣層，覆蓋上述基材晶片的一頂面上；一感測元件層，設置於上述第一絕緣層的一頂面上，其包含一外環區與一感測構件區，上述感測構件區與上述外環區之間具有一空氣溝槽，其中上述感測構件區包含一固定構件與一可動構件；一第二絕緣層，設置於上述感測元件層的一頂面上，並架橋於上述外環區和部分上述固定構件上；一導線圖案，設置於上述第二絕緣層上，並電性連接上述固定構件。In view of this, an embodiment of the present invention provides a microcomputer inductance measuring device and a manufacturing method thereof. A microcomputer inductance measuring device according to an embodiment of the invention includes a substrate wafer; a first insulating layer covering a top surface of the substrate wafer; and a sensing element layer disposed on a top of the first insulating layer The surface includes an outer ring region and a sensing member region, and the sensing member region and the outer ring region have an air groove, wherein the sensing member region comprises a fixing member and a movable member; a second insulating layer is disposed on a top surface of the sensing element layer and is bridged on the outer ring region and a portion of the fixing member; a wire pattern is disposed on the second insulating layer and electrically connected to the above Fixed component.
本發明另一實施例之微機電感測裝置製造方法包括提供一基材晶片；於上述基材晶片的一頂面上沉積一第一絕緣層；進行一第一接合製程，將一絕緣層上覆矽晶片設置於該第一絕緣層的一頂面上感測元件層，其中該絕緣層上覆矽晶片包括一基板層；一感測元件層，其中該感測元件層包含一空氣溝槽，介於一感測構件區與一外環區之間；一第二絕緣層，設置於該基板層和該感測元件層之間，其中該感測元件層接觸該第一絕緣層；移除該絕緣層上覆矽晶片之全部的該基板層；移除部分上述第二絕緣層，以形成一第二絕緣層圖案，以使位於上述感測構件區內的上述感測元件層從上述第二絕緣層圖案暴露出來，並使上述第二絕緣層圖案架橋於上述感測元件層的上述外環區和部分上述感測構件區上；於上述第二絕緣層圖案的一頂面上形成一導線圖案，並延伸連接至暴露出來的上述感測元件層。A method for manufacturing a microcomputer inductance measuring device according to another embodiment of the present invention includes: providing a substrate wafer; depositing a first insulating layer on a top surface of the substrate wafer; performing a first bonding process on an insulating layer The cover wafer is disposed on a top surface of the first insulating layer, wherein the overlying germanium wafer comprises a substrate layer; a sensing device layer, wherein the sensing device layer comprises an air trench Between a sensing member region and an outer ring region; a second insulating layer disposed between the substrate layer and the sensing device layer, wherein the sensing device layer contacts the first insulating layer; Removing the portion of the substrate layer over the insulating layer; removing a portion of the second insulating layer to form a second insulating layer pattern such that the sensing element layer located in the sensing member region is The second insulating layer pattern is exposed, and the second insulating layer pattern is bridged on the outer ring region and a portion of the sensing member region of the sensing element layer; and formed on a top surface of the second insulating layer pattern a wire pattern and extension Above the sensing element is coupled to the exposed layer.
以下以各實施例詳細說明並伴隨著圖式說明之範例，做為本發明之參考依據。在圖式或說明書描述中，相似或相同之部分皆使用相同之圖號。且在圖式中，實施例之形狀或是厚度可擴大，並以簡化或是方便標示。再者，圖式中各元件之部分將以分別描述說明之，值得注意的是，圖中未繪示或描述之元件，為所屬技術領域中具有通常知識者所知的形式。The following is a detailed description of the embodiments and examples accompanying the drawings, which are the basis of the present invention. In the drawings or the description of the specification, the same drawing numbers are used for similar or identical parts. In the drawings, the shape or thickness of the embodiment may be expanded and simplified or conveniently indicated. In addition, the components of the drawings will be described separately, and it is noted that elements not shown or described in the drawings are known to those of ordinary skill in the art.
第1a~6b、7圖為本發明一實施例之微機電感測裝置500a的製程上視圖。第1b至4b圖為沿第1a至4a圖之A-A’切線剖面圖。第5b、6b圖沿第5a、6a圖之C-C’切線剖面圖。在本發明實施例的微機電感測裝置500a可包括振盪器、陀螺儀或磁力計等，而第1a~6b、7圖所示之微機電感測裝置500a係以振盪器做為本發明實施例，然非限制本發明。請參考第1a、1b圖，首先，提供一基材晶片200。在本發明一實施例中，基材晶片200可為例如矽晶片之半導體晶片。在本發明另一實施例中，之後，可於基材晶片200的一頂面201上形成例如光阻之一遮罩圖案(圖未顯示)，以定義出一凹陷區的形成位置。接著，對基材晶片200進行一非等向性蝕刻製程，從基材晶片200的頂面201移除部分基材晶片200，以形成凹陷區202。最後，移除上述遮罩圖案。上述凹陷區202的位置係對應於最終之微機電感測裝置500a的可動構件所在的位置，以使後續形成的上述可動構件設置於凹陷區202內，並利於可動構件於其中自由移動。1a to 6b and 7 are top views of processes of the microcomputer inductance measuring device 500a according to an embodiment of the present invention. Figures 1b to 4b are cross-sectional views taken along line A-A' of Figures 1a through 4a. Figures 5b and 6b are cross-sectional views taken along line C-C' of Figs. 5a and 6a. The microcomputer inductance measuring device 500a according to the embodiment of the present invention may include an oscillator, a gyroscope or a magnetometer, and the microcomputer inductance measuring device 500a shown in FIGS. 1a to 6b and 7 is an oscillator. For example, the invention is not limited. Please refer to FIGS. 1a and 1b. First, a substrate wafer 200 is provided. In an embodiment of the invention, the substrate wafer 200 can be a semiconductor wafer such as a germanium wafer. In another embodiment of the present invention, a mask pattern (not shown) such as a photoresist may be formed on a top surface 201 of the substrate wafer 200 to define a formation position of a recess. Next, an anisotropic etching process is performed on the substrate wafer 200 to remove a portion of the substrate wafer 200 from the top surface 201 of the substrate wafer 200 to form the recessed regions 202. Finally, the above mask pattern is removed. The position of the recessed area 202 corresponds to the position of the movable member of the final microcomputer inductance measuring device 500a, so that the subsequently formed movable member is disposed in the recessed area 202 and facilitates free movement of the movable member therein.
請參考第2a、2b圖，接著，可利用化學氣相沉積(CVD)法、原子層沉積法(ALD)等沉積方式，於基材晶片200的頂面201上順應性沉積一第一絕緣層204。在本發明一實施例中，第一絕緣層204可為一氧化矽層。Referring to FIGS. 2a and 2b, a first insulating layer may be deposited on the top surface 201 of the substrate wafer 200 by a deposition method such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). 204. In an embodiment of the invention, the first insulating layer 204 may be a hafnium oxide layer.
然後，請參考第3a、3b圖，提供一絕緣層上覆矽晶片(SOI wafer)216。在本發明一實施例中，絕緣層上覆矽晶片216包括例如矽之半導體材料構成的感測元件層(device layer)208和基板層(handle layer)214，以及設置於上述兩者之間的第二絕緣層212。Then, referring to Figures 3a and 3b, an SOI wafer 216 is provided. In an embodiment of the invention, the overlying insulating germanium wafer 216 includes a sensing device layer 208 and a handle layer 214 of a semiconductor material such as germanium, and is disposed between the two. The second insulating layer 212.
接著，於絕緣層上覆矽晶片216的感測元件層208中形成溝槽210，以定義出最終形成之微機電感測裝置的固定構件的邊界位置。於感測元件層208上形成一遮罩圖案(圖未顯示)，以定義出後續形成溝槽的位置。之後，進行一非等向蝕刻製程，移除未被圖案化遮罩覆蓋的感測元件層208，以於感測元件層208中形成穿過感測元件層208的溝槽210，此時第一絕緣層204也可做為上述蝕刻製程的蝕刻停止層。最後，移除上述遮罩圖案。如第3b圖之剖面圖所示，溝槽210係橫向介於感測元件層208的感測構件區220與外環區218之間。在本實施例中，溝槽210用以將最終微機電感測裝置500a之感測構件區220的固定構件與外環區218橫向隔開，做為固定構件與上述外環區218之間的電性和空間隔離物，溝槽210內不會填充任何物體和覆蓋任何襯墊層(liner)，且其側壁會直接與空氣接觸(被空氣填充)，因而可視為空氣溝槽210。Next, trenches 210 are formed in the sensing element layer 208 overlying the germanium wafer 216 on the insulating layer to define the boundary locations of the fixed members of the finally formed microcomputer sensing device. A mask pattern (not shown) is formed on the sensing element layer 208 to define a location for subsequent trench formation. Thereafter, an anisotropic etching process is performed to remove the sensing device layer 208 that is not covered by the patterned mask to form a trench 210 through the sensing device layer 208 in the sensing device layer 208. An insulating layer 204 can also be used as the etch stop layer of the above etching process. Finally, the above mask pattern is removed. As shown in the cross-sectional view of FIG. 3b, the trench 210 is laterally interposed between the sensing member region 220 and the outer ring region 218 of the sensing element layer 208. In the present embodiment, the trench 210 is used to laterally separate the fixing member of the sensing member region 220 of the final microcomputer inductance measuring device 500a from the outer ring region 218 as a fixing member and the outer ring region 218. Electrical and spatial spacers, the trench 210 will not be filled with any objects and cover any liner, and its sidewalls will be in direct contact with air (filled with air) and thus may be considered as air trenches 210.
然後，進行一接合製程，將絕緣層上覆矽晶片(SOI wafer)216設置於第一絕緣層204的一頂面205上，上述接合係將絕緣層上覆矽晶片216的感測元件層(device layer)208設置於第一絕緣層204的一頂面205上。在本發明一實施例中，接合製程可包括一共熔接合製程、一高壓接合製程或一熱壓接合製程。由於感測元件層208和第一絕緣層204的材質可皆為含矽的材料，因此接合品質可大為提升，且最終之微機電感測裝置500a可大幅降低熱應力引起的感測漂移。如第3b圖所示，感測元件層208包含一外環區218與被上述外環區218圍繞的一感測構件區220。在本發明一實施例中，可於進行上述接合製程製程之後，進行一薄化製程，從基材晶片200的一背面203移除部分基材晶片200，以降低基材晶片200的厚度。Then, a bonding process is performed to place an SOI wafer 216 on the top surface 205 of the first insulating layer 204. The bonding layer covers the sensing layer of the germanium wafer 216 on the insulating layer ( The device layer 208 is disposed on a top surface 205 of the first insulating layer 204. In an embodiment of the invention, the bonding process may include a eutectic bonding process, a high pressure bonding process, or a thermocompression bonding process. Since the materials of the sensing device layer 208 and the first insulating layer 204 can both be germanium-containing materials, the bonding quality can be greatly improved, and finally the microcomputer inductance measuring device 500a can greatly reduce the sensing drift caused by thermal stress. As shown in FIG. 3b, the sensing element layer 208 includes an outer ring region 218 and a sensing member region 220 surrounded by the outer ring region 218. In an embodiment of the present invention, after the bonding process is performed, a thinning process is performed to remove a portion of the substrate wafer 200 from a back surface 203 of the substrate wafer 200 to reduce the thickness of the substrate wafer 200.
然後，請參考第4a、4b圖，可進行一蝕刻製程，移除絕緣層上覆矽晶片216之全部的基板層214。之後，可於第二絕緣層212上形成一遮罩圖案(圖未顯示)，以定義出後續固定構件和可動構件的形成位置。之後，進行一非等向蝕刻製程，移除未被圖案化遮罩覆蓋的第二絕緣層212，以形成一第二絕緣層圖案212a，並使位於感測構件區220內的感測元件層208從第二絕緣層圖案212a暴露出來，並使第二絕緣層圖案212a架橋(意即橫跨於外環區218和部分感測構件區220)於感測元件層208的外環區218和部分感測構件區220上。如第4b圖所示，第二絕緣層圖案212a從感測元件層208的外環區218橫向延伸覆蓋空氣溝槽210和部分感測構件區220。最後，移除上述遮罩圖案。Then, referring to FIGS. 4a and 4b, an etching process can be performed to remove all of the substrate layer 214 on the insulating layer overlying the germanium wafer 216. Thereafter, a mask pattern (not shown) may be formed on the second insulating layer 212 to define a formation position of the subsequent fixing member and the movable member. Thereafter, an anisotropic etching process is performed to remove the second insulating layer 212 that is not covered by the patterned mask to form a second insulating layer pattern 212a and the sensing element layer located in the sensing member region 220. 208 is exposed from the second insulating layer pattern 212a and bridges the second insulating layer pattern 212a (that is, across the outer ring region 218 and a portion of the sensing member region 220) to the outer ring region 218 of the sensing element layer 208 and Part of the sensing member region 220. As shown in FIG. 4b, the second insulating layer pattern 212a extends laterally from the outer ring region 218 of the sensing element layer 208 to cover the air trench 210 and a portion of the sensing member region 220. Finally, the above mask pattern is removed.
然後，請參考第5a、5b圖，進行一電鍍和圖案化製程，於第二絕緣層圖案212a的一頂面213上形成導線圖案224，並延伸連接至暴露出來的感測元件層208。在本發明一實施例中，導線圖案224的材質可包括鋁、銅、金、銀、鎢或上述組合。上述電鍍和圖案化製程更可形成連接至導線圖案224末端的導電墊226，導電墊226用以做為最終微機電感測裝置500a輸入輸出(I/O)的電性連接，而導電墊226的材質可與導線圖案224相同。Then, referring to FIGS. 5a and 5b, a plating and patterning process is performed to form a wire pattern 224 on a top surface 213 of the second insulating layer pattern 212a and extendly connected to the exposed sensing element layer 208. In an embodiment of the invention, the material of the wire pattern 224 may include aluminum, copper, gold, silver, tungsten or a combination thereof. The electroplating and patterning process further forms a conductive pad 226 connected to the end of the wire pattern 224. The conductive pad 226 is used as an electrical connection between the input and output (I/O) of the final microcomputer inductance measuring device 500a, and the conductive pad 226 The material can be the same as the wire pattern 224.
然後，請參考第6a、6b圖，可進行一圖案化製程，移除從第二絕緣層圖案212a暴露出來的部分感測元件層208，以於感測構件區220中形成固定構件232與可動構件234。如第6a圖所示，固定構件232可藉由一彈性元件與可動構件234連接，且另一固定構件230與可動構件234之間具有一空隙236。如第6b圖所示，在基材晶片200具有凹陷區202的一實施例中，上述可動構件234係位於凹陷區202內，並與第一絕緣層204隔開。而外環區218和固定構件232分別橫向鄰接空氣溝槽210的相對側壁，並利用接合製程固著於具有類似材質的第一絕緣層204上，可大為降低熱應力的影響，因而可提升元件可靠度。因此，可藉由空氣溝槽210和空隙236使外環區218與感測構件區的可動構件234和固定構件232橫向地完全隔開而彼此不接觸，而外環區218、可動構件234和固定構件232的底面238可藉由第一絕緣層204與其下的基材晶片200隔離。另外，第二絕緣層212a覆蓋部分固定構件232的頂面239，且設置於第二絕緣層212a上的導線圖案224係延伸覆蓋部分固定構件232，導線圖案224僅電性連接至固定構件232。經過上述製程，係完成本發明實施例之微機電感測裝置500a。Then, referring to FIGS. 6a and 6b, a patterning process may be performed to remove a portion of the sensing element layer 208 exposed from the second insulating layer pattern 212a to form the fixing member 232 and the movable member in the sensing member region 220. Member 234. As shown in FIG. 6a, the fixing member 232 can be coupled to the movable member 234 by an elastic member, and a gap 236 is formed between the other fixing member 230 and the movable member 234. As shown in FIG. 6b, in an embodiment in which the substrate wafer 200 has the recessed regions 202, the movable member 234 is located within the recessed region 202 and spaced apart from the first insulating layer 204. The outer ring region 218 and the fixing member 232 respectively adjoin the opposite sidewalls of the air groove 210, and are fixed on the first insulating layer 204 having a similar material by a bonding process, which can greatly reduce the influence of thermal stress, thereby improving Component reliability. Therefore, the outer ring region 218 and the movable member 234 of the sensing member region and the fixing member 232 can be completely separated laterally by the air groove 210 and the gap 236 without contacting each other, and the outer ring region 218, the movable member 234, and The bottom surface 238 of the fixing member 232 can be isolated from the underlying substrate wafer 200 by the first insulating layer 204. In addition, the second insulating layer 212a covers the top surface 239 of the partial fixing member 232, and the wire pattern 224 disposed on the second insulating layer 212a extends to cover the partial fixing member 232, and the wire pattern 224 is only electrically connected to the fixing member 232. Through the above process, the microcomputer inductance measuring device 500a of the embodiment of the present invention is completed.
如第7圖所示，接著，在本發明另一實施例中，可再進行另一接合製程，將一蓋層240設置於感測構件區220的上方，並藉由一例如玻璃熔塊(glass frit)之接合圖樣層242接合至感測元件層208的外環區218的頂面243，其中蓋層240與感測構件區220隔開。接合圖樣層242具有一厚度且其上視圖為一封閉圖案，因而與蓋層240接合後可使空隙236形成腔體，以使可動構件234在其中運動而不會碰到蓋層240。在本發明一實施例中，蓋層240可為例如矽晶片之一半導體晶片，其用以保護感測構件區220的固定構件232與可動構件234。As shown in FIG. 7, then, in another embodiment of the present invention, another bonding process may be performed to place a cap layer 240 over the sensing member region 220 and by, for example, a glass frit ( The bond pattern layer 242 of glass frit is bonded to the top surface 243 of the outer ring region 218 of the sensing element layer 208, wherein the cap layer 240 is spaced apart from the sensing member region 220. The bonding pattern layer 242 has a thickness and its top view is a closed pattern so that the gap 236 can be formed into a cavity after engagement with the cover layer 240 to move the movable member 234 therein without touching the cover layer 240. In an embodiment of the invention, the cap layer 240 can be a semiconductor wafer such as a germanium wafer for protecting the fixed member 232 and the movable member 234 of the sensing member region 220.
第8圖為本發明又另一實施例之微機電感測裝置500b的剖面圖。在本發明另一實施例中，可使用一接合層206將感測元件層(device layer)208接合至第一絕緣層204的頂面205。在本發明一實施例中，接合層206可包括一絕緣層或一金屬層。Figure 8 is a cross-sectional view showing a microcomputer inductance measuring device 500b according to still another embodiment of the present invention. In another embodiment of the invention, a bonding layer 206 can be used to bond the sensing device layer 208 to the top surface 205 of the first insulating layer 204. In an embodiment of the invention, the bonding layer 206 may include an insulating layer or a metal layer.
本發明實施例係提供一種微機電感測元件微機電感測裝置及其製造方法，其具有以下優點。以矽基材晶片來取代習知微機電感測裝置使用之玻璃基材，因而微機電感測裝置之總厚度，將會因為不再受限玻璃研磨加工基礎產業之不足而可大幅加工薄化。另外，由於將原先設計於玻璃基材上之固定構件導線，改移至固定構件的一頂面，如此一來，可節省下習知技術之用以保護玻璃基材上方薄導線，因後續晶圓接合高溫保護用氧化層加載用製程圖樣光罩，與固定構件元端面金屬接觸物理崁合所需之另一製程圖樣光罩等共兩個製程光罩，進而達到簡化元件製程、降低成本、提高元件特性穩定度和元件可靠性之目的。Embodiments of the present invention provide a microcomputer inductance measuring device for a microcomputer inductance measuring component and a manufacturing method thereof, which have the following advantages. The enamel substrate wafer is used to replace the glass substrate used in the conventional microcomputer inductance measuring device. Therefore, the total thickness of the microcomputer inductance measuring device can be greatly processed and thinned because the shortage of the glass polishing processing basic industry is no longer limited. . In addition, since the fixing member wire originally designed on the glass substrate is changed to a top surface of the fixing member, the conventional technique can be saved to protect the thin wire above the glass substrate, because the subsequent crystal The round-bonding high-temperature protection oxide layer is used to process the process pattern mask, and the other process pattern mask required for physical contact with the metal surface of the fixed component element is combined to form a mask, thereby simplifying the component process and reducing the cost. Improve the stability of component characteristics and component reliability.
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can be modified and retouched without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
200．．．基材晶片200. . . Substrate wafer
201、205、209、213、239、243．．．頂面201, 205, 209, 213, 239, 243. . . Top surface
203．．．背面203. . . back
204．．．第一絕緣層204. . . First insulating layer
202．．．凹陷區202. . . Sag area
206．．．接合層206. . . Bonding layer
208．．．感測元件層208. . . Sensing element layer
210．．．空氣溝槽210. . . Air trench
212．．．第二絕緣層212. . . Second insulating layer
212a．．．第二絕緣層圖案212a. . . Second insulating layer pattern
214．．．基板層214. . . Substrate layer
216．．．絕緣層上覆矽晶片216. . . Overlying silicon on the insulating layer
218．．．外環區218. . . Outer ring area
220．．．感測構件區220. . . Sensing component area
224．．．導線圖案224. . . Wire pattern
226．．．導電墊226. . . Conductive pad
230、232．．．固定構件230, 232. . . Fixed member
234．．．可動構件234. . . Movable member
236．．．空隙236. . . Void
238．．．底面238. . . Bottom
240．．．蓋層240. . . Cover
242．．．接合圖樣層242. . . Bonding pattern layer
500a、500b．．．微機電感測裝置500a, 500b. . . Microcomputer inductance measuring device
第1a至6b圖為本發明一實施例之微機電感測裝置的製程上視圖。1a to 6b are top views of processes of a microcomputer inductance measuring device according to an embodiment of the present invention.
第1b至4b圖為沿第1a至4a圖之A-A’切線剖面圖。Figures 1b to 4b are cross-sectional views taken along line A-A' of Figures 1a through 4a.
第5b、6b圖沿第5a、6a圖之C-C’切線剖面圖。Figures 5b and 6b are cross-sectional views taken along line C-C' of Figs. 5a and 6a.
第7圖為本發明另一實施例之微機電感測裝置的剖面圖。Figure 7 is a cross-sectional view showing a microcomputer inductance measuring device according to another embodiment of the present invention.
第8圖為本發明又另一實施例之微機電感測裝置的剖面圖。Figure 8 is a cross-sectional view showing a microcomputer inductance measuring device according to still another embodiment of the present invention.
200．．．基材晶片200. . . Substrate wafer
202．．．凹陷區202. . . Sag area
204．．．第一絕緣層204. . . First insulating layer
208．．．感測元件層208. . . Sensing element layer
210．．．空氣溝槽210. . . Air trench
212a．．．第二絕緣層圖案212a. . . Second insulating layer pattern
218．．．外環區218. . . Outer ring area
220．．．感測構件區220. . . Sensing component area
224．．．導線圖案224. . . Wire pattern
232．．．固定構件232. . . Fixed member
234．．．可動構件234. . . Movable member
236．．．空隙236. . . Void
238．．．底面238. . . Bottom
239、243．．．頂面239, 243. . . Top surface
240．．．蓋層240. . . Cover
242．．．接合圖樣層242. . . Bonding pattern layer
500a．．．微機電感測裝置500a. . . Microcomputer inductance measuring device
Claims (15)
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| CN104249991B (en) * | 2013-06-26 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | MEMS and preparation method thereof |
| US20150262902A1 (en) | 2014-03-12 | 2015-09-17 | Invensas Corporation | Integrated circuits protected by substrates with cavities, and methods of manufacture |
| US10002844B1 (en) | 2016-12-21 | 2018-06-19 | Invensas Bonding Technologies, Inc. | Bonded structures |
| US10508030B2 (en) * | 2017-03-21 | 2019-12-17 | Invensas Bonding Technologies, Inc. | Seal for microelectronic assembly |
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| US11004757B2 (en) | 2018-05-14 | 2021-05-11 | Invensas Bonding Technologies, Inc. | Bonded structures |
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| US20040188136A1 (en) * | 2003-03-26 | 2004-09-30 | Shinko Electric Industries Co., Ltd. | Method of production of multilayer circuit board with built-in semiconductor chip |
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