TWI426564B - Structure and fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications - Google Patents

Description

Construction and fabrication of a semiconductor architecture with field effect transistors that is particularly suitable for analog applications

This invention relates to semiconductor technology, and more particularly to an insulated-gate type field effect transistor (FET). Unless otherwise indicated, all of the insulated gate field effect transistors (IGFETs) described below are surface channel enhancement mode IGFETs.

An IGFET is a semiconductor device in which a gate dielectric layer electrically insulates a gate electrode from a channel region extending between a source region and a drain region. The channel region of an enhancement mode IGFET is often referred to as a portion of a body region of a substrate or substrate region that forms a respective pn junction with a source and a drain. In an enhanced mode IGFET, the channel region consists of all semiconductor material between the source and the drain. During IGFET operation, a charge carrier is transmitted along the upper semiconductor surface through one of the channels of the channel region to move from the source to the drain. The threshold voltage is the gate-to-source voltage value, and the IGFET is switched from its on and off states for the known definition of the on and off states. The channel length is the distance between the source and the drain along the upper semiconductor surface.

IGFETs are used in integrated circuits (ICs) to perform a variety of digital and analog functions. As IC operational capabilities have increased over the years, IGFETs have gradually become smaller, resulting in a gradual reduction in the minimum channel length. An IGFET that operates in a manner specified by the classical model of an IGFET is often described as a "Long channel" device. An IGFET is described as a "short channel" device when the channel length is reduced to the extent that the IGFET behavior is significantly off the classical IGFET model. Although both short- and long-channel IGFETs are used in ICs, the vast majority of IC layouts utilizing the digital capabilities of very large integrated applications have the smallest channel lengths that are reliably manufactured by available lithographic techniques.

A depleted region extends along the junction between the source and body regions. Another depleted area extends along the junction between the bungee and the body region. A high electric field is present in each of the depleted areas. Under certain conditions, particularly when the channel length is small, the depleted region can extend laterally to the source depletion region and merge with the underlying semiconductor surface. This phenomenon is called (subject) punchthrough. When penetration occurs, the operation of the IGFET will not be controlled by its gate electrode. Penetration must be avoided.

As IGFET sizes have decreased, various techniques have been utilized to improve the performance of IGFETs, including those operating in short channel states. One performance improvement technique involves providing an IGFET with a two-part drain for reducing heat carrier implantation. The IGFET also typically provides a two-part source of similar architecture.

Figure 1 illustrates such a conventional long n-channel IGFET 20 as described in U.S. Patent No. 6,548,842 B1 (Bulucea et al.). The upper surface of the IGFET 20 is provided with a recessed electrically insulating field insulating region 22 which laterally surrounds the active semiconductor island portion 24, which has an n-type source/drain (S/D, source/ Drain) zones 26 and 28. Each S/D region 26 or 26 is comprised of a very heavily doped main portion 26M or 28M with a lightly doped (but still heavily doped) laterally extending portion 26E or 28E.

The S/D regions 26 and 28 are separated from each other by a channel region 30 of a p-type body material 32. The body material 32 is composed of a lightly doped lower portion 34, a heavily doped intermediate well 36, and an upper portion 38. . While the majority of the upper body material portion 38 is moderately doped, the upper portion 38 includes heavily doped halo pocket portions 40 and 42 that are implanted along the S/D regions 26 and 28, respectively. IGFET 20 further includes a gate dielectric layer 44, an overlying gate electrode 46, electrically insulating gate sidewall spacers 48 and 50, and metal telluride layers 52, 54 and 56.

S/D zones 26 and 28 are primarily mirror images of each other. The ring pocket portions 40 and 42 are also primarily mirror images of each other such that the channel region 30 is longitudinally symmetrically graded with respect to channel dopant concentration. As a result, the IGFET 20 is a symmetrical device. During IGFET operation, S/D region 26 or 28 can serve as a source and another S/D region 28 or 26 can serve as a drain. This is particularly useful in digital situations where the S/D regions 26 and 28 are used as source and drain, respectively, during certain time periods, and as drains and sources, respectively, during other times.

Figure 2 illustrates the net dopant concentration N _{N for} how the IGFET 20 varies as a function of the longitudinal distance x. Since IGFET 20 is a symmetrical device, Figure 2 presents a quantometric profile starting from only half of the center of the channel. The curve segments 26M*, 26E*, 28M*, 28E*, 30*, 40*, and 42* of FIG. 2 represent the net dopant concentration of the regions 26M, 26E, 28M, 28E, 30, 40, and 42, respectively. . The dotted curve segment 40" or 42" refers to the total concentration of p-type dopants forming the ring pocket portion 40 or 42 including introduction to the S/D region 26 during the process of forming the pocket portion 40 or 42 or P-type dopant at position 28.

In addition to helping to alleviate the undesirable voltage of the short channel length In addition to roll-off, the presence of the ring pocket portions 40 and 42 of the IGFET 20 increases the p-type dopant concentration in the channel region 30 along the respective S/D regions 26 or 28, particularly along Each lateral extension 26E or 28E is present. Since the thickness of the portion of the channel region of the depletion region extending along the junction of the source-acting S/D regions 26 or 28 is reduced, the beginning of the penetration is thus alleviated.

The body material 32 provides additional doping characteristics to thereby reduce penetration. Information based on U.S. Patent No. 6,548,842 B1 proposed roughly FIG 3a depicts the p-type and n-type dopant N _T is the absolute concentration along with how to extend through main S / D portion 26M or a vertical line of 28M The function of the depth y varies as a result of the additional doping characteristics. The curved section 26M" or 28M" of Figure 3a represents the total concentration of the n-type dopant defining the primary S/D portion 26M or 28M. The curved segments 34", 36", 38", 40", and 42" collectively represent the total concentration of p-type dopants that define the individual regions 34, 36, 38, 40, and 42.

The additional doping characteristics are achieved by ion implantation of a p-type anti-punch through dopant in the p-type upper body material portion 38, and the p-type APT dopant is below the upper semiconductor surface. A maximum concentration of more than 0.1 micron and a depth of no more than 0.4 micron below the upper surface is achieved. For the case represented by Figure 3a, wherein the major S/D portions 26M and 28M extend about 0.2 microns below the upper surface, the p-type APT dopant reaches a maximum concentration at a depth of about 0.2 microns. By providing the p-type APT dopant in this manner, the thickness of the portion of the channel region of the depletion region extending along the pn junction of the source-acting S/D region 26 or 28 is further reduced, thereby further reducing penetration. .

The well region 36 is defined by ion implantation of a p-type well dopant in the IGFET 20, and the p-type well dopant is maximized at a depth below the maximum concentration of the p-type APT dopant. concentration. Although the maximum concentration of the p-type well dopant is slightly greater than the maximum concentration of the p-type APT dopant, the vertical amount curve of the total p-type dopant is from the position of the maximum well dopant concentration up to the main S The /D portion 26M or 28M is quite flat. In particular, the concentration N _{T of the} total p-type dopant is reduced from the position of the maximum well dopant concentration up to the main S/D portion 26M or 28M to less than 5%.

U.S. Patent No. 6,548,842 B1 discloses: by implanting an additional p-type dopant (which reaches a maximum concentration at a depth between the APT and the depth of the maximum concentration of the well dopant), along The p-type doping dose curve of the above-mentioned vertical line passing through the main S/D portion 26M or 28M can be further planarized. This situation is illustrated in Figure 3b for this variation of IGFET 20, where curve segment 58" refers to the change caused by another p-type dopant. Figure 3b, another p-type dopant the maximum concentration system. Therefore, the concentration of N _T the total p-type dopant in the same position from the maximum dopant concentration of the well to move portion 26M or 28M decreases between APT and the maximum concentration of the well dopant It is quite less than 5%.

A symmetrical IGFET configuration is not required where current flow during device operation flows through an IGFET in only one direction (especially for many analog applications). As further discussed in U.S. Patent No. 6,548,842 B1, the loop pocket portion can be removed from the drain side. IGFET 20 thus becomes a long n-channel IGFET 60, as shown in Figure 4a. IGFET 60 is an asymmetric device because channel region 30 is asymmetrically longitudinally dopant gradual. The S/D regions 26 and 28 of the IGFET 60 serve as source and drain, respectively. Figure 4b illustrates an asymmetric short n-channel IGFET 70 corresponding to long channel IGFET 60. In the IGFET 70, the ring pocket portion 40 on the source side is closely adjacent to the drain pad 28. The net dopant concentration N _N as a function of the longitudinal distance x along the upper semiconductor surface of IGFETs 60 and 70, respectively, is shown in Figures 5a and 5b.

Asymmetric IGFETs 60 and 70 receive the same APT and well dopants as symmetric IGFET 20. Along the vertical line extending through the source 26 and the drain 28, the IGFETs 60 and 70 thus have the dopant profile shown in Figure 3a, but due to the absence of the ring pocket portion 42, the dashed curved segment 62" represents the transmission. The vertical dopant distribution of the drain 28. When the IGFET configuration provides an additional well implant to further planarize the vertical doping dose profile, Figure 3b presents the resulting vertical dopant profile, again in accordance with A curve segment 62" representing the dopant distribution through the drain 28 is represented.

U.S. Patent Nos. 6,078,082 and 6,127,700 (both to Bulucea) describe IGFETs having asymmetric channel regions, but which have different vertical dopant characteristics than those employed by the inventive IGFETs of U.S. Patent No. 6,548,842 B1. IGFETs with asymmetric channel regions have also been examined in other prior art documents such as: (a) Buti et al. "Asymmetric ring source GOLD drain (HS-GOLD) depth half for reliability and performance Micron n-MOSFET design" ( IEDM Tech.Dig., December 3-6, 1989, 26.2.1 to 26.2.4); (b) Chai et al. "Features for RF wireless applications are gradient channels CMOS (GCMOS) and Quasi-Self-Aligned (QSA) NPN Cost-effective 0.25 μm L _eff BiCMOS Technology” ( Procs. 2000 Bipolar/BiCMOS Circs. and Tech. Meeting, September 24-26, 2000, 110-113 Page); (c) Chen et al. “Channel Engineering for High-Speed Subsequent 1.0V Power Supply Deep Sub-micron CMOS” ( 1999 Symp.VLSI Tech., Dig.Tech.Paps., June 14-16, 1999 (69, p. 70); (d) Deshpande et al., "Channel Engineering for Analog Devices Design for Deep Sub-micron CMOS Technology for On-Chip System Applications" ( IEEE Trans.Elec. Devs., September 2002, 1558 to 1565); (e) Hiroki et al. "High-performance 0.1 micron MOSFET with asymmetric channel profile" ( IEDM Tech.Dig., December 1995, 17.7.1 to 17.7 .4 pages); (f) Lamey et al., "Improving the Manufacturing Power of RF Gradient Channel CMOS Processes for Wireless Applications" ( SPIE Conf. Microelec. Dev. Tech. II., September 1998, 147-155 (g) Ma et al., "Fade-Channel MOSFETs (GCMOSFETs) for High Performance, Low-Voltage DSP Applications" ( IEEE Trans.VLSI Systs. Dig., December 1997, pp. 352-358 ); h) Matsuki et al., "Land-Doped Channel (LDC) Construction for Sub-Quarter Micron MOSFETs" ( 1991 Symp. VLSI Tech., Dig. Tech. Paps., May 28-30, 1991) , 113 and 114); and (i) Su et al. "High-performance micron MOSFETs for hybrid analog/digital applications" ( IEDM Tech.Dig., December 1991, pp. 367-370) .

The term "mixed signal" refers to an IC containing digital and analog circuit blocks. Digital circuit systems typically use the most active n-channel and p-channel IGFETs to achieve the maximum potential digital speed for a given current leakage specification. Analog circuits utilize IGFETs and/or bipolar transistors in accordance with the performance requirements of digital IGFETs. The requirements for analog IGFETs typically include: High linear voltage gain, good frequency response of large signals at high frequencies, large signal matching, good parameter matching, low input noise, proper control of electrical parameters for active and passive components, and reduced parasitics, especially It is a reduced parasitic capacitance. While it would be economically attractive to utilize the same transistor for analog and digital block systems, this would typically result in weaker analog performance. Many of the requirements imposed on the performance of analog IGFETs conflict with the results of the other digit.

More specifically, the electrical parameters of the analog IGFET are in stricter specifications than the IGFET of the digital block. To operate as an analog of an IGFET, the output resistance of the IGFET must be maximized to maximize its intrinsic gain. It is also important that the output resistance is set to the high frequency performance of an analog IGFET. Conversely, the output resistance is significantly less important in digital circuits. The reduced value of the output resistance of the digital circuit allows for the exchange of higher current drive and therefore higher bit switching speed as long as the digital circuit can distinguish its logic state, for example: logic "0" and logic "1".

The shape of the electrical signal passing through the analog transistor is critical to circuit performance and must generally be maintained as harmonic distortion and noise as possible. Harmonic distortion is mainly caused by the nonlinearity of the transistor gain and the transistor capacitance. Therefore, the linearity requirements of analog crystals are very high. The parasitic capacitance at the pn junction has a voltage nonlinearity that must be mitigated by the nature of the analog block. Conversely, signal linearity is often a secondary importance of digital circuits.

The analog speed performance of the small signal applied to the IGFET of the analog amplifier is determined by the frequency limit of the small signal and involves the gain of the small signal along the pin. The parasitic capacitance of the pn junction of the source and the drain. The analog speed performance of the large signal of the analog amplifier IGFET is similarly determined by the frequency limit of the large signal and involves the nonlinearity of the IGFET characteristics.

The digital gate speed is defined by the switching time of the large signal of the transistor/load combination, and thus involves the drive current and output capacitance. Therefore, the analog speed performance is determined by the difference in digital speed performance. The analogy and digital speed optimization can be different, resulting in different transistor parameter requirements.

The digital circuit block advantageously uses the smallest IGFET that can be fabricated. Since the resulting size range is essentially large, parameter matching in digital circuits is often quite crude. Conversely, good parameter matching usually requires an analog circuit to achieve the necessary performance. This typically requires that the analog transistor be made larger in size than the digital IGFET, making the analog IGFET as short as possible, with as low a source-to-drain propagation delay as possible.

In view of the foregoing considerations, it is desirable to have a semiconductor architecture that provides good analog properties of the IGFET. The analog IGFET should have high intrinsic gain, high output resistance, high signal speed to reduce parasitic capacitance, and especially reduce parasitic capacitance along the source and drain junctions. It is also desirable that this architecture is capable of providing high performance digital IGFETs.

The present invention proposes such an architecture. In accordance with the present invention, a semiconductor construction system includes a principal IGFET having a relatively low parasitic capacitance along at least one of the pn junctions forming the source/drain boundary. Although available for digital applications, the main IGFETs are especially suitable for analog applications and Achieve superior analog performance.

The semiconductor construction of the present invention can include an additional IGFET that is similar to the primary IGFET but is of opposite polarity. The two IGFETs thus form a complementary IGFET architecture that is particularly useful for one of the analog circuits. The semiconductor construction may also contain a further IGFET that is particularly suitable for use in a digital circuit, or two other IGFETs of opposite polarity. The overall architecture can then be applied to ICs that mix signals.

Returning to the main IGFET, which includes a channel region, a pair of source/drain (S/D) regions, a gate dielectric layer overlying the channel region, and a gate dielectric overlying the channel region A gate electrode above the electrical layer. The primary IGFET is fabricated from a semiconductor body having a semiconductor dopant doped with a first conductivity type as one of the bulk materials of the first conductivity type. The channel region is part of the bulk material and is therefore of the first conductivity type. The S/D region is located along the upper surface of the semiconductor body and is laterally separated by the channel region. Each S/D zone is opposite to one of the first conductivity types of the second conductivity type, thereby forming a pn junction having one of the bulk materials. The body material extends laterally below the S/D regions.

Importantly, the dopant of the first conductivity type of the bulk material has a concentration that decreases to a maximum of 10% from a position of the lower layer body material up to a designator of the S/D regions. Preferably, the reduction is up to 20%, and the position of the underlying body material is no more than 10 times deeper than the designated S/D region below the upper semiconductor surface, preferably no more than 5 times deep. Alternatively, the concentration of the dopant of the first conductivity type of the bulk material is increased by at least 10 times from the designated S/D region downwardly to a position of the body material, preferably Preferably, the body material is at least 20 times deeper than the S/D region below the upper semiconductor surface, preferably no more than 5 times deep. The position of the body material of the subsurface is usually located mostly below all of the channel and the S/D zone. By providing this "hypoabrupt" dopant distributed to the bulk material, the parasitic capacitance along the pn junction between the bulk material and the designated S/D region is relatively low. The main IGFET system can thus achieve high analog performance.

The primary IGFET system is typically an asymmetric device in that the channel region is asymmetrically longitudinally dopant gradual. Specifically, the concentration of the dopant in the first conductivity type of the bulk material is higher in the channel region than in the channel region along the upper surface that meets the remainder of the S/D regions. The semiconductor surface meets the lower portion of the designated S/D region. During IGFET operation, the designated S/D region typically constitutes the drain and the remaining S/D regions form the source. The concentration of the dopant of the first conductivity type of the bulk material is generally higher than where the source region meets the source along the upper surface and the drain region along the upper surface of the channel region It is at least 10% lower, preferably at least 20% lower. Alternatively, the concentration of the dopant in the first conductivity type of the bulk material is higher than the concentration of the dopant in the channel region along the upper surface, where the source region meets the source region along the upper surface. It is usually at least 10 times higher, preferably at least 20 times higher.

The high dopant concentration along the source side of the channel region shields the source from the relatively high electric field at the drain because the electric field line from the drain terminates in the channel region located near the source and Providing ionized dopant atoms at a higher channel region dopant concentration near the source, rather than terminating along The ionized dopant atoms of the source depletion region and the absolute value of the potential barrier against most of the charge carriers from the source are disadvantageously reduced. This reduces penetration. The combination of the sub-steep vertical doping dose curve below the designated S/D region (ie, here a drain) and the increased channel region dopant concentration at the source side can thus achieve a high Analog performance without penetration failure.

The sub-steep vertical doping dose curve below the designated S/D zone can be implemented in a variety of ways. In one embodiment, the concentration of the dopant of the first conductivity type of the bulk material is at a local maximum by placing the aforementioned subsurface bulk material location below the designated S/D region. The concentration of the dopant of the first conductivity type of the bulk material is typically gradually reduced from the position of the body material moving up to the designated S/D region.

In fabricating the foregoing implementation of its primary IGFET in accordance with the present invention, a first conductivity type semiconductor well dopant is typically introduced into the semiconductor body by ion implantation to define one of the first conductivity types. The ion implantation is performed to perform a well doping step such that the well dopant reaches its maximum concentration at the location of the aforementioned subsurface body material. The gate electrode is disposed over the semiconductor material intended to be the channel region and is separated from the semiconductor material by a gate dielectric material. A second conductivity type semiconductor source/drain dopant is introduced to the semiconductor body to form an S/D region.

Additional processing is performed to complete the fabrication of the aforementioned implementation of the primary IGFET. The well doping step and the additional processing are performed under conditions that cause the vertical doping dose curve below the designated S/D region to be sub-steep. In particular, the concentration of the well dopant is reduced upwardly from the aforementioned subsurface body material location to the designated S/D zone to a maximum of 10%.

The body material is of the first conductivity type, at least at the end of the IGFET fabrication. The semiconductor material that constitutes the bulk material and the S/D region at the end of the IGFET fabrication may be initially a second conductivity type. If so, the well doping step converts one of the lower portions of the material to the first conductivity pattern. In one form of the process, the compensation doping is performed by the first conductivity type semiconductor dopant to convert the remainder of the material to the first conductivity pattern. In another form of the process, part of the well dopant is diffused upwardly to the upper portion of the material during additional processing such that it is not significantly exposed to the first or second conductivity after the well doping step The other portions of the other doped materials of the type are all converted to the first conductivity type.

In another implementation of the primary FET, the concentration of the dopant of the first conductivity type of the bulk material moves from the aforementioned subsurface body material position upwardly to the designated S/D region and substantially undergoes a one-step reduction. For example, the body material can comprise: a surface layer (buried) body material portion; and a surface directly overlying the upper layer abutting the body material portion extending to the upper semiconductor surface and containing the S/D region. The subsurface body material portion is disposed below the S/D region and, where it is closest to the S/D regions, is no more than 10 times below the upper semiconductor surface compared to the S/D regions Deep, preferably no more than 5 times deep. For example, the subsurface body material portion can be mostly uniformly doped. The concentration of the dopant of the first conductivity type of the bulk material is such that it substantially undergoes a one-step reduction (typically at least one 10%) from the portion of the subsurface body material that spans the surface adjacent the body material portion, and Moving further upwardly through the surface adjacent body material portion to a designated S/D region while maintaining a lower than at least one factor compared to the subsurface body material portion 10.

Briefly stated, the present invention provides a semiconductor architecture having an IGFET that is particularly suitable for use in an analog circuit, or a pair of IGFETs of opposite polarity. This architecture may include another IGFET that is particularly suitable for digital circuitry, or another pair of IGFETs of opposite polarity. The resulting architecture handles mixed-signal applications very well. The invention thus provides a substantial advance over the prior art.

Reference marks and other regulations

The reference symbols used in the following figures have the following meanings, wherein the adjective "lineal" means the width per unit IGFET, and the adjective "areal" means the area per unit lateral: A _I ≡ current gain

C _da ≡ 空 区域 area capacitor

C _d0a ≡ _{零 零 零 零 反向 反向 反向 反向 反向 反向}

C _DB bungee to body capacitance

C _{DBw 汲} line _{bungee to} body capacitance

C _GB ≡ gate to body capacitance

CG _D ≡ gate to drain capacitor

C _GIa闸 gate dielectric capacitor

C _GS ≡ gate to source capacitance

C _L ≡ load capacitor

C _SB ≡ source to body capacitance

C _{SBw 源} line source to body capacitance

F≡frequency

f _T ≡ cutoff frequency

f _{Tpeak 峰值} peak of cutoff frequency

The intrinsic mutual conductance of g _m ≡IGFET

g _mw线 IGFET line mutual conductance

G _mb互 body electrode mutual conductance

g _{meff ≡} IGFET in the presence of effective mutual conductance of the power supply resistor

g _msatw ≡IGFET cross-conducting on saturated line

H _A ≡ amplifier transfer function

I _D ≡汲 current

I _Dw汲 line 汲 current

I _D0w Leakage value of the line drain current from zero gate to source voltage

i _i small signal input current

i _o ≡ small signal output current

Relative dielectric constant of K _S ≡ semiconductor material

K≡ wave subman constant

L≡ channel length

L _G ≡ gate electrode length

L _GDoverlap ≡ Gate electrode overlaps (or covers) the longitudinal distance of the _bungee

Longitudinal distance of the L _GSoverlap ≡ gate electrode overlap source

N _A ruthenium acceptor dopant concentration

N _{B is} the net dopant concentration of the bulk material

N _B0 , N _B0 '≡ on the lighter doped side of the pn junction, the net dopant concentration value at the near-end fixed concentration portion of the material junction

N _B1 , N _B1 '≡ on the lighter doped side of the pn junction, the net dopant concentration value at the fixed concentration portion of the distal end of the material junction

N _D ≡ donor dopant concentration

N _D0净 The net dopant concentration of the fixed-concentration material on the heavier doping side of the pn junction

N _I ≡ individual dopant concentration

N _N net dopant concentration

N _T ≡ absolute dopant concentration

n _i ≡ essential carrier concentration

Q≡Electronic charge

R _D is the series resistance of the drain of the IGFET

R _G串联 series resistance of the gate electrode of IGFET

_On- resistance of the linear region of R ≡ IGFET

R _S is the series resistance of the source of the IGFET

S≡ transform variable

T≡ temperature

t _d ≡ vacant area thickness

t _d0 is the thickness of the depletion region of the zero reverse voltage

t _G1 ≡ gate dielectric thickness

V _BI ≡ built-in voltage

V _BS ≡DC body to source voltage

V _DB ≡DC汲 to body voltage

V _DD ≡ high supply voltage

V _DS ≡DC drain to source voltage

V _GS ≡DC gate to source voltage

V _g ≡ gate voltage amplitude

Input voltage amplitude V _in ≡

V _out ≡ output voltage amplitude

V _R ≡DC reverse voltage

V _Rmax ≡DC reverse voltage maximum

V _SB ≡DC source to body voltage

V _SS degrades supply voltage

V _T ≡ threshold voltage

V _gs ≡ small signal gate to source voltage

V _nsat ≡ electron saturation speed

W≡ channel width

X≡ longitudinal distance

Y≡ depth, vertical distance, or distance from the pn junction

y _d距离 distance from the pn junction to the distal boundary of the depletion region of the bulk material

y _d0 ≡ distance from the pn junction to the value of a fixed concentration portion of body material proximal end surface, the body having a material based on a uniform net dopant concentration changes in steps of

y _dmax距离 distance from the pn junction to the fixed concentration portion of the distal end of the body material junction, the bulk material has a step change in uniform net dopant concentration

y _D The depth value at the bottom of the bungee

y _S深度 depth value at the bottom of the source

y _ST深度 depth value at the distal end of the body material portion above the proximal end of the junction

y _W深度 depth value at the maximum concentration position of the well dopant

ε ₀ ≡ free space (vacuum) dielectric constant

_{n n} ≡ electron mobility

ω corner frequency

ω _in ≡ the angular frequency of the input pole

ω _out ≡ the angular frequency value of the output pole

ω _z ≡ at the angular value of the zero point

ω _p ≡ at the corner of the pole

The long and short channel n-channel IGFETs (here, hereinafter and above) are referred to as long and short n-channel IGFETs, respectively. Similarly, long channel and short channel p-channel IGFETs are referred to herein as long and short p-channel IGFETs, respectively. As used hereinafter, the term "surface adjacency" means to abut (or extend to) an upper semiconductor surface, i.e., an upper surface of a semiconductor body composed of a single crystal (or predominantly single crystal) semiconductor material.

No specific channel length values are used to generalize the short channel and long channel modes of IGFET operation or to distinguish between a short channel IGFET and a long channel IGFET. A short channel IGFET (or one of the short channel modes IGFETs) is only one of the IGFETs that are characterized by significant short channel effects. A long channel IGFET (or one of the long channel modes IGFET) is the opposite of a short channel IGFET. Although the length of the channel of about 0.4 millimeters (mm) is roughly the boundary between the short channel and the short channel mode of the background art of U.S. Patent No. 6,548,842 B1, the boundary of the long channel/short channel can be Occurs at higher or lower channel length values depending on various factors such as: gate dielectric thickness, minimum printable feature size, channel region dopant thickness, and source/drainage - The junction depth of the body.

The vertical bulk material doping dose curve below the bungee is a sub-steep IGFET, which is attributed to the subsurface maximum of the well dopant concentration. value

Figure 6 illustrates an asymmetric long n-channel IGFET 100 constructed in accordance with the present invention to be particularly suitable for high speed analog applications. The long channel IGFET 100 is fabricated from a single crystal germanium (single germanium) semiconductor body in which a pair of heavily heavily doped n-type source/drain regions (S/D) regions 102 and 104 are located along the upper semiconductor. surface. S/D regions 102 and 104 are generally referred to hereinafter as source 102 and drain 104, respectively, because they generally, although not necessarily, act as source and drain, respectively.

The drain 104 is typically doped slightly more heavily than the source 102. The maximum value of the net dopant concentration N _N along the source 102 of the upper semiconductor surface is typically at least 1 x 10 ²⁰ atoms/cm 3 , typically 4 x 10 ²⁰ atoms/cm 3 . The maximum value of the concentration N _N of the drain 104 along the upper surface is usually at least 1 × 10 ²⁰ atoms / cubic centimeter, typically slightly more than 4 × 10 ²⁰ atoms / cubic centimeter, to slightly exceed the source 102 Maximum upper surface N _N concentration. However, as described below with respect to the IGFET of the invention of FIG. 63, the drain 104 is sometimes less doped than the source 102. For example, when the maximum upper surface N _N concentration of the source 102 is at least 1×10 ²⁰ atoms/cm 3 , the maximum value of the concentration N _N of the drain 104 along the upper surface may be 5×10. ¹⁹ atoms / cubic centimeter, and can be reduced to at least as small as 1 × 10 ¹⁹ atoms / cubic centimeter.

The source 102 extends a distance y _S below the upper semiconductor surface. The drain 104 is extended to a depth y _D below the upper semiconductor surface. The source depth y _S is typically from 0.1 to 0.2 microns, typically 0.15 microns. The bungee depth y _D is typically from 0.15 to 0.3 microns, typically 0.2 microns. The bungee depth y _D is typically above the source depth y _S , typically over 0.05 to 0.1 microns.

Source 102 and drain 104 are laterally separated by an asymmetric channel region 106 of p-type body material 108, which forms (a) source-body pn junction 110 for source 102. And (b) one of the drain-body pn junctions 112 for the drain 104. The p-type body material 108 is comprised of a lightly doped lower portion 114, a heavily doped intermediate well 116 and an upper portion 118, typically upper than the source 102 and the drain 104. The underside of the semiconductor surface extends deeper. The upper body material portion 118 is thus typically comprised of all of the channel regions 106. In any event, the p-lower body material portion 114 and the p+ well 116 extend laterally below the source 102 and the drain 104.

The p+ well 116 is defined by a p-type semiconductor well dopant that is approximately vertically distributed in a Gaussian manner to achieve a maximum sub-plane concentration at a depth y _W below the upper semiconductor surface. The "X" in Figure 6 summarizes the location of the maximum sub-plane concentration of the p-type well dopant. The p-type well dopant concentration at depth y _W is typically 1 x 10 ¹⁸ - 1 x 10 ¹⁹ atoms/cm 3 , typically 5 x 10 ¹⁸ atoms/cm 3 . The depth y _W exceeding the maximum well concentration of the source depth y _S and the drain depth y _D is typically 0.5 to 1.0 microns, typically 0.7 microns. Further, the depth y _W is usually not more than 10 times, preferably not more than 5 times, compared to the drain depth y _D . That is, the position of the maximum concentration of the p-type well dopant is not more than 10 times deep, preferably not more than 5 times below the upper surface, compared to the drain 104.

Because the well 116 is located in the same conductivity type (p-type) doped semiconductor material as the well 116, the heavily doped well 116 is somewhat inaccurate above and below the lower boundary. As indicated below, the semiconductor material defining the well 116 has a generally low uniform p-type background dopant concentration. The upper and lower boundaries of the well 116 typically define a location at which the p-type well dopant concentration is equal to the p-type background dopant concentration. The concentration of total p-type dopant along the upper and lower boundaries of well 116 is p except that well 116 extends to any location other than the p-type material that is more heavily doped than well 116. Type background dopant concentration is twice. Under the definition of such boundaries, the upper boundary of the well 116 is typically 0.2 to 0.5 micrometers (μm) below the upper semiconductor surface, typically 0.3 microns. The lower boundary of the well 116 is typically 0.9 to 1.3 microns below the upper surface, typically 1.1 microns.

A depletion region (not shown) extends from the source-body pn junction 110 across the channel region 106 to the drain-body pn junction 112 along the upper semiconductor surface during IGFET operation. The average thickness of the surface depletion region is typically less than 0.1 mm, typically about 0.05 microns. Although the upper and lower boundary portions of the well 116 are somewhat inaccurate, the concentration of the p-type well dopant is typically reduced to an electrical minute level at a depth of less than 0.1 microns below the upper surface. Therefore, the well 116 is substantially below the surface depletion region.

The p-type upper body material portion 118 includes a heavily doped pocket portion 120 that extends up the source 120 to the upper semiconductor surface and terminates at the source A position between 102 and the drain 104. Figure 6 illustrates an example in which the p+ pocket 120 extends deeper below the upper surface than the source 102 and the drain 104. In particular, FIG. 6 depicts an example in which the pocket portion 120 is laterally extending below the source 102 and primarily to the p+ well 116. As discussed below with respect to Figures 18a through 18c, pocket portion 120 can extend to a lesser depth below the upper surface than that shown in Figure 6. The remainder of the p-type upper body material portion 118 (i.e., the portion on the outer side of the pocket portion 120) is referred to as item 124 of FIG. The upper body material remainder 124 is lightly doped and extends along the drain 104. The channel region 106 formed by all of the p-type semiconductor material between the source 102 and the drain 104 is thus formed in part by the p+ pocket portion 120 on the source side and the remaining portion 124 of the p-upper body material on the drain side. .

A gate dielectric layer 126 is located on the upper semiconductor surface and extends above the channel region 106. A gate electrode 128 is a gate dielectric layer 126 over the channel region 106. The gate electrode 128 portion extends over the source 102 and the drain 104. In the example of FIG. 6, the gate electrode 128 is composed of a very heavily doped n-type polysilicon (polyfluorene). The gate electrode 128 can be formed by other conductive materials such as a metal or a doped p-type electrically conductive polymer.

The top surface of source 102, drain 104, and n++ gate electrode 128 is typically provided with a thin layer (not shown) of conductive metal halide to facilitate electrical contact to regions 102, 104, 128. In this case, the gate electrode 128 forms a composite gate electrode with the metal halide layer overlying it. Source 102, drain 104 and channel region 106 are typically laterally surrounded by an electrically insulating field region (also not shown in Figure 6) which is recessed in the upper half. The body surface defines an active semiconductor island portion that includes one of the regions 102, 104, and 106. Examples of metal telluride layers and field insulating regions are associated with Figures 29.1 and 29.2 and are set forth below.

The presence of the p+ pocket 120 along the source 102 causes the channel region 106 to ramp longitudinally with respect to the channel dopant concentration, i.e., in the direction of the channel length. Because the substantial mirror image of the pocket portion 120 on the source side is not located along the drain 104, the channel region 106 is asymmetrical dopant gradient in the longitudinal direction. The p+ well 116 is located below the p-upper body material remainder 124 that extends along the drain 104. This configuration of the p+ well 116 and the p-upper body material remainder 124 causes the vertical doping dose curve of the portion of the body material 108 that is positioned below the drain 102 to be sub-steep. That is, the concentration of the p-type dopant is greatly increased from the drain-body junction 112 downward through the p-upper body material remainder 124 to the p+ well 116, typically at least 10%. The combination of the longitudinal asymmetric dopant grading in the channel region 106 and the sub-steep vertical doping dose curve of the portion of the body material 108 under the drain 104 that passes through the drain 104 provides the IGFET 100 with excellent analogy characteristics and Avoid penetration.

The longitudinal asymmetry dopant gradient in the channel region 106 and the sub-steep vertical doping dose curve of the portion of the body material 108 below the drain 104 are understood by means of Figures 7a to 7c (collectively "Figure 7"), Figures 8a to 8c (collectively "Figure 8"), Figures 9a to 9c (collectively "Figure 9"), and Figures 10a to 10c (collectively "Figure 10") are promoted. Figure 7 is a graph showing the dopant concentration along the upper surface of the upper half as a function of the longitudinal distance x. An exemplary dopant concentration as a function of one of the depths y across one of the vertical lines 130 of the source 102 is presented in FIG. Figure 9 presents an exemplary dopant concentration for It is a function of one of the depths y of the vertical lines 132 and 134 along one of the transmission channel regions 106. The vertical line 132 passes through the pocket portion 120 on the source side. The vertical line 134 passes through a vertical position between the pocket 120 and the drain 104. An exemplary dopant concentration as a function of depth y along a vertical line 136 through one of the drains 104 is presented in FIG.

Figure 7a clearly illustrates the concentration N _I of the individual semiconductor dopants along the upper semiconductor surface, which primarily define regions 102, 104, 120 and 124 and thus establish a longitudinal dopant gradation of channel region 106. Figures 8a, 9a and 10a clearly illustrate the concentration N _I of individual semiconductor dopants along vertical lines 130, 132, 134 and 136 which are vertically defined regions 102, 104, 114, 116, 120 and 124. And thus a sub-steep vertical doping dose curve of the portion of the bulk material 108 that is established below the drain 104. Curves 102' and 104' represent the concentration N _I (surface and vertical) of the n-type dopant used to form source 102 and drain 104, respectively. Curves 114', 116', 120' and 124' represent the concentration N _I (surface and/or vertical) of the p-type dopant utilized to form regions 114, 116, 120 and 124, respectively. Items 110 ^# and 112 ^# refer to where the net dopant concentration N _N drops to zero and thus indicate the location of the pn junctions 110 and 112, respectively.

Along the upper semiconductor surface in a region 102, 104, and the total concentration of N _T based p-type and total n-type dopant 124 shown in Figure 7b. Figures 8b, 9b, and 10b depict the total p-type and total n-type dopant concentration N _T along regions 109, 104, 114, 116, 120, and 124 along vertical lines 130, 132, 134, and 136. Respectively corresponding to regions 114,116,120 and 124 of curve segments 114 ", 116", 120 "and 124" represents the total concentration of the N _T p-type dopant. Item 106 in Figure 7b the "group corresponding to channel zone 106 and represents the curve segments 120 'and 124" of the channel region portion .n-type dopant concentration of the total system by the N _T respectively corresponding to source 102 and drain 104 The curves 102" and 104" are represented. The curves 102" and 104" in Fig. 7b are the same as the curves 102' and 104' of Fig. 7a, respectively. The curves 102" and 104" in Figs. 8b and 10b are respectively the same. Curves 102' and 104' of Figures 8a and 10a.

Figure 7c illustrates the net dopant concentration N _N along the upper semiconductor surface. The net dopant concentration N _N along vertical lines 130, 132, 134 and 136 is presented in Figures 8c, 9c, and 10c. Curve segments 114*, 116*, 120*, and 124* represent the net concentration N _N of the p-type dopants for the individual regions 114, 116, 120, and 124. Item 106* of Figure 7c represents a combination of curved segments 120* and 124* of the channel region, and thus presents a concentration N _N of the net p-type dopant in channel region 106. The concentration N _N of the net n-type dopant at source 102 and drain 104 is represented by curves 102* and 104*, respectively.

In view of the foregoing generalizations with respect to Figures 7 through 10, Figure 7a indicates that the p-type dopant layer of the pocket portion 120 on the source side has two major components along the upper semiconductor surface, namely: The component of the two doping operations. A major component of the p-type dopant along the upper surface of the pocket portion 120 is the p-type background dopant represented by the curved segment 124' of Figure 7a. The p-type background dopant typically exhibits a low (mostly uniform) concentration throughout all of the monoterpene materials including regions 102, 104, 114, 116 and 120. Below the pocket portion 120 and the upper body material remainder 124, the p-type background dopant is represented by a curved segment 114' as indicated by Figures 8a, 9a, and 10a. The concentration of the p-type background dopant is usually from 1 × 10 ¹⁵ to 1 × 10 ¹⁶ atoms/cm 3 , typically 5 × 10 ¹⁵ atoms / cubic centimeter.

The other major component of the p-type dopant of the pocket portion 120 on the source side is a p-type pocket (or channel graded) dopant as indicated by the curved segment 120' of Figure 7a. The p-type pocket dopant is provided at a high upper surface concentration, typically 5 x 10 ¹⁷ to 2 x 10 ¹⁸ atoms per cubic centimeter, typically 1 x 10 ¹⁸ atoms per cubic centimeter, to define the pocket portion 120. The specific value of the surface concentration of the p-type pocket dopant is strictly adjusted, typically within 10% accuracy, to set the threshold voltage of IGFET 100.

The boundary of the pocket portion 120 on the source side is composed of: (a) a segment of the upper semiconductor surface, (b) a pn junction segment formed by the source-body junction 110, and (c) a bulk material 108 one p-type segment. While the p-segment of the boundary of the pocket 120 is somewhat inaccurate, the p-bag section is typically defined where the concentration of the p-type pocket dopant is equal to the concentration of the p-type background dopant. In the range of the pocket portion 120 that is not intervened into the well 116, the p-type dopant concentration along the boundary of the pocket portion 120 is twice the background dopant concentration, including: p-type pocket boundary The segment is where the semiconductor surface is closed.

A p-type pocket dopant is also present at source 102 as indicated by curve 120' of Figure 7a. The concentration N _I of the p-type pocket dopant in the source 102 is substantially fixed along its upper surface. Moving longitudinally from the source 102 to the channel region 106 along the upper semiconductor surface, the concentration N _I of the p-type pocket dopant is in the middle of the region 106 to be a substantially fixed upper surface level, and then to the source 102 A position between the drain 104 and the drain 104 is substantially reduced to zero from this level.

The doping of the total p-type channel region along the upper surface is due to the sum of the p-type background and the pocket dopant along the upper surface of the total p-type dopant system along the upper semiconductor surface along the upper surface. The agent is represented by curve segment 106" of Figure 7b. Variations in curve segment 106" are shown as moving longitudinally from source 102 to drain 104 and across channel region 106, along the upper surface to region 106. The concentration of the total p-type dopant N _T is a substantially fixed high level in the middle of the region 106, and a position between the source 102 and the drain 104 is reduced from the high level to a low p-type. The background level is followed by the remaining distance to the drain 104 to maintain a low background level.

In some embodiments, the concentration N _I of the p-type pocket dopant at the source 102 may be a substantially fixed source level along only a portion of the upper surface of the source 102, and may then follow The semiconductor surface moves longitudinally, decreasing from a location within the upper surface of the source 102 to the source-body junction 110. In this case, across the region 106 to drain 104 toward the longitudinal movement, the p-type pocket dopant concentration of the channel region 106 of N _I across the source - the body immediately begins to decrease after surface 110. Therefore, across the channel region 106 from the source 102 to drain 104 to move longitudinally, along the upper surface of the concentration of the total p-type dopant region 106 similar to N _T across the surface 110 immediately after The decrease begins, rather than being a substantially fixed source level to the middle of zone 106.

Regardless of whether the concentration N _I of the p-type pocket dopant along the upper semiconductor surface of the channel region 106 is a non-zero distance from the source-body junction 110 in the longitudinal direction to the region 106, whether it is at a substantial source level , in the region along the upper surface of the N _T 106 of total concentration of p-type dopant compared to the region 106 at the source junction and the junction of the drain electrode 102 of the electrode 104 in the area 106 is low. In particular, in the area of the total p-type dopant concentration 106 N _T as compared to the source along the upper surface of the electrode - a body surface 110, generally along the drain electrode on the surface of the - body junction 112 Lower, and at least 10%, preferably at least 20% lower, more preferably at least 50% lower, typically lower than 100% or greater.

Figure 7c shows the system: * represented by the curve 106, along the upper semiconductor surface at a concentration of N concentration _N-N-based channel zone of the net p-type dopant 106 is similar to the total area of the p-type dopant 106 The change in _T except that the net dopant concentration N _N of the net p-type dopant along the upper surface of the region 106 is reduced to zero at the pn junctions 110 and 112. The source side of channel region 106 thus has a high net amount of p-type dopant compared to the drain side. The p-type dopant on the high source side of the channel region 106 reduces the thickness of the channel side portion along the depletion region of the source-body junction 110.

In addition, the source 102 is shielded from the high p-type dopant concentration along the source side of the channel region 106 from the relatively high electric field of the drain 104. This occurs because the electric field lines from the drain 104 terminate in the ionized p-type dopant atoms of the pocket 120, rather than terminating the ionized dopant atoms along the depletion region of the source 102, and are detrimental to degradation. A potential barrier against electrons. The depletion region along the source-body junction 110 thus prevents penetration into the depletion region along the drain-body junction 112. The penetration system is avoided by the IGFET 100 by appropriately selecting the amount of the high source side p-type dopant in the channel region 106.

The p-type dopant of the portion of the bulk material 108 below the source 102, channel region 106 and drain 104 has three major components as indicated in Figures 8a, 9a, and 10a. A major component of the p-type dopant in the bulk material portion below regions 102, 104 and 106 is a p-type background dopant represented by curved segments 124' or 114' of Figures 8a, 9a and 10a. The second major component is as defined by the curved segment 116' of Figures 8a, 9a and 10a. The p-type well dopant of the well portion 116.

The last major component of the p-type dopant in the bulk material portion below regions 102, 104 and 106 is the p-type pocket dopant as indicated by curve 120' of Figures 8a and 9a. The p-type pocket dopant is present substantially only in portions of the body material 108 and adjacent portions of the channel region 106 below the source 102. The amount of p-type pocket dopant present in the portion of bulk material 108 that exists below drain 104 is essentially zero or very low, while substantial electrical properties are not critical. Thus, the total p-type pocket dopant of the bulk material 108 portion below the drain 104 is substantially composed of only the p-type well and the background dopant, as shown along the vertical line 136 of FIG. 10a. The obtained curves 116' and 124' or 114' are indicated separately.

The total p-type dopant portion of the bulk material 108 below the drain 104 is indicated by the curved segment 116" of Figure 10b and its extenders 124" (upward) and 114" (downward). 116" represents the sum of the p-type well of the well 116 and the background dopant. Curve segments 114" and 124" correspond to p-lower body material portion 114 and p-upper body material remainder 124, respectively. Since the concentration N _{I of the} p-type background dopant is relatively uniform, the concentration N _T of the total p-type dopant in the portion of the bulk material 108 below the drain 104 is achieved at a surface position substantially equal to the depth y _W . A maximum, i.e., substantially where the p-type well dopant reaches its maximum concentration.

Changes as shown by curve segment 10b of FIG combined 116 "/ 124", the concentration in the drain portion 108 by the lower electrode 104 of the bulk material of the total p-type dopant from the N _T in the p-type well 116 The subsurface position of the maximum concentration of dopant moves up the vertical line 136 upward to the drain 104, while the second steepness decreases by 10% in pairs. Concentration of those portions of body material 108 below drain 104 to the total p-type dopant in the N _T system is shifted from the position of the maximum concentration of the p-type well portion 104 up to the drain and is preferably reduced to up to 20 %, more preferably up to 40%, even more preferably up to 80%, typically close to 100% or more. Further, as 116 '/ 124 "indicated by the combination of curve segments, is moved upward by the position concentrations portion of body material 108 below drain 104 to the total p-type dopant concentration of the N _T from the maximum p-type well portion To the drain 104, and usually it is gradually decreasing.

The net dopant in the bulk material 108 portion below the drain 104 is a p-type dopant. Figure 10c shows that the net dopant concentration N _N of the bulk material 108 portion below the drain 104 is similar to the bulk material below the drain 104, as represented by the combination of the curved segments 116* and 124*. changes in the concentration of N _T and the vertical portion 108 by the total p-type dopant, in addition: N _N concentration in those portions of lines 108 under the drain electrode 104 of the bulk material in the drain - body junction 112 drops to zero. For the reasons discussed further below, the sub-steep vertical doping dose curve of the portion of the body material 108 below the drain 104 is such that the parasitic capacitance associated with the drain-body junction 112 is reduced. This IGFET 100 has an increased analog speed.

Advancing to the dopant distribution along the vertical line 130 through the source 102, the total p-type dopant portion of the body material 108 under the source 102 is doped with a p-type well, background and pocket The composition of the agents is indicated by curves 116', 124' and 120', respectively, of Figure 8a. For the example of FIG. 6 , the source side pocket portion 120 meets the well portion 116 below the source electrode 102 such that the concentration N _{I of the} p-type well portion and the pocket portion dopant exceeds the convergence position p. The background concentration, the total p-type dopant of the bulk material 108 portion below the source 102 is indicated by the combination of the curved segments 116" and 120" of Figure 8b. In one embodiment, wherein the pocket portion 120 extends below the source 102 without the well portion 116, the total p-type dopant system of the portion of the body material 108 below the source 102 will be a curve. The combination of segments 116" and 120" and a curve segment corresponding to the remainder of the p-top body material 124 is indicated.

The concentration of those portions of body material 108 below source 102 to the total p-type dopant from dopant from the N _T lines shown in the graph of FIG. 8b of the segment combination 116 "/ 120" in the p-type well 116 The secondary surface of the maximum concentration of the dopant moves upwardly through the body material 108 and initially decreases to a maximum of 10%, which is typically close to a maximum of 30%. When a local minimum below the source 102 is reached, the concentration N _T of the total p-type dopant in the portion of the bulk material 108 below the source 102 then rises before reaching the source 102.

The net dopant of the portion of bulk material 108 below source 102 is a p-type dopant. Figure 8c shows: as represented by the combination of curved segments 116* and 120*, for the example of Figure 6, wherein the source side pockets 120 are merged with the well 116 and the bulk material below the source 102 The concentration N _N of the net dopant of the 108 portion is perpendicular to the concentration N _T of the total p-type dopant of the portion of the bulk material 108 below the source 102 except for the body below the source 102 The net dopant concentration N _N of the portion of material 108 is reduced to zero at the source-body junction 110. Depending on various factors, such as the depth of pocket portion 120 being greater than the depth of source 102, this vertical doping dose curve below source 102 is sometimes caused along the source-body junction The parasitic capacitance of 110 is reduced, although it is typically less than the parasitic capacitance along the drain-body junction 112.

Referring briefly to Figure 9, for dopant concentrations N _I , N _T and N _N along vertical lines 132 and 134 of the transmission channel region 106, in parentheses after reference symbols 120', 120" and 120*"132" refers to the dopant concentration along vertical line 132. The brackets "134" after reference to respective symbols 124', 124" and 124* refer to the dopant concentration along vertical line 134.

Figure 11 depicts an asymmetric short n-channel IGFET 140 constructed in accordance with the present invention to be particularly suitable for high speed analog applications. A variation of short channel IGFET 140 long channel IGFET 100 in which the channel length is shortened to the extent that the IGFET operation occurs in the short channel mode. The length of the channel is shortened by appropriately reducing the length of the gate electrode 128. In the example of FIG. 11, the p-bag portion 120 extends far enough across the channel region 106 to just coincide with the meeting pole 104.

Figures 12a through 12c (collectively "Figure 12") present exemplary dopant concentrations N _I , N _T and N _N along the upper semiconductor surface of IGFET 140 as a function of longitudinal distance x, thereby facilitating understanding of IGFET 140. The asymmetric longitudinal dopant gradient of the channel region 106. All of the above-described analysis for IGFET 100 associated with FIG. 7 is applied to IGFET 140 except that the shortened length of channel region 106 of IGFET 140 causes the dopant distribution of channel region 106 of IGFET 140 to be different than IGFET 100. The dopant profile of channel region 106 is as explained below in connection with FIG.

As with Figure 7a, the concentration N _I of the p-type pocket dopant along the upper semiconductor surface is represented by curve 120' of Figure 12a. Unlike the occurrence of the channel region 106 of the IGFET 100, the concentration N _I of the p-type pocket dopant along the upper surface of the channel region 106 of the IGFET 140 is not at a location between the source 102 and the drain 104. The essence is to drop to zero. Rather, as shown by curve 120' of Figure 12a, the concentration N _I of the p-type pocket dopant along the upper surface of channel region 106 of IGFET 140 is greater than substantially all of the upper surface of the channel region. Zero, and thus where the channel region 106/bag portion 120 meets the drain 104 is a small finite value. The concentration N _I of the dopant in the pocket of the IGFET 140 is at a much larger value where the region 106/bag portion 120 meets the source 102 (along the upper surface of the channel region).

The aforementioned variation of the concentration N _I of the p-type pocket dopant along the upper surface of the channel region 106 of the IGFET 140 is reflected in the absolute dopant concentration N _T along the upper semiconductor surface of the IGFET 140 and the net doping. Agent concentration N _N . As in Figure 7b, the curved section 106" of Figure 12b represents the concentration N _T of the total p-type dopant along the upper semiconductor surface to the channel region 106 for which the total p-doping at region 106 is The agent is along the sum of the p-type background of the upper semiconductor surface and the pocket dopant. The variation of the curved section 106" of Figure 12b is shown as moving from the source 102 through the channel region 106 along the upper semiconductor surface. to drain 104, IGFET along the upper semiconductor surface of the total concentration of the N _T based p-type dopant in the middle region 106 to the region 106 to 140 of substantially constant high level to the source electrode 102, and then when the The drain 104 is reached and is reduced from the high level to a level slightly below the background dopant concentration. For more specific, IGFET 140 is to the total concentration of N _T based p-type dopant in channel zone 106 along the upper semiconductor surface from the junction 106 to the drain region 104 of the electrode 102 of the zone 106 meets source On the way, it gradually increased.

Similar to the above described with respect to IGFET 100, the dopant concentration N along the upper surface of the IGFET 140 across the upper semiconductor surface along the upper surface of the IGFET 140 is shifted longitudinally across the channel region 106 to the drain 104. _{The I} system can begin to decrease immediately after passing through the source-body pn junction 110. As seen from the drain 104 to the source 102, rather than from the source 102 to the drain 104, along the upper semiconductor surface from where the region 106 meets the drain 104 until the region 106 meets the source 102 Whereas, the concentration N _T of the total p-type dopant in the channel region 106 of the IGFET 140 is then gradually increased. In any case, the concentration of the N _T based IGFET total p-type dopant in zone 106 of IGFET satisfy the above specification for 100 of the 140 along the upper surface, the area 106 to the juncture of the drain 104 as compared The source 106 is lower in this zone 106.

Figure 12c shows that the concentration of the net p-type dopant N _N along the upper surface of the channel region 106 of the IGFET 140 is similar to the total of the regions 106 of the IGFET 140 along the upper semiconductor surface, as represented by curve 106*. p-type dopant concentration of N _T is changed, in addition: Flora N _N concentration along the upper semiconductor surface of IGFET 140 to 106 of the net p-type dopant in the pn junction 110 and 112 to zero. As with the channel region 106 of the IGFET 100, the source side of the channel region 106 of the IGFET 140 has a high net amount of p-type dopant compared to the drain side of the IGFET 140. The high source side p-type doping of the channel region 106 of the IGFET 140 reduces the thickness of the channel side portion of the depletion region extending along the source-body junction 110.

Source 102 and drain 104 of IGFET 140 are closer to each other than IGFET 100. Therefore, it is likely that the depletion region extending along the source 102 will penetrate into the IGFET 140 as compared to the IGFET 100. The depleted area where the bungee 104 extends. However, the high amount of source side p-type dopant of IGFET 140 in channel region 106 reduces its penetration into IGFET 140 relative to a short n-channel IGFET that is equivalent to one of the other aspects of bag portion 120. possibility.

The dopant concentrations along the vertical lines 130, 132, and 136 of the IGFET 140 that pass through the source 102, the channel region 106, and the drain 104, respectively, are substantially the same as the IGFET 100. The concentrations N _I , N _T and N _N along the vertical lines 130, 132 and 136 shown in FIGS. 8 to 10 are thus applied to the IGFET 140. Thus, IGFET 140 has a sub-steep vertical doping dose curve for the portion of body material 108 below drain 104. This reduces the parasitic capacitance associated with the drain-body pn junction 112, as described further below, such that the IGFET 140 has an increased analog speed.

Source 102 may be a longitudinally dopant graded to reduce its source (series) resistance R _S. As discussed below, reducing the source resistance R _{S is} particularly advantageous for analog IGFET applications. This longitudinal dopant grading at source 102 typically involves configuring it as a major portion and a lightly doped laterally extending portion that terminates in channel region 106 along the upper semiconductor surface. . The drain 104 can be similarly graded with a longitudinal dopant to reduce heat carrier injection. It is advantageous to provide both S/D regions 102 and 104 with a longitudinal dopant grading system, regardless of whether regions 102 and 104 act as source and drain, respectively (normal) or drain and source, respectively.

Figure 13 illustrates an asymmetric long n-channel IGFET 150 constructed in accordance with the present invention, particularly suitable for high speed analog applications, and in particular with longitudinal source/drain dopant grading to reduce source resistance R _S and 汲The hot carrier is injected on the extreme side. IGFET 150 is configured as IGFET 100 except that: (a) n-type source 102 is comprised of a heavily heavily doped main portion 102M and a lightly doped laterally extending portion 102E, and (b)n The type drain 104 is comprised of a very heavily doped main portion 104M and a lightly doped laterally extending portion 104E. Although the primary S/D portions 102M and 104M are lighter doped than the n++ main S/D portions 102E and 104E are still heavily doped in sub-micron complementary IFGET applications, such as this one. The n+ laterally extending portions 102E and 104E terminate in the channel region 106 along the upper semiconductor surface. Gate electrode 128 extends partially over each of n+ laterally extending portions 102E and 104E, but is typically not over n++ primary source portion 102M or n++ primary drain portion 104M.

The main S/D portions 102M and 104M generally extend deeper below the upper semiconductor surface than the laterally extending portions 102E and 104E, respectively. As a result, the source depth y _S and the drain depth y _{D of the} IGFET 150 are the depths of the main source portion 102M and the main drain portion 104M, respectively. The pocket portion 120 extends below the main source portion 102M (and partially alongside) such that the drain depth y _D also typically exceeds the source depth y _S . Additionally, pocket portion 120 extends below (and alongside) source extension portion 102E. As a result, the drain extension portion 104E generally extends deeper below the upper surface than the source extension portion 102E.

The maximum net dopant concentration N _N along the upper semiconductor surface to the n++ main source portion 102M is typically at least 1 x 10 ²⁰ atoms/cm 3 , typically 4 x 10 ²⁰ atoms/cm 3 . The maximum net dopant concentration N _N along the upper semiconductor surface to the n++ main drain portion 104M is typically at least 1 x 10 ²⁰ atoms/cm 3 , typically slightly more than 4 x 10 ²⁰ atoms/cm 3 , thereby slightly exceeding The maximum upper surface N _N concentration of the main source portion 102M. The maximum net dopant concentration N _N along the upper semiconductor surface to the n + source extension portion 102E is typically 1 x 10 ¹⁸ to 1 x 10 ¹⁹ atoms/cm 3 , typically 3 x 10 ¹⁸ atoms/cm 3 . The maximum net dopant concentration N _N along the upper semiconductor surface to the n+ drain extension 104E is typically slightly greater than 3 x 10 ¹⁸ atoms/cm 3 , thereby slightly exceeding the maximum upper surface N _{N of the} source extension 102E. concentration.

In accordance with the vertical dopant grading of source 102 and drain 104, channel region 106 of IGFET 150 is substantially identical to IGFET 100 with asymmetric longitudinal dopant grading. Figures 14a through 14c (collectively "Figure 14") present exemplary dopant concentrations along the upper semiconductor surface of IGFET 150 as a function of longitudinal distance x for verifying the longitudinal direction of source 102 and drain 104 The dopant gradient. Figure 14a depicts the concentration N _I of individual semiconductor dopants along its major defined regions 102M, 102E, 104M, 104E, 120 and 124 along the upper semiconductor surface. The total p-type and total n-type dopant concentration N _T along regions 102M, 102E, 104M, 104E, 120 and 124 of the upper semiconductor surface are depicted in Figure 14b. Figure 14c illustrates the net dopant concentration N _N along the upper semiconductor surface.

Figure 14a is similar to Figure 7a except that curves 102M', 102E', 104M' and 104E' represent the n-type dopant concentration N _I along the upper semiconductor surface to form regions 102M, 102E, 104M and 104E, respectively. 14b is similar to FIG. 7b, the n-type surface condition of the dopant concentration N _T is the total system represented by the following persons along the upper semiconductor: (a) curve 102 'by the pole portion 102M and source respectively corresponding to main source The segments 102M" and 102E" of the extended portion 102E are composed and the (b) curve 104" is composed of segments 104M" and 104E" respectively corresponding to the main drain portion 104M and the drain extension portion 104E. Figure 14c is similar to Figure 7c, with the condition that (a) represents a curve 102* along the net dopant concentration N _N of the upper semiconductor surface to the source 102 by extending correspondingly to the main source portion 102M and the source, respectively. The segments 102M* and 102E* of the portion 102E are formed, and (b) represents a curve 104* along the net dopant concentration N _N of the upper semiconductor surface to the drain 104 by respectively corresponding to the main drain portion 104M. Formed with segments 104M* and 104E* of the drain extension 104E.

The longitudinal dopants of source 102 and drain 104 of IGFET 150 gradually reduce the source resistance R _S and mitigate the heat carrier injection on the drain side, but do not have any asymmetric longitudinal dopant that significantly affects channel region 106. Gradient. Therefore, the dopant gradient in the asymmetric channel region of IGFET 150 is primarily the same as IGFET 100 to avoid penetration.

The configuration of the well 116 and the upper body material remainder 124 of the IGFET 150 is substantially the same as the IGFET 100, such that the vertical doping dose curve through the drain 104 to the underlying body material 108 is sub-steep. Since the vertical lines 130 and 136 pass through the n++ main source portion 102M and the n++ main drain portion 104M, respectively, the vertical dopant concentration curves of FIGS. 8 through 10 are substantially applied to the IGFET 150. The reduced parasitic capacitance associated with the drain-body junction 112 allows the IGFET 150 to have an increased analog speed. The reduction in source resistance R _S further enhances the analog performance in the manner discussed below.

The drain 104 can be a vertical dopant gradient to further reduce its association with The parasitic capacitance of the pole-body junction 112. Source 102 can be similar to a vertical dopant ramp to reduce its parasitic capacitance associated with source-body junction 110. Vertical dopant grading typically involves configuring each S/D region 102 or 104 as a major portion and a lightly doped lower portion. The vertical source/drain dopant gradient can be combined with the above-described longitudinal dopant grading of source 102 and drain 104.

With respect to the foregoing, Figure 15 illustrates an asymmetric long n-channel IGFET 160 constructed in accordance with the present invention to be particularly suitable for high speed analog applications. The IGFETs 160 each provide a vertical dopant gradation for reducing the source/drain of the source resistance R _S and the drain side of the heat carrier, and a source/汲 for reducing the parasitic capacitance of the source/drain Extreme vertical dopant gradient. The IGFET 160 is configured identical to the IGFET 150 except that: (a) the source 102 further includes a lower portion 102L that is lighter doped than the main source portion 102M, and (b) the drain 104 further includes its phase The lower portion 104L is one of the lighter dopings than the main drain portion 104M. The lower source portion 102M and the lower drain portion 104M are heavily doped n-type.

The source depth y _S and the drain depth y _{D of the} IGFET 160 are respectively n+lower source portion 102L and n+lower drain portion 104L (since they are placed in the n++ main source portion 102M and the n++ main drain portion 104M, respectively) Under) the depth. The pocket portion 120 extends below the lower source portion 102L. As a result, the drain depth y _{D is} also typically above the source depth y _S .

The source 102 and the drain 104 of the IGFET 160 include an n+ lateral source extension 102E and an n+ lateral drain extension 104E, respectively, to achieve a longitudinal source-drain dopant gradation. Source in the longitudinal direction of IGFET 160 / The drain dopant gradient has substantially the same characteristics as IGFET 150. Therefore, the longitudinal upper surface dopant concentration profile of FIG. 14 associated with IGFET 150 and the description of FIG. 14 are applied to IGFET 160. Since the source/drain dopant grading in the longitudinal direction of IGFET 150 (and thus IGFET 160) does not have any significant effect on the asymmetric longitudinal dopant grading of channel region 106, the asymmetric channel in IGFET 160 The region dopant gradient is substantially the same as IGFET 100 and avoids penetration of IGFET 160.

The understanding of the vertical dopant grading at IGFET 160 is facilitated by means of Figures 16a to 16c (collectively "Figure 16") and Figures 17a to 17c (collectively "Figure 17"), and Figures 16 and 17 are presented along Exemplary dopant concentrations, respectively, through the vertical lines 130 and 136 of the source 102 and the drain 104 (including: through the lower source portion 102L and the lower drain portion 104L, respectively) as a function of depth y. Figures 16a and 17a clearly illustrate the concentration N _I of the individual semiconductor dopants (along lines 130 and 136, respectively) of the vertically defined regions 102M, 102L, 104M, 104L, 114, 116, 120 and 124. The total p-type and total n-type dopant concentration N _T along lines 130 and 136 for regions 102M, 102L, 104M, 104L, 114, 116, 120 and 124 are depicted in Figures 16b and 17b, respectively. Figures 16c and 17c illustrate the net dopant concentration N _N along lines 130 and 136, respectively.

Figures 16a and 17a are similar to Figures 8a and 10a, respectively, except that: (a) curves 102M' and 102L' represent vertical n-type dopants that are utilized to form primary source portion 102M and lower source portion 102L, respectively. The concentration N _{I of} line 130, and (b) curves 104M' and 104L' represent the concentration N _I along the vertical line 136 of the n-type dopant that is utilized to form the main drain portion 104M and the lower drain portion 104L, respectively. . Similarly, FIG. 16b and 17b are similar to Figures 8b and 10b, the condition is: (a) along the line of the total concentration of N _T n-type dopants, respectively, by the line 130 corresponding to the lower source portion 102M and main source of pole section 102L of the curve segments 102M "and 102L" where this composition 102 "is represented, and (b) along the total n-type dopant concentration of the N _T by the line 136 lines respectively corresponding to main drain portion 104M It is represented by a curve 104" composed of segments 104M" and 104L" of the lower drain portion 104L.

FIG. 16c and 17c are similar to Figures 8c and 10c, the condition is: (a) on behalf of the source line 130 along the net dopant concentration N _N pole 102 of curve 102 * here respectively correspond to main source portion 102M and lower source portion 102L of electrode segments 102M * and 102L * is formed, and (b) represents the line along a net dopant concentration in the drain electrode 104 of the N _N 136 104 * in this graph correspond to the primary of The drain portion 104M is formed with the segments 104M* and 104L* of the lower drain portion 104L. Moreover, the dopant concentration of the IGFET 160 along the vertical lines 132 and 134 of the transmission channel region 106 is substantially the same as the IGFET 100. Therefore, the concentrations N _I , N _T , and N _N along the vertical lines 132 and 134 shown in FIG. 9 are applied to the IGFET 160.

In accordance with the foregoing arguments regarding the vertical dopant grading of source 102 and drain 104 of IGFET 160, the configuration of well 116 and pocket 120 of IGFET 160 is substantially identical to IGFET 100. Therefore, the vertical doping dose curve below the drain 104 of the IGFET 160 is substantially the same as the IGFET 100. Therefore, the parasitic capacitance associated with the drain-body junction 112 is reduced by the IGFET 160, thus enabling it to have an increased analog speed. The vertical dopant grading at source 102 and drain 104 is achieved by reducing (or further reducing) the parasitic capacitance along source-body junction 110 and by further reducing the gate-body interface 112 along the drain The parasitic capacitance enables the IGFET 160 to have a higher analog speed. The longitudinal dopant of source 102 and drain 104 of IGFET 160 gradually reduces the source resistance R _S and at the same time mitigates the heat carrier injection on the drain side.

Figures 18a through 18c illustrate the forms 170, 180 and 190 of asymmetric long n-channel IGFETs 100, 150 and 160, respectively, wherein pocket portion 120 extends below the upper semiconductor surface as compared to source 102 and drain 104. To a smaller depth. For a long n-channel IGFET 180 or 190 whose source 102 and drain 104 respectively include a source extension 102E and a drain extension 104E, the pocket 120 extends below the upper semiconductor surface to a depth deeper than the extension 102E and extension Section 104E.

As explained above in connection with IGFET 100, the p-type segment at the boundary of pockets 120 of each IGFET 170, 180 or 190 is defined as having a p-type pocket dopant concentration equal to the p-type background dopant. The location of the concentration. The total p-type dopant concentration of the p-type segments along the boundaries of the pockets 120 is twice the background dopant concentration of the IGFETs 170, 180 or 190. Thus, some of the p-type pocket dopants are present at the source 102 of the IGFET 170, 180 or 190 and are below the depth shown for the pocket 120 of Figures 18a-18c. This additional p-type pocket dopant at source 102 cancels (compensates) some of the n-type dopants that define source 102 as being along its lower surface. Thus, the drain depth y _D of the IGFET 170, 180 or 190 exceeds the source depth y _S , albeit to a smaller amount than the IGFET 100.

Channel region 106 of each of IGFETs 170, 180, and 190 is substantially asymmetric longitudinal dopant grading for IGFETs 100, 150, and 160, respectively, as described above. In this regard, the dopant concentrations N _I , N _{T ,} and N _N for the upper semiconductor surface of the IGFET 170 are also substantially represented in FIG. 7, respectively. Figure 14 essentially presents dopant concentrations N _I , N _T and N _N along the upper surface for IGFETs 180 and 190. In the manner described above for IGFET 100, penetration is thus avoided by IGFETs 170, 180 and 190.

Each of IGFETs 170, 180, and 190 is substantially a sub-steep vertical doping dose curve below solute 104 for IGFETs 100, 150, and 160 as described above. 10 also substantially presents concentrations N _I , N _{T ,} and N _N along the vertical line 136 through the drain 104 for each of the IGFETs 170 and 180, respectively. The concentrations N _I , N _T and N _N for the vertical line 136 of the IGFET 190 along the pass gate 104 are substantially represented in FIG. The parasitic capacitance along the drain-body junction 112 of each IGFET 170, 180 or 190 is thus reduced, as described above for the IGFET 100, enabling each IGFET 170, 180 or 190 to have an increased analog speed.

FIGS. 19a through 19c (collectively "FIG. 19") and FIGS. 20a through 20c (collectively "FIG. 20") present examples of doping for the IGFETs 170, 180 and 190 along the vertical line 130 passing through the source 102. The concentration of the agent, as a function of depth y. Figure 19 is applied to IGFETs 170 and 180. FIG. 20 is applied to IGFET 190. 19a and 19b clearly illustrate the concentration N _I of individual semiconductor dopants that vertically define regions 102, 114, 116, and 120 along line 130. Along line 130 in a region of the p-type 102,114,116 and 120 of the total concentration of the total n-type dopant N _T depicted in FIG. 19b and 20b. Figures 19c and 20c illustrate the net dopant concentration N _N along line 130, respectively.

As in FIG. 19b and 20b of curve segments 116 'and 124 "of FIG, 108 are part of body material 102 below the source of the total p-type dopant concentration from the N _T based on the p-type well 116 The subsurface position of the maximum concentration of dopant moves up the vertical line 130 up to the source 102 and sub-steep to a maximum of 10%. The shallower pocket portion 120 is formed as compared to the source 102 and the drain 104, thus causing a sub-steep vertical amount variation curve for the total p-type dopant for the portion of the bulk material 108 below the source 102. This occurs because many of the less p-type dopants are below the source 102 of IGFETs 170, 180, and 190 as compared to IGFETs 100, 150, and 160. The curves 120' representing the total p-type pocket dopant concentration N _T along the vertical line 130 of the source 102 are shown in Figures 8b, 16b, 19b and 20b. Most of the bits are at the source in Figures 19b and 20b. Above the depth y _S and in Figures 8b and 16b there is considerable extension below the depth y _S .

The sub-steep vertical doping dose curve of the portion of the body material 108 below the source 102 of the IGFET 170, 180 or 190 is substantially similar to the drain 104 of the IGFET 170, 180 or 190 (and thus for the IGFET 100) The sub-steep vertical doping dose curve of the portion of the bulk material 108 of the lower portion of the drain 104 of 150 or 160. Curve section 116"/120" of the combination of the vertical lines 130 passing through the source 102 of FIGS. 19b and 20b and the curved section 116 of the combination of the vertical lines 136 of the passages 104b and 17b. "/120". Drain electrode 104 is similar to the lower body portion 108 by a material that occurs by, those portions of body material 108 below source in each IGFET 170,180 or 190 of the electrode 102 total p-type dopant concentration from the maximum line N _T The sub-surface position of the p-type well concentration is a very heavily doped material that moves up to the source 102, and is preferably reduced to a maximum of 20%, more preferably to a maximum of 40%, and even more preferably to a maximum of 80. %, typically close to 100%. The sub-steep vertical doping dose curve of the bulk material 108 portion of the IGFET 170, 180 or 190 below the very heavily doped material of the source 102 causes the parasitic capacitance associated with the source-body junction 110 to be reduced. small. The analog speed of the IGFET 170, 180 or 190 is in turn increased.

The dopant concentrations N _I , N _T and N _{N of the} IGFET 170, 180 or 190 along the vertical line 134 of the transmission channel region 106 are substantially as shown in FIG. IGFET 170, 180 or 190 along the through channel zone 106 (comprising: a pocket portion 120) N _I a dopant concentration of a vertical line 134, N _T are shown similar to Figure 9 _N N lines, except: directed to the IGFET N _I concentration curve along the line p-type pocket dopant portions 170, 180 or 190. 132. 120 "is similar to FIG. 19a or 20a of curve 120 along line 130 '.

To describe the simplicity of IGFETs 100, 140, 150, 160, 170, 180, and 190, it is assumed above that the concentration of the p-type background dopant is substantially fixed throughout it containing IGFETs 100, 140, 150, 160, Semiconductor material of any of 170, 180 and 190. However, the concentration of the p-type background dopant can vary as long as the peak of the p-type background dopant is relatively low compared to other p-type dopants.

The well 116 of the body material 108 of each of the IGFETs 100, 140, 150, 160, 170, 180, and 190 is the same conductivity type as the directly underlying lightly doped semiconductor material (lower body material portion 114). . The process associated with Figures 31a through 31o and Figures 31p.1 through 31r. 2 is indicated below, when the p+ well 116 and the p+ pocket 120 are made light. Occurs in the initial region of the doped p-type semiconductor material. The dopant concentration of most of the upper body material remainder 124 is thus often equal to the low background dopant concentration of the p-start region.

Alternatively, the semiconductor material directly below the well 116 can be the opposite conductivity type for the well 116. Since the well 116 is p-type, the semiconductor material directly below the well 116 is then n-type. This alternative is typically present when p+ well 116 and p+ pocket 120 are initially formed in the n-type semiconductor material, typically lightly doped to a fairly uniform net dopant concentration. In one embodiment, it is intended to be the starting n-type region portion of the upper body material portion 118 (ie, the starting n-type region above the well 116 (or above the intended location for the well 116)) Partially) is doped with an absolute concentration of p-type compensating dopant to its n-type background dopant concentration greater than the starting n-type semiconductor region, whereby all of the upper body material portion 118 is p-type. In another embodiment, the portion intended to be the starting n-type region of the upper body material portion 118 is converted to p-type conductivity by the upward diffusion of a portion of the p-type well dopant of the well 116.

The minimum value of the p-type compensation or the net concentration N _N of the well dopant in the upper body material portion 118 may be close to the n-type background dopant concentration. However, to ensure that all of the bulk material portion 118 is p-type, the minimum of the p-type compensation or well dopant concentration N _N at portion 118 is typically a significant amount greater than the n-type background dopant concentration, such as : At least twice as large. The minimum of the p-type compensation or the concentration of the well dopant N _N of most of the bulk material portion 118 on the outside of the well 120 is therefore typically significantly greater than the n-type background dopant concentration.

21 illustrates a variation 100V in accordance with the present invention and which is similar to the asymmetric long n-channel IGFET 100 of FIG. 6, wherein the p-lower body material portion 114 is replaced by a lightly doped n-type lower region 192, A pn junction 194 is formed below one of the p+ wells 116. Since the lower region 192 is not p-type conductive, the p-type body material 108 at the IGFET 100V is comprised of the well 116 and an upper portion 196 of the upper body material portion 118 of the IGFET 100. The upper body material portion 196 portion of the IGFET 100V is formed by the p+ pocket portion 120. The remainder of the upper body material portion 196 (i.e., the portion on the outer side of the pocket portion 120) is referred to as item 198 of FIG. The upper body material remainder 198 is lightly doped p-type with a somewhat higher net concentration than the n-lower portion 192. The mild p-type doping of the remaining body material 198 is achieved by the p-type compensation dopant described above. The IGFET 100V is substantially identical to the IGFET 100 in configuration and configuration, except for the aforementioned differences and differences in synthesized dopant concentrations.

IGFET 100V has the following features similar to those of IGFET 100: (a) asymmetrical longitudinal dopant grading in one of channels 106, and (b) sub-steep portion of body material 108 below drain 104 Vertical doping dose curve. An understanding of these features of IGFET 100V (including: how they can be somewhat different from those of IGFET 100) is by means of Figures 22a to 22c (collectively "Figure 22"), Figures 23a to 23c (collectively "Figure 23 "), and Figures 24a to 24c (collectively "Figure 24"). Figure 22 presents an exemplary dopant concentration along the upper semiconductor surface of IGFET 100V as a function of longitudinal distance x. The IGFET 100V is along the vertical line 130 through the source 102 An example dopant concentration is presented in Figure 23. 24 presents an example dopant concentration along IGFET 100V along vertical line 136 through drain 104.

Figures 22a, 23a and 24a illustrate the concentration N _I of individual semiconductor dopants defining regions 102, 104, 116, 120, 192, 196 and 198. The curves 192' and 198' clearly represent the concentration N _I of the n-type background dopant and the p-type compensation dopant, respectively, which define the n-lower region 192 and the p-upper body material remaining 198, respectively. Item 194 ^# refers to the position below the well 116 where the net dopant concentration N _N becomes zero and thus indicates the position of the lower pn junction 194.

102,104,116,120,192,196 in a region of 198 to the total p-type and total n-type dopant concentration of N _T depicted in FIG. 22b, 23b and 24b. The curved segments 192" and 198" of Figures 22b, 23b and 24b correspond to the n-lower region 192 and the p-upper body material remainder 198, respectively. Figures 22c, 23c and 24c illustrate the concentration N _N of the net p-type dopant and the net n-type dopant for the various regions 102, 104, 116, 120, 192, 196 and 198. The curved segments 192* and 198* of Figures 22c, 23c and 24c correspond to the n-lower region 192 and the p-upper body material remainder 198, respectively.

Figures 22 through 24 represent an example in which: (a) the concentration N _I of the n-type background dopant of the IGFET 100V is approximately equal to the p-type background dopant concentration N _{I of the} IGFET 100, (b) along the IGFET 100V The concentration N _I of the p-type compensation dopant on the upper semiconductor surface is 2 to 3 times the concentration N _I of the n-type background dopant of the IGFET 100V, and (c) the concentration of the p-type compensation dopant N _I The maximum value is 2 to 3 times the concentration N _I of the p-type compensation dopant along the upper semiconductor surface and thus 4 to 9 times the concentration N _I of the n-type background dopant. In addition to these differences, the concentration N _I of the other dopants of IGFET 100V is mostly the same as IGFET 100, respectively.

More specifically, the concentration N _I of the p-type pocket dopant in the IGFET 100V is substantially the same as that of the IGFET 100 in the longitudinal direction. The curved section 120' of Fig. 22a shows: from the source 102 and along the semiconductor surface above the IGFET 100V to the channel region 106, the concentration of the p-type pocket dopant N _I is in the middle of the region 106. It is about a fixed upper surface level, and then a position between the source 102 and the drain 104 is substantially reduced to zero from that level.

The sum of the total p-type dopant pocket portion of the IGFET 100V along the upper semiconductor surface in the channel region 106 and the compensation dopant. This is different from IGFET 100 in that it is the sum of the total p-type dopant pocket portion of the channel region 106 along the upper semiconductor surface and the background dopant. Since the concentration of N _I 2-3-fold concentration of the concentration of N _I N _I illustrates an example of the line-type compensating dopant in the p-type background dopant of n and is therefore in the context of IGFET 100. The p-type dopant 2 Up to 3 times, the minimum value of the total p-type dopant concentration N _I along the upper surface of the IGFET 100V in the illustrated example is the minimum of the total p-type dopant concentration N _I along the upper surface of the IGFET 100. Up to 3 times.

Item 106" of Figure 22b represents the portion of the channel portion of curve segments 120" and 198". Similar to the appearance of IGFET 100, the variation at curve 106" is shown here: IGFET 100V along the upper semiconductor surface in the channel The concentration N _T of the total p-type dopant in region 106 is lower than that in region 106 where the source 102 is merged. Channel IGFET 100V in the areas of the total p-type dopant concentration compared to the N _T 106 along the source electrode on the surface of the - body junction 110 to the upper surface of the pole along the drain - body junction 112 is typically relatively It is 10% lower, preferably at least 20% lower, more preferably at least 50% lower, and typically lower at nearly 100. The typical value for this difference in concentration for IGFET 100V is close to 100% instead of more than 100% (as may occur in IGFET 100). The reason for the illustrated example of IGFET 100V is the total p along the upper surface. Min-type dopant concentration of the N _T IGFET 100 and compared to the 2 to 3-fold higher

Referring to Figure 22c, item 106* here represents a combination of channel zone curve segments 120* and 198*. The segment 198* according to the curve 106* for the IGFET 100V is slightly higher than the segment 124* for the curve 106* of the IGFET 100 of Figure 7c, and the curve 106* of Figures 7c and 22c is quite similar. Therefore, a high-purity p-type dopant is provided on the source side of the channel region 106 of the IGFET 100V compared to the drain side. The thickness of the channel side portion of the IGFET 100V along the depletion region of the source-body junction 110 is thus reduced. Moreover, for the above-described (field line termination) reason associated with IGFET 100, the high p-type dopant concentration along the source side of channel region 106 of IGFET 100V shields source 102 from drain 104 A fairly high electric field. The penetration system is avoided by the IGFET 100V.

The p-type dopant portion of the bulk material 108 below the source 102 and the drain 104 of the IGFET 100V is the primary well and compensating dopant indicated by curves 116' and 198' of Figures 23a and 24a, respectively. The composition, and for the source 102, is comprised of a pocket dopant also indicated by curve 120' of Figure 23a. The variation of curve 198' in Figures 23a and 24a shows that the concentration N _I of the p-type compensation dopant is near the bottom of source 102 and drain 104 to a maximum. This maximum is 4 to 9 times the concentration N _I of the n-type background dopant of the specific examples of Figures 23a and 24a. P-type compensating dopant concentration in N _I-based example of FIG. 23a and 24a is decreased to zero in less than a maximum concentration of the p-type dopant is one of the well depth of the depth y _W portion 116 of the essence.

The total p-type dopant portion of the bulk material 108 below the drain 104 of the IGFET 100V is indicated by the curved segment 116" of Figure 24b and its (upward) extension 198". Since the concentration of N _I p-type compensating dopant lines in one of a depth less than the depth y _W and essentially drops to zero, the body material portion below drain's 104 total p-type dopant concentration of the N _T based on substantive It is equal to the subsurface position of y _W and reaches a maximum value. As occurs in IGFET 100, 116 "/ 198" changes the composition of curve segment 24b in FIG shows: the concentration of those portions of body material 108 below drain 104 of IGFET 100V of the total p-type dopant from the N _T The subsurface position of the maximum concentration of the total p-type dopant at the well 116 is moved upward to the drain 104 and sub-steep to a maximum of 10%.

Specific examples in Figure 24b, the portion 108 of the body's material of IGFET 100V below drain 104 of the total p-type dopant concentration of the N _T is typically based on a position moved upward from the maximum concentration of the p-type well to the drain portion The pole 104 is reduced to a maximum of approximately 15%. The typical value of this steep concentration reduction for IGFET 100V is at most close to 15% rather than close to 100% (as appears in IGFET 100) because the IGFET 100V has a drain 104 of the example of Figure 24a. 4-9 N _I-fold concentration of the p-type background dopant at the bottom of the bottom of the p-type compensating dopant concentration N _I drain line 100 in IGFET 104 is extremely. However, the vertical doping dose curve for the p-type compensation dopant can reduce the concentration N _I of the p-type compensation dopant at the bottom of the drain 104, while still ensuring: the upper body material All of the portions 196 are p-type. The total concentration of N _T line of the p-type body material portion below drain of IGFET 100V to 104 to 108 dopants may be moved upwardly from the position of the shaft portion 116 of the total p-type dopant to the maximum concentration of the drain 104 is easily reduced to at most 20%, and typically at most 40%.

As represented by the combination of curve segments 116* and 198*, Figure 24c shows that the concentration of the net p-type dopant N _N varies vertically in the portion of bulk material 108 below the drain 104 of the IGFET 100V. The concentration N _T of the total p-type dopant in the bulk material portion below the drain 104 is except that the concentration N _N of the bulk material portion below the drain 104 is reduced to the pn junction 112 and 194 to zero. The parasitic capacitance associated with the drain-body junction 112 is also due to the reasons discussed further below due to the sub-steep vertical doping dose curve of the bulk material portion below the drain 104 of the IGFET 100V. Reduced. Although the reduction in parasitic capacitance along junction 104 may be smaller than IGFET 100V compared to IGFET 100, the IGFET 100V system still has an increased analog speed.

The presence of a p-type compensating dopant having a concentration greater than that of the p-type background dopant of IGFET 100 has a relatively small effect on the IGFET compared to the vertical doping dose curve of the pass gate 104 of the IGFET 100V. The vertical doping dose curve of the 100V pass source 102 is because the p-type pocket dopant is also present below the source 102 of the IGFET 100V. As is apparent from a comparison of FIG. 23 and FIG. 24, with respect to the vertical doping dose curve of the IGFET 100 through the source 102, the above-described argument summarizes the vertical doping dose curve applied to the pass source 102 of the IGFET 100V.

Figure 25 illustrates a variation 150V in accordance with the present invention and similar to the asymmetric long n-channel IGFET 150 of Figure 13, wherein the n-lower portion 192 again replaces the p-lower body material portion 114. IGFET 150V also includes a p-type upper body material portion 196 that replaces upper body material portion 118 of IGFET 150. The p-residue 198 of the upper body material portion 196 is again at a slightly higher net dopant concentration than the n-lower portion 192. Like IGFET 100V, the mild p-type doping of the body material remainder 198 above IGFET 150V is achieved by a p-type compensation dopant. The IGFET 150V is substantially identical to the IGFET 150 in the presence of the n-lower portion 192 and the p-upper body material remaining 198, thereby having a longitudinal source/drain dopant gradient to reduce the source resistance R _S and Heat carrier injection on the drain side.

Figures 26a through 26c (collectively "Figure 26") present exemplary dopant concentrations along the upper semiconductor surface of IGFET 150V for verifying the vertical dopant grading at source 102 and drain 104. The concentration N _I of the individual semiconductor dopants along the major defined regions 102M, 102E, 104M, 104E, 120, 192 and 198 of the upper surface is depicted in Figure 26a. Figure 26b illustrates the concentration N _T of the total p-type and n-type dopants along regions 102M, 102E, 104M, 104E, 120, 192 and 198 along the upper surface. The net concentration N _N along the upper surface is illustrated in Figure 26c.

Figure 26 repeats Figure 14 and is modified as shown in Figure 22 to account for the n-lower portion 192 and the p-upper body material remainder 198. The longitudinal dopant grading of source 102 and drain 104 of IGFET 150V does not have any significant longitudinal dopant grading that significantly affects channel region 106. The asymmetrical channel region dopant gradient in IGFET 150V is mostly similar to IGFET 150 and therefore largely as IGFET 100 avoids penetration.

For the IGFET 150V p+ well 116 and p- above the body material remains The configuration of the 198 is such that it passes through the drain 104 and the vertical doping dose curve to the underlying body material 108 is sub-steep and substantially the same as the IGFET 150. The vertical dopant concentration profiles along vertical lines 130 and 136 of Figures 23 and 24 are substantially applied to IGFET 150V. The drain-body junction 112 of the IGFET 150V has a reduced parasitic capacitance, although typically not as much as the IGFET 150, providing an improved analog switching speed for the IGFET 150V.

Figures 27a and 27b illustrate variations 170V and 180V of asymmetric long n-channel IGFETs 170 and 180, respectively, in accordance with the present invention, similar to Figures 18a and 18b, respectively, wherein n-lower portion 192 again replaces the p-lower body material portion. 114. Each IGFET 170V or 180V also contains a p-type upper body material portion 196 that replaces the body material portion 118 above the IGFET 170 or 180. The p-residue 198 of the upper body material portion 196 is again at a slightly higher net dopant concentration than the n-lower portion 192. Like IGFETs 100V and 150V, the mild p-type doping of the body material remainder 198 above each IGFET 170V or 180V is achieved by a p-type compensation dopant. The pockets 120 of the respective IGFETs 170V or 180V extend below the upper semiconductor surface to a lesser depth than the source 102 and the drain 104, in accordance with the presence of the n-lower portion 192 and the p-upper body material remaining 198. . The IGFET 180V also has a source/drain dopant gradation in the longitudinal direction of the IGFET 150V to reduce the source resistance R _S and the heat carrier injection on the drain side.

The channel region 106 of each of the IGFETs 170V and 180V is substantially asymmetric longitudinal doping grading as described above for IGFETs 100V and 150V, respectively. Figure 22 essentially presents concentrations N _I , N _T , and N _N for the upper semiconductor surface of IGFET 170V. For the reasons described above in relation to IGFET 100V, the penetrating system is thus avoided in IGFET 170V. The concentrations N _I , N _T and N _N of the IGFET 180V along the upper semiconductor surface are substantially represented in Fig. 26, respectively. IGFET 180V avoids penetration as described above for IGFET 170V and thus as described above for IGFET 100V.

Each of the IGFETs 170V and 180V has a sub-steep vertical doping dose curve through the drain 104 as described above for the IGFET 100V. Figure 24 also shows concentrations N _I , N _T and N _N for vertical lines 136 across the drain 104 for each IGFET 170V or 180V. As a result, the parasitic capacitance along the drain-body junction 112 of each IGFET 170V or 180V is reduced for the reason described above in relation to the IGFET 100V. The IGFET 170V or 180V thus has an increased analog speed.

Figures 28a through 28c (collectively "Figure 28") present concentrations N _I , N _T and N _N for vertical lines 130 passing through source 102 for respective IGFETs 170V or 180V, respectively. The curve segment 28b in FIG. 116 "and 198" of the changes indicated by the concentration portion of body material 108 below source 102 to the total p-type dopant from the N _T p-type dopant in well portion 116 The subsurface position of the maximum concentration of the agent moves up the line 130 up to the source 102 and sub-steep to a maximum of 10%. As occurs in IGFETs 170 and 180, at IGFETs 170V and 180V, shallower pockets 120 are formed as compared to source 102 and drain 104, resulting in p-type doping for portions of the bulk material below source 102. Sub-steep vertical quantitative curve of the agent.

For each IGFET 170V or 180V, the sub-steep vertical doping dose curve of the portion of the body material 108 below the source 102 is quite similar to the sub-steep vertical doping of the bulk material 108 portion below the drain 104. Dose change curve. In the particular example of FIG. 28, the concentration N _T of the total p-type dopant of the bulk material portion of the IGFET 170V or 180V below the source 102 is moved upward from the position of the maximum p-type well concentration to the source 102. The typical reduction is up to approximately 15%. Although this typical 15% is significantly less than the typical 100% that occurs for the corresponding IGFET 170 or 180, the vertical doping dose profile for the p-type compensation dopant can be reduced. Similar to its vertical doping dose profile for the pass gate 104 of the IGFET 100V, the concentration of the total p-type dopant in the bulk material portion below the source 102 of the IGFET 170V or 180V is described above. The N _T system can be easily reduced from up to 20%, typically up to 40%, from the maximum concentration position of the total p-type dopant of the well 116 up to the source 102.

The sub-steep vertical doping dose curve of the portion of bulk body 108 of IGFET 170V or 180V below source 102 reduces the parasitic capacitance associated with source-body junction 110, although typically compared to IGFET 170 Or one of the smaller quantities of 180. As a result, the analog speed of each IGFET 170V or 180V is further increased.

Variations of IGFETs 140, 160 and 190 may be provided with n-lower portion 192 and p-upper body material remaining 198 (or p-type upper body material portion 196), with regions 192 and 198 (or 196) being provided at IGFET 100V, 150V, 170V and 180V in the same way. These asymmetric long n-channel variations of IGFETs 140, 160, and 190 are hereinafter referred to as IGFETs 140V, 160V, and 190V, respectively.

Complementary IGFET construction for mixed-signal applications

Long channel IGFETs 150, 160, 170, 180, 190, 100V, 150V, Short channel forms of 160V, 170V, 180V and 190V can be made in accordance with the present invention by appropriately reducing the length of the channel. The p-channel IGFET can be implemented by reverse IGFETs 100, 140, 150, 160, 170, 180, 190, 100V, 140V, 150V, 160V, 170V, 180V, and 190V (including: IGFETs 150, 160, 170, 180, 190, The conductivity type of the semiconductor region of the 150V, 160V, 170V, 180V, and 190V short channel variations is also manufactured in accordance with the present invention.

N-channel IGFETs 100, 140, 150, 160, 170, 180, 190, 100V, 140V, 150V, 160V, 170V, 180V and 190V (including: IGFETs 150, 160, 170, 180, 190, 150V, 160V, 170V, The variants of the short channels of 180V and 190V) and the p-channel IGFETs can each be provided in the same semiconductor construction to produce a complementary IGFET semiconductor architecture that is particularly suitable for high speed analog applications. For example, one or more of the n-channel IGFETs 100, 140, 150, 160, 170, 180, and 190 can incorporate changes in one or more of the IGFETs 100V, 140V, 150V, 160V, 170V, 180V, and 190V. By. The complementary IGFET is constructed of a lightly doped p-type semiconductor material using the p-lower body material portion 114 as the p-type equivalent of the n-lower portion 192 for IGFETs 100V, 140V, 150V, 160V, 170V, The change of each p channel of 180V or 190V. Alternatively, one or more of the n-channel IGFETs 100V, 140V, 150V, 160V, 170V, 180V, and 190V may incorporate one or more p-channel variations of the IGFETs 100, 140, 150, 160, 170, 180, and 190. Manufactured from a lightly doped n-type semiconductor material using n-lower portion 192 as the n-type equivalent of p-lower body material portion 114 for IGFET A change in each p-channel of 100, 140, 150, 160, 170, 180, or 190.

IGFETs (n-channel and p-channel) that are particularly suitable for digital circuits can also be provided in semiconductor construction. Bipolar transistors (npn and pnp) can each be provided in a semiconductor construction. The resulting semiconductor architecture is therefore suitable for mixed-signal applications.

Figures 29.1 and 29.2 (collectively "Figure 29") depict two portions of a complementary IGFET semiconductor construction constructed in accordance with the present invention to be particularly suitable for mixed signal applications. The complementary IGFET structure of Figure 29 is fabricated from a doped single germanium semiconductor body having a lower p-body material portion 114. A patterned field region 200, typically one of the electrically insulating materials consisting primarily of yttria, is recessed onto the upper surface of the semiconductor body to define a group of laterally separated active semiconductor islands. Four such island portions 202, 204, 206 and 208 appear in FIG.

Four long channel IGFETs 210, 220, 230 and 240 are formed at the locations of islands 202, 204, 206 and 208 along the upper semiconductor surface, respectively. The IGFETs 210 and 220 of Figure 29.1 are primarily intended for use with asymmetric devices for high speed analog applications. The IGFETs 230 and 240 of Figure 29.2 are primarily intended for use in symmetrical devices for digital applications. IGFETs 210 and 230 are n-channel devices. IGFETs 220 and 240 are p-channel devices.

The asymmetric n-channel IGFET 210 is an implementation of the long n-channel IGFET 180 of Figure 18b and contains all of the regions of the IGFET 180. Therefore, the IGFET 210 is substantially as described above for the IGFET 180 and thus has a sub-deep below the drain 104 for the IGFET 100 as described above. The tangential vertical doping dose curve. Similarly, channel region 106 of IGFET 210 is directed to IGFET 180 as described above and is therefore substantially asymmetric longitudinal doping grading for IGFET 150 as described above.

The source 102, the drain 104, and the channel region 106 of the n-channel IGFET 210 are located at the island 202. In addition to the region depicted in FIG. 18b, IGFET 210 includes a pair of electrically insulating sidewall spacers 250 and 252 positioned along opposing lateral sidewalls of gate electrode 128. Metal telluride layers 254, 256, and 258 are located along the top of source 102, drain 104, and gate electrode 128, respectively.

An asymmetric p-channel IGFET 220 is implemented in the form of a p-channel of a long n-channel IGFET 180V in which the n-lower portion 192 is replaced by a p-lower body material portion 114. IGFET 220 has a p-type source 262 and a p-type drain 264 separated by an n-type channel region 266 of n-type body material 268. The body material 268 is comprised of a heavily doped well 276 and an upper portion 278. Composed of. As a p-channel implementation of n-channel IGFET 180V, p-channel IGFET 220 is substantially identical (inverted by the conductivity type) as described above for n-channel IGFET 180V and thus for n-channel IGFET as described above 100V with a sub-steep vertical doping dose curve below the drain 264. Similarly, the channel region 106 of the p-channel IGFET 210 is substantially identical (again, in the opposite direction of the conductive pattern) as described above for the n-channel IGFET 180V and thus for the n-channel IGFET 150V as described above. Asymmetric longitudinal doping gradient.

The source 262, the drain 264, and the channel region 266 of the p-channel IGFET 220 are located at the island 204. Each p-type S/D region 262 or 264 is comprised of a very heavily doped main portion 262M or 264M and a lightly doped (but still heavily doped) laterally extending portion 262E or 264E to The source resistance R _S and the heat carrier injection on the drain side are reduced. The p+ laterally extending portions 262E and 264E terminate in the channel region 266 along the upper semiconductor surface.

A heavily doped pocket portion 280 of the n-type upper body material portion 278 extends along the source 262, primarily along the source extension portion 262E. As with the pocket portion 120 of the IGFET 210, the n+ pocket portion 280 extends deeper below the upper semiconductor surface than the p+ source extension portion 262E, but is not as deep as the p++ main source portion 262M. The remainder 284 of the n-type upper body material portion 278 is lightly doped and extends along the drain 264. The n+ well 276, n+ pocket 280 and n-upper body material remainder 284 of IGFET 220 typically have p+ well 116, p+ pocket 120 and p-top body material remaining 198, respectively, as IGFET 180V. Most of the same longitudinal and vertical doping characteristics and the conductivity pattern are reversed. The IGFET 220 thus avoids penetration and has a reduced parasitic capacitance along the source-body and drain-body pn junctions.

With respect to the variations of IGFET 220 described below in connection with Figures 32a through 32c and Figures 33a through 33f, the n-upper body material remainder 284 is essentially an extension of only one of the n+ wells 276. The slight n-type doping of the n-upper body material remainder 284 of this variation is produced by the upward diffusion of the n-type dopant portion used to form the n+ well 276 to avoid its use. The remaining 284 is caused to be a separate dopant introduction step for the lightly doped n-type.

A gate dielectric layer 286 is overlying the channel region 266 of the IGFET 220. on. A gate electrode 288 is a gate dielectric layer 286 above the channel region 266. The gate electrode 288 extends partially over each of the lateral S/D extensions 262E or 264E. In the example of Figure 29, the gate electrode 288 is composed of a very heavily doped p-type polyfluorene. A pair of electrically insulating sidewall spacers 290 and 292 are positioned along opposite lateral sidewalls of p++ gate electrode 288. Metal telluride layers 294, 296, and 298 are located along the top of source 262, drain 264, and gate electrode 288, respectively.

Symmetrical n-channel IGFET 230 has one pair of n-type S/D regions 302 and 304 separated by a p-type channel region 306 of p-type body material 308, which is heavily doped by a lower p-portion 114 The adjacent well 316 is formed with an upper portion 318. S/D zones 302 and 304 and channel zone 306 are located on island 206. Each n-type S/D region 302 or 304 is comprised of a heavily heavily doped main portion 302M or 304M and a heavily doped (and therefore lightly doped) laterally extending portion 302E or 304E to reduce Heat carrier injection on the drain side. The n+ laterally extending portions 302E and 304E terminate in the channel region 306 along the upper semiconductor surface.

One of the p-type upper body material portions 318 extends the heavily doped ring pocket portions 320 and 322 along the S/D regions 302 and 304, respectively, in a symmetrical manner. The p+ hoop pockets 320 and 322 extend primarily along the n+ S/D extensions 302E and 304E. In the example of FIG. 29, p+ pockets 320 and 322 extend deeper below the upper semiconductor surface than n+ extensions 302E and 304E, but are not as deep as n++ main drain portions 302M and 304M. Item 324 is above the body material portion 318 that is moderately doped with the p-type remainder.

A gate dielectric layer 326 overlies the channel region 306. One gate The pole 328 is a gate dielectric layer 326 located above the channel region 306. The gate electrode 328 extends partially over each of the lateral S/D extensions 302E or 304E. In the example of Figure 29, the gate electrode 328 is composed of a very heavily doped n-type polyfluorene. A pair of electrically insulating sidewall spacers 330 and 332 are positioned along opposite lateral sidewalls of the n++ gate electrode 328. Metal telluride layers 334, 336 and 338 are located on top of S/D regions 302 and 304 and gate electrode 328, respectively.

In accordance with the formation of the p-lower body material portion 214, the symmetric p-channel IGFET 240 is substantially identical to the IGFET 230 and the conductive pattern is reversed. IGFET 240 thus has a pair of p-type S/D regions 342 and 344 separated by an n-type channel region 346 of n-type body material 348, which consists of a heavily doped well 356 and an upper portion 358. . S/D zones 342 and 344 and channel zone 346 are located on island 208. Each p-type S/D region 342 or 344 is comprised of a very heavily doped main portion 342M or 344M and a lightly doped (but still heavily doped) laterally extending portion 342E or 344E to Reduce the heat carrier injection on the drain side. The p+ laterally extending portions 342E and 344E terminate in the channel region 346 along the upper semiconductor surface.

One of the n-type upper body material portions 358 extends the heavily doped ring pocket portions 360 and 362 along the S/D regions 342 and 344, respectively, in a symmetrical manner. The n+ loop pocket portions 360 and 362 extend primarily along the S/D extensions 342E and 344E. In the example of FIG. 29, n+ pockets 360 and 362 extend deeper below the upper semiconductor surface than n+ extensions 342E and 344E, but are not as deep as n++ main S/D portions 342M and 344M. Item 364 is an upper doped n-type remainder of the upper body material portion 358.

A gate dielectric layer 366 overlies the channel region 346. A gate electrode 368 is a gate dielectric layer 366 located above the channel region 346. The gate electrode 368 extends partially over each of the S/D extensions 342E or 344E. In the example of Figure 29, the gate electrode 368 is composed of a very heavily doped p-type polyfluorene. A pair of electrically insulating sidewall spacers 370 and 372 are positioned along opposite lateral sidewalls of p++ gate electrode 368. Metal telluride layers 374, 376 and 378 are located on top of S/D regions 342 and 344 and gate electrode 368, respectively.

The gate dielectric layers 126, 286, 326, and 366 of IGFETs 210, 220, 230, and 240 are typically composed primarily of hafnium oxide, but may be composed of hafnium oxynitride and/or other high dielectric constant dielectric materials. . The thickness of the dielectric layers 126, 286, 326, and 366 is typically 2 to 8 nanometers (nm), preferably 3 to 5 nm, and is typically 3.5 nm for operation across the 1.8 volt range. The thickness of the dielectric layer is suitably increased for operation across a higher voltage range, or is suitably reduced for operation across a lower voltage range. The sidewall spacers 250, 252, 290, 292, 330, 332, 370, and 372 are generally rough in shape, as they have a right-angled triangle with a convex beveled edge and are illustrated in Figure 29, but may have other shapes. The telluride layers 254, 256, 258, 294, 296, 298, 334, 336, 338, 374, 376 and 378 are typically composed of cobalt telluride.

The channel regions 306 and 346 of IGFETs 230 and 240 have a symmetrical longitudinal doping dose curve similar to that of Figure 2 for the symmetric IGFET 20 of FIG. The p+ loop pockets 320 and 322 of the passage zone 306 There is a reduction in threshold voltage attenuation and to help avoid penetration of IGFET 230. The presence of the n+ loop pockets 360 and 362 in the channel region 346 is similar to mitigate the threshold voltage attenuation and to help avoid penetration of the IGFET 240.

The vertical doping dose curves through the respective n++ main S/D portions 302M and 304M of IGFET 230 and to the underlying p-type body material 308 are similar to those shown for Figure IG for IGFET 20 and are also similar to the following The reference doping dose curves for the computer simulations shown in Figures 40, 44a and 44b are discussed. Similarly, the vertical doping dose curve applied to each of the p++ main S/D portions 342M and 344M through the IGFET 240 and to the lower n-type body material 348 is formed in the p-lower portion 114 according to the body material 348. Instead of a lightly doped n-type single 合并 merged into the lower layer. The intermediate (but elevated) concentration of the p-type dopant of the IGFET 230 to the upper body material portion 324 is co-operating with the heavy p-type dopant concentration provided by the ring pocket portions 320 and 322. Prevention of penetration occurs at IGFET 230. The corresponding doping of the body material portion 364 and the ring pocket portions 360 and 362 above the IGFET 240 is similar to avoid penetration.

As with the maximum concentration of the p-type well dopant defining the well 116 of the IGFET 210, the p-type well dopant defining the well 316 is typically about the same depth below the upper semiconductor surface to a maximum concentration. . Since the concentration of N _I-based p-type background dopant is relatively uniform, as the maximum concentration of the well IGFET 210 of the total p-type dopant 116, the maximum of IGFET 230 in the well 316 of the total p-type dopant of The concentration is typically about the same depth that occurs below the upper surface. The upper body material portion 318 of the IGFET 230 is provided with a p-type anti-penetration (APT) dopant to raise the upper portion 318 to a moderately p-type doping level. The p-type APT dopant in the upper body material portion 318 has a smaller depth below the upper semiconductor surface than the maximum concentration of the p-type well dopant of the well 316 to a maximum concentration.

The combination of the total p-type dopant (ie, p-type well, APT and background dopant) of the bulk material 308 underneath the n++ main S/D portion 302M or 304M is part of the bulk material The concentration N _T of the total p-type dopant is relatively flat along a subsurface position of its maximum p-type dopant concentration from the well 316 extending up to one of the vertical lines of the main S/D portion 302M or 304M. In particular, those portions of body material 308 below in main S / D portion 302M or 304M of the total p-type dopant concentration of the N _T is moved upward from the position of the maximum p-type dopant concentration in well portion 316 to Portion 302M or 304M typically varies (decreases) to greater than 10% and typically greater than 5%.

The same applies to IGFET 240. As with the maximum concentration of the n-type well dopant defining the well 276 of the IGFET 220, the n-type well dopant defining the well 356 of the IGFET 240 is typically about the same depth below the upper semiconductor surface. A maximum concentration is reached. As with the maximum concentration of the total n-type dopant of the well 276 of the IGFET 220, the maximum concentration of the total n-type dopant at the well 356 of the IGFET 240 is thus typically about the same depth that occurs below the upper surface. . The upper body material portion 358 of the IGFET 240 provides an n-type APT dopant to raise the upper portion 358 to a moderate n-type doping level. The n-type APT dopant in the upper body material portion 358 has a smaller depth below the upper semiconductor surface than the maximum concentration of the n-type well dopant of the well 356 to reach a maximum concentration.

The total n-type dopant (ie, mainly n-type well and APT dopant) in the bulk material 348 portion below the S/D region 342M or 344M is the total n of the bulk material portion The concentration of the dopant, N _{T ,} is relatively flat along a subsurface position extending from the maximum n-type dopant concentration of the well 356 to a vertical line of the main S/D portion 342M or 344M. Specifically, the concentration of those portions of body material 348 below in main S / D portion 342M or 344M of the total n-type dopant based on the N _T moves upward from the well portion 356 of the maximum n-type dopant concentration The position is typically changed to greater than 10%, typically greater than 5%, to portion 342M or 344M.

It is true that the ring pocket portions 120 and 280 of the individual IGFETs 210 and 220 can be replaced with a deeper extension below the upper semiconductor surface than the individual source 102 and drain 262. IGFET 210 is implemented as IGFET 150 of Figure 13, and IGFET 220 is implemented in one p-channel form of IGFET 150V. The ring pocket portions 320 and 322 of the n-channel IGFET 230 may extend deeper below the upper semiconductor surface than the S/D regions 302 and 304, as occurs in the computer analog reference short channel configuration B of FIG. . The ring pocket portions 360 and 362 of the p-channel IGFET 240 can likewise extend deeper below the upper semiconductor surface than the S/D regions 340 and 342.

Figures 30.1 and 30.2 (collectively "Figure 30") depict two portions of another complementary IGFET semiconductor construction constructed in accordance with the present invention to be particularly suitable for mixed signal applications. The complementary IGFET structure of Figure 30 includes an asymmetric p-channel IGFET 220 and an asymmetric long n-channel IGFET 380 that are identical to the asymmetric n-channel IGFET 210 except that a heavily doped n-type subsurface 382 is in the p+ Between the well 116 and the p-lower 114 to isolate the p+ well 116 from the p-type upper body material portion 118 from the p-lower portion 114. As a result, the p-type body material 108 for the IGFET 380 does not include the p-lower portion 114 but consists solely of the p+ well 116 and the p-type upper body material portion 118.

The complementary IGFET configuration of FIG. 30 further includes a symmetric p-channel IGFET 240 and a symmetric long n-channel IGFET 390 that are identical to the symmetric n-channel IGFET 230 except that a heavily doped n-type sub-surface layer 392 is located at p+ well 316. Between the p-lower portion 114, the p+ well 316 and the p-type upper body material portion 318 are isolated from the p-lower portion 114. The p-type body material 308 for the IGFET 390 thus does not include the p-lower portion 114 but only consists of the p+ well 316 and the p-type upper body material portion 318. In addition to n+ subsurface layers 382 and 392, n-channel IGFETs 380 and 390 operate the same as n-channel IGFETs 210 and 230, respectively.

Circuit components other than IGFETs 210, 220, 230, 240, 380, and 390 can be provided in other portions of the complementary IGFET configuration of FIG. 29 or 30 (not shown). For example, the short channel form of IGFETs 210, 220, 230, 240, 380, and 390 can exist in any of the complementary IGFET configurations. Bipolar transistors and various types of resistors, capacitors, and/or inductors can be provided in the complementary IGFET configuration of FIG. 29 or 30. Depending on the nature of the additional circuit components, suitable electrical isolation is also provided for any complementary IGFET configuration for the additional components. Admittedly, in some purely analog complementary IGFET configurations, IGFET 240 and 230 or 390 can be removed.

Fabrication of complementary IGFET structures for mixed-signal applications

31a to 31o, 31p.1 to 31r.1, and Figs. 31p.2 to 31.r2 (collectively "Fig. 31") illustrate a semiconductor process according to the present invention, A complementary IGFET semiconductor construction comprising long channel IGFETs 210, 220, 230, and 240 as summarized in FIG. 29 is fabricated. The steps involved in the fabrication of IGFETs 210, 220, 230, and 240 are shown in Figures 31a through 31o until the stage prior to the creation of gate sidewall spacers 250, 252, 290, 292, 330, 332, 370, and 372. Figures 31p.1 through 31r.1 illustrate the fabrication of spacers 250, 252, 290, and 292 and the subsequent steps that result in IGFETs 210 and 220 as depicted in Figure 29.1. Figures 31p.2 through 31.r2 illustrate the fabrication of spacers 330, 332, 370 and 372 and the subsequent steps leading to IGFETs 230 and 240 as shown in Figure 29.2.

The short channel form of IGFETs 210, 220, 230, and 240 can be fabricated simultaneously according to the manufacturing steps that are used to fabricate long channel IGFETs 210, 220, 230, and 240. The short channel IGFETs are smaller channel lengths than the long channel IGFETs 210, 220, 230, and 240, but are otherwise similar to the intermediate IGFET appearance shown in FIG. Simultaneous fabrication of long channel IGFETs 210, 220, 230 and 240 and their short channel forms is carried out by means of a mask (optical mesh) having a pattern for long channel and short channel IGFETs.

Except for the pocket portion (including the ring pocket portion) ion implantation step and the source/drain extension portion ion implantation step, all of the ion implantation steps of this process are roughly perpendicular to the lower semiconductor surface and thus are summarized It is carried out perpendicular to the upper semiconductor surface. More particularly, all implant steps except the pocket and source/drain extension ion implantation steps are performed at a small angle to one of the vertical lines, typically 7 degrees. This small deviation from the verticality is used to avoid undesirable ion channel effects. For simplicity, the small verticality The deviation is not indicated in Figure 31.

Unless otherwise indicated, the species of each n-type ion implanted n-type dopant utilized in the process of Figure 31 consists of a specified n-type dopant in elemental form. That is, each n-type ion implantation is performed with ions that specify ions of the n-type dopant element rather than the compound of the compound containing the n-type dopant. The species of p-type dopant used in each p-type ion implantation is composed of a p-type dopant (usually boron) in the form of an element or a compound. Therefore, each p-type ion implantation is usually carried out with ions of boron ions or with a boron-containing compound (boron difluoride).

In some of the fabrication steps of Figure 31, the opening (substantially) extends through a photoresist mask over its active semiconductor regions for the two IGFETs. When the two IGFETs are formed in the cross section of Fig. 31 to be laterally adjacent to each other, the two photoresist openings are illustrated as a single opening in Fig. 31, even though it may be described below as a separate opening.

The letter "P" at the end of a reference symbol appearing in the diagram of Fig. 31 indicates a precursor (precursor) for one of the regions identified in Fig. 29 for which it is shown in Fig. 29 and which is a portion of the reference symbol preceding "P". ). When the precursor system has been fully developed to form most of the corresponding regions of Fig. 29, the letter "P" is removed from the reference symbol of the pattern of Fig. 31.

The starting point for the process of FIG. 31 is typically a mono-semiconductor body consisting of a heavily doped p-type substrate 400 and an upper layer of lightly doped p-type epitaxial layer 114P. Referring to Fig. 31a, the p+ substrate 400 is a semiconductor wafer by which boron is doped to a concentration of about 5 x 10 ¹⁸ atoms/cm 3 to achieve a typical resistivity of 0.015 ohm-cm (Ω-cm). <100> formed by a single unit. For simplicity, substrate 400 is not shown in the remainder of FIG. Alternatively, the starting point may simply be a p-type substrate that is lightly doped substantially the same as the p- epitaxial layer 114P.

The epitaxial layer 114P is composed of an epitaxially grown <100> single germanium, which is lightly doped with boron to a concentration of about 5×10 ¹⁵ atoms/cm 3 for boron to achieve a typical 5 ohm-cm. Resistivity. The thickness of the epitaxial layer 114P is typically 5.5 microns. When the starting point for the process of Figure 31 is a lightly doped p-type substrate, item 114P is a p-substrate.

Field insulating region 200 is provided along the upper surface of p- epitaxial layer (or p-substrate) 114P, as shown in FIG. 31b, thereby being defined from left to right of FIG. 31b for IGFETs 210, 220, 230, respectively. Active semiconductor islands 202, 204, 206, and 208 of 240. Field insulator 200 is preferably fabricated in accordance with a trench oxide technique, but may be fabricated in accordance with a partial oxidation technique. To provide the field insulation 200, one of the thin barrier insulating layers 402 of yttria is thermally grown along the upper surface of the epitaxial layer 114P.

A photoresist mask 404 having an opening above the island portions 202 and 206 is formed over the shield oxide layer 402, as shown in Figure 31c. The p-type well dopant consisting of boron species is at a heavy dose and high energy while ion implantation is through the uncovered portion of the shield oxide 402 and to the underlying monolayer to define (a) for IGFET 210 The p+ well 116 and (b) are directed to the p+ precursor well 316P of the IGFET 230. Portions of epitaxial layer 114P above well 116 constitute a p-precursor upper body material portion 118P for IGFET 210. The photoresist 404 is removed.

a photoresist mask 406 having an opening above the island portion 206 Formed in the shield oxide 402. See: Figure 31d. The p-type APT dopant consisting of boron species is at a moderate dose while ion implantation is through the uncovered portion of the shield oxide 402 and to the underlying monolayer to define the p precursor precursor body material for the IGFET 230. Part 324P. The photoresist 406 is removed.

A photoresist mask 408 having an opening above the island portions 204 and 208 is formed over the shield oxide 402, as shown in Figure 31e. An n-type well dopant consisting of phosphorus or arsenic is applied at a heavy dose and high energy while ion implantation is through an uncovered segment of the shield oxide 402 and to a single layer of the underlying layer to define (a) for the IGFET 220 n+ well 276 and (b) are directed to n+ precursor well 356P of IGFET 240.

As the photoresist mask 408 is positioned, an n-type compensating dopant consisting of phosphorus or arsenic is also applied to the light dose and medium energy and ion implanted through the oxide 402 above the island 204. The segment is not covered and to the underlying monolayer to define it for one of the n-precursor upper body material portions 278P of the IGFET 220. The n-precursor body material portion 278P overlies the n+ well 276 as it exists at the stage of Figure 31e. The dose and implant energy of the n-type compensating dopant implant is typically sufficient to allow all of the precursor body material portion 278P to be n-type conductive.

The n-type compensating dopant also passes through the uncovered segments of the oxide 402 above the island 208 and to its single turn for the underlying layers of the IGFET 240. Any of the two n-type doping operations using photoresist 408 can be performed first. The photoresist 408 is removed. If it is desired that the single germanium for IGFET 240 does not receive any n-type compensating dopants, the n-type compensating doping operation may be over the island portion 204 without being above the island portion 208 (and also Not at islands 202 and 206 One of the openings above is attached to the photoresist mask, and then the additional photoresist is removed.

During subsequent fabrication steps, some of the n-type well dopants used to define the n+ well 276 for the IGFET 220 are diffused upwardly to the semiconductor material above the n+ well 276 as it exists. This point of the process of Figure 29. That is, part of the n-type well dopant diffuses upward to the upper layer material of the island portion 204 where it is initially doped with a mild p-type. The upward diffusion of the portion of the n-type well dopant defining the n+ well 276 occurs primarily during subsequent manufacturing steps that are performed at elevated temperatures (ie, temperatures significantly greater than room temperature).

Depending on various factors, it is mainly the summing effect of (a) the period of the elevated temperature of the subsequent manufacturing steps and (b) the temperature parameter by which the temperature is increased to facilitate the diffusion of the dopant. The upwardly-diffusing portion of the n-type well dopant defining the n+ well 276 may be distributed throughout the island portion 204 of the IGFET 220 such that the counter-doping is present throughout the island 204. Ignoring any other dopants that are subsequently introduced to the island 204, this upwardly diffusing portion of the n-type well dopant can cause all of the islands 204 to be converted to n-type conductivity. In this case, sometimes the step of implanting the n-type compensating dopant can be eliminated to simplify the process and reduce manufacturing costs. Two variants of the process of Figure 31 are described in Figures 32a through 32c and Figures 33a through 33c below, wherein the step of implanting the n-type compensating dopant is removed.

During subsequent fabrication, some of the n-type well dopants used to define the n+ well 356P for IGFET 240 also diffuse upwardly to the semiconductor material above the n+ well 356P as if it were present Figure 29 This point of the process. However, as discussed below, all of the island portions 208 for IGFET 240 are n-type conductivity at the end of ion implantation and associated activation of the n-type APT dopant introduced into island portion 208. Thus, the decision to retain or remove the n-type compensating implant is determined by its application to the subsequent manufacturing steps for the island portion 204 of the IGFET 220.

A photoresist mask 410 having an opening above the island portion 208 is formed on the shield oxide 402. See: Figure 31f. An n-type APT dopant consisting of phosphorus or arsenic is applied at a moderate dose while ion implantation is through an uncovered portion of the shield oxide 402 and to a single layer of the underlying layer to define one of its precursors for IGFET 240. Upper body material portion 358P. The photoresist 410 is removed.

A thermal anneal such as a rapid thermal anneal (RTA) can be applied to the resulting semiconductor substrate to repair lattice damage and place the implanted p-type and n-type dopants more energy-stable. status. See: Figure 31g. The upper semiconductor surface is clean. A dielectric layer 412 containing a gate dielectric is provided along the upper semiconductor surface, as shown in Figure 31h. Dielectric layer 412 is fabricated by a thermal growth technique.

The precursor gate electrodes 128P, 288P, 328P, and 368P are formed on their dielectric layers 412 containing gate dielectrics above the segments of the upper body material portions 118P, 278P, 318P, and 358P, respectively. See: Figure 31i. The precursor gate electrodes 128P, 288P, 328P, and 368P are formed by depositing a majority of an undoped (essential) layer of polysilicon on the dielectric layer 412 and then patterning the polysilicon. Portions of dielectric layer 412 disposed under precursor gate electrodes 128P, 288P, 328P, and 368P form gate dielectric layers 126, 286, 326, and 366, respectively. Formed by gate dielectric layers 126, 286, 326, and 366 The gate dielectric material is summarized as separating the gate electrodes 128P, 288P, 328P, and 368P and their body material segments intended to be separate channel regions 106, 266, 306, and 346, respectively.

A dielectric sealing layer 414 is thermally grown along the exposed surfaces of the precursor gate electrodes 128P, 288P, 328P and 368P. See again: Figure 31i. During the formation of the dielectric sealing layer 414, portions of the dielectric layer 412 located on the sides of the gate dielectric layers 126, 286, 326, and 366 are somewhat thickened to form a composite surface dielectric layer 416.

A photoresist mask 418 having an opening generally above its intended location for the p+ pocket portion 120 of the IGFET 210 is formed over the dielectric layers 414 and 416. See: Figure 31j. The photoresist 418 is strictly aligned to the precursor gate electrode 128P. The p-type pocket dopant consisting of boron species is ion implanted at a moderate dose in an oblique manner through an uncovered portion of the surface dielectric layer 416 and to a single layer of the underlying layer to define One of the IGFETs 210 is a p+ precursor pocket portion 120P. P-pocket implantation is typically performed at two opposite angles of inclination to the vertical. Alternatively, the p-bag portion can be implanted at a single angle of inclination. The photoresist 418 is removed.

A photoresist mask 420 having an opening outlined above its intended location for the n+ pocket portion 280 of the IGFET 220 is formed over the dielectric layers 414 and 416. See: Figure 31k. The photoresist 420 is strictly aligned with the precursor gate electrode 288P. An n-type pocket dopant consisting of phosphorus or arsenic is ion implanted at an oblique dose in a heavily dosed manner through an uncovered portion of the surface dielectric 416 and to a single layer of the underlying layer to define it for the IGFET One of the 220 n+ front pocket portions 280P. The n-type pocket implant is usually implemented at two opposite tilt angles. However, it can be implemented at a single angle of inclination. The photoresist 420 is removed.

A photoresist mask 422 having openings above the island portions 202 and 206 is formed over the dielectric layers 414 and 416, as shown in FIG. 31. An n-type source/drain extension dopant consisting of arsenic or phosphorus is applied at a heavy dose while ion implantation is through a non-covered portion of the surface dielectric 416 and to a single layer of the underlying layer to define (a) For n+ precursor source extension 102EP of IGFET 210, (b) separate n+ precursor drain extensions 104EP for one of IGFETs 210, and (c) side-separated n+ precursors for one of IGFETs 230 Source/drain extensions 302EP and 304EP. The photoresist 422 is removed.

A photoresist mask 424 having an opening above the island 206 is formed over the dielectric layers 414 and 416. See: Figure 31m. A p-type ring dopant composed of a boron species is ion implanted at an oblique dose in a heavily dosed manner through an uncovered portion of the surface dielectric 416 and to a single layer of the underlying layer to define it for the IGFET 230 One pair of laterally split p-type precursor ring pocket portions 320P and 322P. The photoresist 424 is removed.

A photoresist mask 426 having openings above the island portions 204 and 208 is formed over the dielectric layers 414 and 416, as shown in FIG. 31n. The p-type source/drain extension dopant consisting of boron species is at a heavy dose while ion implantation is through the uncovered portion of surface oxide 416 and to the underlying monolayer to define (a) for One of the IGFETs 220 is a p+ precursor source extension 262EP, (b) is a separate p+ precursor drain extension 264EP for one of the IGFETs 220, and (c) is a laterally separated p+ precursor source for one of the IGFETs 240. / bungee extensions 342EP and 344EP. The photoresist 426 is removed.

a photoresist mask 428 having an opening above the island portion 208 Dielectric layers 414 and 416 are formed. See: Figure 31o. An n+ loop dopant consisting of phosphorus or arsenic is ion implanted at a severe dose in a heavily dosed area through an uncovered portion of the surface dielectric 416 and to a single layer of the underlying layer to define it for the IGFET One pair of 240 pairs of laterally separated n+ precursor ring pocket portions 360P and 362P. The photoresist 428 is removed.

A low temperature furnace anneal can be performed at this point to remove defects caused by the heavy dose implanted by the source/drain extension.

In the remainder of the process of Figure 31, the complementary IGFET construction at each processing stage is illustrated by a pair of graphs "31z.1" and "31z.2", where the "z" series varies from "p" to "r" "One of the letters. Each of Figures 31z.1 illustrates the process of making asymmetric IGFETs 210 and 220, and each of Figures 31z.2 illustrates the simultaneous processing to form symmetric IGFETs 230 and 240. For convenience, the pairs 31z.1 and 31z.2 of each pair are collectively referred to below as "Fig. 31.z". For example, Figures 31p.1 and 31p.2 are collectively referred to as "Figure 31.p."

Gate sidewall spacers 250, 252, 290, 292, 330, 332, 370 and 372 are formed along lateral sidewalls of precursor gate electrodes 128P, 288P, 328P and 368P, as shown in Figure 31p. The sidewall spacers 250, 252, 290, 292, 330, 332, 370, and 372 are formed by depositing a dielectric material on top of the construction and then removing it from the intention to form spacers 250, 252, 290, 292, The dielectric materials of 330, 332, 370, and 372 are implemented, and the removal is primarily an anisotropic etch performed by their normal perpendicular to the upper semiconductor surface. Portions of dielectric layers 414 and 416 are also partially, but not entirely, removed. Items 430 and 432 of FIG. 31p refer to dielectric layers 414 that are not covered by spacers 250, 252, 290, 292, 330, 332, 370, and 372, respectively. With the remainder of 416.

A photoresist mask 434 having openings above the island portions 202 and 206 is formed over the dielectric layers 430 and 432 and the spacers 290, 292, 370 and 372. See: Figure 31q. The n-type main source/drain dopant consisting of arsenic or antimony is at a very heavy dose and ion implanted as a single pass through the uncovered portion of the surface dielectric layer 432 and to the underlying layer to define (a) The n++ main source portion 102M and n++ main drain portion 104M for IGFET 210, and (b) the n++ main S/D portions 302M and 304M for IGFET 230. The n-type main source/drain dopant system also enters precursor electrodes 128P and 328P to convert them to n++ gate electrodes 128 and 328, respectively. The photoresist 434 is removed.

The portions of the regions 102EP, 104EP, and 120P on the outer sides of the main S/D portions 102M and 104M respectively constitute an n+ source extension portion 102E, an n+ drain extension portion 104E, and a p+ pocket portion 120 for the IGFET 210. The p-upper body material remaining 124 is the remaining lightly doped material of the precursor upper body material portion 118P (here, the p-type upper body material portion 118). Portions of the regions 302EP, 304EP, 320P, and 322P on the outer sides of the main S/D portions 302M and 304M respectively constitute n+ S/D extension portions 302E and 304E and p+ ring pocket portions 320 and 322 for the IGFET 230. The remaining 324 of the upper body material is the remaining lightly doped p-type material of the upper body material portion 318P (here, the p-type upper body material portion 318).

When the primary source/drain dopant is composed of arsenic, a thermal anneal can be performed to repair the lattice damage, activate the primary n-type source/drain dopant, and cause it to diffuse outward. This annealing (usually an RTA) also activates the pocket and source / Bipolar extension part of the dopant.

A photoresist mask 436 having openings above the island portions 204 and 208 is formed over the dielectric layers 430 and 432 and the spacers 250, 252, 330, and 332, as shown in FIG. 31r. The p-type main source/drain dopant consisting of boron species is at a very heavy dose while ion implantation is through the uncovered portion of the surface dielectric layer 432 and to the underlying monolayer to define (a) The p++ main source portion 262M and the p++ main drain portion 264M of the IGFET 220, and (b) the p++ main S/D portions 342M and 344M for the IGFET 240. The p-type main source/drain dopant also enters precursor electrodes 288P and 368P to convert them to p++ gate electrodes 288 and 368, respectively. The photoresist 436 is removed.

Portions 262EP, 264EP, and 280P on the outer sides of the main S/D portions 262M and 264M respectively constitute a p+ source extension portion 262E, a p+ drain extension portion 264E, and an n+ pocket portion 280 for the IGFET 220. The remaining lightly doped n-type material of n-upper body material remaining 284 is n-upper body material portion 278P (here, n-type upper body material portion 278). Portions of the regions 342EP, 344EP, 360P, and 362P on the outer sides of the main S/D portions 342M and 344M respectively constitute p+ S/D extension portions 342E and 344E and n+ ring pocket portions 360 and 362 for the IGFET 240. The remaining upper portion of the upper body material 364 is the remaining lightly doped n-type material of the n-precursor upper body material portion 358P (here, the n-type upper body material portion 358).

A cover layer (not shown), typically a dielectric material of yttria, is formed on top of the construction. The semiconductor construction is then thermally annealed to repair lattice damage and activate the implanted primary p-type source/drain dopant. If it is used to activate the main An earlier anneal of the n-type source/drain dopant is not performed, and the final anneal is to activate the pocket dopant and all of the source/drain dopant. The final anneal is typically an RTA.

A thin layer of dielectric material (including dielectric layers 430 and 432) is removed along the upper semiconductor surface and along the top surface of gate electrodes 128, 288, 328, and 368. Metal telluride layers 254, 256, 258, 294, 296, 298, 334, 336, 338, 374, 376 and 378 are along regions 102M, 104M, 128, 262M, 264M, 288, 302M, 304M, 328, respectively. Formed on the upper surface of 342M, 344M and 368. This typically requires the deposition of a thin layer of a suitable material (typically cobalt) on the surface of the construction and a low temperature step to chemically react the metal with the underlying crucible. Remove metal that has not been chemically reacted. A second low temperature step is performed to complete the chemical reaction of the metal with the underlying germanium, and thereby form the vaporized layers 254, 256, 258, 294, 296, 298, 334, 336, 338, 374, 376 and 378. Metal halide formation completes the basic fabrication of IGFETs 210, 220, 230, and 240. The resultant complementary IGFET construction is presented as shown in Figure 29.

The implementation of the p-type well, p-type APT, n-type well, n-type compensation, and n-type APT of Figures 31c to 31f can be summarized as being performed in any order. The implementation of the p-type pocket, the n-type pocket, the n-type source/drain extension, the p-ring, the p-type source/drain extension and the n-ring of Figures 31j to 31o can be summarized as In any order. The n-type main source/drain implementation of Figure 31q is typically performed prior to the implementation of the p-type main source/drain of Figure 31r, especially when the main source/drain dopant is composed of arsenic. Time. However, the implementation of the p-type main source/drain is sometimes implemented in the n-type main source/drain Executed before.

The tilt angles for the p-bag portion, the n-type pocket portion, the p-ring and the n-ring of FIGS. 31j, 31k, 31m, and 31o are usually at least 15 degrees. Although the variation is typically implemented from one bevel to the other, typically 25 to 45 degrees for each bevel.

The complementary IGFET configuration of Figure 30 is typically fabricated in accordance with substantially the same steps as the complementary IGFET configuration of Figure 29, except that it converts IGFETs 210 and 230 to n+ isolation layers 382 and 392 of IGFETs 380 and 390, respectively. Isolation layers 382 and 392 are typically formed between the stages of Figures 31b and 31c, with their own photoresist mask attached to one of the openings above islands 202 and 206. The additional photoresist mask also has openings for heavily doped n-type regions that connect isolation layers 382 and 392 to the upper semiconductor surface to receive a suitable isolation voltage. An isolating dopant consisting of arsenic or phosphorus is applied at a heavy dose while ion implantation is through an uncovered segment of the shield oxide 402 and as a single layer of the underlying layer to define (a) n+ for IGFETs 380 and 390, respectively. The isolation layers 382 and 392 and the (b)n+ isolation layer connection regions.

The process of Figure 31 can be modified as described below to change the asymmetric n-channel IGFET 210 from one implementation of the IGFET 180 to the implementation of the asymmetric n-channel IGFET 190 of Figure 18c, wherein the n-type S/D region 102 is The 104 further includes n+ lower S/D portions 102L and 104L, respectively, which are placed under the n++ main S/D portions 102M and 104M, respectively. Since the lower S/D portions 102L and 104L are lightly doped n-type compared to the main S/D portions 102M and 104M, the lower S/D portions 102L and 104L provide source/drain vertical dopant gradients. To further reduce the parasitic capacitance of the source/drain, as The above is described above for IGFET 160 of FIG.

This process modification begins at the stage of Figure 31q and the photoresist mask 434 is positioned for ion implantation of the n++ main S/D portions 102M and 104M. The n-type underlying source/drain dopant consisting of phosphorus or arsenic is at a heavy dose while ion implantation is through the uncovered segment of the surface dielectric layer 432 and to the underlying monolayer to define n+lower S /D sections 102L and 104L. The implantation of the n+ lower S/D portions 102L and 104L may be performed before or after implantation of the n++ primary S/D portions 102M and 104M.

The implantation energy for the dopants of the n-type main and the lower source/drain is selected so that the dopant of the n-type lower source/drain is compared to the n-type main source/drain dopant. And for a larger implant range. Since the implantation of the n-type main source/drain and the implantation of the n-type source/drain are performed only through the surface dielectric layer 432, the dopants of the n-type source/drain are lower. The n-type main source/drain dopant is implanted to a larger average depth below the upper semiconductor surface. Since the n-type main source/drain dopant is implanted in a very heavy dose and therefore a larger dose than the n-type lower source/drain dopant, the n+ lower S/D portion 102L and 104L are lightly doped and extend deeper below the upper semiconductor surface than the n++ main S/D portions 102M and 104M.

The symmetric n-channel IGFET 230 is simultaneously switched to a variator, wherein the n-type S/D regions 302 and 304 respectively include one of the lighter dopings compared to the main S/D portions 302M and 304M. Below the S/D section. As with the n+ lower S/D portions 102L and 104L for the aforementioned variations of the IGFET 210, the lower S/D for the change of the IGFET 230 Part of the system is heavily doped n-type. If it is desired that IGFET 230 be non-switched to have a change in the n+ lower S/D portion, implantation of the n-type lower source/drain dopant can be performed by an additional photoresist mask, the additional The photoresist mask has an opening above the island 202 without being above the island 206 (and also above the islands 204 and 208) after the additional photoresist is removed.

The process of Figure 31 can be similarly modified to change the implementation of an asymmetric p-channel IGFET 220 from a p-channel form of n-channel IGFET 180V to a p-channel form of n-channel IGFET 190V for which p-type S/D Regions 262 and 264 respectively include a pair of heavily doped p-type lower S/D portions respectively placed under p++ main S/D portions 262M and 264M. The lower S/D portion of p+ provides a source/drain vertical dopant ramp to further reduce the source/drain parasitic capacitance, similar to that described above for IGFET 160 of FIG.

This additional process modification begins at the stage of Figure 31r and the photoresist mask 436 is positioned for ion implantation of the p++ main S/D portions 262M and 264M. The p-type underlying source/drain dopant consisting of boron species is at a heavy dose while ion implantation is through the uncovered segment of surface dielectric layer 432 and to the underlying monolayer to define for IGFET 220 The two p+ lower S/D parts of the changer. The implantation of the source/drain under the p+ can be performed before or after the implantation of the p++ main source/dip. In one example, the p-type lower source/drain dopant is composed of elemental boron, and the p-type main source/drain dopant is composed of boron difluoride.

The implantation energy for the dopants of the p-type main source and the lower source/drain is selected so that the dopant of the p-type source/drain is lower than that of the p-type main source/ The dopant of the drain is a larger implant range. Since the p-type main source/drain implant and the p-type lower source/drain implant are performed only through the surface dielectric layer 432, the p-type lower source/drain dopant is compared. The p-type main source/drain dopant is implanted to a larger average depth below the upper semiconductor surface. Since the p-type main source/drain dopant is implanted in a very heavy dose and thus a larger dose than the p-type lower source/drain dopant, for IGFET 220 The S+D portion below the p+ of the variator is lightly doped compared to the p++ main S/D portions 262M and 264M, and extends deeper below the upper semiconductor surface.

The symmetric p-channel IGFET 240 is simultaneously switched to a variator, wherein the p-type S/D regions 362 and 364 respectively include one of the lighter dopings compared to the main S/D portions 362M and 364M. Below the S/D section. As with the p+ lower S/D portion for the change to IGFET 220, the lower S/D portion for the variator of IGFET 240 is heavily doped p-type. If the IGFET 240 is not switched to have a variation of the lower S/D portion, the p-type lower source/drain implant can be implemented by an additional photoresist mask that is attached After the photoresist is removed, there is an opening that is above the island portion 204 and not above the island portion 208 (and also not above the island portions 202 and 206).

Avoid process variations in n-type compensating implants

Figures 32a through 32c (collectively "Figure 32") illustrate an alternative to the steps of Figure 31e in accordance with the present invention for fabricating a variation of the complementary IGFET semiconductor construction of Figure 29. If modified to incorporate the alternative to Figure 32, the application of the n-type compensating implant to the island 204 (with the island 208) is avoided. 31 process. As a result, a variant 220V containing the asymmetric p-channel IGFET 220 is constructed by using a complementary IGFET fabricated by the alternative of FIG.

The alternative to the process of Figure 32 begins with the configuration of Figure 31d, which is repeated here as Figure 32a. The n-type well doping step described above in connection with Figure 31e is carried out in the configuration of Figure 32a. In particular, a photoresist mask 408 is formed over the shield oxide layer 402, as shown in Figure 32b. Photoresist mask 408 also has openings above islands 204 and 208. The n-type well dopant, also composed of phosphorus or arsenic, is tied to a heavy dose and high energy while ion implantation is through the uncovered segment of the shield oxide 402 and as a single layer of the underlying layer to define (a) The precursor n+ well 276P and (b) of the asymmetric p-channel IGFET 220V are directed to the n+ precursor well 356P of the symmetric p-channel IGFET 240.

The n-type compensation implantation by the photoresist 408 to the island portion 204 (and the island portion 208) is not practiced here. Instead, only the photoresist 408 is removed. After removal of the photoresist 408, a lightly doped p-type portion 278Q for the island portion 204 of the IGFET 220V is present above the precursor n+ well 276P. A lightly doped p-type portion 358Q for island portion 208 of IGFET 240 is similarly present above precursor n+ well 356P.

The alternative of FIG. 32 continues to form a photoresist mask 410 over the shield oxide 402. See: Figure 32c. The photoresist mask 410 also has an opening above the island portion 208. An n-type APT dopant, also composed of phosphorus or arsenic, is applied at a moderate dose while ion implantation is through an uncovered segment of the shield oxide 402 and as a single layer of the underlying layer to define an n-precursor for the IGFET 240. Body material portion 358P. The photoresist 410 is removed.

All p-portions of the n-type APT dopant conversion island portion 208 implanted into the island 208 are 358Q to n-type conductivity. As a result, the p-portion 358Q disappears. Since no large amount of n-type APT dopant is entering island portion 204, p-portion 278Q of island portion 204 is still present at this stage of fabrication.

The structure of Fig. 32c is further processed according to the above-described manufacturing steps associated with Figs. 31g to 31o, Figs. 31p.1 to 31r.1, and Figs. 31p-2 to 31r.2, including associated annealing operations. Some of these further steps are carried out at elevated temperatures, again at temperatures significantly greater than room temperature. During the elevated temperature step, the n-type well dopant portion that is utilized to define the pre-drive n+ well 276P for the IGFET 220V is spread upward to the p-portion 278Q. The upwardly diffusing portion of the n-type well dopant is distributed throughout the island portion 204 such that after the n-type well doping step, the p-type and/or n-type doping is not significantly affected by all of its p- The material is converted to n-type conductivity before the end of fabrication. For some of the lighter doped n-types compared to the n-type upper body material portion 278 fabricated entirely in accordance with the basic process of Figure 31, the p-portion 278Q is largely modified to utilize the alternative of Figure 32. An n-type upper body material material 278 of complementary IGFET construction is fabricated in accordance with the process of FIG. The n-upper body material remainder 284 is also the remaining lightly doped n-type material of the n-type body material portion 278.

As a modification to incorporate the alternative of FIG. 32, the complementary IGFET construction made according to the process of FIG. 31 is mostly presented as shown in FIG. A generalized form of an asymmetric p-channel IGFET 220V fabricated using the alternative of FIG. 32 is depicted in FIG. 34 discussed below.

Figures 33a to 33f (collectively "Figure 33") are illustrated for Figures 31c to 31f An alternative to the present invention is a replacement for the fabrication of the complementary IGFET semiconductor construction of FIG. As with the alternative to FIG. 32, the alternative to FIG. 33 avoids the implantation of an n-type compensation to island portion 204 (and island portion 208). As a result, as a modification to incorporate the alternative of FIG. 33, the complementary IGFET construction fabricated in accordance with the process of FIG. 31 includes an asymmetric p-channel IGFET 220V in place of IGFET 220.

The process replacement of Figure 33 begins with a repeat of the configuration of Figure 31b of Figure 33a. At the stage of Figure 33a, the shield oxide layer 402 has been formed along the upper surface of the epitaxial layer 114P. However, no ion implantation to any of islands 202, 204, 206, and 208 has been made.

A photoresist mask 408 having openings above the island portions 204 and 208 is formed over the shield oxide 402, as shown in Figure 33b. The n-type well dopant, also composed of phosphorus or arsenic, is tied to a heavy dose and high energy while ion implantation is through the uncovered segment of the shield oxide 402 and as a single layer of the underlying layer to define (a) The n+ precursor wells 276P and (b) of the IGFET 220V are directed to the n+ precursor well 356P of the IGFET 240. The photoresist 408 is removed. After removal of the photoresist 408, the p-portion 278Q for the island portion 204 of the IGFET 220V is present above the n+ precursor well 276P. The p-portion 358Q for the island portion 208 of the IGFET 240 is similarly present above the n+ precursor well portion 356P.

A thermal anneal, preferably an RTA, is typically performed here on the resulting semiconductor substrate to repair the lattice damage and place the implanted n-type well dopant in a more energy stable state. See: Figure 33c. Used during annealing to define an n-well for the IGFET 220V pre-drive n+ well 276P Some of the dopants are diffused upward to p-portion 278Q. The portion of the n-type well dopant that is utilized to define the n+ well 356P for the IGFET 240 is similarly spread upward to the p-portion 358Q. The upward diffusion of such portions of the n-type well dopant is typically sufficient to convert the lower portion of the p-portions 278Q and 358Q to n-type conductivity. The lower portions of the p-portions 278Q and 358Q so converted are labeled as n-upper body material portions 278P and 358P, respectively, prior to Figure 33c. Due to the formation of the precursor n-upper body material portions 278P and 358P, the p-portions 278Q and 358Q are vertically contracted as indicated generally in Figure 33c.

As further described below, the majority of the n-type well dopants utilized to define the precursor n+ well 276P are diffused upward to the p-portion 278Q during a later step of the process of FIG. 31, as modified To use the alternative of Figure 33. Similar to the alternative of FIG. 32, the total upward diffusion portion of the n-type well dopant in the alternative of FIG. 33 becomes distributed throughout the island portion 204 such that after the n-type well doping step The p-materials that are not significantly p-typed and/or n-doped are converted to n-type conductivity before the end of fabrication. Importantly, the portion of the n-type well dopant diffuses upward to define the precursor n-upper body material portion 278P (as in the stage of Figure 33c) occurs without affecting the p-type well dopant or any APT , pockets, loops, and source/drain dopants, as the steps for introducing their dopants to the semiconductor construction have not been implemented. Therefore, the implementation of the n-type well implant at this stage of the process helps to ensure that all p-materials of the p-type and/or n-doped islands 204 are not finally converted by other (later) p-type and/or n-doped islands 204. To n-type conductivity without causing p-type well dopants or any APT, pocket, ring and source/drain Undesirable diffusion of dopants.

A photoresist mask 410 is formed over the shield oxide 402. See: Figure 33d. Photoresist 410 also has an opening above island portion 208. An n-type APT dopant (composed of phosphorus or arsenic) is applied at a moderate dose while ion implantation is through an uncovered portion of the shield oxide 402 and to a single layer of the underlying layer to define a body above the IGFET 240 Material portion 358P. All p-portions 358Q to n-type conductivity implanted into the n-type APT dopant conversion island portion 208 of the island portion 208, thereby causing the p-portion 358Q to disappear. The photoresist 410 is removed.

A photoresist mask 404 is formed over the shield oxide layer 402 as shown in Figure 33e. Photoresist 404 also has openings above islands 202 and 206. A p-type well dopant (which consists of a boron species) is applied at a heavy dose and high energy while ion implantation is through a non-covered portion of the shield oxide 402 and to a single layer of the underlying layer to define (a) for The p+ well 116 and (b) of the IGFET 210 are directed to the p+ precursor well 316P of the IGFET 230. Portions of the epitaxial layer 114P above the well 116 are also configured to form a p-precursor upper body material portion 118P for the IGFET 210. The photoresist 404 is removed.

A photoresist mask 406 is formed over the shield oxide 402. See: Figure 33f. Photoresist 406 also has an opening above island portion 206. The p-type APT dopant (which is composed of boron species) is at a moderate dose while ion implantation is through the uncovered portion of the shield oxide 402 and to the underlying monolayer to define the p precursor for the IGFET 230. Body material portion 324P. The photoresist 406 is removed.

The structure of Figure 33f is further processed, according to which is associated with Figure 31g The above manufacturing steps of 31o, 31p.1 to 31r.1, and Figs. 31p.2 to 31r.2 include: an associated annealing operation. During a later elevated temperature step, the larger portion of the n-type well dopant that is applied to define the n+ well 276P for the IGFET 220V is spread up to the p-portion 278Q of the island 204 until During the process, all p-materials that are not subjected to other p-type or/and n-type doping are converted to n-type conductivity. In some lightly doped n-types compared to the n-type upper body material portion 278 fabricated entirely in accordance with the basic process of Figure 31, the p-portion 278Q is largely modified to utilize the alternative of Figure 33. The n-type upper body material material 278 of the complementary IGFET configuration is formed by the process of FIG. The n-upper body material remainder 284 is also the remaining lightly doped n-type material of the n-type body material portion 278.

The complementary IGFET construction made according to the process of FIG. 31 using the alternative of FIG. 33 is mostly presented as shown in FIG. The p-channel IGFET depicted in FIG. 34, discussed below, is also a generalized form of IGFET 220V fabricated using the alternative of FIG.

As noted above, the semiconductor portion of p-channel IGFET 220V is formed from a lightly doped p-type material of island portion 204. In order to ensure that all the island p-materials that are not doped with p-type or/and n-type doping during the n-type well doping during the process are converted to n-type conductivity before the end of fabrication, at the end of manufacture The concentration of the n-type well dopant along the upper surface of the island portion 204 must exceed the initial concentration of the p-type dopant of the island portion 204. Since the island portion 204 is formed by a portion of the p- epitaxial layer 114P (or a lightly doped p-type substrate substantially the same as the epitaxial layer 114P), at the end of fabrication, the island portion 204 is n. The upper surface concentration of the well dopant must exceed the p-type background dopant concentration of epitaxial layer 114P.

The doping and heat treatment conditions of one embodiment of the process of FIG. 31, as modified to incorporate the alternative of FIG. 32 or 33, are selected such that the n-type well dopant along the upper surface of island portion 204 at the end of fabrication The concentration is expected to be at least two times the p-type background dopant concentration of epitaxial layer 114P. The doping and heat treatment conditions are selected in this way so that it is highly probable that the upper surface concentration of the n-type well dopant at the end of fabrication will actually exceed the epitaxy at the end of fabrication due to typical process variations. The p-type background dopant concentration of layer 114P. Therefore, the doping and heat treatment conditions may be selected from the above to change the p-type background dopant concentration of the epitaxial layer 114P and/or from the above to change the n-type well doping conditions. These changes are further processed below in connection with Figures 35a to 35c, Figures 36a to 36c, Figures 37a to 37c, and Figures 38a to 38c.

The channel region 266 of the p-channel IGFET 220V is similar (and typically somewhat stronger (larger)) to the above-described one of the p-channel IGFETs 220 and is typically an asymmetric longitudinal dopant gradation. The condition is the inverse of the conductivity pattern, and the asymmetrical longitudinal ramp at channel region 266 of IGFET 220V is therefore similar (and typically somewhat stronger) to the above for IGFETs 180V and 150V.

The p-channel IGFET 220V is similar (but somewhat weaker) to the sub-steep vertical doping dose curve below the drain 264 for the above-described p-channel IGFET 220. In particular, the total n-type dopant of the bulk material 268 under the drain 264 of the IGFET 220V The concentration is reduced from a subsurface position of the maximum concentration of the n-type dopant from the well 276 vertically to the drain 264 to a maximum of 10% (typically up to about 15%), at n of the well 276. The maximum concentration of the dopant is located no more than 10 times deep (typically no more than 5 times) below the surface of the upper semiconductor than the drain 264. Similarly, the condition is the inverse of the conductivity pattern, and the sub-steep vertical doping dose curve below the drain 264 of the IGFET 220V is therefore typically similar (but somewhat weaker) to the n-channel IGFET 180V and 100V. The above. For the reasons discussed below in connection with Figures 38a through 38c, the sub-steep vertical doping dose curve below the drain 264 of IGFET 220V is such that it has an increased analog speed.

In an alternative process embodiment, the p-type background dopant concentration, the n-type well doping condition, and the subsequent heat treatment conditions of the epitaxial layer 114P are adjusted to provide a portion of the body material 268 below the drain 264 of the IGFET 220V. The concentration of the total n-type dopant decreases from the subsurface position of the maximum concentration of the n-type dopant of the well 276 vertically upward to the drain 264 to be greater than 10%. Although the resulting analog speed may not be as steep as the vertical doping dose curve below the drain 264 of the IGFET 220V, manufacturing the IGFET 220V according to this process embodiment simplifies the process and reduces manufacturing costs.

The asymmetric p-channel IGFET 220V can be substituted for the IGFET 220 of the complementary IGFET semiconductor construction of FIG. Except that it converts IGFETs 210 and 230 to n+ isolation layers 382 and 392 of IGFETs 380 and 390, respectively, such modifications of the complementary IGFET configuration of Figure 30 are typically substantially fabricated in accordance with the process of Figure 31, as modified for inclusion. An alternative to Figure 32 or 33. In the alternative to FIG. 32, spacer layers 382 and 392 are also generally formed between the stages of FIGS. 31b and 31c, using the above-described additional photoresist mask having openings above island portions 202 and 206. When the alternative of Figure 33 is utilized, isolation layers 382 and 392 are formed between the stages of Figures 33a and 33b, in the same manner as the alternative of Figure 32. The isolating dopant diffusion that occurs during the thermal anneal performed directly after the n-type well implant using the replacement of Figure 33 is typically a complementary IGFET configuration that is substantially free of damaging effects.

Alternatively to using Figure 32 or 33, the additional photoresist mask also has openings for heavily doped n-type regions that connect isolation layers 382 and 392 to the upper semiconductor surface to receive isolation voltages. An isolating dopant consisting of arsenic or phosphorus is applied at a heavy dose while ion implantation is through an uncovered segment of the shield oxide 402 and as a single layer of the underlying layer to define (a) n+ for IGFETs 380 and 390, respectively. The isolation layers 382 and 392, and (b) the n+ isolation layer connection region.

A p-channel IGFET with a sub-steep vertical bulk material doping dose curve below the drain, due to the subsurface maximum of the well dopant concentration, avoiding the n-type compensating implant

Figure 34 illustrates a generalized form 220U of an asymmetric p-channel IGFET 220V in accordance with the present invention, wherein the n+ well 276 is for the opposite conductivity type of the p-semiconductor material portion 114 placed directly underneath. The IGFET characteristics caused by the asymmetric p-channel IGFET 220U fabricated in accordance with the present invention are not implanted into the n+ well 276 (such as the n-type well dopant) without the use of a compensating n-type dopant. Above the initial definition of the implant) The p-type part of the island 204. Essentially, one implementation of the IGFET 220V IGFET 220U fabricated in accordance with the process of FIG. 31, modified to incorporate the alternative of FIG. 32 or 33.

The p-channel IGFET 220U is comprised of a two-part p-type source 262, a two-part p-type drain 264, an n-type body material 268, a gate dielectric layer 286, and a gate electrode 288. The n-type body material 268 is also formed by an n+ well 276 and an n-type upper body material portion 278. The upper body material portion 278 is comprised of a n+ source side pocket portion 280 and an n-type body material remainder 394. The n-type channel region 266 of the n-type upper body material portion 278 is similarly laterally separating the n-type S/D regions 262 and 264 as well. The components 262, 264, 266, 268, 276, 278, 280, 286 and 288 of IGFET 220U are constructed and doped to be substantially identical to IGFET 220V.

Item 396 of Figure 34 refers to the pn junction between source 262 and body material 268. Item 398 is the pn junction between the drain 264 and the body material 268. Similar to the n-channel IGFET, the terms y _S and y _D are respectively indicating the depth at which the source 262 and the drain 264 of the p-channel IGFET 220U extend below the upper semiconductor surface, respectively.

For simplicity, the n-type upper body material remaining 394 of the IGFET 220U is labeled "n-" in FIG. 34, similar to how the n-type upper body material remaining 284 of the IGFET 220 is identified by the flag "n-". This article. In order to fabricate the IGFET 220U according to the process of FIG. 31 as modified to incorporate the alternative of FIG. 32 or 33, the upper body material remainder 394 is typically n-doped that is received to be substantially only diffused upward by the lower n+ well 276. Miscellaneous. As further explained below in connection with Figures 37a to 37c, the remaining material is left. The n-type dopant concentration of the remainder 394 is generally gradually decreasing from the well portion 276 to the upper semiconductor surface. Since the well 276 is heavily doped n-type, the body material remainder 394 can be considered as a lightly doped n-type surface abutment portion instead of the n+ well 276 and the lightly doped n-type surface instead of the drawing mode. A moderately doped n-type intermediate portion between adjacent portions is formed.

The doping characteristics of IGFET 220U are understood by means of Figures 35a to 35c (collectively "Figure 35"), Figures 36a to 36c (collectively "Figure 36"), Figures 37a to 37c (collectively "Figure 37"), And as shown in Figures 38a to 38c (collectively "Figure 38"). Figure 35 presents an example dopant concentration along the upper surface of the upper body as a function of longitudinal distance x. An exemplary dopant concentration as a function of depth y along a vertical line 130U through source 262 is presented in FIG. 37 presents an exemplary dopant concentration as a function of depth y along one of the transmission channel regions 266 versus the vertical lines 132U and 134U. The vertical line 132U passes through the pocket portion 280 on the source side. The vertical line 134U passes through a vertical position between the pocket portion 280 and the drain 264. An exemplary dopant concentration as a function of one of the depths y across a vertical line 136U of the drain 264 is presented in FIG. Vertical lines 130U, 132U, 134U, and 136U for p-channel IGFET 220U correspond to vertical lines 130, 132, 134, and 136 for the n-channel IGFET of the present invention, respectively.

Figure 35a illustrates the concentration N _I of individual semiconductor dopants along the upper semiconductor surface that primarily define regions 262, 264, 280, and 394 and thus establish a longitudinal dopant gradation of channel region 266. 36a, 37a and 38a illustrate the concentration N _I of individual semiconductor dopants along vertical lines 130U, 132U, 134U and 136U that vertically define regions 114, 262, 264, 270, 280 and 394 and The sub-steep vertical doping dose curve of the portion of the body material 268 that is established below the drain 264 is thus established. Curves 262' and 264' represent the concentration N _I (surface and vertical) of the p-type dopant that is utilized to form source 262 and drain 264, respectively. Curves 276', 280' and 394' represent the concentration N _I (surface and/or vertical) of the n-type dopants that are utilized to form regions 276, 280 and 394, respectively. Items 396 ^# and 398 ^# refer to the net dopant concentration N _N being reduced to zero and thus refer to the positions of pn junctions 396 and 398, respectively.

Along the upper semiconductor surface in areas 262,264,280 and 394 of the total p-type and total n-type dopant concentration of the N _T shown in FIG. 35b. 36b, 37b, and 38b depict the total p-type and total n-type dopant concentration N _T along regions 109, 262, 264, 276, 280, and 394 along vertical lines 130U, 132U, 134U, and 136U. Respectively corresponding to regions 276, 280 and 394 of curve segments 276 ", 280" and 394 "represents the total n-type dopant concentration N _T. Item 266 in FIG. 35b of" corresponds to channel zone 266 and the representative curve segments 280 " Part of the channel area with 394". The total concentration of the p-type dopant from the N _T lines respectively corresponding to source 262 and drain 264 of the curve 262 'and 264 "represent.

Figure 35c illustrates the net dopant concentration N _N along the upper semiconductor surface. The net dopant concentration N _N along the vertical lines 130U, 132U, 134U, and 136U is presented in Figures 36c, 37c, and 38c. Curve segments 276*, 280* and 394* represent the net concentration N _N of the n-type dopants of the individual regions 276, 280 and 394. Item 266* of Figure 35c represents the combination of curve segments 280* and 394* of the channel region, and thus the concentration N _N of the net n-type dopant present in channel region 266. The concentration N _N of the net p-type dopant at source 262 and drain 264 is represented by curves 262* and 264*, respectively.

The upper surface dopant distribution for the p-channel IGFET 220U shown in FIG. 35 is substantially the same as the upper surface dopant distribution shown for FIG. 26 for the n-channel IGFET 180V, except: (a) The background p-type dopant concentration for the p-lower portion 114 as indicated by the curve 114' of Figure 35a is less than the background n-type dopant for the n-lower portion 192 as indicated by item 192' of Figure 26a. Concentration; and (b) the upper surface dopant concentration for the n-upper body material remainder 394 as indicated by items 394', 394" and 394* of Figure 35a is less than item 198' of Figure 26. The upper surface dopant concentration for 198" and 198* for the remaining 198 of the upper body material of p-. Nevertheless, the p-channel IGFET 220U is constructed similarly to the n-channel IGFET 180V. Thus, the arguments described above with respect to the upper surface dopant profile for the n-channel IGFET 180V shown in Figure 26 are mostly applied to the upper surface shown in Figure 35 for the p-channel IGFET 220U. The dopant profile is changed to regions 262, 262M, 262E, 264, 264M for IGFET 220U, respectively, for regions 102, 102M, 102E, 104, 104M, 104E, 106, 120, 192, and 198 for IGFET 180V. , 264E, 266, 280, 114, and 394 and differ in dopant concentration as indicated.

Next consider Figure 37, for processing a dopant concentration N _I, N _T and N _N along vertical lines 132U and 134U via the channel region of the p-channel IGFET 220U 266. This bracket "132U" will indicate the dopant concentration along the vertical line 132U at each of the reference symbols 280', 280" and 280*. This bracket "134U" will indicate along the respective reference symbols 394', 394" and 394*. The dopant concentration of the vertical line 134U. The n-type dopant of the n+ pocket portion 280 is comprised of: (a) a major portion of the n-type pocket dopant as indicated by the dopant concentration curve 280' of FIG. 37a; (b) A minor portion of the upwardly diffusing portion of the n-type well dopant as indicated by the dopant concentration curve 276' of Figure 37a. The n-type dopant of the n-upper body material remainder 394 is essentially composed of only the upwardly diffusing portion of the n-type well dopant. The concentration N _I of the upwardly diffusing portion of the n-type well dopant of the n-body material remainder 394 is indicated by a portion 394' of the n-type well dopant concentration curve 276' of Figure 37a. The dopant concentration curves 276" and 276*, respectively, of portions 394" and 394* of Figures 37b and 37c are similar to indicate the total dopant concentration _Nt and net doping of the n-body material remainder 394, respectively. Agent concentration N _N .

Since the pocket portion 280 on the source side of the IGFET 220U is heavily doped n-type and the n-type doping of the remaining 394 of the n-upper body material is substantially only provided by the upward diffusion from the n+ well 276, in the channel region The lowest dopant concentration of 266 occurs at or near the upper surface of the n-body material remainder 394, depending on whether any significant amount of the up-diffusion portion of the n-type well dopant is stacked along The remaining 394 depends on the surface. Figure 37 illustrates an example in which there is no significant n-type well dopant buildup along the upper surface of the n-body material remainder 394.

As described above, the p-channel IGFET of the island portion 204 formed by the portion of the semiconductor portion which is formed by the portion of the curved p- epitaxial layer 114P (or a p-type substrate which is substantially the same as the lightly doped epitaxial layer 114P) is formed. For the fabrication of 220V, the n-type well dopant concentration along the upper surface of island 204 at the end of fabrication must exceed the p-type background dopant concentration of epitaxial layer 114P. Applied to IGFET 220U, the n-type well dopant concentration N _I of the upper surface of the doped demand conversion channel region 266 (specifically, the upper surface of the n-upper body material remainder 394) is greater than p - p-type background dopant concentration N _{I of} lower portion 114. The doping and heat treatment conditions are selected such that the upper surface concentration of the n-type well dopant at the end of the IGFET 220V fabrication is expected to be at least two of the p-type background dopant concentration of the epitaxial layer 114P. In this case, the desired manufacturing target is similarly converted to a structural doping requirement in that the n-type well dopant concentration N _I along the upper surface of the n-body material remaining 394 is at least the p-type background dopant concentration N. _I doubled.

35 through 38 depict an example in which the n-type well dopant concentration N _I along the upper surface of the n-body material remainder 394 (as indicated by the curved segment 394' of Figures 35a and 37a) is approximately (as in FIG. 35a and 37a of curve segments 114 'as indicated) p- region 114 below the p-type dopant concentration of twice the background of N _I. Thus, the examples of Figures 35 through 38 satisfy the doping requirements of a particular configuration: the n-type well dopant concentration N _I along the upper surface of the n-body material remainder 394 is at least the p-type background dopant concentration N _I doubled.

In the examples of Figures 35 through 38, the p-type background dopant concentration N _I is about 1 x 10 ¹⁵ atoms/cm 3 . This is for the above-mentioned predetermined range of the p-type background dopant concentration of the range of 1 × 10 ¹⁵ to 1 × 10 ¹⁶ atoms / cubic centimeter. However, instead of using FIG. 32 or 33 to implement IGFET 220U as IGFET 220V, the lower limit of the range for the p-type background dopant concentration is downwardly changed to 5 × 10 ¹⁴ atoms/cm 3 or less. For its use to form the island portion 204 of the IGFET 220U, this provides more flexibility to ensure that the island portion p- which is not p-typed and/or n-doped except for the n-type well doping during the process is doped. The materials are all converted to n-type conductivity before the end of manufacture.

The concentration N _I of the n-type well dopant in IGFET 220U is at a maximum y _w below the upper semiconductor surface. The total n-type dopant of the bulk material 262 of the IGFET 220U and the portion of the body material 268 below the drain 264 consists solely of n-type well dopants, as indicated by curve 276' of Figures 36a and 38a. As a result, those portions 268 of the p- IGFET 220U bulk material below the source 262 and drain 264 of the total n-type dopant concentration in the depth y _w N _T reaches a maximum value, as in FIG. 36b and 38b of the curve Indicated by 276”.

As the curve 276 in FIG. 38b, "the variation shown, those portions of body material 268 below drain 264 of IGFET 220U of the total n-type dopant concentration in the N _T system along vertical lines 136U to move from the well portion The sub-surface position of the maximum concentration of the n-type dopant of 276 is reduced by up to 10%, typically about 15%, to the drain 264. In addition, the position of the maximum concentration of the total n-type dopant in the well 276 is It is no more than 10 times deep (usually no more than 5 times) below the upper semiconductor surface than the drain 264. Therefore, the vertical doping dose curve below the drain 264 of the IGFET 220U is steep. 268 part by the position of the n-type typically total from the maximum concentration of the n-type well dopant concentration portion N _T bulk material below drain 264 of IGFET 220U is moved to the drain 264 is gradually reduced, such as by curve 276 ' the indicated portion, extending from the lower electrode 264 to the drain of the n-type body material 268 part by the total of the maximum concentration of the dopant to a depth y _w which represents the drain - body junction 398 of the item 398 #.

The net dopant of the bulk material 268 below the drain 264 of the IGFET 220U is an n-type dopant. FIG. 38c shows: * as represented by the curve 276, the vertical variation of net dopant concentration of the portion 268 of the body's material below drain 264 of IGFET 220U N _N similarly to the drain electrode 264 of the lower body material The concentration N _T of the total n-type dopant in part 268 except that the concentration N _N of the bulk material 268 portion below the drain 264 drops to zero at the drain-body junction 398. For the above-mentioned reasons associated with the p-channel IGFET 220 and the asymmetric n-channel IGFET of the present invention, the sub-steep vertical doping dose curve of the portion of the bulk material 268 below the drain 264 of the IGFET 220U is associated with The parasitic capacitance of the drain-body junction 398 is reduced. Although the sub-steep vertical doping dose curve of the bulk material 268 portion below the bungee 264 is tied to the IGFET 220U (which avoids the n-type compensating implant) is not as strong as the IGFET 220 (which uses n-type compensatory implants) The second steep vertical doping dose curve of the portion of the body material 26 below the drain 264 of the IGFET 220U causes the drain-body junction 398 to have a reduced parasitic capacitance. The IGFET 220U thus has an increased analog speed.

268 part by the concentration of N _I N _T and the vertical change of electrode body material 262 below source 268 of IGFET 220U are part of the total n-type dopant is largely identical to the drain electrode 264 below the total of the n-type body material The concentration of dopants N _I and N _T . Comparing curves 276' and 276" of Figures 36a and 36b (taken along vertical line 130U through source 262) and curves 276' and 276" of Figs. 38a and 38b (along the vertical line through source 264) 136U obtained). Note that the net dopant of the bulk material 268 under the source 262 of the IGFET 220U is the n-type dopant, and the concentration of the net dopant of the bulk material 268 below the source 262 is N _{N .} The vertical variation is the concentration N _N of the net dopant of most of the body material 268 portion that is below the drain 264. As represented by curve 276* of Figure 36c, the concentration N _N of the net dopant portion of the bulk material 268 below the source 262 of IGFET 220U is thus vertically varied to resemble the portion of body material 268 below source 262. The concentration N _T of the total n-type dopant, except that the concentration N _N of the bulk material 268 portion below the source 262 drops to zero at the source-body junction 396. This vertical doping dose curve below the source 262 of the IGFET 220U typically reduces the parasitic capacitance along the source-body junction 396.

Generalized computer simulation

Computer simulations were performed to examine the device characteristics and performance advantages of the IGFETs constructed in accordance with the present invention, particularly for analog applications. The simulation is based on (a) the Micro Tec 2D device simulator provided by the Siborg system and (b) Avant! The company's Medici two-dimensional device simulator is implemented. The Micro Tec simulator is primarily used for large signal (DC) simulations. The Medici simulator is mainly used for small signal simulation.

Two types of n-channel IGFETs are computer-simulated at the device level: (a) an asymmetric n-channel IGFET constructed in accordance with the present invention and (b) an n-channel that generally corresponds to the invention of computer simulations (but differing in nature) Symmetrical reference n-channel IGFET for IGFETs. The computer simulated asymmetric IGFET of the invention is generally indicated below as construct "A". The inventive asymmetric IGFET summary of construction A corresponds to the long n-channel IGFET 150 of FIG. 13 or to one of the short channel forms of IGFET 150. The reference computer simulated symmetrical IGFET is generally identified below as construct "B". The reference IGFET of the computer simulation of construction B summarizes the long n-channel IGFET 230 corresponding to FIG. Or corresponding to one of the short channel forms of the IGFET 230, the ring pocket portions 320 and 322 for the IGFET 230 are respectively extended below the S/D regions 302 and 304.

Structures A and B are based on an analytical quantitative curve model that generalizes the Gaussian doping dose-varying curve. It is assumed that the structures A and B of each group being compared are manufactured according to the same processing flow as those of FIG. In addition to producing variations in the doping characteristics of the bulk material of the present invention, and unless otherwise indicated below, the compositions A and B of each group being compared have substantially the same dopant profile. The configurations A and B of the compared groups also have substantially the same geometric dimensions, such as gate length, gate stack height, and source/drain length. The computer simulation of constructions A and B represents the device fabricated at the 0.18 micron technology node, namely the IGFET fabricated by its minimum printable design rule with a feature size of 0.18 micron.

Computer simulations are outlined to enhance analogy performance. Construction B is therefore computer simulated as it is expected to produce parameter values for the enhanced analog performance of Construction A. Since the basic architecture of Construction B is for digital applications, some of the parameter values applied to computer simulation construct B to achieve enhanced analog performance are different from the parameter values that will result in enhanced digital performance.

It is assumed that the structures A and B are arranged in a plurality of IGFET configurations, and the insulated filled trenches are utilized to implement a field of insulating regions, such as the field insulating region 200 of FIG. 29, for lateral isolation from the plurality of IGFET structures. IGFET in the middle. The trenches having the same dimensions for the structures A and B are as deep as 50% and as wide as 20% wider than those required to optimize the reference structure B in the plurality of IGFET configurations. Corresponding to the respective The asymmetric n-channel IGFET 150 of FIG. 13 is deeper than the IGFET well of the p+ well 116 and 316 of the symmetric n-channel IGFET 230 of FIG. 29 as compared to the digital performance required to optimize the configuration B. Up to 20%. The Structure A of the invention appears to require a wider/deeper trench, whereby a good IGFET is maintained when there is a well whose average dopant concentration is lower than one of the constructs B optimized for digital performance. Isolated.

Both structures A and B have the same threshold voltage V _T and the same background p-type dopant concentration, namely: 0.4 volts and 5 x 10 ¹⁵ atoms/cm 3 . The p-type implant defining its pocket along the upper semiconductor surface of configurations A and B controls its threshold voltage V _T for a given p-type background dopant concentration. In view of this, the peak upper surface concentration of the p-type bag portion dopant in the single bag portion of the inventive structure A is appropriately adjusted to achieve the p-ring ring dopant of the two ring pocket portions of the reference structure B. The same threshold voltage caused by the peak concentration on the peak. More specifically, the inventive-asymmetric configuration A receives a heavier dose of the pocket dopant compared to the reference symmetric configuration B, taking into account the fact that the reference configuration B has twice as many bags of the inventive configuration A. unit. The higher doping of the single pocket portion of the inventive asymmetric configuration A increases its penetration resistance compared to any pocket portion having a reference symmetrical configuration B as compared to the pocket portion of the comparative asymmetric configuration. The same doping is the same as one of the configuration A asymmetric IGFET configurations.

Figure 39 presents a three-dimensional doping dose curve for a short channel form of the asymmetric configuration A of the invention. A three-dimensional doping dose curve for a corresponding short channel form of reference symmetric configuration B is presented in FIG. Figures 39 and 40 clearly illustrate that the net dopant concentration N _N is a function of the longitudinal distance x and the depth y. The only implementation of configurations A and B is shown in Figures 39 and 40. Although both constructions A and B are assumed to be fabricated at 0.18 micron technology nodes, computer simulations of configurations A and B of Figures 39 and 40 have a gate length L _G of 0.2 microns, resulting in lithography. One channel length L is aligned from 0.12 to 0.14 microns.

The implementation of the inventive construction A of FIG. 40 is substantially in the form of a short channel corresponding to the IGFET 150. The implementation of the reference configuration B of FIG. 40 is substantially in the form of a short channel corresponding to the IGFET 230, and the implementation of the configuration B according to FIG. 40 is to summarize the parameter values of the analog performance simulated in the implementation of the enhancement configuration A and in accordance with the ring of the IGFET 230. The pocket portions 320 and 322 extend below the S/D regions 302 and 304, respectively. For convenience, the implementation of the short channel configurations A and B of Figures 39 and 40 is labeled with reference numerals for their use to identify the single-turn regions of IGFETs 150 and 230. Since construction B is simulated for analog applications, S/D regions 302 and 304 are labeled as source 302 and drain 304, respectively, of FIG. Except as indicated below, the reference to the short channel form of configurations A and B, or the configuration A and B for the short channel, is meant to be the embodiment shown in Figures 39 and 40, respectively.

Each of the S/D regions of each of the configurations A or B consists of a very heavily doped main portion and a lightly doped (but still heavily doped) laterally extending portion. The drain 104 in the form of a short channel of construction A thus consists of a main portion 104M and a laterally extending portion 104E. However, regions 104M and 104E of drain 104 are difficult to identify in Figure 39 and are therefore not separately labeled in Figure 39.

Figures 41 and 42 present a two-dimensional dopant profile for the respective short channel forms of configurations A and B. The dopant profile is obtained by passing the short channel structures A and B along a vertical plane. Regions 104M and 104E of short channel configuration A are clearly identified in Figure 41 and are therefore labeled in Figure 41. As shown by the position of the pn junctions 110 and 112 of FIG. 41, the main drain portion 104M of the short channel structure A extends deeper below the upper semiconductor surface than the main source portion 102M. That is, for the asymmetric structure A of the invention, the drain depth y _D is greater than the source depth y _S . Conversely, the test of FIG. 42 shows that the main source portion 302M of the reference symmetrical structure B and the main drain portion 304M are substantially the same depth below the upper semiconductor surface.

Figure 43 presents a function of longitudinal distance x for structures A net dopant concentration along the upper semiconductor surface N _N, as measured from a B to a short-channel version of reference S / D zone location. The measurement reference S/D zone position is about 3.5 microns from the center of the channel zone. Figure 43 and its later rendering of the computer simulation data for constructions A and B, representing a circle marked as small for the construction of construction A to distinguish the data curve from the additional indication for Refer to the material of construction B. Where the structures A and B have substantially the same data, the curved segments for the structures A and B are visually indistinguishable from each other.

Similar to the curved section of Fig. 14c, the curved sections 102M*, 104M*, 102E* and 104E* of Fig. 43 represent the net of the regions 102M, 104M, 102E and 104E along the upper semiconductor surface of the short channel structure A of the invention, respectively. The concentration of the n-type dopant N _I . The curve segments 106* and 120* of Fig. 43 represent the concentration N _I of the net p-type dopant along the regions 106 and 120 of the upper semiconductor surface of the short channel structure A, respectively. Curve segments 302M*, 304M*, 302E*, and 304E* represent the concentration N _I of the net p-type dopant along the regions 302M, 304M, 302E, and 304E of the upper semiconductor structure B of the reference short channel configuration B, respectively. Curve segments 306*, 320*, and 322* represent the concentration of the net p-type dopant of regions 306, 320, and 322 along the upper semiconductor surface of short channel configuration B, respectively.

The curved section 106* of Figure 43 illustrates the asymmetric dopant grading of the channel region 106 of the short channel construction A of the invention. In particular, the curved segment 106* shows that the net dopant concentration N _I along the upper semiconductor surface of the short channel structure A is close to the source 102 and is about 1×10 ¹⁸ atoms/cm 3 . A high value, and then gradually decreases in position from the high value across the channel region 106 toward the drain 104. Although not shown in the computer simulation, the channel region in the short-channel structures A total p-type dopant concentration of the N _T 106, compared to the region along the upper surface 106 meets the drain electrode 104, the region 106 based thereon Along the upper surface is where the source 102 is converged and is as low as 10% (typically less than 100%). Conversely, the symmetrical dopant grading of the channel region 306 of the short channel structure B is illustrated by the curved segment 306*, which shows that the concentration N _I along the upper surface of the short channel structure B is close to the source 102 and 汲. The poles 104 are at approximately equal peaks and are slightly lower values in the middle of the channel region 306.

Figure 44a presents an absolute (total p-type and total n-type) vertical doping dose curve for the transmitted S/D position for the short channel form of configurations A and B. The longitudinal distance x used in Figure 43 is the same measurement reference S/D zone position measured from it, and the absolute dopant concentration N _T for the short channel configuration A of the invention is illustrated in Figure 44a along the main source portion. 102M is a vertical line (or plane) at a distance x equal to 0.0 microns and a vertical line passing through the main drain portion 104M at a distance x equal to 0.7 microns. Figure 44a is similarly depicting the concentration N _T of the short channel configuration B for reference, along a vertical line extending through the main source portion 302M at a distance x equal to 0.0 microns and along the extension through the main drain portion 304M. x is a vertical line equal to 0.7 microns.

Similar to the curves of Figures 8b and 10b, the curved segments 102" and 104" in Figure 44a are respectively the source 102 and the drain 104 corresponding to the short channel configuration A of the invention and thus represent the source 102 and the drain 104 (definitely the main source portion 102M and the main drain portion 104M) are at a concentration N _T of the total n-type dopant of a vertical line having a distance x of 0.7 and 0.7 μm, respectively. The curved segments 114", 116", 118", 120" and 124" of Fig. 44a are respectively representative of the regions 114, 116, 118, 120 and 124 corresponding to the short channel configuration A and thus each representative along the transmitting source 102. and drain 104 to a distance x concentration N _T 0.0 and 0.7 of the vertical line m of the total p-type dopant. item ^# 110 and ^# 112 are indicated with respect to the pn junction 110 of short-channel structures a 112.

The maximum concentration of the p-type well dopant of the well portion 116 of the inventive short channel configuration A occurs at a depth y _W equal to 0.7 microns, as indicated by the curved segment 116" of Figure 44a. The curved segment 116" and The combination of 124" illustrates the sub-steep nature of the vertical doping dose curve of the short channel configuration A below the drain 104 along a vertical line having a distance x equal to 0.7 microns. In particular, the combined curve segment 116 "/ 124" shows: directly below the drain 104 of the body material portion of the total p-type dopant concentration of N _T moves from a position at the maximum p-type well dopant concentration at the bottom to drain 104 The pn junction 112 is reduced by about 100% and thus by significantly more than 10%.

For the short channel configuration A of the invention of Fig. 44a, the depth y _D of the drain-body junction 112 is about 0.2 microns. Since the depth of the maximum concentration of the N _T below drain 104 of the total p-type dopant in the body material portion y _W 0.7 micron lines, the short-channel structures A to the total doped p-type body material portion below drain 104 The maximum concentration of the dopant, N _T , is about 3.5 times deeper than the drain 104 above the upper semiconductor surface. As a result, the bulk material in the total p-type dopant concentration of 108 N _T based on the position from the maximum dopant concentration of the p-type well section (as compared to its drain 104 below the upper surface of the semiconductor is not deeper More than 5 times) moving up to the drain 104 and decreasing to about 100%.

The curve segments 302" and 304" in Fig. 44a are respectively the source 302 and the drain 304 of the short channel configuration B corresponding to the reference and represent a distance x between the source 302 and the drain 304 of 0.0 and 0.7 micron. The concentration of the total n-type dopant of the vertical line N _T . Curve segments 114", 316", 318", 320", and 322" are regions 114, 316, 318, 320, and 322 corresponding to short channel configuration B, respectively, and thus represent along source 302 and drain 304. x is from 0.0 to 0.7 microns concentration N _T of the vertical line of the total p-type dopant. in this connection, curve segments 114 "are applied to short-channel structures a and B.

As with the case of the well 116 of the short channel configuration A of the invention, the maximum concentration of the p-type well dopant in the well 316 of the reference short channel configuration B occurs at a depth y _W equal to 0.7 microns, as The curve segment 316" of Figure 44a is indicated. However, in the short channel configuration B, the combination of curve segments 316", 318" and 322" (or 320") is directly below the drain 304 (or source 320). The p-type body material portion is relatively flat. The combined curved segment 316"/318"/322" shows that the total p-type dopant concentration N _T directly below the drain 304 is in the bulk material portion. The position from the maximum p-type well dopant concentration to the pn junction at the bottom of the drain 304 is significantly changed to less than 5%, and thus is significantly less than 10%. That is, the vertical doping dose curve of the short channel structure B directly under the drain 304 in the body material portion is not steep.

For the short channel form of configurations A and B, the net vertical doping dose curve corresponding to the absolute vertical doping dose curve of Figure 44a is presented in Figure 44b. The curved segments 102* and 104* of Fig. 44b represent the concentration N _N of the net n-type dopant of the source 102 and the drain 104 of the short channel structure A of the invention, respectively, along the source 102 and the drain 104. A line perpendicular to the distance x between 0.0 and 0.7 microns is defined (through the primary source portion 102M and the main drain portion 104M). The curve segments 114*, 116*, 120*, and 124* each represent a concentration N _N of the net p-type dopant in the regions 114, 116, 120, and 124 of the short channel structure A, along the source 102 and the source The poles 104 are perpendicular to the distance x from 0.0 and 0.7 microns.

The curve segments 302* and 304* in FIG. 44b represent the concentration N _N of the net n-type dopant of the source 302 and the drain 304 of the reference short channel configuration B, respectively, along the source 302 and the drain 304. (Immediately through the main source portion 302M and the main drain portion 304M) vertical lines having a distance x of 0.0 and 0.7 microns, respectively. The curve segments 114*, 316*, and 318* represent the concentration N _N of the net p-type dopant in the regions 114, 316, and 318 of the short channel structure B, respectively, along the distance x between the source 302 and the drain 304. It is a vertical line of 0.0 and 0.7 microns. Curve segments 114* are applied to short channel configurations A and B.

45a and 45b illustrate the linear linear range mutual conductance g _mw and the line saturation mutual conductance g _msatw as a function of the gate-to-source voltage V _GS , respectively. For the short channel form of the structures A and B, the gate length L _G is 0.2 microns. Figures 46a and 46b illustrate linear linear range transconductance g _mw and line saturation transconductance g _msatw as a function of gate-to-source voltage V _GS , respectively, for the long channel form of constructions A and B, which are substantially identical to the short channel The structures A and B are constructed except that the gate length L _G is 0.5 μm. For the linear range _gmw plots of Figures 45a and 46a, the drain-to-source voltage V _DS is 0.1 volts. For the saturated g _msatw plots of Figures 45b and 46b, the voltage V _DS is 2.0 volts. FIG. 45a, 45b, 46a and 46b are also indicative of the linear range of the transconductance g _mw saturated transconductance _g msatw to determine a change from its line of the drain current I _Dw.

46a and FIG. 46b shows, in the form of long channel as compared to the reference structure B, in the form of long channel configuration A of the invention exhibit significantly higher mutual conductance (transconductance g _mw linear range and the saturation transconductance _g msatw). As indicated in Figure 45a, the short channel form of Construction A exhibits a slightly higher (roughly 10% higher) linear range transconductance _gmw than the short channel form of Construction B. Figure 45b shows that the short channel forms of configurations A and B have nearly identical g _msatw characteristics. A configuration of the invention is directed to transconductance g _mw and higher values are summarized _g msatw enable it has a higher voltage gain and thus improve its analog performance.

47 illustrates for short-channel structures A and B forms of the current - voltage transfer characteristics, namely: line for the drain current I _Dw changes the gate-to-source voltage V _GS, the 2.0 volts on the gate-to-source voltage V _GS . As shown in Fig. 47, the configurations A and B of the short channel have almost the same current-voltage characteristics. It is also expected that the long channel forms of configurations A and B will have mostly the same current-voltage characteristics.

Note the fact that the upper body portion 318 of the reference short channel configuration B is provided with a high concentration of p-type APT dopant to help avoid penetration of the short channel structure B, and for the short channel structures A and B are almost The same current-voltage characteristics show that, in inventive construction A, the absence of a p-type APT dopant at a position that is similar to the p-type APT dopant of reference configuration B does not result in penetration of the inventive construct A. . A qualitative physical explanation for this result consists in the penetration resistance of the p-type pocket dopant to the structure A. More specifically, the p-type pocket dopant of the pocket portion 120 of the inventive construction A provides a larger blend than the p-ring implant of either of the pocket portions 320 and 322 of the reference configuration B. Miscellaneous, for construction A to have the same threshold voltage V _T as configuration B. This difference can be seen by comparing curve segment 120* and curve segments 320* and 322* of FIG. The higher doping of the p-type pocket implant of the inventive construction A enables it to avoid penetration and at the same time operate at low current leakage comparable to the reference configuration B.

The foregoing conclusions are further supported by a computer simulation of another reference short channel IGFET configuration C, which lacks the APT implant of the reference short channel configuration B and otherwise equals the short channel configuration B. The current-voltage transfer characteristic for the reference configuration C with a V _DS value of 2.0 volts is indicated by the curve labeled C in FIG. The leakage current I _D0w is the value of the drain current I _Dw whose gate-to-source voltage V _GS is zero. As shown in FIG. 47, the drain leakage current I _D0w for the reference configuration C is about 50 times higher than the short channel configuration A of the invention. This line indicates that penetration occurs in reference construction C.

Figure 48 depicts the line drain current I _Dw as a function of the drain to source voltage V _DS , for the short channel form of construction A and B, in the range from 0.5 volts to 2.0 volts gate to source voltage V _GS Value. As indicated in FIG. 48, at each of the indicated V _GS values, the inventive short channel configuration A summarizes a slightly higher value of the gate current I _Dw than the reference short channel configuration B. The construction A of the invention therefore has a lower channel resistance than the reference configuration B. Furthermore, compared to the reference configuration B, the drain current I _Dw is higher than the high voltage V _DS of the inventive configuration A as the increased drain-to-source voltage V _DS increases to less. This series indicates that a smaller collapse multiplication and/or a smaller channel width modulation occurs in the inventive construction A than the reference configuration B.

Analysis and performance advantages of the inventive asymmetric IGFET

For good analog performance, the source of an IGFET should be as reasonably shallow as possible to avoid attenuation of the threshold voltage V _T of the short channel length. The source should also be heavily doped as much as possible so that the effective cross-conductance g _meff of the IGFET in which the source resistance R _S is _present is maximized. The effective transconductance g _meff is determined by the intrinsic mutual conductance g _{m of} the IGFET as:

As indicated by equation (1), lowering the source resistance R _S increases the effective transconductance g _meff . The voltage drop across the source resistance R _S is also subtracted from the intrinsic gate to source voltage such that the actual gate to source voltage V _{GS is} tied to a lower value. This de-biass the IGFET at its gate electrode. In short, the source resistance R _S should be as reasonably low as possible.

In addition to requiring a lower series resistance of the source and drain of the IGFET to achieve a lower value of the on-resistance R _on of the IGFET, minimizing the source resistance R _{S is} needed to maximize the effective mutual conductance g _meff . More specifically, the voltage drop across the source resistance R _S is added to the total source to drain voltage drop. This causes the on-resistance R _{on to} increase.

In order to achieve high voltage capability and reduce heat carrier injection, the drain of an IGFET should be as reasonably deep and lightly doped as possible. These needs should be met without causing the on-resistance R _on to increase significantly and not causing the threshold voltage of the short channel to decay.

The parasitic capacitance of an IGFET is an important task in setting the speed performance of its IGFET-containing circuits, especially for high frequency operation of small signals. Figure 49 is a diagram showing the parasitic capacitances C _DB , C _SB , C _GB , C _GD and C _GS of the drain electrode D, the source electrode S, the gate electrode E and the body region electrode B, respectively associated with an n-channel IGFET Q, Among them, C _DB represents the capacitance of the drain to the body, C _SB represents the capacitance of the source to the body, C _GB represents the capacitance of the gate to the body, C _GD represents the capacitance of the gate to the drain, and C _GS represents the gate to the gate The capacitance of the source. An equivalent model of one of the small signals of IGFET Q is presented in Figure 50, where _VBS is the body-to-source voltage, _gmb is the mutual conductance of the body electrodes, and items 440 and 442 are the current sources.

The bandwidth of the amplifier is defined as the gain of the amplifier drops to 1/ of its low frequency value. Frequency value (approximately 0.707). It is generally desirable that the bandwidth of the amplifier is as large as possible.

FIG IGFET Q 49 may be disposed on the three main amplifier configured to provide as a function of input voltage V _in the amplified output voltage V _out, according to the _{relation: V out = H A V in} (2) where, H _A A complex transfer function of an IGFET. These three configurations are shown in common source, common gate, and common drain configurations shown in Figures 51a through 51c, where the C _L is a load capacitor, V _DD is a high supply voltage, and V _SS is a low supply voltage. . Amplifier input voltage V _in supplied from a voltage source 444. The elements 446 of Figures 51b and 51c are a current source, and the signal V _G of Figure 51b is a gate voltage. The test of the transfer function H _{A for} the three configurations of Figures 51a to 51c demonstrates that the parasitic drain-to-body capacitance C _DB and/or the parasitic source-to-body capacitance C _SB are improved in this group. IGFET performance for each mode: Transfer function H _A for the common source amplifier configuration of Figure 51a Input pole/output pole function: Among them, R _D is the drain (series) resistance, ω _in is the angular frequency of the input pole, ω _out is the angular frequency of the output pole, s is the complex frequency operator equal to jω, and the ω is the angular frequency. The parasitic capacitance of the IGFET Q in the common source configuration is input to equation (3) by setting the pole frequencies ω _in and ω _out as follows:

The parasitic bungee-to-body capacitance C _DB appears at the output pole frequency ω _{out of} equation (5). For the case where the source resistance R _{S of the} common source configuration is zero, according to equation (4), the input pole is infinite. The bandwidth of the IGFET Q of Fig. 51a is then equal to ω _out as defined by equation (5). For a given value of the gate resistance R _D and the parasitic gate to drain capacitance C _GD , the output pole frequency ω _out increases with decreasing drain to body capacitance C _DB . Reducing the parasitic buck to body capacitance C _{DB is} therefore desirable to increase the bandwidth of the IGFET Q common source configuration of Figure 51a.

Furthermore, as shown in Figure 51a, the parasitic drain-to-body capacitance C _DB in the common source configuration is paralleled to the load capacitance C _L . Reducing the drain to body capacitance C _{DB is} therefore advantageous to reduce its output load effect.

The transfer function H _A for the common gate amplifier configuration of Figure 51b is the input pole/output pole function: Among them, the input pole frequency ω _in for the common gate configuration is defined as: Reducing the source-to-body capacitance C _SB increases the input pole frequency ω _in . The performance of this system enabled IGFET Q is improved in the common gate configuration of Figure 51b.

The output pole frequency ω _out for the common gate amplifier configuration of Figure 51b is defined by equation (5). Reducing the parasitic drain to the bulk capacitance C _DB thus increases the bandwidth of the common gate configuration of Figure 51b.

The transfer function H _A for the common drain amplifier configuration of Figure 51c is a single zero/single pole function: Where ω _z is at the angular frequency of zero and ω _p is at the angular frequency of the pole. The parasitic capacitance is input to the equation (8) by setting the zero point frequency ω _z and the pole frequency ω _p as follows: The parasitic source-to-body capacitance C _SB appears at the pole frequency ω _{p of} equation (10). By lowering the capacitance C _SB , the pole frequency ω _{p is} increased. This is a modification of the frequency characteristics of the IGFET of the common blip configuration of Figure 51c.

Similar to the buck-to-body capacitance C _DB of the common source configuration of Figure 51a, the parasitic source-to-body capacitance C _{SB is} connected in parallel to the load capacitance C _L in the common drain configuration shown in Figure 51c. . Reducing the source-to-body capacitance C _{SB is} therefore advantageous for reducing its output load effect in a common drain configuration.

Figure 52 illustrates a small signal model of the shorted output form of the common source amplifier configuration of Figure 51a. In the small signal model of FIG. 52, the drain electrode D of the IGFET Q is electrically shorted to the source electrode S. Figure 53 presents a small signal equivalent circuit of the model of IGFET Q of Figure 52. Element 448 of Figure 53 is a voltage controlled current source. The items v _gs , i _i , and i _o in Figures 52 and 53 are the gate-to-source (input) voltage of the small signal, the input current of the small signal, and the output current of the small signal, respectively.

The cutoff frequency f _{T of} an IGFET is defined as the value of the frequency f at which the absolute value of the current gain A _I of the short-circuit output common source configuration of the IGFET drops to one. which is: The cutoff frequency f _{T is} derived from the equivalent circuit of the small signal of Figure 53 as: The capacitance C _GB of the equation (12) is a parasitic capacitance between the gate electrode G and the IGFET body region outside the active region occupied by the IGFET Q.

An enlarged IGFET improve transconductance g _m of lines are usually improve its performance capabilities, because it increases the voltage gain is typically based. Since the cutoff frequency f _T is increased according to the equation (12) as the mutual conductance g _m is increased, one of the cutoff frequencies f _{T is an} indicator of the improved IGFET performance.

Classical long-channel model for IGFET Q (for which: source resistance R _S is zero), mutual conductance g _m : Among them, W is the IGFET width, L is also the channel length, μ _n is the electron mobility, and C _GIa is the gate dielectric capacitance per unit area. The velocity saturation model of the short channel of IGFET Q, the mutual conductance g _m system: g _m = Wv _nsat C _GIa (14) where v _nsat is the electron saturation velocity due to the IGFET Q-based n-channel device. The verification of equations (13) and (14) shows that the mutual conductance g _m of the long channel and short channel models is proportional to the gate gate dielectric capacitance C _GIa .

For the classical long-channel model of IGFET Q, for saturation, capacitors C _GS , C _GD and C _GB are:

_{C GD = WL GDoverlap C GIa (} 16)

C _GB =WLC _GIa (17) wherein the L _GSoverlap and L _GDoverlap system gate electrodes overlap the longitudinal distance of the source and the drain of the IGFET Q, respectively. Item _WL GSoverlap C GIa system due to the gate electrode overlapping the source parasitic capacitance. Item _WL GDoverlap C GIa system due to the gate electrode overlaps the drain parasitic capacitance. Inserting equations (15) through (17) into equation (12) produces a cutoff frequency f _T for saturation of an ideal long channel IGFET.

Equations (15) and (16) are not intended to be accurate for the asymmetric IGFET of the present invention due to the asymmetric longitudinal doping gradient of its channel region. However, equations (15) and (16) can be used as indicators of the tendency to calculate parasitic capacitances C _GS and C _GD for evaluating the cutoff frequency f _T of the asymmetric IGFET of the present invention. The more accurate values of the capacitances C _GS and C _GD can be determined by computer simulation.

By definition, the cutoff frequency f _T relates to the short circuit condition of the output of the common source configuration. As a result, the frequency f _T is essentially the effect of destroying the parasitic drain to the bulk capacitance C _DB . Furthermore, the frequency f _T does not reflect the effect of the parasitic source-to-body capacitance C _SB , since it utilizes a common source configuration.

The cutoff frequency f _T has a peak cutoff value f _Tpeak which is dependent on the operating current (ie, the drain current I _D ). Although the peak cutoff frequency f _Tpeak has IGFET performance for evaluating high frequencies, the circuit typically operates at a frequency that is one to two factors below the peak f _Tpeak of 10. In addition to being desirably high for the peak f _Tpeak of an IGFET, it is generally desirable to have a decrease in the cutoff frequency f _T as the operating current is reduced below the operating current level corresponding to the peak f _Tpeak . Variety.

Pn junctions 110 and 112 such as the inventive IGFETs 100, 140, 150, 160, 170, 180, 190, 210, 100V, 140V, 150V, 160V, 170V, 180V and 190V, the source body and the drain body are connected The face is usually reverse biased. When a pn junction is reverse biased, the surface capacitance C _da which is determined to be one of the following small signals is present along the depletion region of the junction: Where ε ₀ is the absolute dielectric constant, the relative dielectric constant of the K _S -based semiconductor material, and t _d is the voltage-dependent thickness of the depletion region.

For a pn junction formed along a uniformly doped substrate, the thickness t _d of the depletion region for the ideal pn junction is: Wherein, V _R is a reverse voltage applied, a built-in voltage of the V _BI junction, q is an electron charge, and N _B0 is a uniform background dopant concentration of the substrate. The built-in voltage V _BI varies with the background dopant concentration N _B0 according to the following relationship: Wherein, k is a Boltzmann's constant, a T-system temperature, and n _i is an essential carrier concentration.

Figure 54 illustrates how the net dopant concentration N _D -N _A varies with the distance y of the p-type substrate material to a pn junction model, which can have three basic types of doping dose curves. In one case, N _D and N _A are absolute donor and acceptor dopant concentrations, respectively. The junction model is also shown in Figure 54. As indicated by the junction model shown, the p-type material is thicker and therefore less lightly doped than the n-type material of the junction. Curves 450, 452, and 454 of Figure 54 indicate examples of sub-steep, steep, and ultra-steep doping dose curves for p-type materials, respectively. The distance y _d refers to the thickness of the p-type portion of the depletion region along the junction.

The sub-steep quantitation curve 450 is approximately representative of the buckoo-body of the inventive n-channel IGFETs 100, 140, 150, 160, 170, 180, 190, 210, 100V, 140V, 150V, 160V, 170V, 180V and 190V. The vertical doping dose curve below the junction 112. The illuminator 104 includes IGFETs 150, 160, 180, 190, 210, 150V, 160V, 180V, and 190V of the main drain portion 104M and the lateral drain extension portion 104E, and the curve 450 is specifically representative of the main portion 104M. A vertical doping dose curve below the bottom bungee-body junction 112. For the IGFET whose source 102 is deeper below the upper semiconductor surface than the pocket 120 170, 180, 190, 170V, 180V and 190V, curve 450 also represents the vertical doping dose curve below the source-body junction 110, specifically for the IGFET 180, 190, 180V and 190V Below the junction portion of the bottom of the main source portion 102M. In the opposite direction of the conductivity pattern, curve 450 represents a vertical doping dose curve below the bottom of the main portion 264M of the drain 264 of each of the inventive p-channel IGFETs 220, 220U and 220V. Flat curve 452 represents a p-type material of the ideal steep pn junction included in equations (18) through (20).

Figure 55 depicts the parasitic capacitance of the depletion area surface C _da varies with how to FIG. 54 across the pn junction of the model of the reverse voltage V _R. 55 in graph 464 with the means 460, 462, 450, 452, and changes its C _da 454 are directed to the graph of FIG. 54. In particular, curve 462 is a qualitative expression indicating the power law variation for the ideal pn junction as determined by equation (18), using the t _d data from equation (19) (and the V _BI data from equation (20). ).

The parasitic drain of the inventive n-channel IGFET 100, 140, 150, 160, 170, 180, 190, 210, 100V, 140V, 150V, 160V, 170V, 180V or 190V along the drain-body junction 112 The bulk capacitance C _DB is approximately proportional to the surface depletion capacitance C _da , as represented by curve 460 of FIG. 55 , which corresponds to the sub-steep junction variation curve 450 of FIG. 54 . FIG 55 shows the curve for the depletion capacitance C _da 460 based on the lower of (a) curve 452 corresponds to the curve in FIG. 54 for the amount of the steep surface (flat) or 462 (b) for the corresponding to FIG. The ultra-steep junction of curve 54 is a curve 464 of the curve 454. Thus, ultra-steep vertical doping below the drain-body junction 112 of each IGFET 100, 140, 150, 160, 170, 180, 190, 210, 100V, 140V, 150V, 160V, 170V, 180V or 190V The dose curve reduces the drain to body capacitance C _DB . The same applies to the capacitance C _DB of the p-channel IGFET 220, 220U or 220V of the invention along the bottom of the drain 264. The parasitic source-to-body capacitance C _{SB is} also generally reduced, particularly the n-channel IGFETs 170, 180, 190, 170V, 180V whose source 102 is deeper than the pocket 120 below the upper semiconductor surface. 190V

Further, by the curve 460 as compared to curve 462 of FIG. 55 and 464 stated amount of surface curve 450 curve 460 compared to the depletion capacitance C _da for curve 462 or 464 times in a steep surface 54 corresponds to FIG. It changes slowly with the reverse bias voltage V _R . Parasitic buck-to-body capacitance C _{DB of} each inventive IGFET 100, 140, 150, 160, 170, 180, 190, 210, 100V, 140V, 150V, 160V, 170V, 180V, 190V, 220, 220U or 220V Therefore, the variation is reduced with the reverse voltage V _R . This is advantageous because less compensation is needed to account for variations in the capacitance C _DB . The same argument applies to the parasitic source to body capacitance C _SB , especially for IGFETs 170, 180, 190, 170V, 180V and 190V.

Further examining the sub-steep doping dose curves below the drains 104 and 264, consider an extreme example of a sub-steep junction quenching curve in which the semiconductor material along the lighter doped side of the pn junction The net dopant concentration N _B is formed from a first dopant concentration value to a higher second dopant concentration value by sufficiently approaching the junction to affect a selected distance along one of the parasitic capacitances of the junction. One step change. This example is modeled in Figure 56, which illustrates how the net dopant concentration, N _{B ,} varies with the distance y of the self-joining surface.

The two-step pn junction of Fig. 56 is constructed in the following manner. The lighter doped side of the pn junction is formed with respect to the p-type material, wherein the net dopant concentration N _B is extended to a distance y _d0 from the self-joining surface to a distance of the first value N _{B0 .} At a distance y _d0 , the concentration N _B is changed stepwise to a second value N _B1 . The distance y _d0 is the position of the p-type boundary of the depletion region, and the reverse voltage V _R is zero. If the concentration N _B of the p-type material is at the low value N _B0 , the distance y _d0 is at least one to the outside. The position above which the change in concentration of the p-type material N _B will not significantly affect the parasitic capacitance along the junction.

As the reverse voltage V _R increases from zero to a certain maximum value V _Rmax , the depletion region of the junction along the model of FIG. 56 extends from the distance y _d0 to the maximum distance y _dmax . Above the distance y _dmax , the net dopant concentration N _{B of the} p-type material can have any amount of variation curve, as shown in FIG. As also indicated in Figure 56, the concentration N _B of the heavily doped n-type material along the junction is based on a larger uniform value N _D0 than N _B1 .

Figure 56 depicts the quantitative curve of the dopant in the p-type material, with the high concentration value N _B1 ranging from N _B0 (the step change in the concentration of the distance y _d0 disappears) until 20N _B0 , in the typical y _d0 The value is 0.2 μm and the typical N _B0 value is 3 × 10 ¹⁶ atoms/cm 3 . If the pn junction of the model is at the drain-body junction of the depth y _D below the upper semiconductor surface, the step of increasing the concentration N _B from N _B0 to N _B1 occurs at a depth y _D below the upper surface. +y _d0 .

The surface depletion capacitance C _da of the two-step pn junction of Fig. 56 is affected by the following differential equation: The condition is that the depletion region extends to the distance y _d0 when the reverse voltage V _R is zero, and the integral of equation (21) is generated to produce the following values for the distance y _d0 : Binding of formula (18) and (20) to produce the following results for the depletion capacitance C _da:

Figure 57 illustrates how the surface depletion capacitance C _da varies with the reverse voltage V _R for values ranging from N _B0 (also over the junction of the model) up to a high concentration value N _B1 of 20 N _B0 , as determined by equation (23). Figure 57 shows that the increased ratio N _B1 /N _B0 causes the capacitance C _da to change slowly with voltage V _R . For this reason, it is desirable that the concentration ratio N _B1 /N _{B0 is} as high as possible, so that the parasitic capacitances C _DB and C _SD are slowly changed to the asymmetric IGFET of the present invention.

The surface depletion capacitance is when the reverse voltage V _R is zero and is at an initial value C _d0a . The voltage V _R set to the equation (23) to zero is generated:

As expected, the initial depletion capacitance value _{CdOa is} for a classical value of one of the ideal pn junctions of the zero reverse voltage. According to equation (24), according to the square root of the low value N _B0 , the capacitance value C _d0a decreases as the low concentration value N _B0 decreases. Combined with a high value of one of the selected concentration ratios N _B1 /N _B0 to have a slow variation of the parasitic capacitances C _DB and C _SB , the low concentration value N _B0 should be low so that the capacitances C _DB and C _{SB are} at zero reverse voltage V _R It is low.

Computer simulation of capacitance and frequency parameters

Considering the above information about the capacitance and frequency parameters, the small signal simulation is performed by the Medici simulator to describe the characteristics of the junction capacitance of the construction A of the invention. Figures 58a and 58b depict short and long channel versions of configuration A produced by the McDutch simulator, respectively, for junction capacitance characteristics. Items 470 and 472 are indicated at the source and drain contacts (or source and drain electrodes) of Figures 58a and 58b, respectively. Metal telluride layers 254 and 256 are incorporated at contacts 470 and 472, respectively. The doping profile of the p-type body material (or region) 108 of each of Figures 58a and 58b illustrates the grading properties of the doping of the bulk material 108. The short channel IGFET of Figure 58a has a gate length L _G of 0.15 microns. The gate length L _G of the long channel IGFET for Figure 58b is 1.0 micron.

Figure 59 illustrates that the parasitic line drain to body capacitance C _DBw is a function of the drain to body voltage V _DB , for the short channel implementation of the inventive construction A ( _{approximately} similar to the short channel implementation of construction A of Figure 58a) and for The short channel implementation of reference configuration B, which is a short channel implementation that substantially corresponds to the configuration A of FIG. 59 in terms of size and dopant aspects, in addition to the doping features of the present invention. The gate length in Figure 59 is 0.2 microns instead of 0.15 microns in Figure 58a. The gate-to-source voltage V _GS for the C _DBw simulation of Figure 59 is 0.9 volts. As shown in FIG. 59, the _buck-to- body capacitance C _{DBw for} this short channel form of the inventive construction A is relatively low compared to the corresponding short channel form for the reference configuration B. In particular, the V _DS range of the short channel form capacitance C _DBw for the inspection of the construction configuration A is 0 to 2 volts, which is about 50% of the capacitance C _DBw in the short channel form for the inspection of the reference configuration B.

Figure 60 depicts the parasitic line source to body capacitance C _SBw as a function of source to body voltage V _SB for the short channel implementation of configurations A and B of Figure 59. The gate to source voltage V _GS is also 0.9 volts. As shown in FIG. 60, the source-to-body capacitance C _{SBw in the} form of the short channel for the inspection of the inventive configuration A is considerably lower than the corresponding short channel form for the reference configuration B. Although the C _SBw reduction is not as large as the C _DBw reduction, the short channel form of the construction A test is at a V _SB value of 2.0 volts which is about 35 to 40% lower than the short channel form of the test of construction B. The C _SBw value, and the V _SB value at 0 volts has a lower C _SBw value of about 25 to 35% compared to the short channel _version of the test of reference configuration B.

For the short channel form of the configuration A of Figure 59, some minor improvements in the source-to-body capacitance C _SBw are expected because the total p-type dopant in the source 102 is due to the p-type pocket implant. Increased by the entry. Moreover, in many applications, source-to-body capacitance _C SBw compared to the drain to body capacitance _C DBw It was important, since the source material 102 to the body 108 based shortening. As desired, a further reduction in the source-to-body capacitance C _SBw for the short channel form of construction A can be achieved by making the well 116 deeper.

Figure 61 illustrates the cutoff frequency f _T as a function of the line drain current I _Dw for the short channel implementation of the configurations A and B of Figure 59. Figure 61 also illustrates the change in the cutoff frequency f _T of the line A drain current I _Dw for a change in the short channel configuration A of the invention. In FIG. 61 and subsequent figures of the computer simulation data for the structures A and A' of the invention, the curve representing the material for the structure A' is indicated as a solid circle to distinguish the data from the structure A. Information marked as a hollow circle. A particular feature of another inventive construction A' is described below in connection with Figures 63 and 64. As indicated in Fig. 61, the cutoff frequencies f _T for the simulated short channel configurations A, A' and B are mostly the same.

For the long channel form of the implementation of constructions A, A' and B of Fig. 61, the change in the cutoff frequency f _T of the line drain current I _Dw is illustrated in Fig. 62. As indicated in Fig. 62, the cutoff frequency f _T of the long channel form for the configurations A and A' of the invention is mostly the same. Importantly, the frequency f _T for the long channel form of the constructs A and A' of the invention is considerably larger than the long channel form for the reference configuration B. Therefore, the long channel form of the inventive structures A and A' has better performance than the long channel form of the reference structure B.

The vertical bulk material doping dose curve below the bungee is a sub-steep additional IGFET, due to the subsurface maximum of the well dopant concentration

Figure 63 illustrates a short n-channel implementation 480 of its asymmetric IGFET configuration A&apos; in accordance with the present invention. In addition to summarizing the architectural details, the doping profile for IGFET 480 is depicted in Figure 63 as a function of depth y and the longitudinal distance x from a source location. The source position for measuring the distance x is about 0.35 microns from the center of the channel region.

IGFET 480 is summarized as being similar to short channel IGFET 140 of Figure 11, except that source 102 of IGFET 480 is comprised of n++ main source portion 102M and n+ lightly doped laterally extending portion 102E, as The long channel IGFET 150 of Figure 13. This results in a decrease in the source resistance R _{S of the} IGFET 480 and thus improves its analog performance. As with IGFETs 140 and 150, p-type pocket portion 120 extends deeper below the upper semiconductor surface than source 102. The drain depth y _D for IGFET 480 is greater than the source depth y _S by about 50%.

Figure 64 presents a net dopant concentration N _N along the upper semiconductor surface for the inventive configuration A of Figure 39 and for the inventive configuration A' of Figure 63 (i.e., IGFET 480) as a longitudinal direction from the source location The function of distance x. As in Figures 12c and 14c, the curved segments 106* and 120* are here representative of the concentration N _N of the net p-type dopants in the respective regions 106 and 120 and the curved segments 102M*, 102E*, 104M*, 104E* And 104* represent the concentration N _N of the net n-type dopant in the respective regions 102M, 102E, 104M, 104E and 104. Although only the circles are indicated as hollow, the curved segments 102M*, 102E*, 106* and 120* are applied to the construction A and the construction A'.

As indicated by the curved segments 104* and 102M* of FIG. 64, the IGFET 480 of the inventive configuration A' has a somewhat lower maximum net addition to the drain 104 along the upper surface than the main source portion 102M. The concentration of the dopant. More specifically, the maximum value of the net dopant concentration N _N of the IGFET 480 along the upper surface of the drain 104 is typically 20 to 50% of the maximum upper surface value of the concentration N _N of the main source portion 102M, Typically 30 to 40%. Although FIG. 64 illustrates an example in which the maximum upper surface value of the concentration N _N at the drain 104 is slightly more than 1 × 10 ²⁰ atoms/cm ² , the maximum upper surface N _N concentration of the drain 104 of the short channel IGFET 480 is It is easy to significantly reduce, for example, 5 × 10 ¹⁹ atoms/cm ² to 1 × 10 ¹⁹ atoms/cm ² or less, depending on the maximum upper surface N _N concentration of the main source portion 102M. In addition, the drain 104 of the IGFET 480 extends somewhat deeper below the upper surface than the main source portion 102M. Essentially, an IGFET (such as IGFET 150) whose source is composed of a major portion and a lightly doped lateral portion is formed by a major portion and a lightly doped lateral portion. The two-part drain is replaced by IGFET 480 with a deeper, lighter doped drain. The reduced doping of the drain 104 of the IGFET 480 causes a reduced electric field at the drain 104 and causes the IGFET 480 to operate at an electric field magnitude that occurs away from undesirable buckling ionization.

Figure 65 illustrates the threshold voltage V _{T as a} function of the gate length L _G . For the computer simulation of the inventive configuration A', the reference configuration B, and another symmetric reference structure D, the reference structure D lacks construction. The ring pocket portion of B is otherwise substantially the same size and doping mode as construction B. In the simulation of Figure 65, the gate dielectric thickness t _GI is 4.0 nanometers (nm).

As shown in FIG. 65, the threshold voltage decay is compared to the reference configuration B or D in that the inventive configuration A' is a lower value shifted to the threshold voltage V _T . Figure 65 also shows that the inventive configuration A' incurs less undesirable reverse short channel effects than the reference configuration B or D. That is, compared to the reference configuration B or D, the inventive configuration A' undergoes less variation (typically less reduction) of the threshold voltage V _T as it increases in the gate length L _{G of the} long channel domain. Construction A therefore has better short channel and longer channel characteristics than reference configuration B or D.

Manufacture of additional IGFET

The n-channel IGFET 480 implementing the asymmetric IGFET configuration A' of FIG. 63 is typically fabricated in accordance with the present invention and is employed in accordance with the process of FIG. 31 to fabricate an asymmetric n-channel IGFET 210 in accordance with an n-type source/drain Appropriate modifications to the extension and main source/drain implantation steps, and in accordance with the use of additional masking steps and associated ion implantation operations. These differences are described below with respect to IGFET 480, as appropriate, using the same reference numerals used to describe the fabrication of IGFET 210.

In particular, at the stage of Figure 31l, the n+ precursor source extension 102EP The definition is for IGFET 480 without defining an n+ precursor drain extension for one of IGFET 480. This need to form a photoresist mask 422 to extend over a position where the precursor drain extension will otherwise form an IGFET 480, with an opening above the location of the source extension 102OP for the IGFET 480. In this regard, the photoresist 422 is strictly aligned with respect to the IGFET 480 front gate electrode 128P. The n-type source/drain extension portion implant is performed as described above in connection with FIG. 31l, after which the photoresist 422 is removed. Because the photoresist 422 is masked relative to the position of the MOSFET 480 prior to the drain extension, the precursor source extension 102EP forms a corresponding precursor drain extension for the IGFET 480 without forming a corresponding one.

Later in the stage of FIG. 31q, the photoresist mask 434 is configured to extend over the location for the drain 104 of the IGFET 480 and has an opening above the location for the main source portion 102M of the IGFET 480. The photoresist 434 is strictly aligned to the gate electrode 128P before the IGFET 480. The n-type primary source/drain implant system is implemented as outlined above in connection with Figure 31q, after which the photoresist 434 is removed. Since the photoresist 422 is masked for the location of the drain 104 of the IGFET 480, the primary source portion 102M is defined for the IGFET 480 without the need to redefine the drain 104. Portions of the precursor source extension portion 102EP on the outer side of the main source portion 102M constitute the source extension portion 102E. As part of the IGFET 480 front gate electrode 128P is uncovered during implantation, the n-type main source/drain dopant also enters the uncovered portion of the electrode 128P.

An additional photoresist mask (not shown) having an opening above the intended position of the source 102 of the IGFET 480 is formed for the IGFET 480 The dielectric layers 430 and 432 and the gate sidewall spacers 252, the gate sidewall spacers 250 and 252 and the gate sidewall spacers 290, 292, 330, 332, 370 and 372 for the IGFET 210. The additional photoresist is strictly aligned to the gate electrode 128P before the IGFET 480. The n-type drain dopant is at a very high dose while ion implantation is through the uncovered portion of the surface dielectric layer 432 and to the underlying monolayer to define the n++ drain 104 of the IGFET 480. Although the dose used to define the n-type drain dopant of the drain 104 of the IGFET 480 is extremely high, the dose of the n-type drain dopant is less than the amount used to define the primary source portion 102M of the IGFET 480. Extremely high dose of n-type main source/drain dopant. Thus, the drain 104 of IGFET 480 is lightly doped compared to its main source region 102M.

The n-type drain implant for IGFET 480 is also implemented with its drain 104 being deeper below the upper semiconductor surface than its main source portion 102M and its precursor source extension 102EP. For example, n-type main source/drain implants and n-type drain implants for IGFET 480 can be implemented with the same n-type dopant (arsenic or antimony). In this case, the n-type drain implant for IGFET 480 is implemented at a higher implant energy than the n-type main source/drain implant. Alternatively, the second implant can be performed with different n-type dopants, and the n-type drain dopant of IGFET 480 is lower molecular weight than the n-type main source/drain dopant. By. In one example, arsenic is the primary source/drain dopant and the phosphorus-based IGFET 480 is an n-type drain dopant. Compared to the foregoing, the implant energy of this alternative is closer to each other. However, in both cases, the range of n-type drain implants is greater than the range of n-type main source/drain implants. In targeting After the n-type drain of the IGFET 480 is implanted, the additional photoresist is removed.

The portion covered during the main source/drain implantation period for the IGFET 480 front gate electrode 128P is mostly uncovered during the n-type drain implant period for the IGFET 480. This system is enabled for the n-type drain dopant of IGFET 480 to enter a portion of electrode 128P that is covered during n-type main source/drain implantation. As a result, substantially all of the IGFET 480 precursor gate electrode 128P is at this time heavily doped n-type. The IGFET 480 precursor gate electrode 128P thus becomes its n++ gate electrode 128.

The n-type drain implant for IGFET 480 can be performed before, but not after, the n-type main source/drain. In either case, the remainder of the fabrication of IGFET 480 is performed as described above for IGFET 210.

If IGFET 210 is also present in the semiconductor configuration, the configuration of photoresist masks 422 and 434 above the intended location of IGFET 210 is the same as described above in connection with Figures 31l and 31q, respectively. The formation of IGFET 480 does not affect the formation of IGFET 210.

Complementary IGFET construction for another hybrid signal application

Figure 66 illustrates a variation of the complementary IGFET configuration of Figure 29.1 in accordance with the present invention. The complementary IGFET configuration of Figure 66 is particularly well suited for mixed signal applications. The main structural difference between the complementary IGFET configurations of Figures 29.1 and 66 is that the complementary IGFET structure of Figure 66 is fabricated from a starting configuration such as a bonded wafer.

In the complementary IGFET configuration of FIG. 66, a primary surface electrical insulating layer 482 consisting essentially of yttrium oxide is typically separated from the semiconductor layer 484 There is a semiconductor layer on one of the island portions 202 and 204, and the island portions 202 and 204 are laterally separated by the field insulating region 200 along the upper semiconductor surface. The lower semiconductor layer 484 is typically composed of a p-type or n-type single turn. Figure 66 presents an example in which the lower semiconductor layer 484 is lightly doped p-type. An electrically insulating extension 486, typically of the trench type and also typically composed primarily of yttria, extends from the field insulating region 200 to the sub-surface insulating layer 482. The field insulation 200 and the insulative extensions 486 laterally surround the islands 202 and 204 laterally such that they are completely dielectrically isolated from each other.

The islands 202 and 204 are typically composed of doped <100> monoterpenes. The island 202 has a low substantially uniform n-type background dopant concentration, which is typically provided with a low (but slightly higher) substantially uniform p-type background dopant added to the p-type semiconductor dopant aluminum. concentration. Therefore, portions of the island portion 202 that do not receive any other dopant (p-type or n-type) are lightly doped p-type. The island 204 has only a low substantially uniform n-type background dopant concentration.

The island 202 provides a single turn to target a change 210W of the long n-channel IGFET 210. The source 102 and drain 104 of the long n-channel IGFET 210W are separated by a channel portion of the p-type body material 108. The body material 108 is comprised of a lightly doped lower portion 488, a p+ well 116, and an upper portion 490. The p-lower body material portion 488 and the p-type upper body material portion 490 correspond to the p-lower body material portion 114 and the p-type upper body material portion 118 of the IGFET 210, respectively. The upper body material portion 490 of the IGFET 210W is comprised of a p+ pocket portion 120 that contacts the source and a lightly doped p-type residual 492, with the remainder 492 corresponding to the p-upper body material remainder 124 of the IGFET 210. Due to the lower n-type background concentration applied to the island portion 202 of the IGFET 210W due to the low p-type background dopant concentration, the net dopant concentration N _N of the bulk of each region 488 or 492 is predominantly p-type. The difference from the n-type background dopant concentration.

The n-channel IGFET 210W is substantially identical in configuration and configuration to the n-channel IGFET 210 except for the structural differences described above and the presence of two background dopant concentrations in the island portion 202. The p-lower body material portion 488 can be removed such that the p+ well 116 extends down to the sub-surface insulating layer 482.

The island 204 provides a single turn to target a change 220W of the long p-channel IGFET 220. The source 262 and the drain 264 of the long p-channel IGFET 220W are separated by a channel portion of the n-type body material 268. The body material 268 is composed of a lightly doped lower portion 494, an n+ well portion 276, and an upper portion 496. The upper portion 496 corresponds to the n-type upper body material portion 278 of the IGFET 220. The upper body material portion 496 of the IGFET 220W is comprised of an n+ pocket portion 280 that contacts the source and a lightly doped n-type remainder 498, with the remainder 498 corresponding to the n-upper body material remainder 284 of the IGFET 220. Unlike IGFET 220, IGFET 220W does not have a low p-type background dopant concentration and does not utilize an n-type compensation dopant to ensure that all of the upper body material portion 496 is n-type conductive. Net dopant concentration N _N based on the body 494 or 498 of the respective regions are merely n-type background dopant concentration.

The p-channel IGFET 220W is substantially identical in configuration and configuration to the p-channel IGFET 220 except that the structural differences described above and the n-type compensating dopant concentration are absent to ensure that all of the upper body material portion 496 is n-type. The n-lower body material portion 494 can be removed such that the n+ well 276 is extended downward The subsurface insulating layer 482 is extended.

Fabrication of another complementary IGFET construction

The complementary IGFET structure of Figure 66 is fabricated in the following manner in accordance with the present invention. A configuration is provided first, wherein the sub-surface insulating layer 482 is sandwiched between the lower semiconductor layer 484 and an upper semiconductor region, and the upper semiconductor region is composed of a low uniform dopant concentration of <100>n-type germanium. . This initial configuration can be made, for example, by bonding the two semiconductor wafers together by forming an electrically insulating material of the sub-surface insulating layer 482 therethrough. One of the wafers provides a <100>n-type single turn for the upper semiconductor region. The other wafer provides a semiconductor layer 484 which is also typically composed of a single germanium, such as the p-type or n-type as illustrated in the illustrated example.

Insulation extension 486 is formed in the n-up semiconductor region in accordance with a deep trench isolation technique. Field insulating region 200 is then formed along the outer (upper) surface of the n-up semiconductor region to define island portions 202 and 204 in accordance with a shallow trench isolation technique. Using a photoresist mask having an opening above the island portion 202, typically a p-type semiconductor dopant composed of aluminum is introduced to the island portion 202 at a light dose, the light dose system being sufficiently high To convert all of the material of the island portion 202 to p-type conductivity at a low net concentration. When aluminum is used to effect p-type doping of the island portion 202, the aluminum system diffuses relatively rapidly through the island portion 202 such that it becomes substantially uniformly doped p-type for a relatively short period of time.

The p+ well 116 and the n+ well 276 are formed on the islands 202 and 204, respectively, in the manner described above in relation to the fabrication of the IGFETs 210 and 220. Portions of the island 202 are placed below the well 116 and form a p-lower body material portion 488. Part of the island 204 is also placed under the well 276 and constitutes N-lower body material portion 494. For regions 102, 104, 120, 126, 128, 250, 252, 254, 256 and 258 of IGFET 210W and regions 262, 264, 280, 286, 288, 290, 292, 294, 296 for IGFET 220W 298 is then formed as described above for IGFETs 210 and 220. The p-type single raft above the well 116 constitutes a p-type upper body material portion 490, the portion of which is on the outer side of the p+ pocket portion 120 constitutes the p-upper body material remainder 492. The n-type single turn above the well 276 constitutes an n-type upper body material portion 496, the portion of which is on the outer side of the n+ pocket portion 280 constitutes the n-upper body material remainder 498.

The vertical bulk material doping dose curve below the bungee is a sub-steep IGFET due to the step change of the dopant concentration of the bulk material.

The vertical doping dose curve of the asymmetric IGFET constructed according to the present invention below the drain can be made hyperaburpt in a manner different from the concentration of dopants defined by the conductivity type of the bulk material. _T gradually decreases from the position of the maximum well dopant concentration upward to the drain to a maximum of 10%. In particular, the vertical doping dose curve below the drain can be made sub-steep by providing a body material for the underside of the drain to include (a) a drain abutment, wherein the conductive pattern Defining a dopant to a majority of the uniform first concentration; and (b) a distal portion of the drain directly disposed on the lower layer, wherein the conductivity pattern defines the dopant to be at a substantially uniform second concentration, The conductivity pattern is significantly larger than the conductivity pattern of the contiguous portion of the drain, which is typically at least 10 times greater.

The conductivity pattern defines the concentration of the dopant to be a step from the portion of the material of the distal end of the body of the drain that extends upwardly through the portion of the body of the body adjacent to the body of the body to the drain. The level is reduced, usually to a maximum of 10%. One of the n-channel IGFETs providing this second type of buck-under-hierarchy steep doping dose curve and the asymmetric channel region doping characteristics of the inventive construct A or A' is generally referred to herein as inventive construction E.

Figure 67 summarizes the vertical doping dose curves for the transmissive drains of the n-channel IGFETs constructed to construct A/A', B, and E and to the underlying body regions. More particularly, to a structure for A / A ', B, and E are each an n-channel of IGFET of, as a function of depth y along through one of the vertical drain line absolute dopant concentration of N _T The change is shown in Figure 67. Similar to those shown in Figure 56, along the transmission total p-type dopant concentration of the drain of a vertical line of the n-channel IGFET configured of E N _T based on the semiconductor surface from a depth y _ST to be uniform in density value of N _B0 , the depth y _ST is equal to the bungee depth y _D plus the distance y _d0 . The p-type dopant concentration N _T of the drain from the depth y _D to the depth y _ST adjoining the body material portion extending the distance y _d0 is thus N _B0 . The distance y _d0 is typically from 0.05 to 1.0 microns, typically 0.1 microns.

The depth y _ST, N _T the absolute dopant concentration level changes made to step from N _B0 and up to a value greater than that of N _B1 N _B0, which is typically greater than at least 10% N _B0. The concentration N _T of the portion of the distal end body material extending downward from the depth y _ST is tied to the value N _B1 , and beyond the outward to a certain depth, the concentration of the p-type dopant in the bulk material does not have Any significant influence on the characteristics of the bungee-body junction, especially the drain-to-body capacitance C _DB . Therefore, the p-type dopant concentration of the bulk material in the direction across N _T system from which the p-type dopant concentration is equal to N _T N drain electrode _B1 of the distal end portion of the body to which material is p-type dopant concentration _T N is equal to N pole adjoining body-material portion made step _B0 and the drain stage is reduced (typically at least 10%) and followed until the drain - body junction is maintained at N _B0.

Figure 68a illustrates an asymmetric n-channel IGFET 500 constructed in accordance with the present invention to implement Configuration E, thereby being particularly suitable for high speed analog applications. IGFET 500 is configured substantially identical to IGFET 170 of Figure 18a except that p-type body material 108 is comprised of a heavily doped lower subsurface portion 502 extending therefrom to an upper surface abutment portion 504 of one of the upper semiconductor surfaces. The p+ subsurface body material portion 502 is placed under the source 102, the drain 104, and the channel region 106. The upper boundary (top) of the subsurface body material portion 502 is at a depth y _ST below the upper semiconductor surface. The depth y _ST is usually not more than 10 times the drain depth y _D , preferably not more than 5 times. Where it is closest to the source 102 and the drain 104, the subsurface portion 502 is thus generally less than 10 times deeper than the source 102 and the drain 104 below the upper semiconductor surface, preferably not exceeding 5 times deep.

The p-type surface abutting body material portion 504 overlies and meets the p+ sub-surface body material portion 502. The channel region 106 is a surface that abuts a portion of the body material portion 504. The p+ pocket 120 (here shallower than the source 102) is also a portion of the surface that abuts the body material portion 504. The item 124 of Figure 68a is a surface that abuts the lightly doped material of the body material portion 504, i.e., a section of the portion 504 that is outside the pocket portion 120.

The p-type dopant of the portion below the drain 104 that abuts the portion of the body material portion 504 exhibits a concentration that is substantially equal to a majority of N _B0 . A typical value for a concentration N _B0 is 5 x 10 ¹⁵ atoms/cm 3 . The p-type dopant in the section of the sub-surface body material portion 502 below the surface of the body material portion 504 and thus below the drain 104 presents a uniform, higher concentration equal to most of N _B1 . N _B1 value of N _B0 is generally at least 10 times, preferably N _B0 is at least 20 times, more preferably N _B0 is at least 40-fold, typically 100-fold of proximity N _B0.

Figure 68b illustrates another asymmetric long n-channel IGFET 510 constructed in accordance with the present invention to implement Configuration E, particularly for high speed analog applications. IGFET 510 is configured identically to IGFET 500 except that a primary surface electrical insulating layer 512, typically composed primarily of yttria, contacts subsurface body material portion 502 along its bottom surface. In IGFET 510, the p-type dopant of the sub-surface body material portion 502 disposed below the drain 104 from the depth y _ST down to the sub-surface electrical insulating layer 512 is mostly uniformly doped at concentration N. _B1 .

The sub-steep vertical doping dose curve of the lower layer body material 108 of the IGFETs 500 and 510 below the drain 104 is understood by means of Figures 69a to 69c (collectively "Figure 69"), Figures 70a to 70c (collectively "Figure 70"), and Figs. 71a to 71c (collectively "Fig. 71") are promoted. 69 summarizes the dopant concentration of an example of IGFET 500 or 510 along vertical line 130 through source 102, similar to FIG. An exemplary dopant concentration along the vertical lines 132 and 134 through the channel region 106 is presented in FIG. 70, which is summarized similar to FIG. 71 summarizes the dopant concentration of an example of IGFET 500 or 510 along vertical line 136 through drain 104, similar to FIG.

Figures 69a, 70a, and 71a illustrate the pocket portion 120 and portions of the body material portion 504 that form the source 102, the drain 104, the sub-surface body material portion 502, and the surface abutment along the vertical lines 130, 132, 134, and 136. The concentration N _I of the individual semiconductor dopants of the remainder 124 of 504. Along lines 130, 132, 134 and 136 to the total area 102,104,502,120 and p-type dopant concentration of the total n-type dopant in the N _T 124 depicted in FIG. 69b, 70b and 71b. Figures 69c, 70c and 71c depict the net dopant concentration N _N along lines 130, 132, 134 and 136.

The curves/curves segments 102', 102", 102*, 104', 104", 104*, 120, 120", 120*, 124', 124" and 124* of Figures 69-71 are associated with respectively The meanings described above in Figures 8 to 10. The curve 502' of Figures 69a, 70a and 71a refers to the concentration N _I of the n-type dopant used to form the sub-surface body material portion 502 along the vertical lines 130, 132, 134 and 136. The curved section 502" of Figures 69b, 70b and 71b represents the concentration N _T of the total n-type dopant along the lines 130, 132, 134 and 136 of the sub-surface portion 502. The curves of Figures 69c, 70c and 71c Segment 502* refers to the concentration N _N of the net n-type dopant along portion lines 502 along lines 130, 132, 134 and 136.

Referring to Figure 71a, the p-type dopant of the bulk material 108 portion of the IGFET 500 or 510 below the drain 104 has two major components, referred to herein as "lower" p-type dopants and "above". P-type dopant. As indicated by curve segment 502', the lower p-type dopant is at a high fixed concentration N _B1 at subsurface body material portion 502. As indicated by curve 124', the upper p-type dopant is at a low fixed concentration N _B0 at the surface adjacent to the remainder 124 of the body material portion 504. The upper p-type dopant is also present at the drain 104 as indicated by the extension of the curve 124' entering the area covered by the curve 104'.

The total p-type dopant of the bulk material 108 portion of the IGFET 500 or 510 below the drain 104 is indicated by the combination of the curved segments 502" and 124" of Figure 71b. The composition changes from the curve 502 "/ 124" is shown, in a concentration of 108 part by below drain 104 of body material of the total p-type dopant in the N _T based on subsurface body across from the concentration of N _B1 The material portion 502 substantially undergoes a one-step reduction with respect to the upper body material portion 124 of the concentration N _B0 and is then maintained at the concentration N _B0 for further upward movement to the drain 104 . Given the generally high concentration N _B1 N _B0 is at least 10-fold, 108 are in the lower part of the drain 104 of body material of the total p-type dopant concentration N _T from subsurface body-material portion 502 is a permeable material portion 124 moves up to the drain 104, while the second steepest decreases to a maximum of 10%.

As described above, the high concentration N _B1 system preferably N _B0 is at least 20 times, more preferably at least 40 times the N _B0. Therefore, the steep decrease in the concentration N _T of the total p-type dopant in the portion of the bulk material 108 below the drain 104 is preferably at most 20%, more preferably at most 40%.

Figure 71c shows a vertical variation in the concentration N _N of the net p-type dopant in the bulk material 108 portion below the drain 104 of the IGFET 500 or 510, as represented by the combination of the curved segments 502* and 124*. The concentration N _T of the total p-type dopant that is similar to the portion of the bulk material 108 below the drain 104, except for the concentration of the net p-type dopant N _N of the bulk material 108 portion below the drain 104 The drain depth y _D (ie, at the drain-body junction 112) drops to zero. As with the aforementioned IGFET of the present invention, the sub-steep doping profile of the bulk material 108 portion below the drain 104 reduces the parasitic capacitance along the drain-body junction 112 of the IGFET 500 or 510. The increased analog speed is thus achieved for IGFETs 500 and 510.

Turning to the vertical dopant profile below the source 102 of the reference IGFET 500 or 510, the curved segments 502' and 124' of Figure 69a have substantially the same shape as Figure 71a. Although the curve 120' appears in FIG. 69a, the total p-type dopant of the portion of the bulk material 108 below the source 102 is composed of a p-type dopant below and below the respective concentrations N _B0 and N _B1 because In the example of Figures 68a and 68b, the p-type pocket 120 is shallower than the source 102. A portion of the combined curve segments 502" and 124" at a depth greater than the source depth y _S of FIG. 69b is shaped substantially the same as the combined curve segment 502 at a depth greater than the drain depth y _D of FIG. 71b" Part of /124". Concentration is based on 108 part by the concentration of those portions of body material 108 below source electrode 102 of the total p-type dopant N _T are the same in most of the drain electrode 104 below the body material of the total p-type dopant N _T changes steeply. Therefore, the parasitic capacitance along the source-body junction 110 is also reduced, thereby further enhancing the analog performance of the IGFET 500 or 510.

Similar to the IGFET 100 of FIG. 6, the p-type pocket portion 120 of the IGFET 500 or 510 can be modified to extend deeper below the upper semiconductor surface than the source 102 and the drain 104. In this case, the p-type pocket dopant in pocket portion 120 causes the bulk material below the source electrode 102 by portion 108 of the concentration of N _T the total p-type dopant to the source in the - body junction 110 Below it is some rise and therefore just below the bottom of the source 102 is somewhat larger than N _B0 . The parasitic capacitance along the source-body junction 110 is higher than the examples of Figures 68a and 68b, but is still reduced by proper selection of doping and depth for the pockets 120. This is also to enhance the analog performance of IGFET 500 or 510. Compared to the source 102 and the drain 104, modifying the pocket portion 120 to extend deeper below the upper semiconductor surface does not have any significant effect on the drain characteristics of the IGFET 500 or 510 because it is substantially free of p-type pockets. The dopant is then located in the drain 104.

The channel region 106 of IGFET 500 or 510 is mostly the same as the channel region 106 of IGFET 170 of Figure 18a and is asymmetrically longitudinally doped. Since the dopant distribution of FIG. 7 and the related information described above with respect to FIG. 7 are applied to IGFET 170, this information is generally applied to IGFETs 500 and 510. Penetration is thus avoided by IGFETs 500 and 510. The channel length of IGFET 500 or 510 can be substantially reduced to convert it into a short channel device. In this case, the surface dopant profile of FIG. 12 and the associated information described above with respect to FIG. 12 are summarized for IGFETs 500 and 510.

Each of the S/D regions 102 or 104 of the IGFET 500 or 510 can be modified to consist of a main portion 102M or 104M and a lightly doped laterally extending portion 102E or 104E. Alternatively or additionally, each S/D region 102 or 104 of IGFET 500 or 510 may include a lightly doped lower portion 102L or 104L. In such cases, the dopant profiles presented in Figures 14, 16 and 17 and their associated information regarding their dopant profiles are summarized for use in IGFETs 500 and 510, respectively, in curves/curves segments 502', 502" Curves/curve segments 116' and 114', 116" and 114" and 116* and 114* are replaced with 502* instead of the cases of Figs.

Another complementary IGFET configuration suitable for mixed-signal applications and having a step change in dopant concentration of the bulk material

Figure 72a illustrates another complementary IGFET configuration constructed in accordance with the present invention to be particularly suitable for mixed signal applications. The complementary IGFET structure of Figure 72a is made of a doped germanium material, such as a bonded wafer. Electricity One of the gas insulating material patterned field regions 520 extends along the upper surface of the tantalum material to define a group of laterally separated semiconductor island portions, including island portions 522 and 524. Two asymmetric long channel IGFETs 530 and 540 are formed along the upper semiconductor surface at locations of islands 522 and 524, respectively.

IGFET 530 implements an n-channel device of IGFET 510 of Figure 68b. The source 102, the drain 104, and the channel region 106 are located on the island portion 522. The body material 108 of the IGFET 530 is comprised of <100> p-type single turns. A lower semiconductor layer 550 composed of a lightly doped <100> p-type germanium is placed under the insulating layer 512 and contacts the insulating layer 512 such that it is a primary surface layer. The field insulating region 520, which is typically a trench, is vertically separated from the sub-surface insulating layer 512.

IGFET 540 is essentially a p-channel device that is identical to n-channel IGFET 500 of Figure 68b and whose conductivity type is reversed. IGFET 540 thus has a heavily doped p-type source 562 and a lightly doped p-type drain 564 separated by a channel region 566 of n-type body material 568, the body material 568 being heavily doped underneath. The subsurface portion 572 is comprised of an abutment portion 574 that extends to an upper surface of one of the upper semiconductor surfaces. Source 562, drain 564, and channel region 566 are located on island portion 524.

The body material 568 is formed by a <100>n-type single crucible. The subsurface portion 572 of the n-type body material 568 extends over the p-lower semiconductor layer 550 and through an opening in the sub-surface insulating layer 512 to form a lateral pn junction 576 for the semiconductor layer 550. Subsurface body material portion 572 also forms a vertical pn junction 578 for p+ subsurface body material portion 102 of IGFET 530. A reverse bias is applied across the pn junction 578 to place the IGFET 530 and 540 are isolated from each other.

The n-type surface abuts the heavily doped pocket portion 580 of one of the body material portions 574 along the source 562 of the IGFET 540. The n+ pocket 580 causes the channel region 566 to be an asymmetrical longitudinal dopant gradation similar to the asymmetric longitudinal dopant grading of the channel region 106 of the IGFET 530. Item 584 is a surface that is adjacent to the lightly doped n-type remainder of body material portion 574. A gate dielectric layer 586, typically composed primarily of yttrium oxide, overlies the channel region 566. A gate electrode 588 is located above the gate dielectric layer 586 above the channel region 566. The gate electrode 588 portion extends over the source 562 and the drain 564. In the example of Figure 72a, the gate electrode 588 is composed of a very heavily doped p-type polyfluorene.

The n-type dopant layer in the subsurface body material portion 572 is present in a majority of the uniform concentration N _B0 '. The n-type dopant adjacent the surface of the body material portion 574 below the drain 564 is the segment present at a majority of the uniform concentration N _B1 ' greater than N _B0 '. Similar to the concentration N _B1 and N _B0, concentration N _B1 'typically N _B0' is at least 10 times, preferably N _B0 'is at least 20 times, more preferably N _B0' is at least 40 times, typically N _B0 ' It is close to 100 times. In part of the bulk material 568 below the drain 564, the IGFET 540 thus has a sub-steep doping dose curve that summarizes the properties of the bulk material 108 portion of the IGFET 530 that is below the drain 104. The vertical doping dose curve for the portion of bulk material 568 of IGFET 540 below source 562 is also a vertical doping dose curve that is quite similar to the portion of bulk material 108 of IGFET 530 below source 102. Thus, IGFET 540 has a reduced parasitic capacitance along its drain-body and source-body junctions.

Figure 72b illustrates a variation of the complementary IGFET configuration of Figure 72a. In the variation of Fig. 72b, the field insulating region 520 is provided with an electrically insulating extension portion 590 which is typically trenched to the subsurface insulating layer 512. The combination of field insulating region 520 and insulating extension portion 590 laterally surrounds the subsurface body material portion 502 of IGFET 530. This isolates IGFETs 530 and 540 from each other in a dielectric lateral direction.

The conductivity pattern of the complementary IGFET configuration of Figures 72a and 72b can be reversed. The n-type body material and the n-lower semiconductor layer respectively corresponding to the p-type body material 108 and the p-lower semiconductor layer 550 are then <110>n-type single turns. The p-type body material corresponding to the n-type body material 568 is <110> p-type monoterpene.

Figure 72c depicts yet another variation of the complementary IGFET configuration of Figure 72a. Figure 72d depicts a corresponding variation of the complementary IGFET configuration of Figure 72b. In the variation of FIGS. 72c and 72d, the lower semiconductor layer 550 is replaced by a lower semiconductor layer 592 composed of a lightly doped <110>n-type germanium. The complementary IGFET configuration of Figures 72c and 72d is formed for the n-type body material 568 of the p-channel IGFET 540 by a <110>n-type single turn instead of a <100>n-type single turn. In the complementary IGFET configuration of Figures 72c and 72d, the p-type body material 108 for the n-channel IGFET 530 continues to be a <100> p-type single turn.

The conductivity pattern of the complementary IGFET configuration of Figures 72c and 72d can be reversed. In this case, both the p-type body material and the p-lower semiconductor layer corresponding to the n-type body material 568 and the n-lower semiconductor layer 592 are <100> p-type single turns, respectively. The n-type body material corresponding to the p-type body material 108 is <110>n-type monoterpene.

Fabrication of a complementary IGFET structure having another step change in dopant concentration of bulk material

The complementary IGFET structure of Figure 72a is fabricated in accordance with the following aspects of the present invention. A configuration is first provided wherein: (a) a primary surface semiconductor region consisting of a <100> p-type single germanium heavily doped with a high uniform concentration N _B1 is adjacent to the electrical insulating layer of the surface layer, (b) is low A lightly doped <100> p-type single germanium of uniform concentration N _B0 is formed by a surface adjacent to the semiconductor region adjacent to and overlying the sub-surface semiconductor region, and (c) is lightly doped <100> One of the p-type single turns consists of a lower semiconductor layer adjacent to and below the insulating layer of the sub-surface layer. The lightly doped lower semiconductor layer constitutes the p-lower semiconductor layer 550.

The initial configuration can be made, for example, by joining together two semiconductor wafers by forming an electrically insulating material of a sub-surface insulating layer therethrough. One of the wafers has a lightly doped <100> p-type single-turn substrate that forms the lower semiconductor layer 550. The other wafer has a <100> p-type single-turn substrate which is substantially uniformly doped to one of the concentrations N _B1 and N _{B0 ,} and an upper-layer lightly doped <100> p-type single-turn epitaxial layer. A semiconductor region adjacent to the surface of the subsurface semiconductor region is formed separately.

Field insulating region 520 forms an outer (upper) surface of the semiconductor region adjacent along the p-surface to define an island portion 522 for IGFET 530 and a location defining island portion 524 for IGFET 540. The field isolation region 520 can be partially extended to pass through the p-surface adjoining semiconductor region such that after completion of the complementary IGFET configuration shown in Figure 72a, the field insulation 520 extends deep to (but not fully transmissive) the p-type surface abutting body Material portion 504. Alternative In other words, the field insulation 520 can be extended to completely penetrate the semiconductor region adjacent to the p-surface and partially to the p+ sub-surface semiconductor region of the underlying layer. The portion of the semiconductor region adjacent to the p-surface of the island portion 522 constitutes a precursor to the body material portion 504 adjacent to the p-type surface. The lower portion of the p+ subsurface semiconductor region substantially constitutes the p+ subsurface body material portion 502.

At a position for the island portion 524, a cavity portion is formed to penetrate the semiconductor region adjacent to the p-surface, pass through the lower layer of the p+ sub-surface semiconductor region, and pass through the lower layer of the sub-surface insulating layer to face down to the p-lower semiconductor layer 550. The remaining portion of the sub-surface insulating layer constitutes the sub-surface insulating layer 512. The heavily doped <100>n-type monoterpene is epitaxially grown in the exposed portion of the lower semiconductor layer 550 at a uniform concentration of N _B1 ' to substantially form the n+ sub-surface body material portion 572. The lightly doped <100>n-type monoterpene is epitaxially grown at the sub-surface portion 572 of the cavity at a uniform concentration N _B0 ' to form a precursor to one of the body material portions 574 adjacent to the n-type surface. The body material portion 572 forms an island portion 524 with respect to the former body member 574.

The gate dielectric layers 126 and 586 are exposed to the precursor material portion 574 adjacent to the p-type surface adjacent to the p-type surface of the IGFET 530 and the body material portion 574 adjacent to the n-type surface of the IGFET 540, respectively. surface. Gate electrodes 128 and 588 are formed on gate dielectric layers 126 and 586, respectively. The n++ source 102, n++ drain 104 and p+ pocket 120 are formed in front of the body material portion 504 adjacent to the surface. The remainder of the p-type precursor for body material portion 504 then substantially constitutes portion 504 for IGFET 530. The p++ source 562, the p++ drain 564 and the n+ pocket 580 are also formed in the body material portion adjacent to the n-type surface. 574 before the drive. The remainder of the previous driver for the n-type surface abutting body material portion 574 is then also substantially configured to be portion 574 for IGFET 540. The operations involved in forming gate electrodes 128 and 588, n++ source 102, n++ drain 104, p+ pocket 120, p++ S/D regions 562 and 564, and n+ pocket portion 580 can be performed in a variety of sequences.

The complementary IGFET configuration of Figure 72b is identical to the complementary IGFET configuration of Figure 72a and is fabricated in accordance with the present invention except that the insulating extension portion 590 for the field insulating region 520 is formed in the p+ subsurface semiconductor region during the formation of the field insulating 520.

The complementary IGFET configurations of Figures 72c and 72d are fabricated in accordance with the present invention, respectively, in the same complementary IGFET configuration as Figures 72a and 72b, except that the lower semiconductor layer is replaced by a lightly doped <110>n-type single germanium. P-lower semiconductor layer 550. The lightly doped lower semiconductor layer is an n-lower semiconductor layer 592. The initial configuration of the complementary IGFET configuration used to form Figure 72c or 72d can be made in the same manner as the initial configuration used to create the complementary IGFET configuration of Figure 72a or 72b, except that the first described wafer has a slight The doped <110>n-type single-turn substrate is not a lightly doped <100> p-type single-turn substrate.

In addition, n+ times after the formation of the cavity portion is a semiconductor region adjacent to the p-surface adjacent, through the lower layer of the p+ sub-surface semiconductor region, and through the lower layer of the sub-surface insulating layer and down to the n-lower semiconductor layer 592 The bulk material portion 572 of the surface layer is epitaxially grown under the cavity below the semiconductor layer 592 for the heavily doped <110>n-type germanium at a concentration N _B1 '. For the n-surface adjacent body material portion 574, the precursor is then epitaxially grown in the n+ subsurface portion 572 of the cavity as a lightly doped <100>n-type single turn of concentration N _B0 '.

Changer

While the invention has been described with respect to the specific embodiments thereof, this description is intended to be illustrative only and not to limit the scope of the invention. For example, the semiconductor body and/or the gate electrodes 128, 288, 328, 368, and 588 can be replaced by other semiconductor materials. Alternative candidates include: tantalum, niobium alloys, and alloys such as Group 3a-5a of arsenic arsenide.

A metal telluride layer can be provided as the source 102 and 562, the drains 104 and 564, and the upper surfaces of the gate electrodes 128 and 588 of the IGFETs 530 and 540 constructed along the complementary IGFETs of Figs. 72a through 72d. Synthetic gate electrodes 128/258, 288/298, 328/338, 368/378 and/or Figs. 72a through 72d of IGFETs 210, 220, 230, 240, 380 and 390 of complementary IGFET constructions of Figs. 29 and 30 The gate electrode 128/588 of the IGFETs 530 and 540 of the complementary IGFET configuration may be replaced by a gate electrode consisting essentially of or substantially entirely of metal germanium, such as cobalt telluride or nickel telluride, doped The agent is provided on the telluride gate electrode to control its operational function. A variety of modifications can be made by those skilled in the art without departing from the true scope of the invention, as defined by the appended claims.

20, 60, 70, 100, 100V, 140, 140V, 150, 150V, 160, 160V, 170, 170V, 180, 180V, 190, 190V, 210, 210W, 220, 220U, 220V, 210W, 220W, 230, 240, 380, 390, 480, 500, 510, 530, 540‧‧‧Insulated Gate Field Effect Transistor (IGFET)

22, 200, 520‧ ‧ field insulation area

24, 202, 204, 206, 208, 522, 524‧ ‧ island

26, 28, 300, 302, 340, 342‧‧‧ source/drainage (S/D) areas

26E, 28E‧‧‧ lateral extension

26M, 28M‧‧‧ main part

26E*, 26M*, 28E*, 28M*, 30*, 34”, 36”, 38”, 40”, 40*, 42”, 42*, 58”, 62”, 102', 102”, 102* , 102E', 102E", 102E*, 102L', 102L", 102L*, 102M', 102M", 102M*, 104', 104", 104*, 104E', 104E", 104E*, 104L', 104L ", 104L*, 104M', 104M", 104M*, 106", 106*, 106M*, 114', 114", 114*, 116', 116", 116*, 118", 120', 120", 120*, 120M*, 124', 124", 124*, 192', 198', 198", 198*, 262', 262", 262*, 264', 264", 264*, 266*, 276' , 276", 276*, 280', 280", 280*, 302", 302*, 302E*, 302M*, 304", 304*, 304E*, 304M*, 306*, 316", 316*, 318 ", 318*, 320", 320*, 322", 322*, 394', 394", 394*, 450, 452, 454, 460, 462, 464, 502', 502", 502*‧‧‧ curves (segments)

30, 106, 266, 306, 346, 566‧‧‧ passage area

32, 108, 268, 308, 348, 568‧‧‧ body materials

34, 114, 192, 488, 494‧‧‧ lower

36, 116, 276, 316, 356‧‧ ‧ wells

38, 118, 196, 278, 318, 358, 490, 496 ‧ upper

40, 42, 120, 280, 320, 322, 360, 362, 580‧‧ ‧ bags

44, 126, 286, 326, 366, 586‧‧ ‧ gate dielectric layer

46, 128, 258, 288, 298, 328, 338, 368, 378, 588 ‧ ‧ gate electrodes

48, 50, 250, 252, 290, 292, 330, 332, 370, 372 ‧ ‧ spacers

52, 54, 56, 254, 256, 258, 294, 296, 298, 334, 336, 338, 374, 376, 378 ‧ ‧ metal telluride layers

102, 262, 302, 342, 562‧ ‧ source

102E, 262E, 302E, 342E‧‧‧ source extension

102EP, 262EP‧‧‧Precursor source extension

102L‧‧‧ below the source part

102M, 262M, 302M, 342M‧‧‧ main source parts

104, 264, 304, 344, 564‧‧ ‧ bungee

104E, 264E, 304E, 344E‧‧‧ bungee extension

104EP, 264EP‧‧‧Precursor bungee extension

104L‧‧‧ below the pole part

104M, 264M, 304M, 344M‧‧‧ main bungee part

110, 396‧‧‧ source-body junction

110 ^# , 112 ^# , 194 ^# , 396 ^# , 398 #‧‧‧ The location of the junction

112, 398‧‧‧Bungee-body junction

114P‧‧‧ Epilayer

118P, 278P, 318P, 324P, 358P‧‧‧ front part of the body material

120P, 280P‧‧‧ Front Bag Department

124, 198, 324, 364, 394, 492, 498‧‧‧ the remainder of the ontology material

128P, 288P, 328P, 368P‧‧‧ front gate electrode

130, 130U, 132, 132U, 134, 134U, 136, 136U‧‧‧ vertical lines

194, 576, 578‧ ‧ pn junction

276P, 316P, 356P‧‧‧ Precursor

278Q, 358Q‧‧ ‧ p-part of the island

302EP, 304EP, 342EP, 344EP‧‧‧Precursor S/D extensions

262M, 264M, 342M, 344M‧‧‧ main S/D parts

320P, 322P, 360P, 362P‧‧‧Pre-drive ring pocket

342E, 344E‧‧‧S/D extension

382, 392‧‧‧ isolation layer

402‧‧‧Shield Oxide

404, 406, 408, 410‧‧‧ photoresist mask

412, 414, 416, 430, 432‧‧ dielectric layers

418, 420, 422, 424, 434, 436 ‧ ‧ photoresist mask

440, 442, 446, 448‧‧‧ current source

444‧‧‧voltage source

470‧‧‧ source contact

472‧‧‧汲 contact

482, 512‧‧‧ surface insulation

484, 550, 592‧‧‧ lower semiconductor layer

486, 590‧ ‧ insulation extension

502, 572‧‧‧ surface material parts

504, 574‧‧‧ surface adjacent to the body material portion

584‧‧‧lightly doped n-type remainder

1 is a front cross-sectional view of a prior art symmetric long n-channel IGFET.

2 is a graph of net dopant concentration along the upper semiconductor surface for the IGFET of FIG. 1 as a function of the longitudinal distance from the center of the channel.

Figures 3a and 3b are graphs of absolute dopant concentrations along the vertical lines passing through the source/drain regions for the two different well doping conditions of the IGFETs of Figures 1, 4a, and 4b. A function of depth.

Figures 4a and 4b are front cross-sectional views of prior art asymmetric long and short n-channel IGFETs, respectively.

Figures 5a and 5b are graphs of net dopant concentration along the upper semiconductor surface for the respective IGFETs of Figures 4a and 4b as a function of the longitudinal distance from the center of the channel.

6 is a front cross-sectional view of an asymmetric long n-channel IGFET constructed in accordance with the present invention, thereby having a semiconductor well like the same conductivity type of semiconductor material placed directly underneath.

Figures 7a through 7c are graphs of the individual, absolute, and net dopant concentrations along the upper semiconductor surface of the IGFET of Figures 6, 18a, 68a, or 68b as a function of longitudinal distance.

Figures 8a through 8c are graphs of the individual, absolute, and net dopant concentrations of the IGFET of Figure 6, 11, or 13 along a vertical line through the source as a function of depth.

Figures 9a through 9c are graphs of the individual, absolute, and net dopant concentrations of a pair of vertical lines along the pass channel region of the IGFET of Figures 6, 11, 13, or 15, as a function of depth.

Figures 10a to 10c are IGFETs of Figures 6, 11, 13, 18a, or 18b A plot of the individual, absolute, and net dopant concentrations along the vertical line through the drain as a function of depth.

Figure 11 is a front cross-sectional view of an asymmetric short n-channel IGFET constructed in accordance with the present invention, thereby having a semiconductor well having the same conductivity pattern as the semiconductor material directly placed underneath.

Figures 12a through 12c are graphs of the individual, absolute, and net dopant concentrations along the upper semiconductor surface for the IGFET of Figure 11, as a function of longitudinal distance.

13 is a front cross-sectional view of another asymmetric long n-channel IGFET constructed in accordance with the present invention, thereby having a semiconductor well like the same conductivity type of semiconductor material placed directly underneath.

Figures 14a through 14c are graphs of the individual, absolute, and net dopant concentrations along the upper semiconductor surface of the IGFET of Figures 13, 15, 18b, or 18c as a function of longitudinal distance.

15 is a front cross-sectional view of yet another asymmetric long n-channel IGFET constructed in accordance with the present invention, thereby having a semiconductor well like the same conductivity type of semiconductor material placed directly underneath.

Figures 16a through 16c are graphs of the individual, absolute, and net dopant concentrations of the IGFET of Figure 15 along a vertical line extending through the source as a function of depth.

Figures 17a through 17c are graphs of the individual, absolute, and net dopant concentrations of the IGFET of Figure 15 or 18c along a vertical line extending through the drain as a function of depth.

Figures 18a to 18c are three separate lengths constructed in accordance with the present invention. A front cross-sectional view of a channel IGFET whereby a semiconductor well having the same conductivity pattern as the semiconductor material directly placed underneath.

Figures 19a through 19c are graphs of the individual, absolute, and net dopant concentrations of the IGFET of Figure 18a or 18b along a vertical line extending through the source as a function of depth.

Figures 20a through 21c are graphs of the individual, absolute, and net dopant concentrations of the IGFET of Figure 18c along a vertical line extending through the source as a function of depth.

21 is a front cross-sectional view of an asymmetric long n-channel IGFET constructed in accordance with the present invention, thereby having a semiconductor well like the same conductivity type of semiconductor material placed directly underneath.

Figures 22a through 22c are graphs of the individual, absolute, and net dopant concentrations along the upper semiconductor surface of the IGFET of Figure 21 as a function of longitudinal distance.

Figures 23a through 23c are graphs of the individual, absolute, and net dopant concentrations of the IGFET of Figure 21 or 25 along the vertical line through the source as a function of depth.

Figures 24a through 24c are plots of individual, absolute, and net dopant concentrations along the vertical line through the drain of the IGFET of Figures 21, 25, 27a, or 27b as a function of depth.

Figure 25 is a front cross-sectional view of another asymmetric long n-channel IGFET constructed in accordance with the present invention, thereby having a semiconductor well for the opposite conductivity pattern of the semiconductor material directly placed underneath.

Figures 26a to 26c are directed to the IGFET of Figure 25 or 27b. A plot of the individual, absolute, and net dopant concentrations of the semiconductor surface as a function of longitudinal distance.

27a and 27b are front cross-sectional views of two separate long n-channel IGFETs constructed in accordance with the present invention, thereby having a semiconductor well for the opposite conductivity pattern of the semiconductor material directly placed underneath.

Figures 28a through 28c are graphs of the individual, absolute, and net dopant concentrations of the IGFET of Figure 27a or 27b along a vertical line extending through the source as a function of depth.

Figures 29.1 and 29.2 are front cross-sectional views of two portions of a complementary IGFET semiconductor construction constructed in accordance with the present invention.

30.1 and 30.2 are front cross-sectional views of two portions of another complementary IGFET semiconductor construction constructed in accordance with the present invention.

31a to 31o, 31p.1 to 31r.1, and 31p.2 to 31r.2 are front cross-sectional views representing the steps of fabricating the complementary IGFET semiconductor construction of Figures 29.1 and 29.2. The steps of Figures 31a through 31o are applied to the structural portions shown in Figures 29.1 and 29.2. Figures 31p.1 to 31r.1 present further steps leading to the construction of Figure 29.1. Figures 31p.2 to 31r.2 present further steps leading to the construction of Figure 29.2.

32a through 32c are front cross-sectional views showing the steps of an alternative to the step of Fig. 31e in accordance with the present invention for fabricating a variant of the complementary IGFET semiconductor construction of Figs. 29.1 and 29.2, beginning with a repeating diagram. The construction of Figure 31d of 32a.

Figures 33a to 33f are front cross-sectional views showing the steps of another alternative to the steps of Figures 31c to 31f according to the present invention for making a drawing A variation of the complementary IGFET semiconductor construction of 29.1 and 29.2 begins with repeating the configuration of Figure 31b of Figure 33a.

Figure 34 is a front cross-sectional view of an asymmetric long p-channel IGFET constructed in accordance with the present invention so as to have a semiconductor well portion fabricated in accordance with the present invention having an opposite conductivity pattern disposed directly beneath the underlying semiconductor material. A compensated n-type dopant is not implanted into the semiconductor material as above the initially defined well. Asymmetric p-channel IGFETs fabricated according to the processes of Figures 31a to 31o, 31p.1 to 31r.1, and 31p.2 to 31r.2 and using the alternative steps of Figures 32a to 32c or Figures 33a to 33f An implementation of a p-channel IGFET.

Figures 35a through 35c are graphs of the individual, absolute, and net dopant concentrations along the upper semiconductor surface for the IGFET of Figure 34 as a function of longitudinal distance.

Figures 36a through 36c are graphs of the individual, absolute, and net dopant concentrations of the IGFET of Figure 34 along a vertical line through the source as a function of depth.

Figures 37a through 37c are graphs of the individual, absolute, and net dopant concentrations of a pair of vertical lines along the transmission channel region of the IGFET of Figure 34 as a function of depth.

Figures 38a through 38c are plots of individual, absolute, and net dopant concentrations along the vertical line through the drain of the IGFET of Figure 34 as a function of depth.

Figures 39 and 40 are separate computer simulations for (i) an asymmetric short n-channel IGFET constructed in accordance with the present invention, and (ii) a reference A three-dimensional plot of the net dopant concentration of a symmetric short n-channel IGFET as a function of depth and longitudinal distance.

Figures 41 and 42 present plots of dopant profiles for the respective computer-simulated IGFETs of Figures 39 and 40 as a function of depth and longitudinal distance from the source locations.

Figure 43 is a graph of net dopant concentration for the computer-simulated IGFETs of Figures 39 and 40 as a function of the longitudinal distance from the source position.

Figures 44a and 44b are graphs of the absolute and net dopant concentrations for the computer-simulated IGFETs of Figures 39 and 40 as a function of the depth of a pair of vertical lines passing through the source and the drain, respectively.

Figures 45a and 45b are plots of line conductance and line drain current for critical and saturation conditions for the computer-simulated IGFETs of Figures 39 and 40, respectively, as a function of gate-to-source voltage.

Figures 46a and 46b are plots of line conductance and line drain current for critical and saturation conditions, respectively, as a function of gate-to-source voltage, computer simulation for (i) generalization corresponding to the figure An inventive asymmetric long n-channel IGFET of the short channel IGFET of the invention of 39 and (ii) an asymmetrical long n-channel IGFET summarizing a reference to the short channel IGFET of the reference of FIG.

Figure 47 is a computer simulation of (i) the IGFET of the invention of Figure 39, (ii) the reference IGFET of Figure 40, and (iii) the reference symmetry short of one of the other one of the anti-penetration implants. A plot of the channel IGFET branch line drain current density as a function of gate to source voltage.

Figure 48 is a line diagram of the computer simulated IGFET of Figures 39 and 40. A plot of the pole current as a function of the gate to source voltage.

Figure 49 is a circuit diagram of an n-channel IGFET with associated parasitic capacitance.

Figure 50 is a circuit diagram of a small signal model of the n-channel IGFET and associated parasitic capacitance of Figure 49.

Figures 51a through 51c are circuit diagrams of a single IGFET amplifier configured in a common source, a common gate, and a common drain configuration, respectively.

Figure 52 is a circuit diagram of a single IGFET amplifier configured in a common source, shorted output configuration.

Figure 53 is a circuit diagram of a small signal model of the amplifier of Figure 52.

Figure 54 is a graph of net dopant concentration for three different p-type dopant profiles as a function of distance from the pn junction.

Figure 55 is a graph of the depletion layer capacitance for the three dopant distribution models of Figure 54 as a function of reverse bias.

Figure 56 is a graph of the net bulk dopant concentration for a model of a junction capacitor as a function of the distance from the pn junction with the lighter doped side having a dopant concentration One of the one-step changes is a doping dose curve.

Figure 57 is a graph of the junction capacitance of the junction capacitor modeled in Figure 56 as a function of reverse bias.

Figures 58a and 58b are synthetic front cross-sectional views/graphs of dopant profiles for respective asymmetric short and long n-channel IGFETs constructed in accordance with the present invention as one of the depth and longitudinal distance from the center of the channel function.

Figure 59 is a plot of line-to-body capacitance for the computer-simulated IGFET of Figures 39 and 40 as a function of drain-to-body voltage.

Figure 60 is a plot of line source to body capacitance for the computer simulated IGFET of Figures 39 and 40 as a function of source to body voltage.

Figure 61 is a graph of the cutoff frequency for the computer-simulated IGFET of Figures 39 and 40 and the other inventive IGFET of Figure 63 as a function of the line drain current.

Figure 62 is a graph of cutoff frequency as a function of line drain current, computer simulation for (i) an asymmetrical long n-channel IGFET corresponding to the short channel IGFET of the invention of Figure 39, ( Ii) a reference symmetric long n-channel IGFET corresponding to the short channel IGFET of FIG. 40, and (iii) another inventive asymmetric long n-channel IGFET corresponding to the short channel IGFET of another invention of FIG. .

Figure 63 is a front cross-sectional view of another computer-simulated asymmetric short n-channel IGFET constructed in accordance with the present invention.

Figure 64 is a graph of net dopant concentration for the computer-simulated IGFETs of Figures 39 and 63 as a function of the longitudinal distance from a source location.

Figure 65 is a graph of threshold voltage as a function of channel length for (i) an asymmetric n-channel IGFET constructed in accordance with the present invention, (ii) having a ring along each source/drain region The reference portion of the pocket is a symmetric n-channel IGFET, and (iii) it does not have a reference symmetric n-channel IGFET along the ring pocket portion of each source/drain region.

Figure 66 is a front cross-sectional view of yet another complementary IGFET semiconductor construction constructed in accordance with the present invention.

Figure 67 is a graph of absolute dopant concentration as a function of depth for (i) two asymmetric n-channels constructed in accordance with the present invention. IGFET, and (ii) a reference symmetric n-channel IGFET.

Figures 68a and 68b are front cross-sectional views of two separately asymmetric long n-channel IGFETs constructed in accordance with the present invention.

Figures 69a through 69c are graphs of the individual, absolute, and net dopant concentrations of the IGFET of Figure 68a or 68b along a vertical line through the source as a function of depth.

Figures 70a through 70c are graphs of the individual, absolute, and net dopant concentrations of a pair of vertical lines along the transmission channel region of the IGFET of Figure 68a or 68b as a function of depth.

Figures 71a through 71c are graphs of the individual, absolute, and net dopant concentrations of the IGFET of Figure 68a or 68b along a vertical line extending through the drain as a function of depth.

Figures 72a through 72d are front cross-sectional views of four additional separate complementary IGFET semiconductor configurations constructed in accordance with the present invention.

The same reference numerals are used in the drawings and the description of the preferred embodiments to represent the same or very similar items. The numerical part of the reference symbol with a single apostrophe ('), double apostrophe ("), asterisk (*), and pound sign ( ^# ) in the graph containing the graph is indicated by other schemas, respectively. The same labeled area or region. The "X" mark of the cross-sectional view of the IGFET providing one of the semiconductor well dopants indicates the location of the maximum concentration of the well dopant. Electrically insulating spacers (not shown) are possible. The sidewalls of the gate electrodes of the IGFETs located along Figs. 13, 15, 18b, 18c, 25, 27b, and 34 are dependent on how the IGFETs are fabricated.

In the dopant profile, "individual" dopants are concentrated Degree means the individual concentrations of the respective introduced n-type dopants and the respective introduced p-type dopants, and the "absolute" dopant concentration means the total n-type dopant concentration and p Type dopant concentration. The "net" dopant concentration in the dopant profile is the difference between the absolute (or total) n-type dopant concentration and the absolute (or total) p-type dopant concentration. The net dopant concentration is indicated as a net "n-type" when the absolute n-type dopant concentration exceeds the absolute p-type dopant concentration, and exceeds the absolute n-type dopant concentration at the absolute p-type dopant concentration. The indication is a net "p-type".

100‧‧‧Insulated Gate Field Effect Transistor (IGFET)

102‧‧‧ source

104‧‧‧汲polar

106‧‧‧Channel area

108‧‧‧ Body material

110‧‧‧Source-body pn junction

112‧‧‧Bungee-body pn junction

114‧‧‧ lower

116‧‧‧ Wells

118‧‧‧ upper

120‧‧‧ bag department

124‧‧‧The remainder of the ontology material

126‧‧ ‧ gate dielectric layer

128‧‧‧gate electrode

130, 132, 134, 136‧‧ vertical lines

Claims (100)

A configuration comprising a main field effect transistor (FET) comprising: a main channel region of a main body material having a semiconductor body of an upper semiconductor surface, the body material being sufficiently doped with a first conductivity type semiconductor a dopant as the first conductivity type; a pair of main source/drain (S/D) regions located along the upper semiconductor surface of the semiconductor body, laterally separated by the channel region, and In a second conductivity type opposite to the first conductivity type, the body material extends laterally below the S/D regions, and the dopant of the first conductivity type of the body material has a concentration Reducing a maximum of 10% from a major lower level surface layer body material moving up to a designated one of the S/D regions, the subsurface body material position being compared to the designated S/D region The surface of the upper semiconductor is not more than 10 times deep; a main gate dielectric layer overlies the channel region; and a main gate electrode overlies the gate dielectric layer above the channel region. The structure of claim 1, wherein the subsurface body material is no more than 5 times deeper than the designated S/D region below the upper semiconductor surface. The structure of claim 1 or 2, wherein the subsurface body material is located below most of the channel and the S/D zone. The structure of claim 1 or 2, wherein the concentration of the dopant of the first conductivity type of the bulk material is decreased from the position of the subsurface body material upward to the designated S/D region and is reduced to Up to 20%. For example, the structure of claim 1 or 2, wherein The channel region meets a remainder of the S/D regions along the upper semiconductor surface, and the concentration of the dopant of the first conductivity type of the bulk material meets the designation along the upper semiconductor surface in the channel region The S/D area is lower. The structure of claim 5, wherein the concentration of the dopant of the first conductivity type of the bulk material is compared to where the remaining S/D region is merged along the upper semiconductor surface in the channel region The channel region is at least 10% lower along where the upper semiconductor surface meets the designated S/D region. The structure of claim 5, wherein the concentration of the dopant of the first conductivity type of the bulk material is compared to where the remaining S/D region is merged along the upper semiconductor surface in the channel region The channel region is at least 20% lower along where the upper semiconductor surface meets the designated S/D region. The configuration of claim 5, wherein the designated S/D region extends deeper below the upper semiconductor surface than the remaining S/D region. The structure of claim 1 or 2, wherein the concentration of the dopant of the first conductivity type of the bulk material moves upward from the position of the subsurface body material to the designated S/D region substantially Experience a one-step reduction. The configuration of claim 1 or 2, wherein each S/D region comprises a main S/D portion and a laterally extending portion thereof which is lightly doped continuously to one of the main S/D portions, the channel The regions are terminated by the lateral extensions along the upper semiconductor surface. The structure of claim 1 or 2, wherein the remainder of the S/D regions comprises a main S/D portion and a laterally extending portion that is lightly doped continuously to one of the main S/D portions The channel region is terminated by a lateral extension of the designated S/D region along the upper semiconductor surface and the remaining S/D regions. The structure of claim 11, wherein each S/D region defines a semiconductor dopant along the upper semiconductor surface to reach a maximum net concentration, as compared to the remaining S/D region, at the designated S The /D area is lower. The structure of claim 12, wherein the maximum net concentration of the dopants in the S/D regions is at least 20% lower than the remaining S/D regions in the designated S/D region. . The structure of claim 1 or 2, wherein each S/D region includes a main S/D portion and a lightly doped lower portion located below the main S/D portion and The main S/D portion is continuous. The configuration of claim 1 or 2 further includes an additional FET of the same polarity of the main FET, the other FET comprising: another channel region of the body material; and a pair of other S/D regions Provided along the upper semiconductor surface in the semiconductor body, laterally separated by the other channel region, and being of the second conductivity type, the concentration of the dopant of the first conductivity type of the body material The position of the material of the other lower layer surface body is substantially the same as the position of the material material of the main subsurface layer is deeper than the position of the material of the other lower layer body is moved to the other S/D area upwards to be more than 10%. a lower surface of the upper semiconductor layer; a further gate dielectric layer overlying the other channel region; and a further control electrode covering another gate electrode over the other channel region Above the electrical layer. The structure of claim 15 wherein: the mains are merged along the upper semiconductor surface in the main channel region Where the remainder of the S/D region is desired, the concentration of the dopant of the first conductivity type of the bulk material is lower in the main channel region along the upper semiconductor surface where the designated main S/D region meets And a concentration of the dopant of the first conductivity type of the bulk material in the other channel region meeting one of the other S/D regions and meeting the other channel region The other part of the S/D area is about the same. An additional FET further comprising an opposite polarity of the main FET, the additional FET comprising: an additional channel region of the additional body material of the semiconductor body, the additional body material being sufficiently doped, as in the configuration of claim 1 or 2 a second conductivity type semiconductor dopant as the second conductivity type; a pair of additional S/D regions located along the upper semiconductor surface of the semiconductor body, laterally separated by the additional channel region, And in the first conductivity type, the dopant of the second conductivity type of the additional body material has a concentration that moves from an additional lower layer surface body material position upward to the additional S/D regions One of the specified S/D regions is reduced to a maximum of 10%, and the additional lower layer skin material position is no more than 10 times deep below the upper semiconductor surface compared to the specified additional S/D region; An additional gate dielectric layer overlying the additional channel region; and an additional gate electrode overlying the additional gate dielectric layer above the additional channel region. The structure of claim 17, wherein: the first conductivity of the main body material is compared to the remainder of the main S/D regions along the upper semiconductor surface along the upper channel region The concentration of the dopant of the type is lower in the main channel region along the upper semiconductor surface meeting the designated main S/D region; and the additional S is combined along the upper semiconductor surface in the additional channel region The remainder of the /D region, the concentration of the dopant of the second conductivity type of the additional body material is lower where the additional channel region meets the specified additional S/D region along the upper semiconductor surface. A third FET of the same polarity of the main FET, the third FET comprising: a third channel region of the main body material; and a pair of third S/D regions, as in the configuration of claim 17 Located along the upper semiconductor surface, the semiconductor body is laterally separated by the third channel region, and is of a second conductivity type, the concentration of the dopant of the first conductivity type of the main body material is from one The third lower layer skin material is moved upward to the respective third S/D regions and substantially fixed or changed to be 10% larger, and the third lower layer skin material position is approximately as deep as the main sub surface body material position. a third gate dielectric layer overlying the third channel region; and a third control electrode overlying the third gate dielectric layer above the third channel region on. The configuration of claim 19, further comprising a fourth FET of the same polarity of the additional FET and thus the opposite polarity of the main FET, the fourth FET comprising: a fourth channel region of the additional body material; a pair of fourth S/D regions located along the upper semiconductor surface and located in the semiconductor The body body is laterally separated from the fourth channel region and is of a first conductivity type, and the concentration of the dopant of the second conductivity type of the additional body material is moved upward from a fourth lower layer body material position to Each fourth S/D region is substantially fixed or changed to be greater than 10%, and the fourth lower layer body material is positioned approximately as if the additional subsurface body material is located deeper than the upper semiconductor surface; a fourth gate dielectric layer Overlying the fourth channel region; and a fourth gate electrode overlying the fourth gate dielectric layer above the fourth channel region. A configuration comprising a main field effect transistor (FET) comprising: a main channel region of a main body material having a semiconductor body of an upper semiconductor surface, the body material being a first conductivity type; a main source/drain (S/D) region located along the upper semiconductor surface of the semiconductor body, laterally separated by the channel region and being opposite one of the first conductivity types and a second conductivity pattern One of the body materials has a major well extending below the channel and the S/D region, the well being substantially defined by the first conductivity type of the main semiconductor well dopant and compared to the body material The upper layer and the lower layer are heavily doped, and the well dopant has a concentration that does not exceed the extent of the upper semiconductor surface along an S/D region of the S/D regions. A primary subsurface maximum is achieved at a position 10 times deep, such that all dopants of the first conductivity type of the bulk material have a concentration, and a subsurface maximum of the concentration of the dopant from the well The position moves up to the designated S/D area and decreases to Up to 10%; a primary gate dielectric layer overlying the channel region; and a primary gate electrode overlying the gate dielectric layer above the channel region. The structure of claim 21, wherein the position of the subsurface maximum of the concentration of the dopant at the well is no more than 5 times below the upper semiconductor surface compared to the designated S/D region. deep. The structure of claim 21 or 22, wherein a pocket portion of the body material extends along a remainder of the S/D regions to include a portion of the channel region up to the upper semiconductor surface, The pocket portion is defined by the first conductivity type semiconductor pocket portion dopant such that the pocket portion is heavily doped compared to an adjacent portion of the body material, as compared to the upper semiconductor surface in the channel region Where the remaining S/D regions are merged, the concentration of all dopants in the first conductivity pattern of the bulk material is lower in the channel region along the upper semiconductor surface meeting the designated S/D region. The structure of claim 23, wherein all of the dopants of the first conductivity type of the bulk material are compared to where the remaining S/D regions are joined along the upper semiconductor surface in the channel region. The concentration is at least 10% lower in the channel region along the upper semiconductor surface meeting the designated S/D region. The configuration of claim 23, wherein the designated S/D region extends deeper below the upper semiconductor surface than the remaining S/D region. The configuration of claim 21 or 22 further includes another FET of the same polarity of the main FET, the other FET comprising: another channel region of the body material; a pair of additional S/D regions, Located along the upper semiconductor surface, the semiconductor body is laterally separated by the other channel region, and is of a second conductivity type, one of the body materials extends in the other channel and the S Below the /D zone, the other well is essentially the other half of the first conductivity type The conductor well dopant is defined such that the other well is heavily doped compared to a lower portion of the bulk material, the other well dopant having a concentration along which the other A channel and a position below the S/D region reach a further surface maximum such that the concentration of all dopants in the first conductivity type of the bulk material is upward from the position of the other surface maximum Moving to each of the other S/D regions and changing to greater than 10%; a further gate dielectric layer overlying the other channel region; and a further gate electrode overlying the other Above the other gate dielectric layer above the channel region. A configuration comprising a main field effect transistor (FET) comprising: a main channel region of a main body material having a semiconductor body of an upper semiconductor surface, the body material being sufficiently doped with a first conductivity type semiconductor a dopant as the first conductivity type; a pair of main source/drain (S/D) regions located along the upper semiconductor surface of the semiconductor body, laterally separated by the channel region, and In the case of a second conductivity type opposite to the first conductivity type, the body material comprises (a) a major sub-surface body material portion disposed under the channel and the S/D region and at its closest Where the S/D regions are no more than 10 times deeper than the upper semiconductor surface than the S/D regions, and (b) a major surface abuts the body material portion, extending to the upper portion a semiconductor surface comprising the channel region and covering and meeting the subsurface body material portion, the dopant of the first conductivity type of the body material having a concentration from the subsurface body material portion facing upward Across the surface adjacent to the body material portion And the main experience is greater than 10% of the step reduction, and further through the surface abutment The body material portion moves upwardly to one of the S/D regions and is maintained at least 10% lower than the subsurface body material portion; a primary gate dielectric layer overlying the channel region And a primary gate electrode overlying the gate dielectric layer above the channel region. The structure of claim 27, wherein the subsurface body material portion is located closest to the S/D regions, and is not below the upper semiconductor surface of the S/D regions. More than 5 times deep. The structure of claim 27 or 28, wherein the first conductivity type of the body material is compared to the remainder of the S/D regions along the upper semiconductor surface in the channel region The concentration of the dopant is lower in the channel region along where the upper semiconductor surface meets the designated S/D region. The structure of claim 29, wherein the concentration of the dopant of the first conductivity type of the bulk material is compared to where the remaining S/D region is merged along the upper semiconductor surface in the channel region At least 10% lower at the channel region along the upper semiconductor surface meeting the designated S/D region. The structure of claim 27 or 28, wherein the concentration of the dopant of the first conductivity type is approximately fixed throughout the material portion of the subsurface body. An additional FET including the opposite polarity of the main FET, the additional FET comprising: an additional channel region of the additional body material of the semiconductor body, the additional material is fully doped, as in the configuration of claim 27 or 28 a two-conductivity type of semiconductor dopant as the second conductivity type; a pair of additional S/D regions located along the upper semiconductor surface a conductor body laterally separated by the additional channel region and having a first conductivity type, the additional body material comprising (a) an additional sub-surface body material portion disposed in the additional channel and the S/D region And, where it is closest to the additional S/D regions, extends no more than 10 times deep below the upper semiconductor surface compared to the additional S/D regions, and (b) an additional surface abutment a body material portion extending to the upper semiconductor surface, the additional channel region comprising and covering the additional sub-surface body material portion, the dopant of the second conductivity type of the additional body material having a a concentration that extends from the portion of the additional sub-surface body material upwardly to the additional surface abutting the body material portion and is primarily subjected to a stepwise reduction of up to 10%, and further moving upwardly from the additional surface abutting the body material portion via the One of the additional S/D regions specifies an additional S/D region that is at least 10% lower than the additional sub-surface body material portion; an additional gate dielectric layer overlying the additional channel region; And an additional gate electrode Overlying above the additional channel zone of the additional gate dielectric over the dielectric layer. The structure of claim 32, wherein: the first conductivity type of the main body material is compared to the remainder of the main S/D regions along the upper semiconductor surface along the upper channel region The concentration of the dopant is lower in the main channel region along the upper semiconductor surface meeting the designated main S/D region; and the additional S/ is combined along the upper semiconductor surface in the additional channel region. The remainder of the D region, the concentration of the dopant of the second conductivity type of the additional body material in the additional channel region along the upper semiconductor surface The place where the additional S/D area is specified is lower. The structure of claim 32, wherein: the concentration of the dopant of the first conductivity type is approximately fixed throughout the portion of the main sub-surface body material; and the concentration of the dopant of the second conductivity type is approximately A portion of the material that extends through the additional subsurface body. A method of fabricating a semiconductor structure, the method comprising: introducing a first conductivity type of a first semiconductor dopant to a semiconductor body to define a first conductivity type for a primary field effect transistor (FET) a primary well; defining a primary gate electrode for the FET, above a portion of the semiconductor body intended to be a primary channel region of the first conductivity type and being addressed by the primary gate dielectric layer Vertically separating; introducing a first semiconductor dopant opposite to the second conductivity type of the first conductivity type to the semiconductor body to define a second conductivity pattern laterally separated by the channel region for the FET a pair of primary source/drain (S/D) regions; and performing additional processing to complete fabrication of the FET such that (a) the semiconductor body has an upper semiconductor surface after completion of fabrication of the structure, (b) The channel region and the well portion are part of a first conductivity type and laterally extending below the main body material below the S/D regions, and (c) all semiconductor doping of the first conductivity type in the semiconductor body Miscellaneous agent Concentration, moving from a major underlying subsurface body-material location up to the designator of such one S / D zone is reduced to at most 10%, of the subsurface body-material location as compared to the finger The S/D region is defined to be no more than 10 times deep below the upper semiconductor surface. The method of claim 35, wherein the first conductivity type first dopant is introduced and an additional processing action is performed, the processing operation being performed under the condition that the first conductive after the fabrication of the structure is completed The concentration of all dopants in the pattern is moved upward from the subsurface body material location to the designated S/D region and reduced to a maximum of 10%. The method of claim 35, wherein after the fabrication of the structure, the subsurface body material is positioned no more than 5 times deeper than the designated S/D region below the upper semiconductor surface. The method of claim 35, wherein after the fabrication of the structure, the concentration of all dopants of the first conductivity type moves upward from the subsurface body material to the designated S/D region. Reduce to a maximum of 20%. The method of claim 35 or 36, further comprising: introducing a second conductivity type second semiconductor dopant to the semiconductor body to define a pocket portion along the remaining of the S/D regions Extending to its subsequently present upper surface such that after completion of the fabrication of the structure, (a) the pocket forms part of the body material and is more heavily doped than the adjacent material of the body material, and (b) All of the dopants of the first conductivity type of the bulk material have a meeting along the upper semiconductor surface in the channel region as compared to the remaining S/D regions along the upper semiconductor surface in the channel region The S/D zone is at a lower concentration. The method of claim 39, wherein after the fabrication of the structure is completed, the remaining portion is merged along the upper semiconductor surface in the channel region. Where the remaining S/D regions, the concentration of all dopants in the first conductivity pattern of the bulk material is at least 10% lower where the channel region meets the designated S/D region along the upper semiconductor surface. The method of claim 35, further comprising: introducing a first conductivity type of the second semiconductor dopant to the main body material to define a portion of the precursor material above the precursor of the first conductivity type, such that the precursor A portion of the body material overlies the well. The method of claim 35, wherein the portion of the semiconductor body (a) covers the well that exists after the action of directly introducing the first semiconductor dopant of the first conductivity type Above the portion, and (b) then being a second conductivity type; and a portion of the first dopant of the first conductivity type is diffused upwardly to the aforementioned portion of the semiconductor body during an additional processing operation Therefore, the substantial portion of the aforementioned portion of the semiconductor body that is not significantly affected by the first or second conductivity type after the first dopant is introduced into the first conductivity type is converted into The first conductivity type. The method of claim 35, wherein the introducing the second conductivity type of the first semiconductor dopant comprises: introducing a second conductivity type of the laterally extending portion of the semiconductor dopant through the lateral direction Extending a portion of the opening of the mask, passing through an upper surface of the semiconductor body, and a laterally spaced apart portion of the semiconductor body, the laterally extending portion of the mask, the gate electrode, and along Any material of the gate electrode acts as a dopant blocking shield; providing a spacer material to the lateral side of the gate electrode; Introducing a main portion of the semiconductor dopant of the second conductivity type through an opening of one of the main portions of the mask, through the subsequently existing upper surface of the semiconductor body, and to another portion of the semiconductor body that is laterally separated from each other, The main portion of the mask, the gate electrode and the spacer material are used as a dopant blocking shield. The method of claim 35, wherein the introducing the second conductivity type of the first semiconductor dopant comprises: performing one of the following (a) applying the second conductivity type to a main portion of the dose; a main portion of the semiconductor dopant is introduced to the semiconductor body and has a major portion of the average depth below the upper surface of the semiconductor body, and (b) a lower portion doses the lower portion of the second conductivity type semiconductor a dopant is introduced into the semiconductor body and to a lower portion of the lower surface of the semiconductor body below the upper surface, the main portion of the dose is greater than the lower portion of the dose, the lower portion of the average depth is greater than the main portion of the average depth; And performing the introduction of the other portion and the lower portion of the dopant to cause the main portion of the dopant to define a main S/D portion that is laterally separated from one of the S/D regions, respectively, such that the lower portion The dopant defines a lower S/D portion that is laterally separated from one of the S/D regions, such that the lower S/D portions are lighter than the main S/D portions. Miscellaneous, respectively placed under the main S/D portions and vertically perpendicular to the main S/D portions. The method of claim 35, wherein the act of introducing the first dopant of the first conductivity type comprises: introducing an additional first semiconductor dopant of the first conductivity type to the semiconductor a further well defining a first conductivity pattern of another FET for the same polarity of the primary FET; the gate electrode delimiting action includes defining another gate electrode for the other FET, Directly separating a portion of the semiconductor body of the other conductivity region of the first conductivity type and vertically separating it by another gate dielectric layer; introducing a first dopant of the second conductivity type The action includes introducing a second conductivity type of another first semiconductor dopant to the semiconductor body to define a pair of additional S of the second conductivity pattern laterally separated by the other channel region for the other FET /D zone; and the act of performing additional processing includes completing the fabrication of the other FET such that (a) the other channel region and the other well portion are part of the body material after the fabrication of the structure is completed, (b) The bulk material extends below the additional S/D regions, and (c) the first conductivity of the first conductivity type has a concentration that is upward from a further lower layer of the surface body material Move to each additional S/D area and be physically fixed or changed Larger than 10%, the further underlying subsurface body-material location approximately as the main subsurface body-material location and the depth below the surface of the semiconductor. The method of claim 35, wherein the method comprises introducing a second conductivity type second semiconductor dopant to a semiconductor body to define an additional FET for the opposite polarity of the main FET. An additional well portion of the two conductivity type; the gate electrode defining action includes defining an additional gate electrode for the additional FET, which is intended to be an additional channel region of the second conductivity type The semiconductor body is over a section of the semiconductor body and vertically separated by an additional gate dielectric layer; the method further includes introducing a first conductivity type second semiconductor dopant to the semiconductor body for the other FET Defining a pair of additional S/D regions of the second conductivity pattern laterally separated by the additional channel region; and performing the additional processing includes completing the fabrication of the additional FET such that after the fabrication of the structure is completed, (a) The additional channel region and the additional well portion are part of an additional body material that is a second conductivity type and extends below the additional S/D regions, and (b) the semiconductor body All of the semiconductor dopants of the two conductivity type have a concentration that moves from an additional lower layer surface body material position upward to one of the additional S/D regions to specify an additional S/D region and is reduced to a maximum of 10% The additional lower layer skin material location is no more than 10 times deeper than the designated additional S/D region below the upper semiconductor surface. The method of claim 46, wherein the act of introducing the first dopant of the first conductivity type comprises: introducing another first semiconductor dopant of the first conductivity type to the semiconductor body to define a third well portion of a first conductivity type of a third FET of the same polarity of the primary FET; the gate electrode defining action includes defining a third gate electrode for the third FET, which is intended as a conductive region of a third channel region over a portion of the semiconductor body and vertically separated by a third gate dielectric layer; the act of introducing a second conductivity type first dopant includes introducing First a second conductivity type of another first semiconductor dopant to the semiconductor body to define a pair of third S/D regions of a second conductivity pattern laterally separated by the third channel region for the third FET; And performing the additional processing includes completing the fabrication of the third FET such that after the fabrication of the structure is completed, (a) the third channel region and the third well portion are also portions of the primary body material, the primary body material extending over Below the third S/D regions, and (b) the concentration of all dopants of the first conductivity type is moved upward from a third lower layer skin material position to each of the third S/D regions Fixed or changed to greater than 10%, the third lower level skin material is positioned about the same depth as the primary subsurface body material location below the upper semiconductor surface. The method of claim 47, wherein the act of introducing the second dopant of the second conductivity type comprises introducing another second semiconductor dopant of the second conductivity type to the semiconductor body to define a fourth well portion of a second conductivity type of the fourth FET of the same polarity of the additional FET and thus the opposite polarity of the main FET; the gate electrode defining action includes defining a fourth gate for the fourth FET a pole electrode that is vertically separated by a fourth gate dielectric layer over a section of the semiconductor body that is intended to be a fourth channel region of the second conductivity type; a first conductivity type is introduced The action of the second dopant includes introducing another second semiconductor dopant of the first conductivity type to the semiconductor body to define a first conductivity type laterally separated by the fourth channel region for the fourth FET a pair of fourth S/D zones; and The act of performing the additional processing includes: completing the fabrication of the fourth FET such that the fourth channel region and the fourth well portion are part of the additional body material, the additional body material extending below the fourth S/D region, And causing another second dopant of the second conductivity type to have a concentration that moves from a fourth lower layer surface body material position upward to each of the fourth S/D regions to be substantially fixed or changed to be greater than 10 %, the fourth lower level surface layer body material is located at a depth below the upper semiconductor surface as the additional sub-surface body material position. A method comprising: introducing a first conductivity type of a first semiconductor dopant to a semiconductor body to define a well portion for a first conductivity type of a field effect transistor (FET), such that the semiconductor body The material (a) is overlying the well portion that exists immediately after the action of introducing the first dopant of the first conductivity type, and (b) is then opposite to the first conductivity type a two-conductivity type; defining a gate electrode for the FET that is vertically separated above the semiconductor body material of the channel region intended to be the first conductivity type and vertically separated by a gate dielectric material; subsequently introducing a second conductivity a first semiconductor dopant of the type to the semiconductor body to form first and second source/drain (S/D) regions of the second conductivity pattern laterally separated by the channel region for the FET; And performing additional processing to complete the fabrication of the FET such that (a) a portion of the first dopant of the first conductivity type is diffused upwardly to the semiconductor body material over the well during an additional processing operation To make it Introducing the first conductivity of the first dopant after the first conductivity type is introduced, and is not significantly affected by the first or second conductivity type of the other portions of the semiconductor body to be converted into the first conductivity type And (b) the channel region is constructed at least in part with at least a portion of the semiconductor body above the well. The method of claim 49, wherein (a) the act of performing the additional treatment is performed at least partially at an elevated temperature, and (b) the act of introducing the first dopant of the first conductivity type comprises: ions A first dopant of a first conductivity type is implanted. The method of claim 49, wherein the portion of the first dopant of the first conductivity type diffuses upward during the at least one portion of the additional treatment performed at elevated temperature. The method of claim 49 or 50, further comprising introducing a first conductivity type of additional semiconductor dopant to the semiconductor body to define a first portion of the pocket portion only along the first S/D region The S/D region extends upwardly to its contiguous upper surface such that after the additional processing is performed, (a) the semiconductor body has an upper semiconductor surface, and (b) the channel region and the well portion are of a first conductivity type And extending laterally below the portion of the body material below the S/D regions, (c) the pocket portion forming part of the body material and being more heavily doped than the abutting material of the body material, and (d Comparing all of the dopants of the first conductivity type of the bulk material with the upper semiconductor surface in the channel region compared to the first S/D region meeting along the upper semiconductor surface in the channel region The second S/D zone is at a lower concentration. For example, the method of applying for the scope of patent No. 52, in which the additional point is implemented After the action, the concentration of all dopants in the first conductivity type of the bulk material is in the channel region compared to the region where the first S/D region is merged along the upper semiconductor surface in the channel region. The upper semiconductor surface meets at least 10% lower at the second S/D region. The method of claim 49, wherein the introducing the second conductivity type of the first semiconductor dopant comprises: introducing a second conductivity type of the laterally extending portion of the semiconductor dopant through the side Applying the laterally extending portion of the mask to the main portion of the extension portion, through the upper surface of the semiconductor body and then to the laterally spaced apart portion of the semiconductor body, the gate electrode and the gate electrode Any material of the gate electrode is shielded as a dopant; a spacer material is provided to the lateral side of the gate electrode; and a main portion of the semiconductor dopant introduced into the second conductivity type is transmitted through a main portion of the mask An opening, an additional portion that is then transmitted through the upper surface of the semiconductor body and laterally separated from one of the semiconductor bodies, the main portion mask, the gate electrode and the spacer material are blocked as a dopant shield. A method comprising: providing an initial configuration, wherein (a) a first conductivity type of a first surface semiconductor region is adjacent to and overlying a surface electrical insulating layer, (b) a first conductivity type is lighter The doped surface is adjacent to and overlying the subsurface semiconductor region, and (c) the semiconductor regions are doped with a dopant of the first conductivity type such that the dopant of the first conductivity type has a self The subsurface semiconductor region spans upward to the surface adjacent to the semiconductor region The domain undergoes a stepwise reduction to a concentration of up to 10%, and (d) the semiconductor layer is adjacent and placed under the subsurface insulating layer; forming a cavity through the semiconductor regions and the subsurface insulating layer Downward to the lower semiconductor layer, whereby (a) the remaining portion of the subsurface semiconductor region constitutes a major subsurface body material portion of the first conductivity type, and (b) the surface is adjacent to one of the semiconductor regions remaining a portion of the first conductive type partially constituting the lighterly doped precursor main surface adjacent to the body material portion; introducing a semiconductor material opposite to the second conductive type of the first conductive pattern to the cavity portion to be a) an additional subsurface body material portion of the second conductivity type extending downwardly to the lower semiconductor layer to form a pn junction, and (b) a lightly doped precursor of the second conductivity type An additional surface abutting the body material portion, the additional semiconductor portion being doped with a dopant of the second conductivity type such that the dopant of the second conductivity type has a portion that extends upward from the additional subsurface body material portion Adding a surface adjacent to the bulk material portion to substantially undergo a stepwise reduction to a concentration of up to %; and providing (a) a second conductivity type of a pair of primary source/drain (S/D) regions on the precursor major surface Adjacent to and along the upper surface of the body material, the primary surface abuts the primary channel region of one of the body material portions and laterally separates the primary S/D regions, (b) a pair of additional S/s of the first conductivity pattern The D zone is adjacent to the body material portion along the upper surface of the precursor, and the additional channel region of the additional body material portion is laterally separated from the additional S/D regions, (c) respectively in the main and additional The main and additional gate dielectric layers above the channel region, and (d) above the main and additional channel regions, respectively The primary and additional gate electrodes are primarily above the additional gate dielectric layer. The method of claim 55, wherein: the concentration of the dopant of the first conductivity type is approximately fixed throughout the portion of the main sub-surface body material; and the concentration of the dopant of the second conductivity type is approximately fixed Throughout the additional subsurface body material portion. The method of claim 56, further comprising: selectively introducing a first conductivity type of the main semiconductor pocket dopant to the precursor main surface adjacent to the body material portion to define along the main S/D regions One of the S/D regions extends one of the main pocket portions, whereby the primary pocket portion is heavily doped to the first conductivity pattern compared to the adjacent material of the main body material portion; and selectively introduces the second conductivity a pattern of additional semiconductor pocket dopants to the precursor additional surface adjacent the body material portion to define an additional pocket along an S/D zone extending along the additional S/D regions, whereby the additional pocket The portion is more heavily doped to the second conductivity pattern than the abutting material of the additional surface abutting the body material portion. The method of any one of claims 55 to 57, wherein: along a portion extending from the main sub-surface body material portion to a designated S/D region of the main S/D regions, The concentration of the first conductivity type dopant of the surface adjacent to the body material portion is at least 10% lower than the primary subsurface body material portion; and extending along the portion from the additional subsurface body material a position of one of the designators of the additional S/D zone, adjacent to the body material portion at the additional surface The concentration of the dopant of the second conductivity type is at least a factor of 10 lower than the portion of the additional subsurface body material. A method comprising: introducing a primary bulk dopant of a first conductivity type to a portion of a starting semiconductor material of a second conductivity type opposite one of the first conductivity type to convert the portion of the starting material The surface of the first conductivity type is adjacent to the main body material such that the main body dopant has a relatively uniform concentration throughout the main body material, and a remaining portion of the starting material constitutes a surface of the second conductivity type adjacent to the addition a bulk material; introducing a primary well dopant of a first conductivity type to the primary body material to form a primary well portion at a primary surface location of the primary body material to a maximum concentration reaching the primary well portion; Adding a second well conductivity type of additional well dopant to the additional body material to form an additional well portion at a primary surface location of the additional body material to a maximum concentration of the additional well portion; and providing (a) A pair of surfaces of the second conductivity pattern abut the main source/drain (S/D) region of the main body material such that one of the main body materials is the main channel region Separating the primary S/D regions and causing all of the dopants of the first conductivity type of the primary bulk material to move up from a position of the maximum concentration of the primary well dopant to the primary S/ A designated one of the D regions is reduced to a concentration of at most 10%, and (b) a pair of additional S/D regions of the first conductivity type are attached to the additional body material, such that one of the additional body materials is added to the channel region Separating the additional S/D regions laterally and causing all dopants of the second conductivity pattern of the additional body material to have doping from the additional well The position of the maximum concentration of the agent is moved up to a specified additional S/D zone of the additional S/D zone to a concentration of up to 10%, and (c) is predominantly above the primary and additional channel zones, respectively And an additional gate dielectric layer, and (d) primary and additional gate electrodes over the primary and additional gate dielectric layers above the primary and additional channel regions, respectively. The method of claim 59, wherein: the first and second conductivity types are p-type and n-type, respectively; and the first conductivity-based main dopant comprises aluminum. A semiconductor structure comprising: first and second body material regions of a semiconductor body having an upper surface, the body material regions being doped with a semiconductor dopant in a first conductive form to cause first conductivity a first region and a second region in a second conductive form opposite the first conductive form in the upper semiconductor surface of the semiconductor body, the first body material region and the second body material region, respectively Extending below the first and second regions and respectively reciprocating to form a first pn junction and a second pn junction with the first and second regions, respectively, such that (a) each The pn junction will reach a maximum depth below the upper surface of the body, (b) the first conductive form of dopant will appear in both regions and have a concentration in the individual first surface layer body The material position and the second surface body material position (located in the first body material region and the second body material region, respectively, and extending laterally below the first and second regions, respectively) are partially reached Subsurface maximum concentration and the maximum concentration of the second skin layer, (c) compared to the maximum depth of the first pn junction and such a second pn junction, The first surface layer body material position and the second surface layer body material position respectively appear less than 10 times deep below the upper surface of the body, and (d) the first conductive form of the dopant The concentration will: (i) decrement to a maximum of 10% from the position of the first surface body material along a selected first vertical line through the first region up to the upper surface of the body, (ii) from the The first surface layer body material position is decremented in a substantially monotonous manner as it moves along the first vertical line to the first pn junction, and (iii) from the second surface layer body material location along a selected first The two vertical lines reach at least one additional subsurface maximum concentration as they move up through the second zone to the upper surface of the body. The semiconductor structure of claim 61, wherein the concentration of the dopant of the first conductive form is moved from the first surface layer body material along the first vertical line to the body via the first region The upper surface is decremented to a maximum of 20%. The semiconductor structure of claim 61, wherein the concentration of the dopant of the first conductive form is moved to the first vertical line along the first vertical line from the first vertical line via the first region to the The upper surface of the body is decremented to a maximum of 40%. The semiconductor structure of any one of claims 61 to 63, wherein a concentration of the dopant of the first conductive form is from the second surface body material position along the second vertical line via the first When the two zones are moved up to the upper surface of the body, they are decremented to more than 10%. The semiconductor structure of claim 64, wherein the concentration of the dopant of the first conductive form is along the first vertical line at a depth of each additional subsurface concentration maximum in the second region. The first district Change in most monotonous ways. The semiconductor structure of any one of clauses 61 to 63, wherein when moving downward from the position of the first surface layer body material to a depth of 10 times the maximum depth of the first pn junction, The first surface maximum concentration is substantially the only local subsurface maximum of the dopant concentration of the first conductive form. A structure comprising a polar-like field effect transistor (FET), the FET being provided along an upper surface of a semiconductor body, the body material of the semiconductor body being doped with a semiconductor dopant in a first conductive form, The first conductive form, each FET includes: a channel region of the body material; first and second source/drain (S/D) regions, which are along the upper surface of the semiconductor body And in a semiconductor body, laterally separated by the channel region, and as a second conductive form opposite the first conductive form to form an individual pn junction with the body material, such that (a) each pn junction Will reach a maximum depth below the upper surface of the body, (b) the body material will extend laterally below both S/D regions, and (c) the first conductive form of dopant will appear The concentration in both of the S/D regions will locally reach a major portion at a major subsurface body material location that will extend laterally beyond most of the channel regions and each of the S/D regions. Subsurface maximum concentration, and (d) compared to each S/D The maximum depth of the pn junction of the main subsurface body-material location views appear in place beneath the upper surface of the body is less than 10 times the depth; a gate dielectric layer overlying the channel region which is based on; and a gate electrode overlying the gate dielectric layer on the channel region, wherein the concentration of the dopant in the first conductivity form is: (i) from a primary subsurface body material for the first FET The position is reduced to at most 10% along a selected first vertical line via a designated S/D region of the S/D region of the first FET to the upper surface of the body, (ii) from a primary sub-surface body material location of a FET that decreases in a substantially monotonous manner as it moves along the vertical line to a pn junction of a designated S/D region of the first FET, and (iii) on the upper surface of the body At least one additional subsurface maximum concentration is achieved between the primary subsurface body material locations of the second FET, such that each additional subsurface maximum concentration of the second FET occurs at an additional subsurface body material location, It extends laterally below most of the material of the gate electrode of the second FET for overlying its channel region and at least a portion of each of its S/D regions. The structure of claim 67, wherein the concentration of the first conductivity form dopant is from the first sub-surface body material location of the first FET along the first vertical line via the first FET Specifies that the S/D area is decremented to a maximum of 20% when moved to the upper surface of the body. The structure of claim 67, wherein the concentration of the first conductivity form dopant is from the first sub-surface body material location of the first FET along the first vertical line via the first FET Specifies that the S/D zone is decremented to a maximum of 40% when moved to the upper surface of the body. The structure of any one of clauses 67 to 69, wherein the concentration of the dopant of the first conductivity form is along a selected vertical line from the position of the main subsurface body material for the second FET. Via the first When any S/D region of the two FETs is moved up to the upper surface of the body, it is decremented to greater than 10%. The structure of claim 70, wherein the concentration of the dopant of the first conductive form is greater along the first vertical line at a depth of each additional subsurface maximum concentration for the second FET Partial monotonous way to change. The structure of any one of clauses 67 to 69, wherein the downward movement to the first FET is performed along the first vertical line from a position of the primary subsurface body material for the first FET When the depth of the pn junction of the S/D region is 10 times deep, the main subsurface maximum concentration of the first FET is substantially the only partial subsurface of the dopant concentration of the first conductive form. maximum. The structure of any one of claims 67 to 69, wherein each S/D region of each FET includes a main portion and a lightly doped lateral extension that laterally continues the main portion and Extending laterally below the gate electrode of the FET, the channel terminates its channel region along its upper surface along its upper surface. The structure of any one of claims 67 to 69, wherein the pocket portion of the body material of each FET extends along its first S/D region into its channel region, and the doping level is greater than A laterally adjacent material of the body material. The structure of claim 74, wherein the pocket portion of the first FET has its channel region asymmetrical to its S/D region. For example, the structure of claim 74, wherein the body material The other pocket extends along the second S/D region of the second FET into its channel region and is doped to a greater extent than the laterally adjacent material of the body material. A method of fabricating a semiconductor structure, the method comprising: introducing a first conductivity form of a semiconductor dopant into a semiconductor body to define a first body material region and a second body material region, such that each body material region becomes a conductive form; and introducing a second conductive form of semiconductor dopant opposite the first conductive form into the semiconductor body to define a first region and a second region of the second conductive form, respectively After the fabrication of the structure is completed (a) the first body material region and the second body material region respectively form a first pn junction and a second pn junction with the first and second regions and respectively extend Below the first and second regions, (b) each pn junction extends below the upper surface of the semiconductor body to a maximum depth, (c) the first conductivity form of the semiconductor dopant Appearing in both of the regions, (d) the concentration of all semiconductor dopants in the first conductive form in the semiconductor body will be at the individual first surface layer body material location and the second surface layer body material location ( Positioning the first surface layer maximum concentration and the second surface layer maximum concentration locally in the first body material region and the second body material region, respectively, and extending laterally below the first and second regions, respectively. (e) the first surface body material position and the second surface body material position respectively appear below the upper surface of the body, compared to the maximum depths of the first pn junction and the second pn junction Up to 10 times deep, (f) the concentration of all dopants in the first conductivity form will be: (i) from the first surface layer body material location along the selected first vertical line via the first One area moves up to the book The upper surface of the body is decremented to a maximum of 10%, (ii) decreasing in a substantially monotonous manner from the position of the first surface body material along the first vertical line to the first pn junction, and (iii) At least one additional subsurface maximum concentration is achieved from the second surface body material location along a selected second vertical line as it moves up through the second region to the upper surface of the body. The method of claim 77, wherein after the fabrication of the structure is completed, the concentration of all dopants of the first conductive form is from the second surface layer material location along the second vertical line When moved to the upper surface of the body, it is reduced to more than 10%. The method of claim 77, wherein the concentration of the dopant of the first conductive form is greater than the maximum value of each additional subsurface concentration in the second region after the fabrication of the structure is completed. The change will be in most monotonous manner along the first vertical line. The method of claim 77, wherein after completing the fabrication of the structure, moving down the first vertical line from the first surface body material location to the first pn junction At a depth of 10 times the maximum depth, the first surface maximum concentration is substantially the only local subsurface maximum of all dopant concentrations of the first conductive form. A method of fabricating a structure comprising first and second types of polar field effect transistors (FETs), the method comprising: introducing a first conductivity form of a semiconductor dopant into a semiconductor body to define a first body material region, respectively And a second body material region, such that after the fabrication of the structure is completed, each of the body material regions becomes the first conductive form; Defining a pair of gate electrodes of the FETs, respectively, such that the gate electrode of each labeled FET is located above the body material region of the same number that is expected to be part of the channel region of the FET, and will have a corresponding The gate dielectric layer is vertically separated; and a second conductivity form of semiconductor dopant opposite the first conductivity form is introduced into the semiconductor body to form a second laterally separated by the channel region of the FET for each FET The first and second source/drain (S/D) regions of the conductive form, such that after the fabrication of the structure is completed (a) each of the labeled body material regions will be respectively associated with the same labeled FET S The /D region forms a pair of pn junctions and extends laterally below the S/D regions of the same labeled FET, respectively, (b) each pn junction extends below the upper surface of the semiconductor body to a maximum depth, c) the first conductive form of the semiconductor dopant will be present in each of the S/D regions, (d) the concentration of all of the semiconductor dopants of the first conductive form in the semiconductor body for the first FET Will be below the upper surface of the body A first primary subsurface body material reaches a first primary subsurface maximum concentration, and the second FET reaches a second major at a second major subsurface body material location below the upper surface of the body The subsurface maximum concentration, (e) is greater than the maximum depth of the pn junction of each S/D region of the FET, and the primary subsurface bulk material location of each label extends laterally over most of the same labeled FET. The channel region is below each of the S/D regions and appears less than 10 times deep below the upper surface of the body, and (f) the concentration of all dopants in the first conductive form is: (i) designating from the first primary subsurface body material location along a selected vertical line via the S/D region of the first FET The S/D region is decremented to a maximum of 10% when moved up to the upper surface of the body, (ii) moved from the first primary subsurface body material location along the vertical line to a designated S/D region of the first FET The pn junction is decremented in a substantially monotonous manner, and (iii) at least an additional subsurface maximum concentration is achieved between the upper surface of the body and the second primary subsurface body material location of the second FET, such that each An additional subsurface maximum concentration will occur at a corresponding additional subsurface body material location that extends laterally over the second FET over its channel region and at least a portion of its S/D region. Most of the gate electrode is underneath all of the material. The method of claim 81, wherein after the fabrication of the structure is completed, the concentration of all dopants of the first conductive form is from the second primary subsurface body material location along a selected second The vertical line is decremented to greater than 10% as it moves up any of the S/D regions of the second FET to the upper surface of the body. The method of claim 81, wherein the concentration of all dopants in the first conductive form is at a depth of each additional subsurface maximum concentration for the second FET after completion of fabrication of the structure The change will be in most monotonous manner along the first vertical line. The method of claim 81, wherein the first primary subsurface body material location moves down the first vertical line to a maximum of a pn junction for a designated S/D region of the first FET. At a depth of 10 times the depth, the first major subsurface maximum concentration is substantially the only local subsurface maximum of all dopant concentrations of the first conductive form. For example, the method of claim 81 or 82, wherein the definition is The operation of the gate electrode is mostly carried out after the action of introducing the dopant of the first conductivity form. The method of claim 81 or 82, wherein the act of introducing the dopant of the second conductivity form is carried out mostly after the action of defining the gate electrodes. The method of claim 81 or 82, wherein the act of introducing the dopants of the second conductivity form must form each S/D region of each FET to include a main portion and a lighter a doped lateral extension that laterally continues the main portion and extends laterally below the gate electrode of the FET such that after completion of fabrication of the structure, the channel region of each FET is along the top of the body The surface terminates in its extension. The method of claim 81 or 82, further comprising introducing the additional dopant in the first conductive form into the semiconductor body such that the pocket portion of each of the labeled body material regions will follow the same The first S/D region of the labeled FET extends into its channel region and is doped to a greater extent than the laterally adjacent material of the first body material region. The method of claim 88, wherein the pocket portion of the first FET causes its channel region to be asymmetrical to its S/D region. The method of claim 88, wherein the act of introducing the additional dopant in the first conductive form causes another pocket portion of the second body material region to follow a second S/D region of the second FET Extending into its channel region and doping to a greater extent than laterally adjacent material of the second body material region. A method of fabricating a semiconductor structure from a semiconductor body, comprising: defining a primary gate electrode for a primary field effect transistor (FET), Above a section of the semiconductor body intended to be the main channel region of the first conductivity type and vertically separated by a primary gate dielectric layer; introducing a second conductivity pattern opposite one of the first conductivity patterns Substituting a semiconductor dopant to the semiconductor body to define a pair of primary source/drain (S/D) regions of the second conductivity pattern opposite the first conductivity pattern laterally separated by the channel region for the FET After the fabrication of the structure is completed, (a) the semiconductor body has an upper semiconductor surface, (b) the channel region is a first conductivity type and a portion of the main body material laterally extending below the S/D regions And (c) the concentration of all of the semiconductor dopants of the first conductivity type in the semiconductor body is from a major lower level surface layer body material location (below the upper semiconductor surface compared to a specified S/D region) When moving up to the designated S/D area of the S/D area up to 10 times deep, it will be reduced to a maximum of 10%. The method of claim 91, wherein after the fabrication of the structure, the subsurface body material is positioned no more than 5 times deeper than the designated S/D region below the upper semiconductor surface. The method of claim 91, wherein after the fabrication of the structure, the concentration of all dopants of the first conductivity type decreases from the position of the subsurface body material upward to the designated S/D region. Up to 10%. The method of claim 91, further comprising introducing a first conductivity type semiconductor dopant into the semiconductor body to define a pocket portion along a remaining S/D region of the S/D regions Extending upwardly to the upper surface that is then present, such that after the fabrication of the structure is completed, (a) the pocket forms part of the body material and is more heavily doped than an adjacent material of the body material, and b) compared to the upper semiconductor surface in the channel region Where the remaining S/D regions are combined, a concentration of all of the dopant material of the first conductivity type in the bulk material meets the designated S/D region along the upper semiconductor surface in the channel region Lower. The method of claim 91, wherein: the gate electrode defining action comprises defining another gate electrode for another FET of the same polarity as the main FET, which is intended to be another one of the first conductivity type A portion of the semiconductor body of the channel region is vertically separated by another gate dielectric layer; and the act of introducing the dopant of the second conductivity type includes doping another first semiconductor of the second conductivity pattern a dopant is introduced into the semiconductor body to define a pair of additional S/D regions of the second conductivity pattern laterally separated by the other channel region for the other FET, such that after the fabrication of the structure is completed, (a) The other channel region also extends over a portion of the bulk material below the additional S/D regions, and (b) the concentration of all dopants of the first conductivity pattern is at a location from another lower layer skin material (in the The depth below the upper semiconductor surface is approximately fixed or changed to greater than 10% when moving up to each additional S/D region as the primary subsurface body material location. The method of claim 91, wherein: the gate electrode delimiting action comprises an additional gate electrode defining an additional FET opposite the polarity of the main FET, which is intended to be an additional channel region of the second conductivity type A portion of the semiconductor body is vertically separated by an additional gate dielectric layer; the method further includes introducing a first conductivity type semiconductor dopant into the semiconductor body to define the additional channel region for the additional FET Place a pair of additional S/D regions of the first conductivity pattern that are laterally separated such that after the fabrication of the structure is completed, (a) the additional channel region is the second conductivity pattern and extends in the additional S/D regions a portion of the underlying body material, and (b) the concentration of all of the semiconductor dopants of the second conductivity type in the semiconductor body is from an additional lower level surface layer body material location (as compared to a specified additional S/D region) Up to 10% of the designated additional S/D zone moving up to the additional S/D zone is moved up to no more than 10 times deep below the upper semiconductor surface. The method of claim 96, wherein: the gate electrode delimiting action includes defining a third gate electrode for a third FET of the same polarity as the main FET, which is intended to be the third of the first conductivity type A portion of the semiconductor body of the channel region is vertically separated by a third gate dielectric layer; the act of introducing the dopant of the second conductivity type includes doping another first semiconductor of the second conductivity pattern a dopant is introduced into the semiconductor body to define a pair of third S/D regions of the second conductivity pattern laterally separated by the third channel region for the third FET, such that after the fabrication of the structure is completed, (a The third channel region also extends over a portion of the bulk material below the third S/D regions, and (b) the concentration of all dopants of the first conductivity type is at a location from the third lower layer skin material (the depth below the upper semiconductor surface is about the same as the primary subsurface body material location) moving upwards to each of the third S/D regions is substantially fixed or changed to greater than 10%. The method of claim 97, wherein: the gate electrode delimiting action comprises defining a fourth gate of a fourth FET for the same polarity as the additional FET and thus opposite the polarity of the main FET An electrode above the segment of the semiconductor body intended to be the fourth channel region of the second conductivity type and vertically separated by a fourth gate dielectric layer; the act of introducing the dopant of the second conductivity type comprises Introducing a second conductivity type of another first semiconductor dopant into the semiconductor body to define a pair of fourth S/ of the first conductivity pattern laterally separated by the fourth channel region for the fourth FET Zone D, such that after completion of the fabrication of the structure, (a) the fourth channel region also extends over a portion of the bulk material below the fourth S/D regions, and (b) all doping of the second conductivity pattern The concentration of the agent is substantially fixed or changed when moving from the fourth lower layer skin material position (the depth below the upper semiconductor surface is about the same as the main subsurface body material position) to the respective fourth S/D regions. It is greater than 10%. The method of any one of claims 91 to 98, further comprising introducing the first conductivity type semiconductor dopant into the method prior to the act of introducing the dopant of the second conductivity type At least the material of the underlying material of the semiconductor material of the semiconductor material of the main S/D region. The method of claim 99, wherein the act of introducing the dopant of the first conductivity type is performed such that after the fabrication of the structure is completed, the dopant of the first conductivity type is along the main The position of the underlying body material will reach a very high concentration.