TWI425333B - Control device semiconductor apparatus - Google Patents

Description

Control device for semiconductor equipment

The invention relates to a control device.

In a scanning exposure apparatus or an overhead type machine tool, the position of a plurality of moving members or the positions of a plurality of control axes are synchronously controlled with high accuracy. Therefore, conventionally, master-slave synchronization control has been implemented. In the master-slave synchronization control, one of the plurality of moving members is used as a body, and the other moving members are used as slaves, and when the disturbance occurs in the body, the slaves follow the displacement of the body. In this way, synchronization accuracy is improved. The disturbances occurring in the slaves are reduced by controlling the slaves.

In addition, two-way synchronous control has been proposed to further improve the synchronization accuracy between the wafer table and the reticle stage (Japanese Laid-Open Patent Application No. 08-241126). In the two-way synchronous control, when the disturbance occurs in any of the control targets, the subject and the slave are operated such that they both compensate the synchronization error at the same time, without distinguishing between each other. Further, Japanese Patent Application No. 2006-310849 discloses master-slave synchronization control to which iterative learning control is applied.

It is believed that the synchronization performance of the two-way synchronization control (or similarly, the multilateral synchronization control for two or more control axes) may be better than the synchronization performance of the master-slave synchronization control. However, the former control system has a complicated structure and it is difficult to obtain or adjust the control system. As a result, it is difficult to improve the synchronization accuracy.

According to an embodiment of the present invention, a control device includes: a first control circuit configured to control a position of the first control target; and a second control circuit configured to control a position of the second control target a calculation unit configured to calculate a synchronization error between the first control target and the second control target; an iterative learning control circuit including inputting the synchronization error to the first and second learning of the same a filter, and configured to, based on the output of one of the first learning filters, impart a control input to the first control target and to deliver a control input to the second based on the output of the second learning filter Control objectives.

Other features and embodiments of the present invention will become more apparent from the following detailed description of exemplary embodiments.

Hereinafter, a first exemplary embodiment will be described.

1 is a block diagram depicting a control device for synchronously controlling the position of a wafer stage and a reticle stage in a semiconductor exposure apparatus. The control device includes a control circuit 7 (first control circuit) that controls the position of the wafer table, and a control circuit 8 (second control circuit) that controls the position of the wafer table, and synchronizes the two control circuits.

The detecting units 11 and 12 detect the positions y _W and y _R of the wafer stage (first control target) and the reticle stage (second control target) of the control target. It is assumed that the transfer function of the wafer stage is P _W and the transfer function of the mask stage is P _R . The subtraction units 13 and 14 subtract the outputs of the detection units from the target trajectories r and Nr (N-type exposure magnification), and input the deviations e _W and e _R therebetween into the feedback controller (refer to the transfer function as K) _W and K _R ). The calculation unit 15 calculates the synchronization error y _S[k] which is the difference between the outputs Ny _W and y _R and inputs the synchronization error to the iterative learning control circuit ILC. The output of the iterative learning control circuit ILC is applied to the outputs u _W and u _R , which are the control inputs of the feedback controllers K _W and K _R and provide the added values to the control targets.

In this regard, in this exemplary embodiment of the invention, the synchronization error compensation is implemented on both the wafer table P _W and the reticle stage _{R R} to implement two-way synchronous control. In addition, iterative learning control is implemented for this synchronization error compensation. The iterative learning control repeatedly implements tracking control on the target trajectory to reduce the synchronization error. Next, the iterative learning control will be described with reference to the control block depicted by circle 1 and the flow chart depicted in FIG. The iterative learning control circuit ILC includes a learning filter L in which the input signal is synchronized with the error y _S[k] , the stabilization filters Q _W and Q _R , and the frequency band not required for learning is passed, and the memory 1 and 2 are stored. The output of these stabilization filters.

In step S1, the first operation is performed. In this step, the wafer stage and the reticle stage need not be controlled by any input from the iterative learning control circuit. The synchronization error y _{S[1] is} output to the learning filter L, and the output of the learning filter L is passed through the stabilization filters Q _W and Q _R (the first stabilization filter and the second stabilization filter) as f _{W[2 ]} and f _{R[2] are} stored in the memories 1 and 2 (the first memory device and the second memory device). In step S2, the kth (k>1) operation starts. In this case, since the digital control is implemented, the control inputs to the i-th sample during the kth operation are referred to as f _W[k]i and f _R[k]i , and the synchronization error thereof is referred to as y _{S [ k]i} . Here, assume that the total number of samples in an operation is j. The initial conditions are as follows: the maximum value of the synchronization error y _Smax is 0; and the number i of the sample is zero. In step S3, the control inputs f _W[k]i and f _R[k]i previously stored in the memories are fed forward and added to the outputs u _Wi and u _Ri . In this way, in the kth operation, the control targets are controlled.

In the kth operation, the (k+1)th control input is generated in step S4 and then stored in the memories 1 and 2. More specifically, the synchronization error y _{S[k]i is} input to the learning filter L, and the output of the learning filter is added to the control inputs f _W[k]i and f _R by the adders 16 and 17 _{[ k]i} . Then, the added values are stored in the memories 1 and 2 via the stabilization filters Q _W and Q _R as f _W[k+1]i and f _R[k+1]i . In step S5, the synchronization error y _{S[k]i is} compared with the maximum value y _{Smax of} the synchronization error. If the synchronization error y _{S [k] i} is more than the maximum synchronization error y _Smax, updates the maximum y _Smax. In step S6, if j < i (YES in step S6), the program proceeds to step S7. If j>i (NO in step S6), i=i+1 is set, and the program proceeds to step S3. In step S7, the kth operation ends. In step S8, the maximum value y _{Smax of} the synchronization error is compared with a predetermined set value. If the maximum value y _{Smax is} less than the set value (YES in step S8), it is determined that the deviation is sufficiently small and the learning ends. If the maximum value y _{Smax of} the synchronization error is _larger than the set value (NO in step S8), k = k + 1 is set and the routine proceeds to step S2.

FIG. 3A is a block diagram depicting the detailed structure of the learning filter L. The learning filter L includes a first learning filter L ₁ and a second learning filter L ₂ , which include transfer functions substantially equivalent to the following arithmetic expressions 1 and 2:

Further, the learning filter L includes a filter F ₁ that adds the output of the first learning filter L _{1 to} the output of the second learning filter L ₂ and adds the output of the second learning filter L ₂ to the first learning filter. Filter F ₂ of the output of L ₁ . This synchronization error is input to the learning filters L ₁ and L ₂ . The output of the learning filter L ₁ passes through the filter F ₁ and is applied to the output of the learning filter L ₂ . Similarly, the output of the learning filter L ₂ passes through the filter F ₂ and is applied to the output of the learning filter L ₁ . Therefore, one of the outputs of one of the two learning filters is added to the output of the other learning filter. The output of the learning filter L ₁ to which the output of the filter F ₂ has been applied is input to the adder 16, and the output of the learning filter L ₂ to which the output of the filter F ₁ has been applied is input to the adder 17 .

FIG. 3B shows a block diagram depicting a modification of the learning filter depicted in FIG. 3A. The learning filter L includes a first learning filter L ₁ and a second learning filter L ₂ , which include transfer functions substantially equal to the arithmetic expressions 1 and 2. Further, the learning filter L includes a filter F ₁ ' and a filter F ₂ ', and is classified into a control block including a learning filter L ₁ , a filter F ₁ ', and a learning filter L _{2 which} are serially connected to each other. The group A, and the learning block L ₂ , the filter F ₂ ′, and the control block group B of the learning filter L ₁ are connected in series with each other. More specifically, the output of the learning filter L ₁ is multiplied by the output of the learning filter L ₂ . The synchronization error is input to the two control block groups. The output of the control block group A is input to the adder 16, and the output of the control block group B is input to the adder 17.

The learning filter may have the structure depicted in Figure 3C. The learning filter L includes a first learning filter 71 and a second learning filter 72. The learning filter 71 includes transfer functions P _W and P _{R of the} wafer stage and the reticle stage, and transfer functions K _W and K _{R of the} feedback controllers. The learning filter 72 also includes transfer functions P _W and P _{R of the} wafer stage and the reticle stage, and transfer functions K _W and K _{R of the} feedback controllers. The output of the learning filter 71 is input to the adder 16, and the output of the learning filter 72 is input to the adder 17. If L1 + L2F2 depicted in FIG. 3A is the learning filter 71 and L2+L1F1 depicted in FIG. 3A is the learning filter 72, the structure depicted in FIG. 3A is included in the structure depicted in FIG. 3C. Similarly, if the control block group A depicted in FIG. 3B is the learning filter 71 and the control block group B depicted in FIG. 3B is the learning filter 72, the structure depicted in FIG. 3B also includes This structure is depicted in Figure 3C.

Next, a method of obtaining the learning filter will be described. First, the modeling of the control target is performed to obtain the learning filter L. Assuming that the wafer stage and the reticle stage are a mass system, the wafer stage and the reticle stage are shifted by x _W and x _R , the control inputs are u _W and u _R , and their mass is m _W and m _R , the wafer stage and the mask stage are represented by the following equations of motion:

The state vector is represented as follows:

The equation of state and the output equations obtained by Equations 3 and 4 are expressed as follows:

y _W =[1 0] x _W = C _W x _W (7)

y _R =[1 0] x _R = C _R x _R (9).

To obtain a two-way iterative learning control system, the enhancement system depicted in FIG. 4 is obtained, wherein the observation output is the displacement y _W of the wafer stage, the displacement of the reticle stage y _R , and the wafer stage and the Synchronization error y _S between the reticle stages. In FIG. 4, P _W shows the model of the wafer stage indicated by Equations 6 and 7, and P _R shows the model of the mask table indicated by Equations 8 and 9. The synchronization error y _S between the wafer stage and the reticle stage is described as Ny _W -y _R because of the N-type projection magnification. The equation of state and the augmentation system The output equation is expressed as follows:

x _e =[ x _W x _R ] ^T , u _e =[ u _W u _R ] ^T (12).

Figure 5 depicts a block diagram of the synchronization control to which the iterative learning control is applied.

The enhancement system represented by Equation 10. In the kth iteration, the feedback controller Output control inputs u _W[k] and u _{R[k] are used} to track the target trajectories r and Nr of the wafer stage and the reticle stage. e _W[k] and e _R[k] represent tracking errors of the target trajectories r and Nr of the wafer stage and the reticle stage and the shifts y _W[k] and y _R[k] . The synchronization error y _S[k] between the wafer stage and the reticle stage is input to the learning filter L. Adding the output of the learning filter to the feedforward inputs f _W[k] and f _{R[k] in} the kth iteration, and then passing the following stabilization filter Stored in the memory m as the (k+1) feedforward input f _W[k+1] and f _R[k+1] , the stabilization filter does not allow the frequency band that does not need to be learned to pass:

In this case, the learning rules of the iterative learning control are defined as follows:

f _{[ k ]} =[ f _{W [ k ]} f _{R [ k ]} ] ^T (15).

The closed loop system P _{c1 is} defined as depicted in Figure 6, wherein Means the enhanced system and Means the feedback control system. The block diagram depicted in FIG. 5 is equivalently exchanged with the structure depicted in FIG. 7 by using a closed loop system P _c1 . The output of the closed-loop system P _c1 is only the synchronization error y _S[k] , however, to the stabilization filter The input is tied to the wafer stage and the feedforward input of the reticle stage. Therefore, the learning filter L having one input and two outputs is obtained. Because the following equations are built from Figure 6:

y _S[k] =P _c1 f _[k] (16).

The following relationship between f _[k+1] and f _[k] is established by Equation 14:

If the convergence of the synchronization error y _S[k] is considered to be equivalent to the convergence of the feedforward input by the iterative learning control, the following conditions can be satisfied:

The multiplexed learning filter L that satisfies the above conditions is obtained by using the portion surrounded by the broken line in Fig. 7 as a generalized control object and using the H ^∞ control theory.

In this exemplary embodiment, it is assumed mass m _R m _W and the wafer table and the reticle circuits to 40kg. Assuming that the desired servo bandwidth of the wafer stage and the reticle stage are different from each other according to the conditions of the mechanical structure, and the feedback control system It is designed such that the servo bandwidth is 350 Hz and 250 Hz. Here, assume a feedback control system It is used in decentralized control systems for each station, regardless of the bidirectional nature of the feedback control system. When considering the bidirectional nature of the feedback control system, the system may also be similarly designed as follows. First, both the stabilization filters Q _W and Q _R for the wafer stage and the reticle stage are designed using a 5th order Battens filter having a cutoff frequency of 300 Hz. Second, as depicted in Figure 6, an enhancement system P _{c1 is obtained} . Next, a stable filter as shown in Equation 13 is formed. And use the enhanced system P _c1 and the stabilization filter The generalized object represented by the dashed line of Fig. 7 is generated. Finally, the learning filter L is obtained by using the H ^∞ control theory.

Figure 8 is a diagram depicting the gain of the learned filter. The learning filters that are generated by the synchronization error to the wafer circuit and the feedforward input of the reticle stage are respectively indicated by solid lines and broken lines.

Next, a simulation response for synchronously controlling the wafer stage and the reticle stage using the control device according to the present exemplary embodiment will be described. In this simulation, a feedforward input for tracking target drive is provided to the iterative learning control and feedback control, the feedforward input being obtained by multiplying the acceleration obtained by the second order differential position profile by the mass. Further, in this simulation, a zero-phase low-pass filter is used as the stabilization filters Q _W and Q _R . Since the zero-phase low-pass filter cannot instantaneously filter the data, the synchronization error y _{S is} stored in the memories 1 and 2 and the learning represented by the arithmetic expression 14 is performed each time the iterative operation ends.

Figure 9 is a diagram depicting the positional profile of the target track of the wafer table and the reticle stage. The projection magnification is 1/4. 10A to 10D depict a simulated response when the first to fourth operations are performed. The solid line indicates the tracking error of the target trajectory of the wafer table, and the broken line indicates the tracking error of the target trajectory of the reticle stage. The wafer table has a tracking error of four times.

11A to 11D depict that when the iterative learning control system is independently implemented on the wafer table and the reticle stage (in other words, the master-slave synchronization control or the two-way synchronization control is not implemented), when the first to fourth operations are performed The analog response. In the following, this control is referred to as independent iterative learning control and is distinguished from master-slave synchronization control or two-way synchronization control.

As can be seen from Figures 10A through 11D, according to the present exemplary embodiment, when the number of iterations rises, the tracking error of the wafer table is closer to the tracking error of the reticle stage.

In the present exemplary embodiment, the servo bandwidth of the wafer stage is set to be higher than the servo bandwidth of the reticle stage. Therefore, when no disturbance occurs, the wafer stage used as a main body and the reticle stage used as a slave can be synchronized with each other. In the two-way synchronization control to which the iterative learning control is applied, the learning system is implemented such that the displacement of the wafer table automatically tracks the displacement of the reticle stage, thereby reducing the synchronization error.

In FIG. 12, the solid line indicates the synchronization error caused by the two-way synchronization control to which the iterative learning control is depicted by FIGS. 10A to 10D, and the broken line indicates the independent iterative learning control depicted by FIGS. 11A to 11D. The resulting synchronization error. In Figure 12, the horizontal axis indicates time. Figure 12 depicts the response of this fourth operation before 0.1 seconds.

In this independent iterative learning control, the synchronization error is maintained at approximately 0.09 seconds. However, in the two-way synchronous control to which the iterative learning control is applied, the synchronization error is about zero at 0.07 seconds. More specifically, in the two-way synchronous control to which the iterative learning control is applied, it is possible to quickly converge the synchronization error with the same number of iterations.

In the two-way synchronization control to which the iterative learning control is applied, the learning filter uses a model design that takes into account dynamic features between the stations, the stations including the feedback control depicted in FIG. system. Meanwhile, in the two-way synchronous control according to the prior art, the synchronous path controller is to be adjusted by the trial and error method according to the dynamic characteristics of the station and the variation in the feedback control system. However, in the exemplary embodiment of the present invention, the learning filter is designed based only on the platform and the model of the control system, and appropriate synchronization control is achieved only by the iterative operation. Therefore, it may be relatively easy to obtain or adjust the synchronous control system.

Next, a response to the synchronous control simulation when a sine wave disturbance is applied to the wafer stage will be described. 13A to 13D depict simulated responses when the first to fourth operations are performed in the two-way synchronization control to which the iterative learning control is applied. In FIGS. 13A to 13D, the solid line indicates the tracking error of the wafer stage, and the broken line indicates the tracking error of the reticle stage. 14A to 14D depict simulation responses when the first to fourth operations are implemented in the independent iterative learning control, which are comparative examples.

When the disturbance is applied to the wafer stage, the controllability of the wafer stage deteriorates. In this case, in the two-way synchronous control to which the iterative learning control is applied, the synchronization error that occurs due to the disturbance applied to the wafer stage is compensated by the control input to the reticle stage. Thus, the reticle stage is synchronized to track the wafer stage, and the wafer stage tracks the reticle stage during the high frequency band for an operation period of up to 0.05 seconds. In this manner, the two-way synchronization control is characterized as the synchronization errors compensated by the stations without distinction between the subject and the slave. In the prior art, it is difficult to adjust the control system of the two-way synchronous control. However, in the present exemplary embodiment of the present invention, it is possible to easily adjust the control system by repeatedly performing the iterative operation.

In Fig. 15, the solid line indicates the synchronization error generated by the two-way synchronization control to which the iterative learning control is depicted by Figs. 13A to 13D, and the broken line indicates the independent iterative learning control depicted by Figs. 14A to 14D. The resulting synchronization error. Similar to the undisturbed time, in the two-way synchronous control to which the iterative learning control is applied, the synchronization error may be quickly converged with the same number of iterations as compared to the independent iterative learning control.

Figure 16 depicts a comparison between the two-way synchronization control applied to the iterative learning control and the response of the master-slave synchronization control to which the iterative learning control is applied. In Fig. 16, the solid line indicates the synchronization error of the two-way synchronous control to which the iterative learning control is applied. The thick dashed line indicates the synchronization error of the master-slave synchronization control to which the iterative learning control is applied, and the thin dashed line indicates the synchronization error of the independent iterative learning control.

Figure 16 depicts the response during a period from 0.05 seconds to 0.07 seconds. Here, the stabilizing filters Q _W and Q _{R of} the wafer stage and the reticle stage have the same cutoff frequency, and the two-way synchronous control applied to the iterative learning control is slightly better than the iterative learning control applied to The master-slave synchronization control, but there is not much difference between them. This is because the reticle stage is used as a main body, and the wafer stage is used as a slave, and the effect of the two-way synchronous control is hard to occur. Therefore, the cutoff frequency of the stabilizing filter Q _R of the wafer stage is changed to 357 Hz and the learning filter is redesigned.

In this way, a feedforward input having a wider frequency component is applied to the reticle stage, and the bidirectional compensation of the synchronization error of the reticle stage is improved. In this case, a feedforward input that exceeds the servo bandwidth of the reticle stage is generated. Therefore, the feedforward input is to be adjusted such that it does not excite the vibration mode of the reticle stage. In the master-slave synchronization control, since there is no feedforward input to the reticle stage, it is not necessary to perform the adjustment. As a result, as described in FIG. 16, the two-way synchronization control to which the iterative learning control is applied can minimize the synchronization error.

Figure 24 is a schematic depiction of a scanning exposure apparatus including the control device in accordance with an exemplary embodiment of the present invention. The exposure apparatus according to the present embodiment is merely an example, and the present invention is not limited thereto. Light emitted from the illumination optical system 181 is incident on the photomask 182 of the original board. The pattern on the mask 182 is miniature and projected at the projection magnification of the miniature projection lens 184, and the pattern image is formed on the imaging surface.

The reticle 182 is placed on the movable reticle stage 183, and the position information of the reticle stage 183 is always measured by the laser interferometer 190. A mirror 189 for measuring the amount of light of the interferometer is fixed to the mask stage 183. A photoresist is applied to the surface of the wafer 185 which is to be exposed to the substrate, and a flash formed in the exposure process is disposed on the surface of the wafer. The wafer 185 is loaded onto the moving wafer table 186, and the position information of the wafer 186 is always measured by the interferometer 188. A mirror 187 for measuring the amount of light of the interferometer is fixed to the wafer table 186. Wafer table 186 and reticle stage 183 are simultaneously controlled during scanning (exposure).

The iterative learning control device 180 according to the exemplary embodiment of the present invention generates a control signal based on the position information output from the interferometer 190 and the interferometer 188. Then, the iterative learning control device 180 controls the positions of the mask table 183 and the wafer table 186, performs the iterative operation several times before the start of exposure, and generates a control input. After the exposure begins, iterative learning control device 180 may or may not update the control input.

Next, a method of manufacturing a device (for example, a semiconductor device or a liquid crystal display device) according to an exemplary embodiment of the present invention will be described. Here, a method of manufacturing a semiconductor device will be described as an example.

The semiconductor device is manufactured as a product by a pre-process in which an integrated circuit is formed on a wafer and a post-process in which an integrated circuit wafer is formed on a wafer. The pre-process includes a process of exposing a wafer having a photosensitizer thereto using the above exposure apparatus and a process of developing the wafer. The post process includes a combined process (dicing and pressure welding) and a packaging process (package). The liquid crystal display device is manufactured by a process of forming a transparent electrode. The process for forming a transparent electrode includes a process of applying a photosensitizer on a glass substrate having a transparent conductive film thermally adhered thereto, a process of exposing a glass substrate having a photosensitizer thereto using the above exposure apparatus, and developing the film The process of glass substrate.

According to the device manufacturing method of the present exemplary embodiment, it is possible to manufacture a high quality device as compared with the prior art.

The first exemplary embodiment relates to the two-way synchronization control. In the second exemplary embodiment, an example of multilateral synchronization control will be described. In this second exemplary embodiment, a description of components similar to those in the first exemplary embodiment will be omitted.

Figure 17 is a control block diagram depicting a control device according to a second exemplary embodiment. The control apparatus includes a control system P _S and iterative learning control circuit ILC, the control system comprising a plurality of targets. The control system P _S outputs w ₁ , w ₂ , ..., w _n (n is the number of axes to be synchronized), and the arithmetic units 31, 32, and 33 calculate synchronization errors h ₁ , h ₂ , ..., h _{n- 1} . The synchronization errors h ₁ , h ₂ , . . . , h _{n-1 are} input to the iterative learning control circuit ILC. The iterative learning control circuit ILC generates feedforward control inputs f ₁ , f ₂ , . . . , f _m based on the inputs and outputs the generated control inputs to the control system P _S .

Figure 18 is a block diagram showing the detailed structure of the control system P _S . The control system includes a control target P (m and 1 is a natural number equal to or greater than 2) having m inputs and 1 output, a detecting unit 6 detecting a position y of the control target, having 1 input and m The output feedback controller K and the subtraction unit 5 that subtracts the output of the detection unit from the target trajectory r. The feedforward control input is via the adder 4 to the input of the control target. The control system P _S obtains n outputs (n is a natural number equal to or greater than 2) to be synchronized between the one output of the control target, and calculates a matrix C _W for arbitrarily configuring the acquired outputs.

Fig. 19 is a block diagram showing the detailed structure of the iterative learning control circuit ILC. The iterative learning control circuit repeatedly performs tracking control on the target trajectory, similar to the first exemplary embodiment. All of the moving members (control axes) have the same target trajectory r, or the target trajectory of one moving member (control axis) is an integral multiple of the position of the other moving members (control axes).

The iterative learning control circuit ILC includes a learning filter L, m stable filter groups Q ₁ , Q ₂ , . . . , Q _m that cut off the learning band of the learning filter L, and stores the outputs of the stabilization filters. Memory devices 91 to 94.

When the number of iterative learning operations is k, the learning filter L generates m control inputs f ₁ based on n-1 synchronization errors h _1[k] , h _2[k] , . . . , h _{n-1[k] [k]} , f _2[k] , ..., f _m[k] , which are input. The generated input is fed forward to a moving member (control axis) corresponding to each control input.

Thus, in the exemplary embodiment, the control input and the synchronization error are expressed as follows:

f _[k] = [f _1[k] ,...,f _m[k] ] ^T (19), and

h _[k] = [h _1[k] ,...,h _n-1[k] ] ^T (20).

Since the digital control is implemented in a similar manner to the first exemplary embodiment, the control input of the i-th sample in the kth operation and the synchronization error are referred to as f _[k]i and h _[k]i .

Since the program flow according to the second exemplary embodiment is substantially the same as the program flow according to the first exemplary embodiment, a detailed description thereof will not be repeated. First, in the kth (k>2) operation, a control input f _{[k]i is} applied to the control target. In this case, the synchronization error h _{[k]i is} input to the learning filter L. The output of the learning filter L is applied to the control input f _[k]i by the adders 81 to 84, and the added value is passed through the stabilization filters Q ₁ , Q ₂ , ..., Q _m as the following (k+) 1) Control inputs are stored in these memories:

f _[k+1]i = [f _1[k+1] ,...,f _m[k+1] ] ^T (21).

This operation was repeated to decide all embodiments a synchronization error during a maximum value h _max of the operation is sufficiently small.

Second, the results of the simulation of the multilateral iterative learning control will be described. In this simulation, the control target has four axes. It is assumed that each shaft is a mass system and its mass is 40 kg.

When the outputs of the isometric are described as w ₁ , w ₂ , w ₃ , and w ₄ , the synchronization error between the axes is described as follows:

h ₁ =w ₁ -w ₂ (22)

h ₂ =w ₂ -w ₃ (23), and

h ₃ = w ₃ - w ₄ (24).

The feedback controller is designed for each axis and their servo bandwidths are 355 Hz, 306 Hz, 217 Hz, and 177 Hz. All of these stabilization filters are 5th order Battens filters with a 300 Hz cutoff frequency, and the learning filter with three inputs and four outputs is obtained by the same process as the first exemplary embodiment.

Figure 22 depicts the tracking error of the 5th iteration operation when the above control device is used to control all axes to track the target trajectory. The target trajectory indicated by the solid line in Fig. 9 is used. The first axis is indicated by a solid line, the second axis is indicated by a thick broken line, the third axis is represented by a single-dot chain line, and the fourth axis is indicated by a broken line. Sinusoidal disturbances having different frequencies are applied to the first and third axes. Figure 20 depicts the tracking error prior to the implementation of the iterative learning control, which is a comparative example.

Figure 23 depicts the synchronization error between the axes in the fifth iteration operation. The synchronization error between the first axis and the second axis is indicated by a solid line, the synchronization error between the second axis and the third axis is indicated by a broken line, and the synchronization error between the third axis and the fourth axis is Single point chain line representation. Figure 21 depicts the synchronization error prior to the implementation of the iterative learning control, which is a comparative example.

As can be seen from Figure 22, the tracking errors of all of the equiaxions are substantially equal to each other. As can be seen from Figure 23, the synchronization error between the axes is reduced. As can be seen from the comparison between Figures 22 and 20, there are no specific axes tracked for other axes. In other words, the multilateral synchronization control is achieved by the iterative learning control.

According to the present exemplary embodiment, in the bidirectional (multilateral) synchronous control, it is possible to improve the synchronization accuracy while simply acquiring or adjusting the control system.

While the invention has been described with reference to exemplary embodiments, it is understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the claims below is to be construed in the broadest scope of

1, 2, 91, 92, 93, 94, m. . . Memory

4, 16, 17, 81, 82, 83, 84. . . Adder

5. . . Subtraction unit

6. . . Detection unit

7, 8. . . Control circuit

11,12. . . Detection unit

13, 14. . . Subtraction unit

15. . . Computing unit

31, 32, 33. . . Arithmetic unit

71, L ₁ . . . First learning filter

72, L ₂ . . . Second learning filter

180. . . Iterative learning control device

181. . . Lighting optical system

182. . . Mask

183. . . Movable reticle

184. . . Miniature projection lens

185. . . Wafer

186, P _W . . . Wafer table

187, 189. . . Reflector

188, 190. . . Laser interferometer

C _W . . . matrix

e _R , e _W . . . deviation

e _R[k] , e _W[k] . . . Tracking error

F ₁ , F ₂ , F ₁ ', F ₂ '. . . filter

f _[k]i , f _m[k] , f _R[k] , f _W[k] , u _R[k] , u _W[k] . . . Control input

h _n-1 , y _S , y _S[k] . . . Synchronization error

ILC. . . Iterative learning control circuit

K, K _R , K _W , ‧‧‧Feedback controller

L‧‧‧ learning filter

N‧‧‧ Projection magnification

N _yW , u _R , u _W , w _n ‧‧‧ output

P‧‧‧Control target

‧‧‧Enhanced system

P _c1 ‧‧‧ Closed loop system

P _R ‧‧‧mask table

P _S ‧‧‧Control System

Q _m ‧‧‧stabilization filter group

Q _W , Q _R , ‧‧‧stable filter

r, Nr‧‧‧ target trajectory

Y‧‧‧ position

y _R , y _W , y _R[k] , y _W[k] ‧‧‧ Shift

The exemplary embodiments, features, and implementations of the present invention are described in conjunction with the accompanying drawings, and the description

1 is a block diagram depicting iterative learning control in accordance with a first exemplary embodiment.

2 is a flow chart depicting iterative learning control in accordance with a first exemplary embodiment.

3A, 3B, and 3C are block diagrams showing the detailed structure of the learning filter depicted in FIG. 1.

4 is a block diagram depicting an enhancement system associated with shifting wafer table and reticle stage, and synchronization error as an output.

Figure 5 is a block diagram depicting bidirectional iterative learning control using the enhanced system depicted in Figure 4.

Figure 6 is a block diagram depicting a closed loop system depicted in the combination of the enhanced system and the feedback system of Figure 4.

Figure 7 is a block diagram depicting a generalized control object for obtaining an iterative learning filter.

Figure 8 is a diagram depicting the gain of the learned filter.

Figure 9 is a diagram depicting the target trajectory of the wafer stage and the reticle stage.

10A to 10D are diagrams depicting tracking errors as analog responses according to the first exemplary embodiment.

11A through 11D are graphs depicting tracking errors as a response to an independent iterative learning control simulation.

Figure 12 is a diagram depicting synchronization errors as a simulated response in accordance with a first exemplary embodiment.

Figures 13A through 13D are graphs depicting tracking error as a simulated response when a disturbance occurs in a first exemplary embodiment.

Figures 14A through 14D are graphs depicting tracking errors as a response to an independent iterative learning control simulation when a disturbance is applied.

Figure 15 is a graph depicting the synchronization error as a simulated response when a disturbance occurs in the first exemplary embodiment.

Figure 16 is a diagram depicting synchronization errors as simulated responses in accordance with a first exemplary embodiment.

Figure 17 is a block diagram depicting iterative learning control in accordance with a second exemplary embodiment.

Figure 18 is a diagram depicting the detailed structure of the control system P _S depicted in Figure 17.

FIG. 19 is a diagram depicting the detailed structure of the iterative learning control circuit ILC depicted in FIG.

Figure 20 is a diagram depicting tracking error as a simulated response when iterative learning control according to the second exemplary embodiment is not implemented.

Figure 21 is a diagram depicting the synchronization error as a simulated response when the iterative learning control according to the second exemplary embodiment is not implemented.

Figure 22 is a diagram depicting tracking error as a simulated response in accordance with a second exemplary embodiment.

Figure 23 is a diagram depicting synchronization errors as a simulated response in accordance with a second exemplary embodiment.

Figure 24 is a diagram depicting an exposure apparatus.

1, 2. . . Memory

16, 17. . . Adder

7, 8. . . Control circuit

11,12. . . Detection unit

13, 14. . . Subtraction unit

15. . . Computing unit

e _R , e _W . . . deviation

f _R[k] , f _W[k] . . . Control input

K _R , K _W . . . Feedback controller

L. . . Learning filter

N. . . Projection magnification

u _R , u _W . . . Output

Q _W , Q _R . . . Stabilization filter

y _R , y _W . . . Shift

Ys[k]. . . Synchronization error

P _W . . . Wafer table

P _R . . . Mask table

ILC. . . Iterative learning control circuit

f _W[k+1]i , f _R[k+1]i . . . Deposited in memory

Claims (17)

A control device comprising: a first control circuit configured to control a position of a first control target; a second control circuit configured to control a position of a second control target; a computing unit, configuration Calculating a synchronization error between the first control target and the second control target; and an iterative learning control circuit, including inputting the synchronization error to the first and second learning filters, and configuring And assigning a control input to the second control target based on an output of the first learning filter to a control input to the first control target and based on the output of the second learning filter. The control device of claim 1, wherein each of the first and second learning filters includes a transfer function of the first and second control targets and a transfer function of a controller of the first and second control circuits . The control device of claim 1, wherein the first learning filter includes a transfer function of the first control target and a transfer function of a controller of the first control circuit, and the second learning filter A transfer function of the second control target and the transfer function of the controller of the second control circuit are included. The control device of claim 3, wherein a part of the output of the first learning filter is added to the second The output of the filter is applied, and a portion of the output of the second learning filter is applied to the output of the first learning filter. The control device of claim 1, wherein the iterative learning control circuit comprises: a first stabilization filter configured to transmit a predetermined frequency band of the output of the first learning filter; and a second stabilization A filter configured to transmit a predetermined frequency band of the output of the second learning filter. The control device of claim 1, wherein the iterative learning control circuit comprises: a first memory device configured to store the output of the first learning filter; and a second memory device, a group The state is stored to store the output of the second learning filter. A control device comprising: a control circuit configured to control a position of each of a plurality of control targets; a calculation unit configured to calculate a synchronization error between the plurality of control targets; and an iterative learning control a circuit comprising: inputting the synchronization error to a plurality of learning filters thereof, and configured to, based on one of each of the learning filters, direct a control input to each of the learning filters The control target. The control device of claim 7, wherein the plurality of learning filters include a transfer function of the plurality of control targets and a transfer function of a controller of the plurality of control circuits. The control device of claim 7, wherein the output of each of the learning filters is added to the output of the other learning filter. A scanning exposure apparatus comprising: the control device according to any one of claims 1 to 4, wherein one of the substrates placed on one of the substrates and one of the original plates placed thereon is contained. One unit is synchronized with each other by the control device. A method of manufacturing a device comprising: exposing a substrate to a pattern using a scanning exposure apparatus as in claim 10; and developing the exposed substrate. A control method includes: controlling a position of a first control target; controlling a position of a second control target; calculating a synchronization error between the first control target and the second control target; and an iterative learning The control method includes inputting the synchronization error to the first and second learning filters thereof, and granting a control input to the first control target based on an output of the first learning filter and based on the second learning One of the filters outputs a control input to the second control target. For example, the control method of claim 12, Each of the first and second learning filters includes a transfer function of the first and second control targets and a transfer function of a controller of the first and second control circuits. The control method of claim 12, wherein the first learning filter includes a transfer function of the first control target and a transfer function of a controller of the first control circuit, and the second learning filter A transfer function of the second control target and the transfer function of the controller of the second control circuit are included. The control method of claim 14, wherein a portion of the output of the first learning filter is added to the output of the second learning filter, and a portion of the output of the second learning filter is added. To the output of the first learning filter. The control method of claim 12, wherein the iterative learning control method comprises: transmitting a predetermined frequency band of the output of the first learning filter; and transmitting a predetermined frequency band of the output of the second learning wave filter . The control method of claim 12, further comprising: storing the output of the first learning filter; and storing the output of the second learning filter.