TWI424483B - Die seal ring - Google Patents

Description

Grain seal

The invention relates to a grain sealing structure, in particular to a grain sealing structure capable of blocking noise.

Due to the continuous advancement of semiconductor process technology, a large number of circuit components can be fabricated on a single wafer, coupled with the market demand for a variety of electronic products with high complexity and powerful functions, so that the entire circuit of a single chip can be integrated. It includes functions such as microprocessor, memory, peripheral and chip bus to achieve low power, high efficiency, small size and high reliability.

With the continuous advancement of the integrated circuit in the process, the complexity of the chip design has also increased, resulting in less demand for the time-to-market. System-on-a-chip (SoC) integrates computing functions (such as microprocessor cores, digital signal processing cores, MPEG cores or graphics cores), as well as memory, logic/analog circuits, and mixed-signal circuits. Or the RF circuit is on a single wafer for a specific purpose integrated circuit IC. The system's single chip provides a high degree of integration of integrated circuit ICs, greatly simplifying system design, reducing manufacturing costs, and reducing time-to-market.

Please refer to FIG. 1 , which is a top view of a conventional single crystal structure of a system. As shown in FIG. 1, a semiconductor substrate 12, such as a germanium wafer, is first provided, and then a die region 14, a die seal ring region 16, and a dicing street are defined on the semiconductor substrate 12. Subscribe line) area 18. Wherein, the periphery of the die of the die region 14 is provided with a plurality of input/output pads (I/O pads) 26 which are disposed on the periphery of the die region 14 and the die seal region 16 and cover the entire die. The ring seal region 16 is disposed between the die region 14 and the dicing region 18 to serve as a retaining wall structure when the wafer is diced and to avoid stress damage to the die region 14. The scribe line area 18 is mainly divided into two parts, including a first part 20 and a second part 22. The first portion 20 is adjacent to the die seal region 16 and is not cut by the cutter when the wafer is diced. The second portion 22 of the scribe line region 18 is disposed on the outer periphery of the first portion 20, and a plurality of wafer acceptance test pads 24 can be disposed on the process according to the process requirements. For example, four wafer test pads are used, and this part is cut by the tool when cutting the wafer.

In the design of system single-chip, noise interference, such as analog digital block interference or electromagnetic interference (EMI), is an urgent problem to be solved. Taking the above-described conventional system single-chip architecture as an example, the input/output pad provided in the die area 14 is adjacent to the die seal region 16, so that the noise generated by the input/output pad 26 is easily The entire die seal diffuses and extends to the surrounding area, affecting the operation of the entire component. Since noise interference can seriously affect the performance of the wafer operation, the wafer must address these issues during the physical design phase.

Therefore, the present invention discloses a die seal structure to improve the problem that conventional crystal ring seals are prone to noise.

According to a preferred embodiment of the present invention, the die ring is disposed on a periphery of the die region of the semiconductor substrate, and includes: a first isolation structure, a second isolation structure, and a plurality of third isolation structures disposed on the first Between the isolation structure and the second isolation structure; a plurality of first regions are disposed between the first isolation structure, the second isolation structure, and the third isolation structure; a second region is disposed under the first region and the third isolation structure; And a third region is disposed under the first isolation structure and a fourth region is disposed under the second isolation structure.

The invention mainly forms different types of wells in the semiconductor substrate in the grain sealing zone and under the shallow trench isolation, such as a P-type well and an N-type well, and the position between the P-type well and the N-type well. Can be poor to block the noise transmitted by the grain area. In addition, the present invention may alternatively form different types of doped regions or Schottky contacts between the shallow trench isolation and the semiconductor substrate above the well, as well as making deeper deep wells below the well. The conductive patterns of the doped regions, wells, and deep wells may each be composed of dopants of the same or different conductivity types.

Please refer to FIG. 2 to FIG. 3 . FIG. 2 is a top view of the die seal ring according to the first embodiment of the present invention, and FIG. 3 is a cross section of the die seal ring along the tangential line AA′ in FIG. 2 . schematic diagram. As shown in FIGS. 2 to 3, a semiconductor substrate 42, such as a P-type semiconductor substrate, is first provided, and then a die region 44 is defined on the semiconductor substrate 42 (only a die region is exemplified in the figure) and A grain sealing zone 46. The die region 44 has a circuit region (not shown), and the die seal region 46 is disposed on the periphery of the die region 44 and exhibits an approximately octagonal shape. An isolation process is then performed, such as a shallow trench isolation process in the circuit region to form a plurality of shallow trench isolations 54, 56, 58 in the region of the semiconductor substrate 42 adjacent the surface. Then, a P-type well 50 and an N-type are respectively formed in the semiconductor substrate 42 of the die-sealing region 46 by an ion implantation process, for example, an ion implantation process which can be accompanied by a P-type well and an N-type well in the circuit region. Well 52 is disposed around P-well 50. Subsequent to another ion implantation process, such as an ionic source/drainage ion implantation process in the circuit region, to form a P+ on the surface of the P-well 50 between the shallow trench isolations 54, 56, 58 Doped region 60. The interlayer dielectric layer process and the contact plug process in the die region 44 can then be selected according to the product requirements to form an interlayer dielectric layer 78 and a plurality of interlayer dielectric layers in the die ring region 46. The conductive plugs 80 in the electrical layer 78 are respectively connected to the P+ doped regions 60, and the contact plugs 80 can be connected to the interconnect structure, in particular the via bar and the metal bar. This practice is also within the scope of the invention. Finally, a contact pad process is performed to form a plurality of input/output pads 48 in the die region 44.

In the present embodiment, the P+ doping region 60 is disposed between the shallow trench isolations 54, 56, 58. The P-well 50 is a semiconductor substrate disposed under the P+ doping region 60 and the shallow trench isolations 54, 56, 58. 42, while the N-well 52 is disposed in the semiconductor substrate 42 below the shallow trench isolation 54 and the shallow trench isolation 58 and surrounds the P-well 50 at the same time. A PN junction is formed between the N-well 52 disposed below the shallow trench isolation 54 and the shallow trench isolation 58 and the P-well 50 also surrounding the N-well 52, and each has a different fee. The Fermi level, so the present invention can be transmitted by the input/output pads 48 of the die region 44 by the energy difference produced by the two different conductivity types 50, 52. The noise. It should be noted that, in this embodiment, although the P-type well 50 is implanted on the P-type semiconductor substrate 42 by P-type ions, the step may be omitted, and the P-type well 50 is directly replaced by the P-type semiconductor substrate 42 and then Forming the N-well 52 described above around the P-type semiconductor substrate 42 is also within the scope of the present invention.

Please refer to FIG. 4 to FIG. 5 . FIG. 4 to FIG. 5 are schematic cross-sectional views of a die seal ring according to another embodiment of the present invention. As shown in the figure, a P-type semiconductor substrate 42 is first provided, and then an N-type ion implantation process is performed after the shallow trench isolation process to form a deep N in the region around the semiconductor substrate 42 in the die seal region 46. A deep n-well 62, as shown in FIG. 4, or a semiconductor substrate 42 in the die seal region 46 forms a deep N well 64 relative to the central region, as shown in FIG. Then, a P-type well 50 and an N-type 52 well surround the P-type well 50 are formed by implanting N-type and P-type ions in the semiconductor substrate 42 on the deep N well 62 or 64, respectively. Another ion implantation process is then performed to form a plurality of P+ doped regions 60 on the surface of the P-well 50 between the shallow trench isolations 54, 56, 58. Similarly, the required processes can be a single independent process or a semiconductor process accompanying various components in the circuit region. For example, each of the P+ doping regions 60 can be selectively electrically connected by a conductive plug (not shown). The practice is also within the scope of this embodiment.

In the embodiments of FIGS. 4 and 5, the P+ doping region 60 is disposed between the shallow trench isolations 54, 56, 58 and the P-well 50 is disposed between the P+ doping region 60 and the shallow trench isolation 54, The semiconductor substrate 42 below the 56, 58 and the N-well 52 are disposed in the semiconductor substrate 42 below the shallow trench isolation 54 and the shallow trench isolation 58 and surround the P-well 50 at the same time. In the embodiment of FIG. 4, the deep N well 62 is disposed in the semiconductor substrate 42 directly below the N-well 52, and in the embodiment of FIG. 5, the deep N well 64 is disposed in the P-well 50. Directly below and in the semiconductor substrate 42 below the portion of the N-well 52.

Please refer to FIG. 6. FIG. 6 is a schematic cross-sectional view showing a grain seal ring in which a P+ doped region is replaced by a Schottky contact according to another embodiment of the present invention. As shown in FIG. 6, similarly, a P-type semiconductor substrate 42 is first provided, and then a P-type well 50 is formed in the semiconductor substrate 42 of the die-sealing region 46 by ion implantation process after the shallow trench isolation process. An N-type well 52 is disposed around the P-type well 50. A tantalum metal process is then performed to form a plurality of Schottky contacts 66 on the surface of the P-well 50 between the shallow trench isolations 54, 56, 58. For example, a salicide process on the die region 44 can be used to form a metal layer (not shown) composed of cobalt, titanium, nickel, platinum, palladium or molybdenum. The surface of the semiconductor substrate 42 of the die ring-locking region 46 is then subjected to a heat treatment for reacting the metal layer with the semiconductor substrate surface 42 using a high temperature to form a plurality of Schottky contacts 66, and finally removing the unreacted metal layer. In the present embodiment, since the surface of the semiconductor substrate 42 of the die seal region 46 does not have any doped regions, the formed Schottky contact 66 has an effect similar to that of the PN junction and can be used to block the crystal grains. The noise transmitted by the input/output pad 48 of the area 44.

Please refer to FIG. 7 to FIG. 8 . FIG. 7 to FIG. 8 are schematic cross-sectional views of a die seal ring according to another embodiment of the present invention. As shown in FIGS. 7 and 8, the present invention can also integrate the Schottky contact process disclosed in FIG. 6 and the deep N well process disclosed in FIGS. 4 and 5 to complete another die seal. The design of the ring. For example, a deep N well 62 may be formed in the area surrounding the P-type semiconductor substrate 42 within the grain seal region 46 after the shallow trench isolation process, as shown in FIG. 7, or in the grain seal region 46. The inner semiconductor substrate 42 forms a deep N-well 64 relative to the central region, as shown in FIG. Then, a P-type well 50 and an N-type well 52 are formed in the semiconductor substrate 42 of the deep N well 62 or 64 by N-type and P-type ions, respectively, and the N-type well 52 is simultaneously set in the deep N well. Directly above 62, as shown in Figure 7, or deep N well 64 is placed just below P-well 52 and below part of N-well 52, as shown in Figure 8. Finally, the Schottky contact process described in FIG. 6 is performed to form a plurality of Schottky contacts 66 on the surface of the semiconductor substrate 42 between the shallow trench isolations 54, 56, 58. Similarly, the required processes can be a single process or a semiconductor process that accompanies various components in the circuit region. For example, a Schottky contact 66 can be selectively electrically connected to a conductive plug (not shown). The practice is also within the scope of this embodiment.

Please refer to Fig. 9 to Fig. 12, and Fig. 9 to Fig. 12 are variations of the embodiment in Fig. 3. As shown in FIG. 9, a P-type semiconductor substrate 42 may be provided first, and then an N-type and P-type ion implantation may be sequentially performed after the shallow trench isolation process to form an N-type well 70 in the semiconductor substrate 42 and A P-well 72 surrounds the N-well 70. Another ion implantation process is then performed to form a plurality of P+ doped regions 74 on the surface of the N-well 70 between the shallow trench isolations 54, 56, 58. Structurally, the P+ doped region 74 is disposed between the shallow trench isolations 54, 56, 58. The P+ doped region 74 and the shallow trench isolations 54, 56, 58 are provided with an N-type well 70, and the shallow trench is isolated. A P-well 72 is surrounded just below the 54 and 58 and around the N-well 70. In this embodiment, the N-well 70 and the P-well 72 have a PN junction, and the N-well 70 and the P+-doping 74 also have a PN junction. The difference in bit energy generated between the PN junctions blocks the noise transmitted by the input/output pads 48 of the die region 44.

The die seal shown in Fig. 10 is similar to the structure disclosed in Fig. 9. The main difference is that the shallow trench isolations 54, 56, 58 are formed by replacing the P-type ion implants with N-type ion implantation. A plurality of N+ doped regions 76 are formed on the surface of the N-well 70 between the shallow trench isolations 54, 56, 58. Structurally, the N+ doped region 76 is disposed between the shallow trench isolations 54, 56, 58. The N+ doped region 76 and the shallow trench isolations 54, 56, 58 are provided with an N-type well 70, and the shallow trench is isolated. A P-well 72 is surrounded just below the 54 and 58 and around the N-well 70. Since both the N-well 70 and the N+ doped region 76 have the same dopant, in this embodiment only a potential difference is generated between the N-well 70 and the surrounding P-well 72.

The die seal shown in Fig. 11 is similar to the structure disclosed in Fig. 3, the main difference being that the formation of shallow trench isolations 54, 56, 58 will replace the P-type ion implantation with N-type ion implantation. A plurality of N+ doped regions 76 are formed on the surface of the P-well 50 between the shallow trench isolations 54, 56, 58. Structurally, the N+ doped region 76 is disposed between the shallow trench isolations 54, 56, 58. The N+ doped region 76 and the shallow trench isolations 54, 56, 58 are provided with a P-type well 50, and the shallow trench is isolated. An N-type well 52 surrounds the lower portion of the 54 and 58 and the P-type well 50. In this embodiment, the P-well 50 has a PN junction with the surrounding N-well 52, and the P-well 50 and the N+ doping 76 also have a PN junction, thereby generating potential energy. difference.

The grain seal disclosed in Fig. 12 mainly incorporates the previously described deep N well process and the structure shown in Fig. 11. Structurally, the N+ doped region 76 is disposed between the shallow trench isolations 54, 56, 58. The N+ doped region 76 and the shallow trench isolations 54, 56, 58 are provided with a P-type well 50, and the shallow trench isolation 54 An N-type well 52 is surrounded by the bottom of the 58 and the P-type well 50, and a deep N well 64 is disposed under the P-type well 50 and the partial N-type well 52. In this embodiment, the P-well 50 will have a PN junction with the N+ doped region 76, the N-well 52, and the deep N well 64 to generate a potential difference to block the input/output pads 48 of the die region 44. The noise that was transmitted. In addition, the processes required in FIGS. 9 to 12 can be a single independent process or a semiconductor process accompanying various components in the circuit region. For example, a conductive plug (not shown) can be selectively connected to each P+. The doped region 74 or the N+ doped region 76 is also within the scope of this embodiment.

Please refer to FIG. 13, which is a diagram of a die seal ring according to an embodiment of the present invention. As shown in the figure, the grain seal ring region 46 is surrounded by the periphery of the die region 44 in a straight line and a continuous pattern as compared to the above embodiment, and the present invention may be selected as a staggered type and separated. The pattern surrounds the die seal region 46 around the die region 44 and is thereby designed to block the transmission of noise. In addition, the present invention can directly arrange the staggered die seal ring structure in the die ring ring region according to the requirements of the product, or can selectively integrate the staggered design and various die seal rings disclosed in the foregoing embodiments. Structures, such as forming different conductivity type wells and doped regions in a semiconductor substrate, etc., are variations within the scope of the present invention.

In summary, the present invention mainly forms different types of wells in a semiconductor substrate in a grain sealing zone and under shallow trench isolation, such as a P-type well and an N-type well, and is formed by a P-type well and an N-type well. The potential difference between the wells blocks the noise transmitted by the grain regions. In addition, the present invention may alternatively form different types of doped regions or Schottky contacts between the shallow trench isolation and the semiconductor substrate above the well, as well as making deeper deep wells below the well. According to the above embodiments, the conductivity patterns of the doped regions, wells, and deep wells may each be composed of dopants of the same or different conductivity types.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

12. . . Semiconductor substrate

14. . . Grain zone

16. . . Grain seal zone

18. . . Cutting road area

20. . . first part

twenty two. . . the second part

twenty four. . . Wafer test pad

26. . . Input/output pad

42. . . Semiconductor substrate

44. . . Grain zone

46. . . Grain seal zone

48. . . Input/output pad

50. . . P-well

52. . . N-type well

54. . . Shallow trench isolation

56. . . Shallow trench isolation

58. . . Shallow trench isolation

60. . . P+ doped region

62. . . Deep N well

64. . . Deep N well

66. . . Schottky contact

70. . . N-type well

72. . . P-well

74. . . P+ doped region

76. . . N+ doped region

78. . . Interlayer dielectric layer

80. . . Conductive plug

Figure 1 is a top view of a conventional system single wafer structure.

Fig. 2 is a top plan view of a die seal ring according to a first embodiment of the present invention.

Figure 3 is a schematic cross-sectional view of the die seal ring along the tangential line AA' in Figure 2.

4 to 5 are schematic cross-sectional views showing a grain seal ring according to another embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view showing a grain seal ring in which a P+ doped region is replaced by a Schottky contact according to another embodiment of the present invention.

7 to 8 are schematic cross-sectional views showing a grain seal ring according to another embodiment of the present invention.

9 to 12 are schematic cross-sectional views showing a grain seal ring according to another embodiment of the present invention.

Figure 13 is a diagram of a die seal ring in accordance with an embodiment of the present invention.

42. . . Semiconductor substrate

50. . . P-well

52. . . N-type well

54. . . Shallow trench isolation

56. . . Shallow trench isolation

58. . . Shallow trench isolation

60. . . P+ doped region

78. . . Interlayer dielectric layer

80. . . Conductive plug

Claims (18)

A die ring is disposed on a periphery of a die region of a semiconductor substrate, and includes: a first isolation structure, a second isolation structure, and at least one third isolation structure disposed on the first isolation structure and the second Between the isolation structures; a plurality of first regions are disposed between the first isolation structure, the second isolation structure, and the third isolation structure; a second region is disposed between the first regions and the third isolation structure And a third region is disposed only under the first isolation structure and the second isolation structure, wherein the second region directly contacts the first region, the third region, the first isolation structure, and the second isolation structure And the third isolation structure, and further the third region comprises an N-type well. The grain seal ring of claim 1, wherein the first region and the second region have different conductivity type dopants. The die seal of claim 1, wherein the first region and the second region have the same conductivity type dopant. The grain seal ring of claim 1, wherein the second region and the third region have different conductivity type dopants. The die seal ring of claim 1, further comprising a fourth region disposed under the second isolation structure. The grain seal ring of claim 5, wherein the second region and the fourth region have different conductivity type dopants. The die seal of claim 5, wherein the third region and the fourth region have the same conductivity type dopant. The grain seal ring of claim 5, wherein the third zone and the fourth zone are an N well, a P well, an N well, and a deep N-well. Combination, or a P-type semiconductor substrate. The die seal ring of claim 5, further comprising a fifth region disposed at least part of the second region, the third region or the fourth region. The grain seal ring of claim 9, wherein the second region and the fifth region have different conductivity type dopants. The grain seal ring of claim 9, wherein the second region and the fifth region have the same conductivity type dopant. The die seal of claim 9, wherein the third region, the fourth region, and the fifth region have the same conductivity type dopant. The grain seal ring of claim 9, wherein the fifth zone is a deep N well. The grain seal ring of claim 1, wherein the grain seal ring is a staggered type structure. The die seal ring of claim 1, further comprising a plurality of contact plugs for connecting the first regions. The die seal of claim 1, wherein the first isolation structure, the second isolation structure, and the third isolation structure comprise shallow trench isolation. The grain seal ring of claim 1, wherein the first region comprises an N+ doped region, a P+ doped region, or a Schottky contact. The grain seal ring of claim 1, wherein the second region is an N well, a P well or a P-type semiconductor substrate.