TWI497087B - Semiconductor wafers, and testing methods thereof - Google Patents

Description

Semiconductor wafer and its test method

The present invention is primarily a semiconductor wafer, particularly a semiconductor wafer having an off-chip test circuit for testing a die.

At present, in a conventional semiconductor wafer process, an integrated circuit formed in a die (or a wafer) needs to be tested for functionality, program integrity, device characteristics, and reliability. 1 is a top view of a conventional semiconductor wafer 10 including a plurality of dies 12 formed on a die wafer 14 on a semiconductor wafer 10, and other regions on the semiconductor wafer 10 are defined as Cutting area 16. Further, in the conventional semiconductor wafer 10, a test circuit 18 for testing an integrated circuit in a die is also formed in the die in the die region 14. However, the embedding of the test circuit 18 into the die increases the size of the die, in other words, the range of die regions that can be provided to the main integrated circuit is relatively reduced. Furthermore, in view of the problem of the size of the die, the test function of the test circuit needs to be reduced.

Furthermore, the test circuit 18 for the conventional semiconductor wafer 10 can be used as a test interface (eg, conductive pads, conductive bumps) for external test equipment, so that the external test equipment can obtain test information or test results. Determine if the tested die is normal. However, users who attempt to steal information may use this test interface to steal information from the integrated circuits in the die, which is quite unsafe. Therefore, there is a need for an improved test circuit and method.

In order to solve the above problems, the present invention provides a semiconductor wafer having a die region and a dicing region, and the semiconductor wafer includes a die and a test circuit. The die is formed on the die region of the semiconductor wafer and has a main circuit. The test circuit is disposed on the dicing region of the semiconductor wafer and electrically connected to the die to test the main circuit. In some embodiments of the present invention, the test circuit can be divided into two parts, wherein a part of the test circuit is disposed in the cutting area, and another part of the test circuit is disposed in the die area.

In some embodiments, the semiconductor wafer further includes a ring and a well region. The seal ring is disposed on the periphery of the die, and the well region is formed under the seal ring. The test circuit is electrically connected to the die through the well region.

In some embodiments, when testing the main circuit, the test circuit further transmits a test data to the main circuit. And when the main circuit receives the test data, transmitting a response data to the test circuit, and then the test circuit determines whether the response data is the same as the test data to detect the connection reliability.

In some embodiments of the invention, the die further includes a decoding circuit coupled between the main circuit and the test circuit. The test circuit further encodes the test data and transmits the encoded test data to the decoding circuit, and the decoding circuit decodes the encoded test data. The main circuit transmits the response data according to the test data of the decoding circuit.

In some embodiments of the invention, the die further has a non-volatile memory fuse for storing a value that determines a function of one of the main circuits. The test circuit described above provides a high voltage to the non-volatile memory fuse to perform an erase operation or a write operation.

The present invention further provides a test method suitable for a semiconductor wafer having a die region and a dicing region. The above test method includes: forming a die on the die region of the semiconductor wafer, wherein the die comprises a main circuit; forming a test circuit in the cutting region of the semiconductor wafer; and electrically connecting the test The circuit is applied to the above die to test the above main circuit.

In some embodiments of the present invention, the testing method further includes: forming a ring around the periphery of the die; and forming a well region to electrically connect the test circuit to the main circuit of the die. Further, the well region is formed below the seal ring.

In some embodiments of the present invention, the testing method further includes: transmitting, by the test circuit, a test data to the main circuit; receiving, by the test circuit, response data from one of the main circuits; and determining whether the response data is the same The above test data. In addition, the main circuit of the die described above generates the response data according to the test data.

In some embodiments of the invention, the die further includes a decoding circuit coupled between the main circuit and the test circuit. In this embodiment, the testing method further includes: encoding the test data; transmitting the encoded test data to the decoding circuit; and decoding the encoded test data by using the decoding circuit. In addition, the above main circuit is based on the above decoded power The above test data of the road transmits the above response data.

In some embodiments of the invention, the die further has a non-volatile memory fuse for storing a value that determines a function of one of the main circuits. In this embodiment, the above test method further comprises: using the test circuit to provide a high voltage to the non-volatile memory fuse to perform an erase operation or a write operation.

10, 100‧‧‧ semiconductor wafer

12, 120‧‧‧ grain

14, 140‧‧‧ grain area

16, 160‧‧‧ cutting area

18, 180‧‧‧ test circuit

122‧‧‧Main circuit

124‧‧‧Decoding circuit

126‧‧ ‧ ring

DNW‧‧‧Deep N well

Ls‧‧‧ cutting line

NW1, NW2‧‧‧N well

N+‧‧‧N+ diffusion zone

PSUB‧‧‧P type substrate

The disclosure of the present invention can be more fully understood by reading the following detailed description and the accompanying drawings. FIG. 1 is a top view showing a conventional semiconductor wafer 10 including a plurality of dies and test circuits.

2 is a top view of a semiconductor wafer including a plurality of dies and a test circuit in accordance with an embodiment of the present invention.

3 is a schematic diagram showing a die and a test circuit according to an embodiment of the invention.

4A is a schematic diagram of a die and a test circuit in accordance with an embodiment of the present invention.

4B is a partial cross-sectional view of a semiconductor wafer in accordance with an embodiment of the present invention.

Embodiments of the invention are described below in conjunction with the drawings. It should be understood that the present description provides various embodiments to illustrate the technical features of various embodiments of the invention. The arrangement of the components in the embodiments is for the purpose of simplifying the description and is not intended to limit the invention. In addition, the parameters in the embodiment may be Repetition is repeated for the sake of simplicity of description and does not imply an association between different embodiments.

2 is a top view of a semiconductor wafer including a plurality of dies and a test circuit in accordance with an embodiment of the present invention. In this embodiment, semiconductor wafer 100 includes a plurality of dies 120 and a plurality of test circuits 180. The dies 120 are distributed in respective die regions 140 on the semiconductor wafer 100, and the test circuit 180 is distributed over the dicing regions 160. In addition, the test circuit 180 is separately disposed beside the corresponding die 120, and the test circuit 180 is electrically connected to the corresponding die 120 to test the main circuit of the die 120.

In one embodiment, when testing the main circuit in die 120, test circuit 180 tests the main circuit through the path of its electrical connections. For example, the test circuit 180 can communicate with the main circuit in the die 120 through the connection path, and the test circuit 180 determines the test result of the die 120 according to the response of the main circuit. It will be appreciated that the test circuit 180 can provide different commands, data, external bias signals, and/or combinations thereof (hereinafter referred to as "test signals") to the main circuit of the die 120 for testing purposes. Additionally, the main circuit in die 120 can have a dedicated bus bar for testing that receives the aforementioned test signals from test circuit 180. In addition, the main circuit of the die 120 can have a general data bus. After the synchronization between the main circuit of the die 120 and the test circuit 180 is established, the general data bus can also receive the test signal from the test circuit 180. Used as a test. In the semiconductor wafer process, after the die 120 is tested, the die 120 can be divided into individual components by removing the dicing region 160. Since the test circuit 180 formed in the cutting area 160 is also removed in this program, the user attempting to steal information cannot use the test power. Path 180 accesses the information in die 120. The testing of the dies will be further explained in the following paragraphs.

In an embodiment of the invention, the test circuit 180 can transmit test data to the main circuit of the die 120 to test the connection reliability. When the main circuit of the die 120 receives the test data, the main circuit can transmit the response data to the test circuit 180. Finally, the test circuit 180 determines whether the connection is normal or not based on the response data of the main circuit of the die 120. For example, when detecting connection reliability, the test circuit 180 can determine whether the response data is the same as the test data. When the response data is the same as the test data, the test circuit 180 can determine that the connection is normal. When the response data is different from the test data, the test circuit 180 can determine that the connection is an error. In some embodiments, for security reasons to avoid users attempting to steal information into the test mode, the data from the test circuit 180 can be encoded, and the main circuit in the die 120 can decode and determine the received data. Whether the information comes from a trusted source. In addition, synchronization will be established when the data received by the main circuit in die 120 is from a trusted source.

It should be appreciated that in some embodiments there may be external test equipment. In this embodiment, test circuit 180 can provide an output to an external test device, while an external test device can collect test information from test circuit 180. In some embodiments, the test circuit can provide an input to an external test device, while an external test device can control the test circuit 180 for testing.

In order to improve the information security of the main circuit in the die, the present invention further provides a decoding system. 3 is a schematic diagram showing a die and a test circuit according to an embodiment of the invention. In an embodiment of the invention, die 120 includes a main circuit 122 and a decoding circuit 124. Decoding circuit 124 is connected to main circuit 122 is between the test circuit 180. To test the main circuit 122, the test circuit 180 encodes the test data/instructions and transmits the encoded test data/instructions to the decode circuit 124. Next, the decoding circuit 124 decodes the encoded test data/instructions and provides the decoded test data/instructions to the main circuit 122. When the main circuit 122 receives the decoded test data/instruction, the response data is transmitted to the test circuit 180. Finally, the test circuit 180 can determine the result of the test based on the response data of the main circuit 122. It should be appreciated that in some embodiments of the invention, decoding circuitry 124 may also be included in main circuitry 122. Since the communication between the main circuit 122 and the test circuit 180 has a mechanism of encoding and decoding through the decoding circuit 124, a user attempting to steal information cannot easily access the correct data/instruction in the main circuit, thereby strengthening the main The safety of the circuit.

In some embodiments of the invention, the die may comprise a non-volatile memory fuse. This non-volatile memory fuse is used to store values that determine the function of the main circuit in the die 120, and these values in the non-volatile memory fuse are set during the test. Therefore, in order to ensure that the non-volatile memory fuse is tampered with after the die cutting process, the erase operation of the non-volatile memory fuse is only provided by the test circuit 180. For example, test circuit 180 can provide a high voltage to non-volatile memory fuse to perform an erase operation. Since the communication path between the non-volatile memory fuse and the test circuit 180 is removed after the die cutting process, the contents of the non-volatile memory fuse can be protected.

In some embodiments of the present invention, in order to avoid stress and contamination of the die 120 by die cutting, a seal may be formed around the die 120, as shown in Figures 4A and 4B. 4A is a schematic diagram of a die and a test circuit in accordance with an embodiment of the present invention. In this embodiment, the seal ring 126 can be made of a metal layer, An oxide layer, a diffusion layer, or a combination thereof is formed. Since the seal ring 126 is disposed on the periphery of the die 120, if the test circuit 180 is disposed in the cut region 160 of the die region 160 as shown in FIG. 2, the test circuit 180 will be difficult to electrically connect to the main circuit of the die 120. It should be noted that although the metal layer or the diffusion layer can serve as a communication path or a connection path between the main circuit 122 of the die 120 and the test circuit 180, it is only necessary to break the seal ring 126 to form an opening. However, the opening of the seal ring 126 may cause contamination of the die 120, and the opening is easily observed by a user attempting to steal information, thereby increasing the risk of the information being stolen.

In order to solve the above problems, an embodiment of the present invention provides a well as a communication path between the main circuit of the die 120 and the test circuit 180. For example, Figure 4B shows a partial cross-sectional view of a semiconductor wafer as shown in the embodiment of Figure 4A. Since the main circuit 122 and the test circuit 180 may have different structures depending on their functions or functions, in order to simplify the description, only the squares are used to represent the main circuit 122 and the test circuit 180 in FIG. 4B. As shown in FIG. 4B, the semiconductor wafer includes a P-type substrate PSUB, a deep N-type well DNW, an N-type well NW1, an N-type well NW2, and an N+ diffusion region N+ formed in the N-type wells NW1, NW2. The main circuit of the die 120 is connected to the N+ diffusion region N+ of the N-well NW1, and the test circuit 180 is connected to the N+ diffusion region N+ of NW2. Since the deep N-type well DNW is connected between the N-type wells NW1 and NW2, the communication path between the die 120 and the test circuit 180 can be realized. In this embodiment, the test circuit 180 can transmit data or instructions to the main circuit of the die 120 via the N-well NW2, the deep N-well DNW, and the N-well NW1. In addition, when the main circuit of the die 120 receives the data or instructions, it can respond to the test circuit 180 via the N-well NW1, the deep N-well DNW, and the N-well NW2. Since the deep N-well DNW phase is formed on the lower layer than the seal ring 126, it may not be necessary to form an opening on the seal ring 126. And a communication channel between the main circuit of the die 120 and the test circuit 180 can be established. It will be appreciated that the connection between the main circuit 122 and the test circuit 180 can be accomplished by any layer of the die 120, such as a metal layer (not shown). Since the metal layer is relatively higher than the well region, in order to increase safety, in the preferred embodiment, the connection between the main circuit 122 and the test circuit 180 is achieved by the well regions NW1, DNW, NW2.

In addition, after the end of the test of the die 120, the semiconductor wafer is diced along the dashed line Ls in the dicing process, and the test circuit 180 will be removed. The connection between the main circuit of die 120 and test circuit 180 is formed by a deep N-well DNW (Deep N Well), while the deep N-well DNW has broken after the cutting process. Therefore, the connection between the main circuit of the die 120 and the test circuit 180 is not easily found after the cutting process.

While the invention and its advantages have been described in detail, it is understood that various changes, substitutions and modifications may be made without departing from the spirit and scope of the invention. Further, the scope of the application is not intended to limit the processes, machines, manufacture, structures, structures, methods, and steps of the particular embodiments described. . Accordingly, the scope of the appended patent is intended to cover the scope of the process, machine, manufacture, structure, In addition, each request item constitutes a different embodiment and a combination of different request items and embodiments, and is included in the scope of the present invention.

100‧‧‧Semiconductor wafer

120‧‧‧ grain

140‧‧‧Grain area

160‧‧‧cutting area

180‧‧‧Test circuit

Claims (8)

A semiconductor wafer having a die region and a dicing region, comprising: a die formed in the die region of the semiconductor wafer and having a main circuit; and a test circuit disposed on the semiconductor wafer The cutting area is electrically connected to the die to test the main circuit; wherein the test circuit further transmits a test data to the main circuit, and when the main circuit receives the test data, transmits a response data to the above The test circuit and the test circuit determine whether the response data is identical to the test data. The semiconductor wafer of claim 1, further comprising: a ring disposed on the periphery of the die; and a well region formed under the seal; wherein the test circuit is electrically connected through the well region To the above grains. The semiconductor wafer of claim 1, wherein the die further comprises a decoding circuit connected between the main circuit and the test circuit; wherein the test circuit further encodes the test data and encodes the same. The test data is transmitted to the decoding circuit, the decoding circuit decodes the encoded test data, and the main circuit transmits the response data according to the test data of the decoding circuit. The semiconductor wafer of claim 1, wherein the die further has a non-volatile memory fuse for storing a value determining a function of the main circuit, and the test circuit provides a high voltage to the above A non-volatile memory fuse to perform an erase operation or a write operation. A test method for a semiconductor wafer having a die region and a dicing region, comprising: forming a die on the die region of the semiconductor wafer, wherein the die includes a main circuit; Forming a test circuit on the dicing area of the semiconductor wafer; and electrically connecting the test circuit to the die to test the main circuit; further comprising: transmitting a test data to the main circuit by using the test circuit; and using the test circuit Receiving a response data from one of the main circuits; and determining whether the response data is identical to the test data; wherein the main circuit of the die generates the response data according to the test data. The test method of claim 5, further comprising: forming a ring around the periphery of the die; and forming a well region to electrically connect the test circuit to the main circuit of the die; wherein the well region is formed Below the above seal. The test method of claim 5, wherein the die further comprises a decoding circuit connected between the main circuit and the test circuit, and the testing method further comprises: encoding the test data; Testing the data to the decoding circuit; and decoding the encoded test data by the decoding circuit; The main circuit transmits the response data according to the test data of the decoding circuit. The test method of claim 5, wherein the die further has a non-volatile memory fuse for storing a value determining a function of the main circuit, and the test method further comprises: using the test circuit A high voltage is supplied to the non-volatile memory fuse to perform an erase operation or a write operation.