TWI423587B - Pin sharing circuit - Google Patents

Description

Pin sharing circuit

The present invention relates to an integrated circuit, and more particularly to a pin sharing circuit of an image sensor.

Image sensors are commonly used in electronic devices, and as the electronic devices are miniaturized, the area of the image sensor's wafers needs to be reduced. The number of pins is one of the important determinants in reducing the wafer area. The first figure shows a pin diagram of a complementary metal oxide semiconductor (CMOS) image sensor of a video graphics array (VGA) specification, the pins of which include Data[7:0], HSYNC, VSYNC, SCL, SDA, VDD, GND, MCLK, PCLK, and PWRDN require a total of 17 pins.

For example, a through-silicon via (TSV) ball grid array (BGA) package technology, 4x4 solder balls are arranged to accommodate 17 pins of a VGA image sensor, so 4x5 must be used. Arrange the solder balls. As a result, three solder ball areas are wasted. At this point, if you can combine the functions of some pins With a single pin and retaining its original function, a smaller array of solder balls can be used to reduce the wafer area.

Therefore, it is not necessary to propose a mechanism for sharing one or more pins by combining the partial pin functions to reduce the total number of pins of the image sensor chip.

In view of the above, one of the objects of the embodiments of the present invention is to provide various pin sharing circuits by reducing the total number of pins by combining the pin functions of the integrated circuit to a single pin, thereby reducing the chip area of the integrated circuit. .

According to the first embodiment of the present invention, the pin sharing circuit includes a toggle detecting circuit and a power-off signal generating circuit. The thixotropic detection circuit receives the input clock to generate a detection signal. The power-off signal generating circuit generates a power-off signal based on the detection signal.

In accordance with a second embodiment of the present invention, the pin sharing circuit includes a phase adjustment circuit that receives an input clock to generate an output clock.

According to a third embodiment of the present invention, the pin sharing circuit includes a controller, a power off signal transmission gate, a function signal transmission gate, and a function switching switch. When the output clock function is selected, the controller issues a function signal of the first state, and when the power off function is selected, the controller issues a function signal of the second state. The function signal transfer gate is controlled by the output of the power off signal transmission gate to determine whether to transmit or block the function signal to generate a selection signal. Function switching The switch switches between a pin between the output clock function and the power off function according to the selection signal. Wherein, when the pin is switched to the output clock function, the controller issues an output clock, which is directly output by the pin via the function switching switch; when the pin is switched to the power-off function, the pin receives the power-off signal, The power switch is transmitted to the controller via the power switch, and the power off signal transmission gate is controlled by the selection signal to determine whether to transmit or block the power off signal.

2‧‧‧ pin sharing circuit

20‧‧‧Tactile detection circuit

201‧‧‧Delay circuit

203‧‧‧mutual exclusion or gate

22‧‧‧Power off signal generation circuit

221‧‧‧ Schmitt trigger circuit

24‧‧‧Software power off circuit

241‧‧‧ and gate

243‧‧‧ reverse gate

200‧‧‧Interface circuit

300‧‧‧ core circuit

3‧‧‧ pin sharing circuit

30‧‧‧ phase adjustment circuit

301‧‧‧ phase adjustment device

4‧‧‧ pin sharing circuit

40‧‧‧ feet

41‧‧‧ function switch

411‧‧‧ reverse gate

42‧‧‧ feet

43‧‧‧ Controller

45‧‧‧ function signal transmission gate

451‧‧‧ reverse gate

453‧‧‧Anti-gate

47‧‧‧Power off signal transmission gate

471‧‧‧ reverse gate

473‧‧‧Anti-gate

MCLK‧‧‧ input clock

DET‧‧‧Detection signal

PWRDN‧‧‧Power off signal

SPD‧‧‧Software power off signal

HPD‧‧‧ hardware power off signal

PCLK‧‧‧ output clock

PCLK_en‧‧‧ function signal

SEL‧‧‧Selection signal

SWA‧‧‧ first switch

SWB‧‧‧second switch

P‧‧‧PMOS transistor

N‧‧‧NMOS transistor

C‧‧‧ capacitor

R1‧‧‧ resistance

R2‧‧‧ resistance

C1‧‧‧ capacitor

The first figure shows the pin diagram of a complementary metal oxide semiconductor (CMOS) image sensor of the video graphics array (VGA) specification.

Figure 2A is a block diagram showing the pin sharing circuit of the first embodiment of the present invention.

The second B diagram illustrates a detailed circuit diagram of the first embodiment shown in the second A diagram.

The second C diagram illustrates waveforms of the input clock MCLK, the delayed input clock MCLK, and the detection signal DET.

Figure 3A is a block diagram showing the pin sharing circuit of the second embodiment of the present invention.

The third B diagram illustrates a detailed circuit diagram of the second embodiment shown in the third A diagram.

Figure 4A is a block diagram showing the pin sharing circuit of the third embodiment of the present invention.

The fourth B diagram illustrates a detailed circuit diagram of the third embodiment shown in FIG.

The following embodiments are exemplified by a complementary metal oxide semiconductor (CMOS) image sensor, which achieves the purpose of reducing the total number of pins by sharing a portion of the pins. The embodiments are also applicable to integrated circuits of other image sensors or non-image sensors. The integrated circuits of these embodiments may use various packaging techniques such as, but not limited to, a spine via (TSV) spherical array (BGA) technology.

Figure 2A is a block diagram showing the pin sharing circuit 2 of the first embodiment of the present invention. In this embodiment, the power-down signal PWRDN can be generated according to the input clock MCLK, so that the input clock MCLK and the power-off signal PWRDN share the same pin. In other words, the integrated circuit thus omits the power-off signal PWRDN pin.

As shown in FIG. 2A, the pin sharing circuit 2 of the present embodiment mainly includes an interface circuit 200 including a toggle detecting circuit 20 and a power-off signal generating circuit 22, and can also omit the thixotropic detection. Circuit 20. The interface circuit 200 is coupled to the pin, and receives the input clock MCLK. When the input clock MCLK is enabled, the interface circuit 200 outputs the input clock MCLK. When the input clock MCLK is disabled, the interface circuit 200 Output enable power off signal PWRDN. The thixotropic detection circuit 20 receives the input clock MCLK to generate a detection signal DET. Next, the power-off signal generating circuit 22 generates a power-off signal PWRDN based on the detection signal. For example, when the input clock MCLK is enabled, the thixotropic detection circuit 20 generates an enable detection signal; then, the power-off signal generation circuit 22 generates a non-energy based on the enable detection signal. Power off signal PWRDN. Conversely, when the input clock MCLK is disabled, an enabled power-off signal PWRDN is generated, which can be turned off. The interface circuit 200 further includes a software power off circuit 24, controlled by The software power off signal SPD controls whether the power off signal PWRDN is passed, wherein the software power off signal SPD can be provided by the internal register. For example, when the integrated circuit is to be turned off by the software power supply, the enabled software power off signal SPD is issued to block the passage of the power off signal PWRDN. Conversely, when the software power-off signal SPD is disabled, the (enable) power-off signal PWRDN can pass through the core circuit 24 to generate a hardware power-off signal HPD. The embodiment further includes a core circuit 300 coupled to the interface circuit 200 for receiving the input clock MCLK or the power-off signal PWRDN.

The second B diagram illustrates a detailed circuit diagram of the first embodiment shown in the second A diagram. In the present embodiment, the thixotropic detection circuit 20 includes a delay circuit 201 and an exclusive OR (XOR) gate 203. The delay circuit 201 delays the received input clock MCLK, and the mutex or gate 203 mutually exclusive ORs the input clock MCLK and the delayed input clock MCLK to generate the detection signal DET. The second C diagram illustrates waveforms of the input clock MCLK, the delayed input clock MCLK, and the detection signal DET. As shown in the second C diagram, when the input clock MCLK is enabled, the detection signal DET is the enabled pulse wave signal; otherwise, the detection signal DET is the non-enabled low level signal.

The power-off signal generating circuit 22 of the present embodiment includes an N-type metal oxide semiconductor (NMOS) transistor N, a P-type metal oxide semiconductor (PMOS) transistor P, a capacitor C, and a Schmitt trigger circuit (221). . Wherein, the gate of the PMOS transistor P is biased as a resistor; the PMOS transistor P and the NMOS transistor N connected in series are connected between the power supply and the ground; and the gate of the NMOS transistor N receives the detection signal DET, The capacitor C is connected in parallel between the source and the drain; the Schmitt trigger circuit 221 receives the contact signal of the PMOS transistor P and the NMOS transistor N to generate a power-off signal. No. PWRDN. When the detection signal DET is enabled, it intermittently turns on the NMOS transistor N to discharge the capacitor C, thereby generating a near-low level signal, which is processed by the Schmitt trigger circuit 221 to generate a (low level) non- The enabled power-off signal PWRDN; conversely, when the detection signal DET is disabled, it turns off the NMOS transistor N, causing the capacitor C to charge, thereby generating a near-high level signal via the Schmitt trigger circuit 221 After processing, a (high level) enabled power-off signal PWRDN is generated.

The software power-off circuit 24 of the present embodiment includes an AND gate 241 and a NOT gate 243. The reverse gate 243 receives the software power off signal SPD, and the inverted software power off signal SPD and the power off signal PWRDN are input to the AND gate 241 to generate a hardware power off signal HPD. When the software power-off signal SPD is at the high level of the enable, the power-off signal PWRDN is blocked from passing through the gate 241. Conversely, when the software power-off signal SPD is at a low level of non-activation, the power-off signal PWRDN can generate a hardware power-off signal HPD through the gate 241.

Figure 3A is a block diagram showing the pin sharing circuit 3 of the second embodiment of the present invention. In this embodiment, the output clock PCLK can be generated according to the input clock MCLK, so that the input clock MCLK and the output clock PCLK share the same pin. In other words, the integrated circuit thus omits the output clock PCLK pin.

As shown in FIG. 3A, the pin sharing circuit 3 of the present embodiment mainly includes a phase adjustment circuit 30 that receives the input clock MCLK to generate an output clock PCLK. Since the integrated circuit omits the output clock PCLK pin, the noise of the integrated circuit can be reduced and the driving requirement of the integrated circuit can be alleviated.

The third B diagram illustrates a detailed circuit diagram of the second embodiment shown in the third A diagram. In the present embodiment, the phase adjustment circuit includes a resistor R1 connected in series, a capacitor C1, and a phase adjustment device 301. The phase adjustment device 301, for example, a divider or/and an inverter, receives the input clock MCLK; one end of the resistor R1 not connected to the capacitor C1 is coupled to the output of the phase adjustment device 301, and the capacitor C1 is not connected to the resistor R1. One end is coupled to ground; the junction of the resistor R1 and the capacitor C1 generates the output clock PCLK.

Figure 4A is a block diagram showing the pin sharing circuit 4 of the third embodiment of the present invention. This embodiment can be switched between the first function (function A) provided by the first embodiment (second A picture) and the second function (function B) provided by the second embodiment (third A picture). When function A is selected, the pin 40 indicating MCLK can generate a power-off signal PWRDN in addition to the input clock MCLK, the details of which are as described in the second embodiment of FIG. 2A; and the PWRDN is indicated. The pin 42 of /PCLK is simply used as the output clock PCLK pin. When function B is selected, the pin 40 indicating MCLK can generate an output clock PCLK in addition to the input clock MCLK, the details of which are as described in the third embodiment of the third A/B diagram; and the PWRDN is indicated. The pin 42 of /PCLK is simply used as the power-off signal PWRDN pin.

In the present embodiment, the pin sharing circuit 4 includes a function switching switch 41, a controller 43, a function signal transmitting gate 45, and a power-off signal transmitting gate 47. When function A is selected, controller 43 issues a first state function signal PCLK_en; then, function signal transfer gate 45 is controlled by the output of power down signal transfer gate 47 to determine the transmit or block function signal PCLK_en to generate a selection. The signal SEL; the function switching switch 41 switches between the PCLK and the PWRDN according to the selection signal SEL to switch the pin PWRDN/PCLK 42. When pin 42 is switched as PCLK, that is, function A, the output from controller 43 The output clock PCLK is directly output from the pin 43 via the function switch 41. When the function B is selected, the controller 43 issues a function signal PCLK_en of the second state, and the selection signal SEL generated by the function signal transmission gate 45 switches the pin 42 to PWRDN, which receives the power-off signal PWRDN via the function switching switch 41. Then, it is transmitted to the controller 43 via the power-off signal transmission gate 47; wherein the power-off signal transmission gate 47 is controlled by the selection signal SEL to decide to transmit or block the power-off signal PWRDN.

In addition, the pin 42 can also be connected to the pull-down resistor R2. In the reset mode, the pin 42 generates a low level signal by the pull-down resistor R2, and the controller 43 controls the function switch 41 to switch the pin 42 to PWRDN, which receives the low level signal, via the function switch 41, and then via The power is turned off by the signal transmission gate 47 and transmitted to the controller 43 for power up.

The fourth B diagram illustrates a detailed circuit diagram of the third embodiment shown in FIG. In the present embodiment, the function signal transfer gate 45 includes a reverse gate 451 and an inverse gate 453. The reverse gate 451 receives the function signal PCLK_en, and its output and the output of the power-off signal transmission gate 47 are input to the inverse gate 453 to generate the selection signal SEL. When the output of the power-off signal transmission gate 47 is low, the function signal PCLK_en can transmit the gate 45 through the function signal; otherwise, the function signal transmission gate 45 is constant to output the low level.

The function switching switch 41 of this embodiment includes a first switch SWA and a second switch SWB. The first switch SWA is controlled by the selection signal SEL. When the function A is selected, the first switch SWA causes the output clock PCLK sent by the controller 43 to be transmitted to the pin 42. The second switch SWB is controlled by the selection signal SEL inverted by the reverse gate 411, when the function B is selected, The second switch SWB transmits the power-off signal PWRDN input from the pin 42 to the power-off signal transmission gate 47. In short, according to the selection function A or B indicated by the selection signal SEL, only the first switch A or the second switch B will be closed to provide a path to the relevant function for transmitting the output clock PCLK or the power off signal. PWRDN.

The power-off signal transmission gate 47 of the present embodiment includes a reverse gate 471 and an inverse gate 473. The reverse gate 471 receives the output of the second switch SWB, and the output of the reverse gate 471 and the selection signal SEL are input to the inverse gate 473. When the selection signal SEL is at the low level, the power-off signal PWRDN can be passed through the power-off signal transmission gate 47; otherwise, the power-off signal transmission gate 47 is constantly outputting the low level.

The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application.

2‧‧‧ pin sharing circuit

20‧‧‧Tactile detection circuit

22‧‧‧Power off signal generation circuit

24‧‧‧Software power off circuit

200‧‧‧Interface circuit

300‧‧‧ core circuit

MCLK‧‧‧ input clock

DET‧‧‧Detection signal

PWRDN‧‧‧Power off signal

SPD‧‧‧Software power off signal

HPD‧‧‧ hardware power off signal

Claims (10)

A pin sharing circuit includes: a pin receiving an input clock; and an interface circuit comprising: a toggle detecting circuit coupled to the pin and receiving the input clock to generate a check And a power-off signal generating circuit, according to the detecting signal to generate a power-off signal, comprising: an N-type metal oxide semiconductor (NMOS) transistor, the gate receiving the detection signal; a metal-oxide-semiconductor (PMOS) transistor having a gate biased as a resistor, wherein the NMOS transistor and the PMOS transistor are connected in series between the power supply and the ground; and a capacitor connected in parallel to the NMOS transistor a source and a drain, and a Schmitt trigger, receiving a contact signal of the PMOS transistor and the NMOS transistor to generate the power-off signal; wherein when the input clock is When enabled, the interface circuit outputs the input clock. When the input clock is disabled, the interface circuit outputs the power-off signal that is enabled; and a core circuit is coupled to the interface circuit to receive The input clock or Power-off signal. For example, in the pin sharing circuit described in claim 1, when the input clock system is enabled, the thixotropic detecting circuit generates the detecting signal that is enabled, and the power off signal is generated. The circuit generates a non-enable power-off signal according to the enable detection signal; conversely, when the input clock is disabled, the power-off signal is enabled. The pin sharing circuit of claim 1, wherein the thixotropic detecting circuit comprises: a delay circuit that delays the input clock; and a mutual exclusion or (XOR) gate, when the input is The pulse and the input clock of the delay are mutually exclusive ORed to generate the detection signal. The pin sharing circuit of claim 1, wherein the interface circuit further comprises a software power-off circuit controlled by a software power-off signal to control whether the power-off signal is passed. The pin sharing circuit of claim 4, wherein the software power-off circuit comprises: a reverse (NOT) gate, receiving the software power-off signal; and an AND gate, inputting the phase-inversion The software power off signal and the power off signal are used to generate a hardware power off signal. The pin sharing circuit as described in claim 1 is applicable to an image sensor, wherein the input clock shares a pin with the power off signal. A pin sharing circuit comprising: a controller, when selecting the output clock function, the controller issues a function signal of the first state, when the power off function is selected, the controller issues a function signal of the second state; a power off signal transmission gate; a function a signal transmission gate controlled by the output of the power off signal transmission gate to determine to transmit or block the function signal to generate a selection signal; a function switching switch to switch a pin to the output clock according to the selection signal And a pull-down resistor connected to the pin to generate a low level signal. In the reset mode, the controller controls the function switch to switch the pin to the power off. a function, the pin receives the low level signal, and transmits the switch to the controller via the power switch via the power switch; wherein, when the pin is switched to the output clock function, the control The device outputs an output clock, which is directly output by the pin through the function switching switch; when the pin is switched to the power-off function, the pin Receiving a power-off signal, transmitting a switch to the controller via the power-off signal transmission gate, wherein the power-off signal transmission gate is controlled by the selection signal to determine whether to transmit or block the power-off signal. The pin sharing circuit of claim 7, wherein the function signal transmission gate comprises: a reverse gate, receiving the function signal; and a reverse gate, inputting the output of the reverse gate and the power off signal The output of the gate is transmitted to generate the selection signal. The pin sharing circuit of claim 7, wherein the function switching switch comprises: a first switch controlled by the selection signal, and when the output clock function is selected, the first switch allows the The output clock sent by the controller is transmitted to the pin; a reverse switch is used to invert the selection signal; and a second switch is controlled by the inverted selection signal when the power off function is selected The second switch transmits the power-off signal input by the pin to the power-off signal transmission gate. The pin sharing circuit of claim 9, wherein the power off signal transmission gate comprises: a reverse gate, receiving an output of the second switch; and a reverse gate, inputting the output of the reverse gate The selection signal.