TWI646781B - Power-on control circuit with state-recovery mechanism and operating circuit utilizing the same - Google Patents

Abstract

A power-on control circuit includes a first detection circuit, a switching circuit, a first buffer, a second detection circuit, and a second buffer. The first detecting circuit detects a voltage of the first voltage source to generate a first detecting signal to a first node. The switching circuit is coupled to the first voltage source and the second voltage source, and outputs the voltage of the first or second voltage source to a second node according to the level of the first node. The first buffer generates a feedback signal and a control signal according to the level of the second node. The second detecting circuit generates a second detecting signal according to the feedback signal, the control signal, the voltage of the second voltage source, and a reply signal. The second buffer generates a reply signal according to the second detection signal.

Description

Electrical control circuit and operating circuit with state recovery mechanism

The present invention relates to a power-on control circuit, and more particularly to a power-on control circuit that operates in accordance with a core voltage.

With the advancement of technology, the types and functions of electronic devices are increasing. In general, there are many integrated circuits inside the electronic device. Each integrated circuit may receive many operating voltages. When an operating voltage does not reach a target value, if the integrated circuit uses the operating voltage, the integrated circuit can easily generate an erroneous signal.

The present invention provides an electrical control circuit with a state recovery mechanism, including a first detection circuit, a switching circuit, a first buffer, a second detection circuit, and a second buffer. The first detecting circuit detects a voltage of the first voltage source to generate a first detecting signal to a first node. The switching circuit is coupled to the first voltage source and the second voltage source, and outputs the voltage of the first or second voltage source to a second node according to the level of the first node. The first buffer generates a feedback signal and a control signal according to the level of the second node. The second detecting circuit generates a second detecting signal according to the feedback signal, the control signal, the voltage of the second voltage source, and a reply signal. The second buffer generates a reply signal according to the second detection signal.

The invention further provides an operating circuit comprising a core circuit, a first output switch, a second output switch and a power-on control circuit. The core circuit receives a voltage of a first voltage source and a voltage of a second voltage source, and generates a first control signal and a second control signal. The first output switch transmits the voltage of the first voltage source to a bonding pad according to the first control signal. The second output switch transmits a ground voltage to the bonding pad according to the second control signal. The power-on control circuit controls the first and second output switches according to the voltages of the first and second voltage sources, and includes a first detection circuit, a switching circuit, a first buffer, a second detection circuit, and A second buffer. The first detecting circuit detects the voltage of the first voltage source to generate a first detecting signal to a first node. The switching circuit is coupled to the first and second voltage sources, and outputs the voltage of the first or second voltage source to a second node according to the level of the first node. The first buffer generates a feedback signal and a control signal according to the level of the second node. The second detecting circuit generates a second detecting signal according to the feedback signal, the control signal, the voltage of the second voltage source, and a reply signal. The second buffer generates a reply signal according to the second detection signal, and controls the first and second output switches according to the second detection signal.

100‧‧‧ operating system

110‧‧‧Operating circuit

120‧‧‧Join pad

111‧‧‧ core circuit

112, 200A, 200B, 200C, 200D‧‧‧ power-on control circuit

113, 114‧‧‧ control switch

115, 116‧‧‧ output switch

131, 132‧‧‧ voltage source

GND‧‧‧ Grounding voltage

S _C1 , S _C2 ‧‧‧ control signals

S _D1 , S _D2 ‧‧‧ drive signal

P11, P12, Pdet, Psw, P21~P26, P28~P30, 311~313, 331, 332, 341, 343‧‧‧P type transistor

N11, N12, Nsw, N21~N30, 321~323, 333, 342‧‧‧N type transistors

210, 240‧‧‧Detection circuit

220‧‧‧Switching circuit

230, 250‧‧‧ buffer

ND1, ND2‧‧‧ nodes

260‧‧‧Setting unit

C‧‧‧ capacitor

Sw_fb‧‧‧Return signal

Sw18‧‧‧ control signal

Rcv_on‧‧‧Response signal

S _DT ‧‧‧Detection signal

241, 242‧‧‧ logic circuits

243‧‧‧Transmission gate

260, 300A, 300B‧‧‧ voltage supply circuit

270‧‧ ‧ level conversion circuit

271‧‧‧Inverter

S _OT ‧‧‧ output signal

V _R ‧‧‧Attenuation voltage

Figure 1 is a schematic diagram of the operating system of the present invention.

2A~2D are possible embodiments of the electrical control circuit with state recovery mechanism of the present invention.

3A-3D are possible embodiments of the voltage supply circuit of the present invention.

FIG. 4A is a schematic diagram of the power-on control circuit of the present invention operating in a power-on mode.

Figure 4B is a schematic diagram of the power control circuit of the present invention operating in a normal mode.

4C is a schematic diagram of the power-on control circuit of the present invention operating in a power-off mode.

In order to make the objects, features and advantages of the present invention more comprehensible, the embodiments of the invention are described in detail below. The present specification provides various embodiments to illustrate the technical features of various embodiments of the present invention. The arrangement of the various elements in the embodiments is for illustrative purposes and is not intended to limit the invention. In addition, the overlapping portions of the drawings in the embodiments are for the purpose of simplifying the description, and do not mean the relationship between the different embodiments.

Figure 1 is a schematic diagram of the operating system of the present invention. The operating system 100 includes an operating circuit 110 and a pad 120. In the present embodiment, the operating circuit 110 is used to control the level of the bonding pad 120. As shown, the operational circuit 110 includes a core circuit 111, a power up control circuit 112, control switches 113, 114, and output switches 115 and 116. The core circuit 111 is coupled to the voltage sources 131 and 132. In one possible embodiment, voltage source 131 is used to generate an input/output voltage (I/O power) and voltage source 132 is used to generate a core power. In the present embodiment, both the input and output voltages and the core voltage are used as the operating voltage of the core circuit 111. In another possible embodiment, the input and output voltages are greater than the core voltage. For example, the input and output voltage is about 3.3V, and the core voltage is about 1.8V. In addition, the core circuit 111 also receives a ground voltage GND.

The core circuit 111 operates in accordance with the voltages provided by the voltage sources 131 and 132 and the ground voltage GND, and generates control signals S _C1 and S _C2 for controlling the output switches 115 and 116. In this embodiment, the control signal S _{C1 is} used to turn on or off the output switch 115. When the output switch 115 is turned on, the output switch 115 supplies the voltage of the voltage source 131 to the bond pad 120. Therefore, the bonding pad 120 is at a high level. In addition, the control signal S _{C2 is} used to turn on or off the output switch 116. When the output switch 116 is turned on, the output switch 116 supplies the ground voltage GND to the bond pad 120. Therefore, the bonding pad 120 is at a low level.

However, when voltage sources 131 and 132 begin to output voltage, the voltages of voltage sources 131 and 132 may gradually rise from 0V. When the voltage of the voltage source 131 reaches a first preset value (such as 0.7V) and the voltage of the voltage source 132 does not reach a second preset value (such as 0.9V), the core circuit 111 may generate an erroneous control signal S _{C1 .} With S _C2 . When control signals S _C1 and S _C2 turn on output switches 115 and 116, respectively, a leakage current will flow through output switches 115 and 116. To solve this problem, the power-on control circuit 112 does not turn on the output switches 115 and 116 when the voltage of the voltage source 132 does not reach the second predetermined value.

For example, when the voltage of the voltage source 131 reaches the first preset value and the voltage of the voltage source 132 does not reach the second preset value, the power-on control circuit 112 enters a power-on mode. In the power on mode, the power up control circuit 112 does not turn on the output switches 115 and 116. When the voltage of the voltage source 131 has reached the first predetermined value and the voltage of the voltage source 132 has reached the second predetermined value, the power-on control circuit 112 enters a normal mode. In this mode, power up control circuit 112 no longer controls output switches 115 and 116. At this time, the output switches 115 and 116 are controlled by the core circuit 111. When the voltage of the voltage source 132 decreases and is lower than the second predetermined value, the power-on control circuit 112 enters a power-off mode. In the power off mode, the power up control circuit 112 again controls the output switches 115 and 116, And the output switches 115 and 116 are not turned on.

The present invention does not limit how the power up control circuit 112 controls the output switches 115 and 116. In a possible embodiment, the power-on control circuit 112 generates the driving signals S _D1 and S _D2 according to the voltages of the voltage sources 131 and 132, and indirectly controls the output switches 115 and 116 through the driving signals S _D1 and S _D2 . For example, when the driving signal S _D1 turns on the control switch 113, the control switch 113 supplies the voltage of the voltage source 131 to the output switch 115 for not turning on the output switch 115. When the driving signal S _D2 turns on the control switch 114, the control switch 114 provides a ground voltage GND to the output switch 116 for not turning on the output switch 116. In other embodiments, control switches 113 and 114 may be omitted. In this example, power-up control circuit 112 is coupled directly to output switches 115 and 116 and controls output switches 115 and 116 via drive signals S _D1 and S _D2 .

The present invention is not limited to the internal architecture of the control switches 113 and 114. In a possible embodiment, the control switch 113 is a P-type transistor P12, and the control switch 114 is an N-type transistor N12. As shown, the gate of the P-type transistor P12 is coupled to the power-on control circuit 112 for receiving the driving signal S _D1 . The source of the P-type transistor P12 is coupled to the voltage source 131. The drain of the P-type transistor P12 is coupled to the output switch 115. When the driving signal S _D1 is at a low level, the P-type transistor P12 is turned on to transfer the voltage of the voltage source 131 to the output switch 115. In addition, the gate of the N-type transistor N12 is coupled to the power-on control circuit 112 for receiving the driving signal S _D2 . The drain of the N-type transistor N12 is coupled to the output switch 116. The source of the N-type transistor N12 receives the ground voltage GND. When the driving signal S _D2 is at a high level, the N-type transistor N12 is turned on to transmit the ground voltage GND to the output switch 116. In other embodiments, the control switch 113 is an N-type transistor and the control switch 114 is a P-type transistor. In some embodiments, control switches 113 and 114 are both N-type transistors or both P-type transistors.

The present invention does not limit the internal circuit architecture of the output switches 115 and 116. In the present embodiment, the output switch 115 is a P-type transistor P11, and the output switch 116 is an N-type transistor N11. The gate of the P-type transistor P11 is coupled to the core circuit 111 and the control switch 113. The source of the P-type transistor P11 is coupled to the voltage source 131. The drain of the P-type transistor P11 is coupled to the bond pad 120. When the P-type transistor P11 is turned on, the P-type transistor P11 transmits the voltage of the voltage source 131 to the bonding pad 120. In addition, the gate of the N-type transistor N11 is coupled to the core circuit 111 and the control switch 114. The drain of the N-type transistor N11 is coupled to the bond pad 120. The source of the N-type transistor N11 receives the ground voltage GND. When the N-type transistor N11 is turned on, the N-type transistor N11 transmits the ground voltage GND to the bonding pad 120. In other embodiments, the output switch 115 is an N-type transistor and the output switch 116 is a P-type transistor. In some embodiments, the output switches 115 and 116 are both N-type transistors or both P-type transistors.

Figure 2A is a possible embodiment of the power control circuit of the present invention. As shown, the power-on control circuit 200A includes detection circuits 210 and 240, a switching circuit 220, and buffers 230 and 250. The detecting circuit 210 detects the voltage of the voltage source 131 for generating a detection signal to the node ND1. The present invention does not limit the circuit architecture of the detection circuit 210. In this embodiment, the detecting circuit 210 is a P-type transistor Pdet. The gate of the P-type transistor Pdet is coupled to the node ND2, the source of which is coupled to the voltage source 131, and the drain of which is coupled to the node ND1.

The switching circuit 220 is coupled to the voltage sources 131 and 132, and outputs the voltage of the voltage source 131 or 132 to the node ND2 according to the level of the node ND1. For example In other words, when the node ND1 is at a high level, the switching circuit 220 outputs the voltage of the voltage source 132 to the node ND2. When the node ND1 is at a low level, the switching circuit 220 outputs the voltage of the voltage source 131 to the node ND2. The present invention does not limit the circuit architecture of the switching circuit 220. In this embodiment, the switching circuit 220 includes a P-type transistor Psw and an N-type transistor Nsw. The gate of the P-type transistor Psw is coupled to the node ND1, the source of which is coupled to the voltage source 131, and the drain of which is coupled to the node ND2. When the node ND1 is at a low level, the P-type transistor Psw is turned on to transfer the voltage of the voltage source 131 to the node ND2. The gate of the N-type transistor Nsw is coupled to the node ND1, the drain of which is coupled to the voltage source 132, and the source of which is coupled to the node ND2. When the node ND1 is at a high level, the N-type transistor Nsw is turned on to transfer the voltage of the voltage source 132 to the node ND2.

In a possible embodiment, the power-on control circuit 200A further includes a setting unit 260. The setting unit 260 is configured to set an initial level of the node ND2. In a possible embodiment, the setting unit 260 is a capacitor C. The capacitor C receives the ground voltage GND for setting the initial level of the node ND2 to a low level (or first level). In this example, during an initial period, when the voltage of the voltage source 131 reaches the first predetermined value, since the node ND2 is at a low level, the P-type transistor Pdet is turned on to transmit the voltage of the voltage source 131 to the node. ND1. However, when the voltage of the voltage source 131 gradually increases and is greater than the second predetermined value, the node ND2 changes from a low level to a high level. Therefore, the P-type transistor Pdet is not turned on to stop the voltage of the voltage source 131 from being transmitted to the node ND1.

The buffer 230 generates a feedback signal sw_fb and a control signal sw18 according to the level of the node ND2. In this embodiment, the level of the feedback signal sw_fb is equal to the level of the node ND2, and the level of the control signal sw18 is relative to the level of the node ND2. For example, when the node ND2 is at a low level, the feedback signal is Sw_fb is low, but the control signal sw18 is at a high level (such as the second level). When the node ND2 is at a high level, the feedback signal sw_fb is at a high level, but the control signal sw18 is at a low level. The present invention does not limit the circuit architecture of the buffer 230. In the present embodiment, the buffer 230 includes P-type transistors P21 and P22 and N-type transistors N21 and N22. The P-type transistor P21 and the N-type transistor N21 constitute a first inverter. The P-type transistor P22 and the N-type transistor N22 constitute a second inverter.

The gate of the P-type transistor P21 is coupled to the node ND2, the source of which is coupled to the voltage source 131, and the drain of which is coupled to the drain of the N-type transistor N21. The gate of the N-type transistor N21 is coupled to the node ND2, and the source thereof receives the ground voltage GND. In the present embodiment, the drain voltage of the N-type transistor N21 is used as the control signal sw18. In addition, the gate of the P-type transistor P22 receives the control signal sw18, the source of which is coupled to the voltage source 131, and the drain of which is coupled to the drain of the N-type transistor N22. The gate of the N-type transistor N22 receives the control signal sw18, and its source receives the ground voltage GND. In the present embodiment, the drain voltage of the N-type transistor N22 is used as the feedback signal sw_fb.

The detecting circuit 240 generates a detecting signal S _DT according to the feedback signal sw_fb, the control signal sw18, the voltage of the voltage source 132, and a reply signal rcv_on. In this embodiment, when the voltage of the voltage source 131 reaches the first preset value and the voltage of the voltage source 132 does not reach the second preset value, the detecting circuit 240 generates the high level detection signal S _DT . When the voltage of the voltage source 131 reaches the first preset value and the voltage of the voltage source 132 reaches the second preset value, the detecting circuit 240 adjusts the detection signal S _DT from a high level to a low level. However, when the voltage of the voltage source 132 decreases and is lower than the second predetermined value, the detecting circuit 240 changes the detection signal S _DT from a low level to a high level. Since the detection signal S _DT returns from a low level to a high level, the detection circuit 240 acts as a state recovery mechanism.

The present invention does not limit the circuit architecture of the detection circuit 240. In a possible embodiment, the detection circuit 240 includes logic circuits 241, 242 and a transmission gate 243. The transmission gate 243 is coupled to the voltage source 132 and transmits the voltage of the voltage source 132 to the logic circuit 242 according to the feedback signal sw_fb and the control signal sw18. In the present embodiment, the transfer gate 243 includes a P-type transistor P23 and an N-type transistor N23. The gate of the P-type transistor P23 receives the control signal sw18, the source of which is coupled to the voltage source 132, and the drain of which is coupled to the logic circuit 242. The gate of the N-type transistor N23 receives the feedback signal sw_fb, the drain of which is coupled to the voltage source 132, and the source of which is coupled to the logic circuit 242. Further, the base of the P-type transistor P23 is coupled to the voltage source 131, and the base of the N-type transistor N23 receives the ground voltage GND.

The logic circuit 242 outputs the detection signal S _DT according to the voltage of the feedback signal sw_fb and the voltage source 132. For example, when the feedback signal sw_fb is at a low level, the logic circuit 242 outputs a high level detection signal S _DT . When the feedback signal sw_fb is at a high level and the voltage of the voltage source 132 reaches a second predetermined value, the logic circuit 242 outputs a low level detection signal S _DT . However, when the feedback signal sw_fb is at a high level and the voltage of the voltage source 132 is lower than the second predetermined value, the logic circuit 242 outputs the high level detection signal S _DT . The present invention does not limit the circuit architecture of logic circuit 242. In the present embodiment, the logic circuit 242 is a NAND.

The logic circuit 241 receives the feedback signal sw_fb and the reply signal rcv_on and is coupled to the node ND1. When the voltage of the voltage source 131 reaches the first preset value and the voltage of the voltage source 132 does not reach the second preset value, since the feedback signal sw_fb is at the low level, the logic circuit 241 outputs the high level to the node ND1. When the voltage of the voltage source 132 reaches the second predetermined value, the logic circuit 241 outputs a low level to the node ND1. The present invention does not limit the circuit architecture of the logic circuit 241. In this embodiment, logic The circuit 241 is a NAND.

The buffer 250 generates a reply signal rcv_on based on the detection signal S _DT . In a possible embodiment, the level of the reply signal rcv_on is relative to the level of the detection signal S _DT . For example, when the detection signal S _DT is at a high level, the reply signal rcv_on is at a low level. When the detection signal S _DT is at a low level, the reply signal rcv_on is at a high level. In a possible embodiment, the reply signal rcv_on can be used as the drive signal S _{D1 of} FIG. In another possible embodiment, the buffer 250 further generates a drive signal S _D2 for driving the control switch 114 of FIG.

In the present embodiment, the buffer 250 includes a P-type transistor P24 and an N-type transistor N24. The P-type transistor P24 and the N-type transistor N24 form a first inverter, and invert the level of the detection signal S _DT to generate a reply signal rcv_on. As shown, the gate of the P-type transistor P24 receives the detection signal S _DT , the source of which receives the voltage of the voltage source 131, and the drain of which is coupled to the drain of the N-type transistor N24 for generating the reply signal rcv_on. . The gate of the N-type transistor N24 receives the detection signal S _DT , and its source receives the ground voltage GND.

In other embodiments, the buffer 250 further includes a P-type transistor P25 and an N-type transistor N25. The P-type transistor P25 and the N-type transistor N25 constitute a second inverter. The second inverter inverts the reply signal rcv_on for generating the drive signal S _D2 . As shown, the gate of the P-type transistor P25 receives the recovery signal rcv_on, the source of which receives the voltage of the voltage source 131, and the drain of which is coupled to the drain of the N-type transistor N25 for generating the driving signal S _D2 . The gate of the N-type transistor N25 receives the return signal rcv_on, and its source receives the ground voltage GND. In another possible embodiment, the buffer 250 further includes a third inverter (not shown). The third inverter inverts the driving signal S _D2 for generating an inverted signal, wherein the inverted signal can be used as the driving signal S _{D1 of} FIG. ₁ .

Figure 2B is another possible embodiment of the power control circuit of the present invention. Fig. 2B is similar to Fig. 2A except that the power-up control circuit 200B has a voltage supply circuit 260. The voltage supply circuit 260 is coupled between the voltage source 131 and the detection circuit 240 for supplying power to the detection circuit 240. In the present embodiment, the voltage supply circuit 260 supplies power to the logic circuit 242.

When the voltage of the voltage source 131 reaches the first predetermined value and the voltage of the voltage source 132 does not reach the second predetermined value, the voltage supply circuit 260 directly supplies the voltage of the voltage source 131 to the logic circuit 242. However, when the voltage of the voltage source 131 reaches the first predetermined value and the voltage of the voltage source 132 reaches the second predetermined value, the voltage supply circuit 260 reduces the voltage of the voltage source 131 to generate an attenuation voltage V _R and pad voltage V _R to provide the logic circuit 242.

The present invention does not limit the circuit architecture of the voltage supply circuit 260. In the present embodiment, the voltage supply circuit 260 includes a P-type transistor P26, N-type transistors N26 and N27. The gate of the P-type transistor P26 receives the feedback signal sw_fb, the source of which receives the voltage of the voltage source 131, the drain of which is coupled to the detection circuit 240, and the base of which receives the voltage of the voltage source 131. When the P-type transistor P26 is turned on, the P-type transistor P26 supplies the voltage of the voltage source 131 to the logic circuit 242. In addition, the gate of the N-type transistor N26 receives the feedback signal sw_fb, the drain of which receives the voltage of the voltage source 131, and the source of which is coupled to the gate and the drain of the N-type transistor N27. The source of the N-type transistor N27 is coupled to the detection circuit 240. The bases of the N-type transistors N26 and N27 receive the ground voltage GND. When N-type transistors N26 and N27 are turned on, N-type transistors N26 and N27 attenuate the voltage of voltage source 131 to generate attenuated voltage V _R and provide attenuating voltage V _R to logic circuit 242.

Figure 2C is another possible embodiment of the power control circuit of the present invention. The 2C diagram is similar to the 2A diagram, except that the power-on control circuit 200C further includes a level shifter 270. The level conversion circuit 270 is coupled between the detection circuit 240 and the buffer 250. In this embodiment, the level conversion circuit 270 is configured to adjust the level of the detection signal S _DT to generate an output signal S _OT . For example, when the detection signal S _DT is 1.8V, the level conversion circuit 270 raises the level of the detection signal S _DT from 1.8V to 3.3V. At this time, the output signal S _OT is 3.3V. When the detection signal S _DT is 0V, the level conversion circuit 270 maintains the level of the detection signal S _DT . Therefore, the output signal S _OT is 0V. The buffer 250 then generates a reply signal rcv_on based on the output signal S _OT . In this embodiment, the level of the reply signal rcv_on is relative to the level of the output signal S _OT . For example, when the output signal S _OT is at a high level (eg, 3.3V), the reply signal rcv_on is at a low level (eg, 0V). When the output signal S _OT is at a low level (eg, 0V), the reply signal rcv_on is at a high level (eg, 3.3V).

The present invention is not limited to the circuit architecture of the quasi-conversion circuit 270. In a possible embodiment, the level conversion circuit 270 includes an inverter 271, P-type transistors P28-P30, and N-type transistors N28-N30. The input end of the inverter 271 receives the detection signal S _DT , and the output end thereof is coupled to the gate of the N-type transistor N29. In the present embodiment, the inverter 271 includes a P-type transistor P30 and an N-type transistor N30. The gate of the P-type transistor P30 receives the detection signal S _DT , the source of which receives the voltage of the voltage source 131 and the drain of which is coupled to the gate of the N-type transistor N29. The gate of the N-type transistor N30 receives the detection signal S _DT , the drain of which is coupled to the drain of the P-type transistor P30, and the source thereof receives the ground voltage GND.

The gate of the P-type transistor P28 is coupled to the buffer 250 and the drain of the P-type transistor P29. The source receives the voltage of the voltage source 131, and the drain is coupled to the drain of the N-type transistor N28 and the P-type. The gate of crystal P29. The gate of the N-type transistor N28 receives the detection signal S _DT , and its source receives the ground voltage GND. The gate of the P-type transistor P29 is coupled to the drain of the N-type transistor N28, the source of which receives the voltage of the voltage source 131, and the drain of which is coupled to the drain of the buffer 250 and the N-type transistor N29. The gate of the N-type transistor N29 is coupled to the drain of the P-type transistor P30, the drain of which is coupled to the drain of the P-type transistor P29, and the source thereof receives the ground voltage GND.

Figure 2D is another possible embodiment of the power control circuit of the present invention. The 2D picture is similar to the 2A picture, except that the power-on control circuit 200D of the 2D figure further includes a voltage supply circuit 260 and a one-bit conversion circuit 270. Since the operation principle of the voltage supply circuit 260 and the level conversion circuit 270 has been described above, it will not be described again. In the present embodiment, the voltage supply circuit 260 supplies power to the logic circuit 242 and the inverter 271. The operation principle of the power-on control circuit 200D will be described later by taking the 2D picture as an example.

Figure 3A is another possible embodiment of the voltage supply circuit of the present invention. As shown, the voltage supply circuit 300A includes P-type transistors 311 to 313. The bases of the P-type transistors 311 to 313 receive the voltage of the voltage source 131. In addition, the gate of the P-type transistor 311 receives the feedback signal sw_fb, the source of which receives the voltage of the voltage source 131, and the drain of which is coupled to the detection circuit 240. The gate of the P-type transistor 312 receives the control signal sw18, the source of which receives the voltage of the voltage source 131. The gate and the source of the P-type transistor 313 are coupled to the drain of the P-type transistor 312, and the drain of the P-type transistor 313 is coupled to the detection circuit 240. In the present embodiment, when the P-type transistor 311 is turned on, the P-type transistor 311 transmits the voltage of the voltage source 131 to the detecting circuit 240. When the P-type transistors 312 and 313 are turned on, the P-type transistors 312 and 313 attenuate the voltage of the voltage source 131 and supply the attenuated voltage to the detecting circuit 240.

Figure 3B is another possible embodiment of the voltage supply circuit of the present invention. The voltage supply circuit 300B includes N-type transistors 321 to 323. In the present embodiment, the bases of the N-type transistors 321 to 323 receive the ground voltage GND. In addition, the gate of the N-type transistor 321 receives the control signal sw18, the drain of which receives the voltage of the voltage source 131, and the source of which is coupled to the detection circuit 240. The gate of the N-type transistor 322 receives the feedback signal sw_fb, and its drain receives the voltage of the voltage source 131. The gate and the drain of the N-type transistor 323 are coupled to the source of the N-type transistor 322, and the source thereof is coupled to the detection circuit 240. In the present embodiment, when the N-type transistor 321 is turned on, the N-type transistor 321 transmits the voltage of the voltage source 131 to the detecting circuit 240. When the N-type transistors 322 and 323 are turned on, the N-type transistors 322 and 323 attenuate the voltage of the voltage source 131 and supply the attenuated voltage to the detecting circuit 240.

Figure 3C is another possible embodiment of the voltage supply circuit of the present invention. As shown, the voltage supply circuit 300C includes P-type transistors 331, 332 and an N-type transistor 333. The bases of the P-type transistors 331 and 332 each receive the voltage of the voltage source 131. In addition, the gate of the P-type transistor 331 receives the feedback signal sw_fb, the source of which receives the voltage of the voltage source 131, and the drain of which is coupled to the detection circuit 240. The gate of the P-type transistor 332 receives the control signal sw18, and its source receives the voltage of the voltage source 131. The gate and the drain of the N-type transistor 333 are coupled to the drain of the P-type transistor 332. The source of the N-type transistor 333 is coupled to the detection circuit 240. The base of the N-type transistor 333 receives the ground voltage GND.

In the present embodiment, when the P-type transistor 331 is turned on, the P-type transistor 332 and the N-type transistor 333 are not turned on. Therefore, the P-type transistor 331 transmits the voltage of the voltage source 131 to the detecting circuit 240. When the P-type transistor 332 and the N-type transistor 333 are turned on, the P-type transistor 331 is not turned on. At this time, P-type transistor 332 and N-type electricity The crystal 333 attenuates the voltage of the voltage source 131 and supplies the attenuated voltage to the detection circuit 240.

Figure 3D is another possible embodiment of the voltage supply circuit of the present invention. The voltage supply circuit 300D includes P-type transistors 341, 343 and an N-type transistor 342. The bases of the P-type transistors 341 and 343 receive the voltage of the voltage source 131. The gate of the P-type transistor 341 receives the feedback signal sw_fb, the source of which receives the voltage of the voltage source 131, and the drain of which is coupled to the detection circuit 240. The gate of the N-type transistor 342 receives the feedback signal sw_fb, and its drain receives the voltage of the voltage source 131. The source of the P-type transistor 343 is coupled to the source of the N-type transistor 342. The gate and the drain of the P-type transistor 343 are coupled to the detection circuit 240.

In the present embodiment, when the P-type transistor 341 is turned on, the N-type transistor 342 and the P-type transistor 343 are not turned on. Therefore, the P-type transistor 341 transmits the voltage of the voltage source 131 to the detecting circuit 240. When the N-type transistor 342 and the P-type transistor 343 are turned on, the P-type transistor 341 is not turned on. Therefore, the N-type transistor 342 and the P-type transistor 343 attenuate the voltage of the voltage source 131 and supply the attenuated voltage to the detecting circuit 240.

4A-4C are schematic diagrams showing the operation of the power control circuit of the present invention. For convenience of explanation, the operation principle of the power-on control circuit 200D will be described below by taking the power-on control circuit 200D shown in FIG. 2D as an example. When the voltage sources 131 and 132 start to output voltages, the voltages of the voltage sources 131 and 132 gradually rise. When the voltage of the voltage source 131 reaches a first preset value and the voltage of the voltage source 132 does not reach a second preset value, the power-on control circuit 200D enters a power-on mode.

In the power-on mode, the initial level of the node ND2 is low, so the detection circuit 210 transmits the voltage of the voltage source 131 to the node ND1. Therefore, the node ND1 is at a high level, causing switching circuit 220 to transfer the voltage of voltage source 132 to node ND2. Since the voltage of the voltage source 132 does not reach the second preset value, the node ND2 is maintained at a low level. Therefore, the buffer 230 outputs a high level control signal sw18 and a low level feedback signal sw_fb.

Since the feedback signal sw_fb is at a low level, the logic circuit 241 sets the node ND1 to a high level. Therefore, the switching circuit 220 continues to output the voltage of the voltage source 132 to the node ND2. In addition, since the feedback signal sw_fb is at a low level, the logic circuit 242 outputs a high level detection signal S _DT . At this time, the buffer 250 outputs a low level reply signal rcv_on.

In a possible embodiment, the reply signal rcv_on is used as a first driving signal for driving the control switch 113 of FIG. In another possible embodiment, the buffer 250 further outputs a high level drive signal S _D2 . In this example, the drive signal S _D2 can be used as a second drive signal for driving the control switch 114 of FIG. In other embodiments, the buffer 250 further has an inverter (not shown) for inverting the drive signal S _D2 and generating a third drive signal. In this example, the third drive signal is used to drive the control switch 113 of FIG. In addition, since the feedback signal sw_fb is at a low level and the control signal sw18 is at a high level, the transfer gate 243 is not turned on. Moreover, since the feedback signal sw_fb is at a low level, the voltage supply circuit 260 supplies the voltage of the voltage source 131 to the logic circuit 242.

Referring to FIG. 4B, when the voltage of the voltage source 131 reaches the first preset value and the voltage of the voltage source 132 reaches the second preset value, the level of the node ND2 changes from the low level to the high level. Therefore, the power-on control circuit 200D enters a normal mode. In this mode, the buffer 230 generates a low level control signal sw18 and a high level feedback signal sw_fb. Since the feedback signal sw_fb is at a high level, the transfer gate 243 provides the voltage of the voltage source 132 to the logic circuit 242. Since the voltage of the voltage source 132 has reached the second predetermined value, the logic circuit 242 outputs the low level detection signal S _DT . At this time, the buffer 250 outputs a high level of the reply signal rcv_on and a low level of the drive signal S _D2 .

Since the reply signal rcv_on and the feedback signal sw_fb are both high, the logic circuit 241 sets the node ND1 to a low level. Therefore, the switching circuit 220 changes the voltage of the output voltage source 131 to the node ND2. Since the voltage of the voltage source 131 has reached the first predetermined value, the node ND2 is maintained at a high level. Further, the reply signal rcv_on may be used as the drive signal S _{D1 of} FIG. ₁ , and therefore, the control switch 113 is not turned on. In addition, since the drive signal S _D2 is at a low level, the control switch 114 is also not turned on. At this time, the output switches 115 and 116 are controlled by the core circuit 111. Additionally, in the normal mode, voltage supply circuit 260 attenuates the voltage of voltage source 131 for generating attenuated voltage V _R to logic circuit 242.

Referring to FIG. 4C, when the voltage source 132 stops the output voltage, the voltage of the voltage source 132 gradually decreases. When the voltage of the voltage source 132 is lower than the second predetermined value, the power-on control circuit 200D enters a power-off mode. In this mode, the transfer gate 243 transmits the low level grant logic 242 since the voltage of the voltage source 132 is below the second predetermined value. Therefore, the logic circuit 242 outputs the high level detection signal S _DT . At this time, the buffer 250 outputs the low level reply signal rcv_on, so that the logic circuit 241 outputs the high level grant node ND1. Therefore, the switching unit 220 changes the voltage of the output voltage source 132 to the node ND2. Since the voltage of the voltage source 132 is lower than the second predetermined value, the node ND2 is at a low level.

At this time, the buffer 230 outputs a high level control signal sw18 and a low level feedback signal sw_fb. Therefore, the voltage supply circuit 260 supplies the voltage of the voltage source 131 to the logic circuit 242. The logic circuit 242 outputs the high level detection signal S _DT , so the buffer 250 outputs the low level reply signal rcv_on. When the reply signal rcv_on is used as the drive signal S _{D1 of} FIG. 1, the control switch 113 is turned on to turn off the output switch 115. Further, since the buffer 250 outputs the high level drive signal S _D2 , the control switch 114 of Fig. 1 is turned on. Therefore, the output switch 116 is not turned on. Since the output switches 115 and 116 are not turned on, leakage current can be avoided.

In the above embodiment, when the voltage of the voltage source 131 has reached the first predetermined value and the voltage of the voltage source 132 has not reached the second preset value, the power-on control circuit 200D enters a power-on mode. In this mode, power-up control circuit 200D controls output switches 115 and 116 to prevent output switches 115 and 116 from being turned on at the same time. When the voltage of the voltage source 132 reaches the second predetermined value, the power-on control circuit 200D enters a normal mode. In this mode, the power up control circuit 200D no longer controls the output switches 115 and 116. At this time, the output switches 115 and 116 are controlled by the core circuit 111. When voltage source 132 ceases to provide an output voltage, the voltage of voltage source 132 gradually decreases. When the voltage of the voltage source 132 is lower than the second predetermined value, the power-on control circuit 200D enters a power-off mode. In this mode, the power-on control circuit 200D again controls the output switches 115 and 116 to prevent the output switches 115 and 116 from being turned on at the same time and the leakage current phenomenon.

Unless otherwise defined, all terms (including technical and scientific terms) are used in the ordinary meaning Moreover, unless expressly stated, the definition of a vocabulary in a general dictionary should be interpreted as consistent with the meaning of an article in its related art, and should not be interpreted as an ideal state or an overly formal voice.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. . For example, the system, apparatus or method of the embodiments of the present invention may be implemented in a physical embodiment of a combination of hardware, software or hardware and software. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (20)

An electrical control circuit with a state recovery mechanism includes: a first detection circuit for detecting a voltage of a first voltage source for generating a first detection signal to a first node; a switching circuit coupled Connecting the first voltage source and a second voltage source, and outputting the voltage of the first or second voltage source to a second node according to the level of the first node; a first buffer according to the second a level of the node generates a feedback signal and a control signal; a second detection circuit generates a second detection according to the feedback signal, the control signal, the voltage of the second voltage source, and a reply signal And a second buffer that generates the reply signal according to the second detection signal. The state control mechanism as claimed in claim 1, wherein the voltage of the first voltage source reaches a first preset value and the voltage of the second voltage source does not reach a second When the value is set, the state control circuit upper electrical control circuit enters a first mode, in the first mode, the first detecting circuit transmits the voltage of the first voltage source to the first node, the switching circuit Outputting the voltage of the second voltage source to the second node, the second detecting circuit generates the second detecting signal according to the feedback signal, and the second buffer generates a first according to the second detecting signal Level of reply signal. The state control mechanism as claimed in claim 2, wherein the voltage of the first voltage source reaches the first preset value and the voltage of the second voltage source reaches the second preset In the case of the value, the electrical control circuit on the state returning mechanism enters a second mode, and in the second mode, the second node a second level, the first buffer generates the feedback signal according to the voltage of the second node, and the second detecting circuit changes the level of the first node according to the feedback signal, and generates the second detection Measuring a signal, the switching circuit outputs a voltage of the first voltage source to the second node according to a level of the first node, and the second buffer generates a response with the second level according to the second detection signal The second level of the signal is higher than the first level. The state control mechanism upper power control circuit as described in claim 3, wherein when the voltage of the second voltage source decreases and is lower than the second preset value, the state feedback mechanism is electrically controlled The circuit enters a third mode. In the third mode, the second detecting circuit generates the second detecting signal according to the voltage of the second voltage source, and the second buffer generates the second detecting signal according to the second detecting signal. The first level of the reply signal is used to change the level of the first node, and the switching circuit outputs the voltage of the second voltage source to the second node according to the level of the first node. The power control circuit of the state recovery mechanism of claim 1, further comprising: a quasi-conversion circuit coupled between the second detection circuit and the second buffer, wherein the bit The quasi-conversion circuit adjusts the level of the second detection signal to generate an output signal, and the second buffer generates the reply signal according to the output signal. The power control circuit of the state recovery mechanism, as described in claim 1, further comprising: a voltage supply circuit coupled between the first voltage source and the second detection circuit, wherein the a voltage of the voltage source reaches the first preset value and the second When the voltage of the voltage source does not reach the second preset value, the voltage supply circuit supplies the voltage of the first voltage source to the second detecting circuit, when the voltage of the first voltage source reaches the first preset value and When the voltage of the second voltage source reaches the second predetermined value, the voltage supply circuit reduces the voltage of the first voltage source to generate an attenuation voltage, and supplies the attenuation voltage to the second detection circuit. The electrical control circuit of the state recovery mechanism as described in claim 6 , wherein the voltage supply circuit comprises: a P-type transistor, the gate receiving the feedback signal, and the source coupled to the first a voltage source having a drain coupled to the second detecting circuit; a first N-type transistor having a gate receiving the feedback signal, a drain coupled to the first voltage source; and a second N-type battery The gate is coupled to the source of the first N-type transistor, and the source is coupled to the second detecting circuit. The state control circuit upper power control circuit according to claim 6, wherein the voltage supply circuit comprises: a first P-type transistor, the gate receives the feedback signal, and the source is coupled to the source a first voltage source having a drain coupled to the second detecting circuit; a second P-type transistor having a gate receiving the control signal, a source coupled to the first voltage source; and a third P-type The gate is coupled to the drain of the second P-type transistor, and the drain is coupled to the second detecting circuit. The state control mechanism is as described in claim 1, wherein the voltage supply circuit comprises: a first N-type transistor having a gate receiving the control signal, a drain coupled to the first voltage source, a source coupled to the second detection circuit, and a second N-type transistor having a gate Receiving the feedback signal, the drain is coupled to the first voltage source; and a third N-type transistor, the gate and the drain are coupled to the source of the second N-type transistor, and the source is coupled The second detecting circuit. The state control circuit of the above-mentioned claim, wherein the second detecting circuit comprises: a first logic circuit, receiving the feedback signal and the voltage of the second voltage source, and Outputting the second detection signal; a transmission gate coupled between the second voltage source and the first logic circuit; and a second logic circuit receiving the feedback signal and the reply signal, and coupling the The first node. An operating circuit includes: a core circuit that receives a voltage of a first voltage source and a voltage of a second voltage source, and generates a first control signal and a second control signal; a first output switch, according to the first a control signal, transmitting the voltage of the first voltage source to a bonding pad; a second output switch transmitting a ground voltage to the bonding pad according to the second control signal; and a power-on control circuit, according to the first And a voltage of the second voltage source, controlling the first and second output switches, and comprising: a first detecting circuit for detecting a voltage of the first voltage source for generating a first detecting signal to a first node; a switching circuit coupled to the first and second voltage sources, and according to the a level of the first node, outputting the voltage of the first or second voltage source to a second node; a first buffer, generating a feedback signal and a control signal according to the level of the second node; The second detecting circuit generates a second detecting signal according to the feedback signal, the control signal, the voltage of the second voltage source, and a reply signal, and a second buffer according to the second detecting signal The reply signal is generated, and the first and second output switches are controlled according to the second detection signal. The operation circuit of claim 11, wherein the power is turned on when the voltage of the first voltage source reaches a first preset value and the voltage of the second voltage source does not reach a second preset value. The control circuit enters a first mode, in which the first detecting circuit transmits the voltage of the first voltage source to the first node, and the switching circuit outputs the voltage of the second voltage source to the second The second detecting circuit generates the second detecting signal according to the feedback signal, and the second buffer generates a return signal having a first level according to the second detecting signal. The operation circuit of claim 12, wherein when the voltage of the first voltage source reaches the first preset value and the voltage of the second voltage source reaches the second preset value, the power-on control The circuit enters a second mode, in which the second node has a second level, the first buffer root The feedback signal is generated according to the voltage of the second node, the second detecting circuit changes the level of the first node according to the feedback signal, and generates the second detection signal, and the switching circuit is configured according to the first node. a level of the first voltage source to the second node, the second buffer generating a reply signal having the second level according to the second detection signal, the second level being higher than the first level One is accurate. The operation circuit of claim 13, wherein when the voltage of the second voltage source decreases and is lower than the second preset value, the power-on control circuit enters a third mode, in the third mode The second detecting circuit generates the second detecting signal according to the voltage of the second voltage source, and the second buffer generates a return signal having the first level according to the second detecting signal, for changing The level of the first node, the switching circuit outputs the voltage of the second voltage source to the second node according to the level of the first node. The operation circuit of claim 11, further comprising: a quasi-conversion circuit coupled between the second detection circuit and the second buffer, wherein the level conversion circuit adjusts the second The level of the detection signal is used to generate an output signal, and the second buffer generates the reply signal according to the output signal. The operation circuit of claim 11, further comprising: a voltage supply circuit coupled between the first voltage source and the second detection circuit, wherein when the voltage of the first voltage source reaches the When the voltage of the second voltage source does not reach the second preset value, the voltage supply circuit supplies the voltage of the first voltage source to the second detecting circuit, when the first voltage source The voltage reaches the first preset value and the voltage of the second voltage source reaches the The second voltage supply circuit reduces the voltage of the first voltage source to generate an attenuation voltage and provides the attenuation voltage to the second detection circuit. The operating circuit of claim 16, wherein the voltage supply circuit comprises: a P-type transistor, the gate receiving the feedback signal, the source coupled to the first voltage source, and the drain coupling Connected to the second detecting circuit; a first N-type transistor, the gate receiving the feedback signal, the drain electrode coupled to the first voltage source; and a second N-type transistor, the gate and the gate The source is coupled to the source of the first N-type transistor, and the source is coupled to the second detecting circuit. The operating circuit of claim 16, wherein the voltage supply circuit comprises: a first P-type transistor, the gate receiving the feedback signal, the source of which is coupled to the first voltage source, and The pole is coupled to the second detecting circuit; a second P-type transistor, the gate receiving the control signal, the source of the second voltage source coupled to the first voltage source; and a third P-type transistor having a gate The source is coupled to the drain of the second P-type transistor, and the drain is coupled to the second detecting circuit. The operation circuit of claim 11, wherein the voltage supply circuit comprises: a first N-type transistor, wherein the gate receives the control signal, and the drain is coupled to the first voltage source, and the source thereof The second detecting circuit is coupled to the second detecting circuit; a second N-type transistor having a gate receiving the feedback signal and a drain coupled to the first voltage source; and a third N-type transistor having a gate and a drain coupled to the second N-type The source of the transistor has a source coupled to the second detecting circuit. The operation circuit of claim 11, wherein the second detection circuit comprises: a first logic circuit, receiving the feedback signal and the voltage of the second voltage source, and outputting the second detection signal a transmission gate coupled between the second voltage source and the first logic circuit; and a second logic circuit that receives the feedback signal and the reply signal and is coupled to the first node.