TWI421965B - Method for treating semiconductor processing components and components formed thereby - Google Patents

Description

Method of processing semiconductor process components and components formed therefrom

The present invention generally relates to methods of processing semiconductor process components for use in semiconductor fabrication environments, and to forming semiconductor process components.

In semiconductor process technology, integrated circuit devices are typically formed by various wafer process technologies in which semiconductor (mainly) wafers are processed through various stages or tools. For example, process operations include high temperature diffusion, thermal processing, ion implantation, annealing, photolithography, polishing, deposition, and the like. With the development of next-generation semiconductor devices, the need to achieve better purity levels during such process operations continues to exist in the industry. In addition, there continues to be a driving force for transitioning to larger semiconductor wafers. The need for superior purity levels and larger wafers introduces another integration challenge for next-generation processes.

Regardless of the industry's efforts to address the next generation of purity issues and the problems associated with handling larger semiconductor wafers, there is a continuing need in the art for further improvements in semiconductor process components, methods for forming such components, and for processing semiconductors. Wafer method.

According to a specific embodiment, a semiconductor process component includes an element having a surface portion other than tantalum carbide, the outer surface portion having a surface impurity level and a bulk impurity level. The surface impurity energy level enters the outer surface portion to a depth of from 0 nm (outer surface) to an average impurity level of 100 nm, and the bulk impurity energy level is at a depth of not less than 3.0 μm into the outer surface portion. Measured, and the surface impurity level of the surface layer is not more than 80% of the impurity level of the bulk.

In accordance with another embodiment, a method of exposing a semiconductor process component includes providing a semiconductor process component having an outer surface portion formed by chemical vapor deposition of SiC, and removing a target portion of the outer surface portion. The outer surface portion has a surface impurity level and a bulk impurity level, wherein the surface impurity level enters the outer surface portion to an average impurity level from 0 nm (outer surface) to 100 nm, the bulk impurity The energy level is measured at a depth of not less than 3.0 microns into the outer surface portion. Further, heat treatment is performed on the element to diffuse the impurity from the surface of the outer surface portion such that the surface impurity level of the surface layer is not more than 80% of the impurity level of the bulk.

In accordance with aspects of the present invention, semiconductor process components and methods for processing semiconductor process components are provided. Semiconductor process components are typically formed at least in part from SiC, including surface portions having a controlled impurity content. The outer surface portion is typically formed by chemical vapor deposition (CVD) and has a surface impurity level no greater than 80% of the bulk impurity level. The outer surface portion may be defined as an identifiable SiC layer formed by CVD, or an outer thickness of a SiC element formed mainly by CVD, as in the case of a freestanding CVD-SiC device, as will be described in detail below.

U.S. Patent No. 6,093,644 discloses a process in which an oxidation step followed by an oxide layer removal is performed. However, the techniques disclosed therein do not adequately address some of the pollution problems and appear to focus on the overall impurity level of the component, rather than the impurity level along critical portions of the component. Additionally, the technique appears to be limited to recovering the purity level of the pre-processing to components within the post-processing state.

Another work in the field of high purity process components has led to the development of process flows that are derived from more rigorous studies of sources of contamination and characterization of impurity profiles extending through the surface portions of the components. One such process flow is described in US 10/824,329, filed on Apr. 14, 2004.

In accordance with one aspect, the inventors have recognized that such deposited CVD-SiC has a peak of impurity energy at its outer surface, typically within the first 0.5 microns of the depth outside the component, such as within the first 0.25 micron. , or the first 0.10 micron. In contrast, the impurity level of the bulk through the outer surface portion is stabilized at a relatively low level, typically one, two or even three magnitudes lower than the impurity level at the outer surface of the element. The bulk impurity level is generally indicative of a constant or nominal impurity level of the impurity level as a function of depth, as further described below. The impurity level is generally based on one of the concentrations of Cr, Fe and Ni between the outer surface of the outer surface portion and the bulk portion. According to a specific embodiment, the impurity energy level is based solely on a Fe. In this regard, although the Fe, Cr and Ni concentrations can be measured in accordance with the specific examples herein, the same concentration trend can be followed, albeit at a lower concentration level.

Herein, in accordance with an embodiment of the present invention, a semiconductor process component having an outer surface portion formed by chemical vapor deposition of SiC is provided, and the process begins with removal of a target portion of the outer surface portion such that the outer surface The surface impurity level of the portion is not more than about ten times the bulk impurity level of the outer surface portion. Although a maximum 10X impurity level difference between the bulk and the surface is generally required, other embodiments have a surface impurity level no greater than about five times the bulk impurity level, such as no more than about two times. In fact, some embodiments have surface impurity levels that are no greater than the bulk impurity level. The process typically continues with further reduction of impurities to form an impurity exposed region along the surface portion of the outer surface portion, as will be described in more detail below.

Semiconductor process components in accordance with embodiments herein can be selected from one of a variety of geometric configurations for different process operations and can be configured to receive wafers of various sizes, for example, 150mm, 200mm or newer. A generation of 300mm wafers. Specific process components include semiconductor wafer paddles, processing tubes, wafer boats, pads, pedestals, boats, cantilevers, wafer carriers, vertical process chambers, and even dummy wafers. In the foregoing, a plurality of semiconductor process components can be configured for direct contact and for receiving components of a semiconductor wafer, such as horizontal or vertical wafer boats, boats, and wafer carriers. In addition, process components can be configured for a single wafer process and can be used in processing chambers, focus rings, rings, carriers, pedestals, and the like.

Semiconductor process components can be fabricated by a variety of techniques. For example, in accordance with a specific embodiment, a process component is formed by providing a substrate that is typically coated with a SiC layer by CVD. The CVD-SiC layer can be advantageously used to attenuate the automatic doping of the lower germanium and to prevent migration of impurities from the bulk of the substrate to the outer surface of the component, which can result in contamination during semiconductor wafer processing. Substrates are commonly used to provide mechanical support and structural integrity, and can be formed from a variety of materials, such as recrystallized SiC, and by various process routes. In one technique, a substrate is formed by spin casting or by pressing, which is mainly composed of SiC. In the case of slip casting, the cast body is dried and heat treated and then impregnated as needed to reduce porosity. Advantageously, the impregnation can be performed by infiltration with molten helium. Other specialized manufacturing techniques can also be used, such as by utilizing a conversion process in which a carbon preform is converted to a tantalum carbide core, or by subtracting a process wherein the core is removed after infiltration, such as by chemical vapor phase infiltration.

Alternatively, the semiconductor process component can be formed of a separate tantalum carbide, formed by one of various processes, such as CVD by tantalum carbide. This particular process technology enables the formation of relatively high purity process elements having substantially the entire block or internal portion of the component.

One embodiment of a wafer process component is shown in FIG. The wafer boat 1 illustrated in Figure 1 has a plurality of grooves 16, each extending along the same radius of curvature. Each trench has individual trench segments 18, 20, and 22 that are processed as needed after proper fabrication of the wafer boat. For example, a wafer boat can be fabricated in accordance with one of the above techniques, for example, by impregnating a tantalum carbide core with a molten tantalum element, and then performing CVD to form a deposited tantalum carbide layer. After the formation of the tantalum carbide layer, processing can be performed. In particular, grooves can be formed and fine-scale control can be performed by machining operations, such as by utilizing a diamond-based processing tool. It is worth noting that while Figure 1 illustrates a horizontal wafer boat, it should be understood that vertical wafer boats or wafer carriers, as well as other semiconductor process components previously mentioned, may also be utilized.

After the process components are formed, the process components are subjected to a processing procedure. That is, the outer portion of the element formed of CVD-SiC is manipulated to improve purity, and in particular to terminate and define impurities of the surface portion of the outer surface of the element. In a specific embodiment, one of the outer surface portions is removed from the target portion, leaving a surface having an impurity content no greater than ten times the bulk impurity content of the outer surface portion.

The removal of the target portion can be performed by any of several techniques. According to one technique, the outer surface portion is removed by an oxidative strip process. During oxidation, the element can be exposed to a reactant species, such as a halogen gas, to further improve purity. Reactant species are typically used to complicate or react with existing impurities and volatilize during high temperature processing. Oxidative stripping also reduces particle count along the outer surface, which is particularly advantageous in the context of semiconductor processing operations.

In more detail, the oxidation of the semiconductor process component is typically performed to form an oxide layer by a chemical reaction to form a conversion layer opposite the deposited oxide layer. Depending on the oxidation treatment, the oxide layer will consume the target portion of the component, a portion of the CVD-SiC material. The oxide layer can be formed by oxidation of the element in an oxidizing environment, for example by oxidizing the element in an oxygen-containing environment at elevated temperatures, for example, in the range of 950 to about 1300 degrees Celsius, and more specifically It is in the range of about 1000 to about 1250 degrees Celsius. Oxidation can be performed in a dry or humid environment and is typically performed at atmospheric pressure. A humid environment can be created by introducing steam and exerting an effect of increasing the oxidation rate. The oxide layer is typically yttrium oxide, typically SiO ₂ . The hafnium oxide layer can be in direct contact with the tantalum carbide of the component, as in the case of a freestanding SiC or substrate coated with tantalum carbide (for example by CVD).

In addition to properly forming an oxide layer along the body, the oxide layer can cause residual niobium carbide particles to be converted to hafnium oxide. In the case of particle conversion, oxidation can result in particle removal at a later stage. In addition, the formation of an oxide coating by a conversion process rather than a deposition process facilitates the capture of residual impurities, such as metallic impurities, within the oxide layer for removal with the stripping of the oxide layer.

The oxide layer can be stripped by exposing the process component to a solution capable of dissolving (decomposing) the oxide layer. In a specific embodiment, the solution is an acid containing fluorine. Typically, the pH of the solution is less than about 3.5, most typically less than about 3.0, and even higher acidity with a pH of less than about 2.5 is achieved for some embodiments. Alternatively, the solution may be an alkaline-based, and improve the bonding temperature (greater than room temperature, but below the boiling point of H ₂ O) and exposed to the layer. Alternatively, high temperatures and H ₂ gases can be used, for example above 1000 ° C.

During oxidation, the semiconductor process component can be exposed to a reactive species, such as a halogen gas, which forms a reaction product with contaminants present on the outer surface of the outer surface portion. In general, exposure to both reactive species and oxidation is performed simultaneously, although steps may alternatively be performed separately. In this regard, the terminology is used without the need to perform the exposure and oxidation steps to be fully coextensive, but rather the steps may partially overlap each other.

The term "halogen gas" means the use of any halogen group element provided in gaseous form, which is typically combined with a cation. Common examples of embodiments the halogen gas may be used depending on the particular embodiment of the present invention include HCl and Cl _2. Other gases include gases containing, for example, fluorine. Typically, the elevated temperature at which the semiconductor process component is exposed to the halogen gas is sufficient to effect a reaction between the halogen gas and impurities contained along an outer surface portion of the semiconductor process component, including along the exposed outer surface of the semiconductor process component. For example, the elevated temperature can range from about 950 °C to about 1300 °C. Additionally, the concentration of the halogen gas can vary and can be present in a heated environment (e.g., a furnace process chamber) in the range of from about 0.01 to about 10% of the total pressure. Typically, the lower limit of the partial pressure is slightly higher, such as about 0.05, or about 0.10%. While the foregoing has focused on halogen gases, other reactive cationic-containing reactants may be utilized, provided that the reactants are selected to form a reaction product with the desired metal impurities and that the reaction product has a higher volatility than the metal impurities themselves. Sex.

Generally, the impurity in which the halogen gas reacts along the outer surface portion of the semiconductor process element is a metal impurity. The metal impurities may be in the form of a metal element or a metal alloy, and may, for example, be mainly aluminum, ion-based or chromium-based. The formation of a reaction product with such metal impurities is caused by the use of a halogen gas such as HCl. The reaction product typically has a higher volatilization than the impurities such that during exposure of the process component to the elevated temperature, the reaction product volatilizes and is therefore removed from the process component.

While the above disclosure has focused on removing a portion of the component by reaction (especially by oxidative stripping), other techniques for removing the target portion may also be utilized. For example, the target portion can be reacted by introducing an etchant species at an elevated temperature to form an etchant product by an etching operation that volatilizes to remove the target portion in whole or in part. For example, the etchant species can be a chlorine containing gas to form a volatilized SiCl _x etchant product. The Cl-containing gas may be HCl, Cl ₂ and other gases. In some cases, carbon can remain as a by-product of the etching operation. This carbon can be removed by a high temperature burnout process. It should be noted that etching is sometimes referred to as graphitization, which illustrates carbon in the form of graphite remaining on the surface of the element. It is also generally desirable to combine the etchant used with impurities present along portions of the outer surface to form volatile species such as FeCl, TiCl, and the like. Additionally, as explained above, in the removal of the target portion by oxidation and oxide stripping, the contaminants may react to form a reaction product, such as by introducing a halogen gas as described in detail above.

While the foregoing has been focused on a single cycle, a re-replication step, such as an oxidation step (treated with an optional halogen gas), is typically repeated several times to achieve the desired level of purity through removal of the target portion.

Prior to removal of the target portion, the component can be subjected to a processing operation to remove, for example, 10 to 100 microns of material outside the component. Although the impurity distribution thus deposited is generally changed by material removal from the processing operation, the processing tends to leave a sharp peak on the outer surface of the element (ie, the surface thus processed) as observed in the thus deposited CVD SiC. By. It has been found that the surface impurity level can extend to the outer surface portion, for example on the order of 1 to 3 microns, before reaching the bulk impurity level. Accordingly, in a particular embodiment that has been processed, the target portion that is typically to be removed has a thickness at the higher end of the above range up to about 20 microns, and the actual thickness removed is on the order of 3 to 5 microns. . Accordingly, in the case where the CVD-SiC surface of the component is subjected to mechanical abrasion or processing (eg, grinding, milling, or polishing), further removal is generally due to the presence in the post-machined surface prior to removal of the target portion. The level of pollution is achieved. Removal of the target portion can be performed using an oxidative stripping cycle or an etch cycle, such as during a time sufficient to achieve high purity.

According to a change, an additional process step can be incorporated before the target portion is removed, with the goal of further reducing the impurity level. For example, the components can be rinsed prior to exposure to the halogen gas and subsequent processes, such as deionized (DI) water. Stirring can be performed during rinsing, such as with an ultrasonic mixer/agitator, to further supplement contaminant removal. Alternatively, the rinsing solution can be an acidic solution to assist in stripping contaminants.

As an alternative or in addition to rinsing, the component may be immersed in an acidic stripping solution, such as an acidic solution, prior to exposure of the halogen gas to further assist in the removal of impurities. The rinsing and/or immersion step can be repeated any number of times before another process.

Due to the observed depth profile as detailed below, typically the target portion has a thickness of at least about 0.25 microns, such as 0.38 microns, 0.50 microns, or even higher. In practice, the target portion most typically has a thickness of at least 1.0 microns, and is preferably at least about 2 microns, such as from about 2 to 10 microns, but typically less than 20 microns. Typically the CVD-SiC layer has a thickness in the range of about 10 to 1000 microns, and certain embodiments have a thickness of up to about 800 microns, 600 microns, 400 microns, or up to about 200 microns. The thickness of the target portion corresponding to the depth of removal of the outer surface portion of the component is generally selected to ensure that the desired surface impurity is reduced, for example, pushing the impurity content from the 1,000X of the block down to the 10X level of the block, Even lower. In fact, as a result of the removal of the target portion, if less than two magnitude levels are reached, the surface impurity level is generally reduced by at least one magnitude.

Moreover, it should be clear that the above-described embodiments achieve maximum impurity level from the outer surface of the component to the bulk impurity content, which is suitably controlled to partially or completely remove the peak or rich region. Generally, the maximum impurity energy level along the initial depth of the outer surface portion extending from the outer surface to the bulk impurity content is not more than 1.5X of the maximum impurity level of the bulk, for example, not more than 1.3X of the maximum impurity level of the bulk. Even the maximum impurity level of the block is approximately the same (1.0X).

According to a specific embodiment, after the surface impurity level of the outer surface portion is reduced by the removal of the target portion, a further process is performed to establish a localized surface portion of the outer surface portion having a further reduced impurity level. . This enhancement is at the purity level of the skin portion that terminates and defines the outer surface of the component, referred to herein as a "naked" region or zone. Exposed is typically performed by high temperature processing, typically in the presence of a deposited or grown layer that covers the outer surface of the component. In a particular embodiment, there is a relatively thick sacrificial layer, typically having a thickness of at least 1.0 microns, and typically a thickness of at least 5.0 microns. This sacrificial layer can be in the form of a polycrystalline germanium or a layer of ruthenium oxide deposited as such. Alternatively, the growth of thermal yttrium oxide is formed prior to the elevated temperature treatment. Such a cover layer is used to "make up" impurities present along the surface portion of the outer surface portion, and the surface portion generally extends from the outer surface portion of the outer surface portion to a depth of at least 100 nm.

During the heat treatment used to push the impurities into the cap layer, which may be referred to herein as a gettering layer, the impurities migrate from the outer surface of the CVD-SiC portion to the gettering due to the high solubility of impurities in the gettering layer at high temperatures. Within the layer. These temperatures are usually not less than 1150 ° C, often not less than 1200 ° C, such as 1250 ° C and higher. The heat treatment can be further extended up to 1300 ° C and higher. The diffusion coefficient of Fe is of significant importance due to the relatively common Fe contamination in SiC-based semiconductor process components relative to the above solubility of impurities in the gettering layer. The diffusion coefficient of Fe in polycrystalline germanium is 10 ⁹ times higher than that in CVD-SiC, making it a particularly suitable material for bare processes. Silicon oxide, comprising a thermally grown silicon oxide, having a ² / Fe diffusion coefficient of 10 ^-12 cm s, so that it than the CVD-SiC of high Fe ^102-fold.

The heat treatment is usually carried out in an inert atmosphere, which optionally contains a halogen gas, as defined above. Specific halogen gases include HCl and Cl ₂ . Alternatively, an inert gas may be combined with H ₂ to an improved absorbent inner layer heteroatom impurities (e.g., Fe) of the diffusion coefficient, based in particular in the case of silicon oxide.

In an alternative bare method, the cover layer is grown in situ during the heat treatment. In this particular embodiment, the exposure is performed according to the reaction of the SiC surface with a defined amount of halide gas, which acts as a metal getter for the gettering of impurities such as Fe and other transition metals. Usually an inert gas system in the halide atmosphere (e.g., Ar or N ₂₎ to provide the inherent relatively low partial pressure. Also, due to the lower boiling point/higher vapor pressure of the metal halide thus formed compared to the metal fluoride salt, the halide gas which may be present is as described above, specifically including Cl ₂ and HCl. The metal fluoride formed by the reaction with the gettering halide gas includes salts such as FeCl ₃ , FeCl ₂ , CrCl ₃ and NiCl ₂ .

As mentioned above, the aforementioned bare method relies on the formation of a layer or a passivation layer, typically a ruthenium oxide layer. This layer is formed in situ by slightly flooding an oxygen-containing gas (such as air) into the heat treatment environment to form a thickness of 100 To 5000 a yttrium oxide film on a grade, and in a particular embodiment, a thickness of 500 to 1500 On the level. For example, air overflow can be performed at a level of 1 to 50 mL/min. Similar to the bare process described above, the exposure with the air overflow to form the original layer can be performed at an elevated temperature, for example, at a temperature not less than 1150 ° C, not less than 1200 ° C, or even not less than 1250 ° C in accordance with the above process flow. Also, the heat treatment can be performed for 4 hours, for example, at least 5 hours, and the typical heat treatment duration is on the order of 10 to 12 hours. It should be noted that the halide content is generally minimized, and the flow rate of the halide gas and the accompanying partial pressure are typically set to minimize carbonization of the surface while still allowing reaction with metal contaminants that diffuse to the outer surface of the component. To further minimize graphitization, a gas (eg, SiCl _x gas) may be added to the reactant gas or entirely within the SiCl _x .

The formation of an oxide layer at the thin source is advantageously used to passivate the outer surface of the component during the bare process. Under this action, the layer can help prevent unwanted reactions with the underlying SiC material, including carbonization.

Typically, the bare process is applied to the component after removal of the target portion of the surface portion as discussed above. The foregoing target partial removal step is performed in a time that is approximately the same as the bulk sufficient to stabilize the surface impurity level. That is, the surface impurity level before bare exposure generally has from 90 to 120% of the bulk impurity level, which is measured at a point deeper than the outer surface portion, typically at least 3 microns. By performing the bare process flow as explained above, the surface portion is preferably detached from the impurities, thereby significantly reducing the impurity energy level to below the impurity level of the bulk.

In quantitative terms, the bare pair is effective to reduce the impurity energy level to no more than 80% of the bulk impurity level, typically no greater than 70%, 60%, 50%, and in some embodiments, no greater than 40% or even It has a lower energy level than the bulk impurity. In some embodiments, the surface impurity level can be at least one full magnitude lower than the bulk impurity level. With reference to specific data points, tests have shown that the surface impurity level is reduced to 100 ppb atomic Fe, usually even lower, such as not more than 50 ppb atomic Fe, or even no more than 35 ppb atom of Fe. In fact, the next generation of ultrapure components have been shown. Implemented; it has an Fe level of less than 20 ppb or even less than 10 ppb.

The foregoing bare method employs the properties of iron halides and transition metal tellurides in the form of impurities to melt and thereby rapidly diffuse along the defects, such as the screw locations and/or particle boundaries of the SiC-containing elements. The preferred diffusion to the free surface can be accomplished by the solid phase gettering method or the gas phase gettering method described above. In either method, gettering is effective in establishing a concentration gradient for various impurity species and continues to be used to propel the diffusion to the outer surface.

According to one feature, the removal of the target portion and subsequent exposure processing can be performed prior to use of the process component in a semiconductor fabrication environment. Likewise, the foregoing steps can be performed off-site (separate from the semiconductor fabrication environment), such as by the manufacturer of the process component rather than the end user (eg, semiconductor component manufacturer/wafer processor). The process components can be fully processed and then packaged in a sealed shipping container for direct and immediate use in a manufacturing environment.

The specific use consists of secondary ion mass spectrometry (SIMS) relative to the specific measurement technique used to characterize the pre- and post-treatment CVD-SiC elements. For example, other technologies include GDMS. The bulk impurity level used herein corresponds to the impurity level at a depth in the outer surface portion of the first stabilized purity level, that is, the impurity level becomes substantially deeper at the depth of the outer surface portion. Constant depth. The aforementioned impurity level of the bulk should not be confused with the deeper impurity level that can be associated with the "dirty" lower component or substrate; therefore, the bulk impurity energy level and the impurity energy from the outer surface (0 nm) position to a constant low point The first occurrence of the order is associated. It should be noted that impurity detection typically assumes a degree of variation, which is represented by a wobble within the measured impurity level as a function of depth. Unless otherwise noted in this document, the specific impurity level data points, especially the bulk impurity levels, are based on the trend of the impurity content of the data, ie, the smoothing data. Based on the characterization studies reported herein, it has been found that typically the bulk impurity level is typically reached by a depth of 3 microns. Therefore, the bulk impurity level can be obtained at a depth in the range of about 3 to 10 μm, for example, in the range of 3 to 5 μm. Given a natural impurity concentration change as a function of distance, the bulk impurity level, such as those reported below, is obtained from the smoothed data curve according to standard smoothing, ie, from the best fit curve representation of the original data. . However, the particular depth value at which the bulk impurity level is reached may depend on the process conditions of the particular CVD process utilized to form the outer surface portion, including the particular tool used, the gas used, temperature, pressure, and other process parameters.

The data and the following discussion focus on the characterization of a number of such deposited CVD-SiC samples and post-processed CVD-SiC samples.

example Example 1

A Si:SiC test piece having a size of 25 mm × 75 nun × 6 mm was prepared using a standard process. The test piece was ultrasonically washed in a diluted acid, rinsed with DI water, and dried. The cleaning test piece was loaded into a CVD reactor, and a CVD film having a thickness of 50 to 75 μm was deposited on the surface of the Si:SiC test piece. Multiple coating processes were performed using two different coating systems (Device A and Device B) to further understand the effect of the equipment on coating purity.

The impurity level on the surface of the CVD coated Si:SiC test piece was analyzed by secondary ion mass spectrometry (SIMS). SIMS analysis was performed with O ₂ ⁺ electric paddles in a depth profile using a Cameca 3f instrument. The instrument is calibrated for accurate impurity determination using the ion implanted SiC standard. The analysis focused solely on Fe and Cr so that the detection limits were good, ie 1 e15 atoms/cc for Fe and 1 e14 atoms/cc for Cr. Some processes were also performed using SIMS instruments with higher sensitivity and lower Fe detection limits of 1 e14 atoms/cc. Unless otherwise stated, the results described below represent such deposited or thus removed CVD-SiC without intermediate processing operations.

The SIMS analysis of the CVD-SiC layer of the sample processed by device A indicates a high surface contamination of both Fe and Cr, which is 500 to 1000 times higher than the block value shown in FIG. The Fe concentration in the block is <1 e15 atoms/cc, and the Cr concentration is <1 e14 atoms/cc, which is typical for CVD-SiC coatings.

Similar high surface impurity concentrations were also observed on the CVD-SiC layer deposited using device B, as shown in FIG.

For a particular sample characterized, the surface Fe concentration was >1 e18 atoms/cc and dropped to a bulk value of 1 e15 atoms/cc within a 0.5 micron depth into the CVD-SiC coating. To verify the prevalence of high impurity concentrations on the surface of the thus deposited coating, a third test was performed on the CVD-SiC coating having higher impurities in the reactant gas used to form the CVD film. Impurity of impurities was also observed on coatings with higher impurity levels, as shown in Figure 4. The Fe concentration at the surface is >5 e17 atoms/cc, and decreases from 0.6 to 0.7 microns to a bulk Fe concentration of 4 e16 atoms/cc.

The mechanism for the concentration of impurities on the surface is not currently known, but may be related to the migration of impurities from the surface of the Si:SiC substrate during the CVD-SiC deposition process or the Fe isolation from the interior of the film to the surface during cooling.

Two different types of CVD-SiC coatings were produced with apparatus A, and a standard coating and a lower impurity coating were selected for the cleaning process. The test piece was loaded into a CVD coated cantilever paddle and placed in a diffusion furnace equipped with a SiC processing tube and a clean quartz baffle.

The test piece was oxidized at 950 to 1350 ° C for 6 to 14 hours in flowing O ₂ with up to 10% HCl gas. The heat treatment conditions are selected to be permeable to a target portion of CVD-SiC equivalent to about 0.45 to 0.60 (nominally 0.5) times the thickness of the oxide so as to be able to grow a thick layer of oxide on the CVD-SiC surface. The oxidation process helps to concentrate transition metal impurities (such as Fe) in the oxide layer on the CVD-SiC. Although the HCl gas helps to volatilize impurities on the surface of the grown oxide, the HCl treatment is not considered to substantially remove the metal trapped in the grown oxide layer. The total system process consumes the contaminated target portion of the CVD-SiC layer by reaction, SiC + 3/2 O ₂ (g) = SiO ₂ + CO (g) to form SiO ₂ .

To remove bulk impurities in the oxide layer, the oxide layer was stripped in an acid bath using a HF-HCl mixture (1:1 acid mixture). The resulting impurity concentration on the surface is shown in Figure 5.

SIMS analysis indicated that the surface Fe concentration decreased from >5e17 atoms/cc on the initial CVD-SiC coupon to <5 e16 atoms/cc on the cleaned test piece, which resulted in a 10-fold improvement due to cleaning. The bulk impurity concentration was kept constant at 1e15 atoms/cc. Although the cleaning cycle reduces the surface impurity concentration, the surface impurity concentration is still 50 times higher than the bulk. Therefore, an additional cleaning cycle is performed to further reduce the Fe concentration at the surface. Due to detection limitations and noise in the analysis, the effect of the second cleaning cycle cannot be quantified using SIMS. Therefore, the cleaning cycle is repeated using CVD-SiC samples with higher impurities (shown in Figure 4) to help resolve small differences in surface and bulk impurity energy levels.

A lower purity CVD-SiC sample was cleaned similar to a standard CVD-SiC sample. The test piece was first oxidized at 950 to 1350 ° C for 6 to 14 hours in a flowing O ₂ having up to 10% HCl gas to grow an oxide layer which was thereafter peeled off by the HF-HCl solution. The cleaning cycle is repeated a second time to remove material deeper into the CVD-SiC surface and thereby remove the Fe-concentrated surface layer.

Figure 6 shows the SIMS analysis of the test pieces after two cleaning cycles. The double cleaning cycle is effective for completely removing the contaminated surface layer, and the surface impurity concentration is similar to the bulk impurity concentration.

Additionally, as illustrated in Figure 7, the techniques described herein can be performed to reduce the surface impurity energy level to no more than the bulk impurity level, i.e., approximately equal to or less than the bulk impurity level. For example, after the initial two cleaning cycles as shown in Figure 7, an additional 2 cleaning cycles were performed without further purity improvement.

Example 2

A Si:SiC test piece having a size of 6 mm x 18 mm x 3 mm was machined to provide a smooth surface and then prepared using standard processes. The test piece was ultrasonically washed in a diluted acid, rinsed with DI water, and dried. The cleaning test piece was loaded into a CVD reactor, and a CVD film having a thickness of between 25 and 35 μm was deposited on the surface of the Si:SiC sheet. The CVD coated sample was recoated with a CVD film having a thickness of 20 to 35 microns to completely seal any thin coating that holds the test piece near the area within the CVD reactor. A test piece of a CVD-SiC film having a regular Fe concentration of 20 ppb and a high Fe concentration of 500 to 900 ppb was prepared for the cleaning test.

The test piece was loaded into a CVD coated cantilever paddle and placed in a diffusion furnace equipped with a SiC processing tube and a clean quartz baffle.

The test piece was first oxidized at 950 to 1350 ° C for 6 to 14 hours in flowing O ₂ with up to 10% HCl gas to grow an oxide layer which was subsequently stripped by the HF-HCl solution. The cleaning cycle was repeated six times to ensure complete removal of the Fe-concentrated surface layer and confirmation of removal of the Fe-concentrated layer by SIMS analysis, as shown in FIG.

The cleaning test piece was loaded into a CVD coated cantilever paddle and placed in a diffusion furnace equipped with a SiC processing tube and a clean quartz separator.

The test piece was thermally annealed at 1000 ° C to 1300 ° C in Ar flowing at 5 to 10 SLPM with up to 10 vol% HCl for 6 to 14 hours. Exposed is dependent on the diffusion of metallic impurities to the surface, where it is thereafter removed by reaction with HCl to form a metal halide. The processing conditions are selected to ensure a sufficient chlorine atmosphere for evaporating the transition metal and transition metal halide into the gaseous metal halide without decomposing the CVD-SiC film. In addition, due to the low diffusion coefficient of Fe (10 ^-14 cm ² /s), a long annealing time is required to achieve a minimum exposed depth of 200 to 250 nm. A small amount of air also overflows into the atmosphere to further limit the CVD attack of CVD-SiC by forming a thin passivation layer in the form of an oxide layer on the test piece. While the addition of air is advantageous for SiC stability, excessive gas flow can result in an oxide layer that is too thick, thereby inhibiting the diffusion of impurities and reducing the effectiveness of the bare. Therefore, the oxide layer thickness is controlled at 500 to 1500 on the CVD-SiC surface. between.

Figure 9 shows the SIMS analysis of the cleaned samples after treatment in Ar and HCl gas. The Fe concentration is reduced by ~100X times from 3 E14 atoms/cc at the surface to 2.2 E16 atoms/cc in the block. The low Fe surface region extends from the surface to a depth as high as 215 nm. The low Fe surface is called the "naked area."

A process cleaning rule Fe purity sample similar to that described for low Fe purity samples was also used. The initial cleaning step in the oxidation of HCl followed by the HF acid cleaning of the Fe concentration in the sample is below the detection limit of the instrument. Therefore, the exposed area on the surface cannot be detected by SIMS analysis. However, a regular Fe purity sample may desirably have a similar "bare zone" at a surface where the Fe concentration is lower than the bulk of the block.

Example 3 (comparative example).

A Si:SiC test piece having a size of 6 mm x 18 mm x 3 mm was machined to provide a smooth surface and then prepared using standard processes. The test piece was ultrasonically washed in a diluted acid, rinsed with DI water, and dried. The cleaning test piece was loaded into a CVD reactor, and double coating was performed for each coating with a CVD film having a thickness of 25 to 35 μm. A test piece of a CVD-SiC film having a high Fe concentration of 500 to 900 ppb was prepared for the cleaning test.

The test piece was loaded into a CVD coated cantilever paddle and placed in a diffusion furnace equipped with a SiC processing tube and a clean quartz baffle.

The test piece was thermally annealed at 1000 ° C to 1300 ° C in Ar flowing at 5 to 10 SLPM with up to 10 vol% HCl for 6 to 14 hours, and cooled in a flowing gas of the same atmosphere. A small amount of air also overflows into the atmosphere to further limit the CVD attack of CVD-SiC by forming a thin passivation layer in the form of an oxide layer on the test piece.

Figure 10 shows the SIMS analysis of the cleaned samples after treatment in Ar and HCl gas. The near surface Fe concentration decreased from 2 E18 atoms/cc in the thus deposited CVD to less than 1 E17 atoms/cc in the sample treated in Ar and HCl gas. In addition, the maximum Fe concentration is also reduced by a factor of two. Therefore, a thin bare region is formed for a depth of 200 nm, and then the Fe concentration is increased. The Fe concentration eventually decreases to less than the 5 E16 block impurity level in the bulk of the material. Due to the slow metal diffusion dynamics, the penetration depth in CVD-SiC is <0.4 microns, and direct thermal annealing in Ar and HCl is effective at cleaning the first 200 nm of the CVD-SiC film. Therefore, for effective bare treatment, it is important to remove the Fe-concentrated impurity profile prior to the bare treatment.

A process cleaning rule Fe purity sample similar to that described for low Fe purity samples was also used. The initial cleaning step in the oxidation of HCl followed by the HF acid cleaning of the Fe concentration in the sample is below the detection limit of the instrument. Therefore, the exposed area on the surface cannot be detected by SIMS analysis. However, a regular Fe purity sample may desirably have a similar "bare zone" at a surface where the Fe concentration is lower than the bulk of the block.

It will be apparent from the foregoing that particular embodiments rely on a process flow incorporating the removal of the target portion, which has the ability to reduce the energy level of the outer surface impurity, and in particular to reduce the surface impurity level to the bulk The level. Subsequent exposure processes are then effective in establishing a localized range of surfaces outside the component that significantly reduces the energy level of the impurity. The aforementioned bare method generally relies on a solid phase gettering mechanism or a gas phase gettering mechanism, which is a method of establishing an impurity level gradient to drive impurities to the surface of the element.

The above examples illustrate a bare zone extending from the outer surface of the component to a depth on the order of 200 nm. Further extension of the bareness can be accomplished by extending the high temperature annealing dwell period, for example to a depth of 300 nm, 400 nm or 500 nm. For example, extending the anneal to 24 hours is desirable to achieve a bare zone extending to 250 nm or greater. The extended bare zone can also be accomplished by increasing the annealing temperature, for example up to 1300 ° C, which should achieve a bare depth of 350 nm or greater. In addition, the extended bare zone can also be completed by increasing the HCl gas flow. In such a case, the above-mentioned surface layer impurity level extends over 100 nm, and may extend to not less than 200 nm, or in other embodiments, not less than 300 nm and not less than 400 nm.

It should be noted that attempts have been made previously to reduce the impurity level of semiconductor grade components, such as the process illustrated in US 6,277,194. Therein, the gettering layer is deposited on an element which can be formed of tantalum carbide. However, the process illustrated in U.S. 194 has little effect on establishing bare areas achieved by embodiments of the present invention. The generalized process flow of US '194 is generally sufficient for the reduction of impurity levels, but does not achieve significant and quantifiable bare areas in accordance with the specific embodiments herein, which are significantly lower than bulk impurity energy in accordance with the above-described embodiments. The impurity level of the CVD-SiC material of the order. Likewise, the cleaning cycle, even repeated many times, has no effect on the formation of exposed areas, and the enhanced impurity reduction described in accordance with various embodiments above cannot be achieved alone.

The above-disclosed subject matter is intended to be illustrative and not restrictive, and the scope of the invention is intended to cover all such modifications, modifications and other embodiments. The scope of the invention is to be determined by the broadest scope of the appended claims and claims

1. . . Wafer boat

16. . . Trench

18. . . Groove fragment

20. . . Groove fragment

twenty two. . . Groove fragment

The invention will be better understood, and its numerous features and advantages will be apparent to those skilled in the art.

1 illustrates an embodiment of the present invention, namely a wafer boat or carrier.

2 and 3 illustrate the impurity depth profile of a CVD-SiC film formed in two different commercially available deposition devices.

Figure 4 illustrates the impurity depth profile of CVD-SiC formed using reactant gases at higher contaminant levels.

Figure 5 illustrates the impurity depth profile of the CVD-SiC layer before and after the initial cleaning step.

Figure 6 illustrates the depth profile of two cleaning cycles from another sample having a relatively low purity CVD-SiC layer.

Figure 7 illustrates the depth profile of the surface Fe concentration after two cleaning and four cleaning cycles of a sample having a relatively low purity CVD-SiC layer.

Figure 8 illustrates the depth profile of a relatively low purity CVD-SiC layer after complete removal of the Fe-concentrated surface layer.

Figure 9 illustrates the purity level of a CVD-SiC layer in three states after deposition, after six cleaning cycles, and after subsequent heat treatment to form a bare skin portion, in accordance with an embodiment.

Figure 10 illustrates the purity level of a CVD-SiC layer in two states after deposition and subsequent heat treatment to form a bare skin portion, in accordance with an embodiment.

The same reference symbols are used in the different figures to indicate similar or identical items.

1. . . Wafer boat

16. . . Trench

18. . . Groove fragment

20. . . Groove fragment

twenty two. . . Groove fragment

Claims (8)

A method of exposing a semiconductor process component, comprising: providing a semiconductor process component having an outer surface portion formed by chemical vapor deposition of SiC; removing a target portion of the outer surface portion, the outer surface The portion has a surface impurity level and a bulk impurity level, wherein the surface impurity level enters the outer surface portion to an average impurity level from 0 nm to 100 nm, and the bulk impurity energy level enters the outer layer The surface portion is measured at a depth of not less than 3.0 μm; and the element is heat-treated to diffuse impurities from a surface of the outer surface portion such that the surface impurity level of the surface layer is not more than 80% of the impurity level of the bulk. The method of claim 1, further comprising forming a gettering layer covering the outer surface portion to push impurities into the gettering layer during the heat treatment. The method of claim 2, wherein the gettering layer has an impurity diffusion coefficient that is at least 10 ² times greater than an impurity diffusion coefficient of the outer surface portion. The method of claim 2, wherein the gettering layer comprises ruthenium oxide formed by oxidation of the outer surface portion or polycrystalline germanium formed by deposition. The method of claim 1, wherein the heat treatment is performed at a temperature of not less than 1150 ° C for a period of not less than 5 hours. The method of claim 1, wherein the heat treatment is performed in the presence of a halide gas. The method of claim 1, wherein the surface impurity level is not greater than 70% of the bulk energy level of the bulk. The method of claim 1, wherein the surface impurity level is not greater than 100 ppb atoms of Fe.