TWI420658B - Solid-state image capturing device and elecrtronic information device - Google Patents

Description

Solid-state imaging device and electronic information machine

The present invention relates to a solid-state imaging device including a semiconductor element for performing photoelectric conversion of image light from an object and capturing an image of the object, in detail, a solid-state imaging element driven by a low voltage (for example, MOS image sensor); and an electronic information machine (for example, a digital camera (digital video camera, digital still camera), multiple image input cameras, scanners, faxes, camera-equipped mobile phones, and the like), It uses a solid-state imaging element as an image input machine for its imaging area.

Conventionally, semiconductor image sensors such as CCD image sensors and MOS image sensors have been used as portable electronic information devices because of their ease of mass production (for example, digital cameras (digital video cameras, digital still cameras), equipped with cameras). The image input machine in the mobile phone machine and the like.

These conventional portable electronic information machines are battery powered. Therefore, it is important to reduce the voltage required to drive power and reduce power consumption. It is also important to reduce production costs and reduce the size of modules.

Therefore, in the field of utilizing image pickup elements for such portable electronic information devices, since the MOS image sensor consumes less power, the cost of the MOS image sensor is easily reduced compared with the CCD image sensor and can be reduced for this purpose. Utilize conventional CMOS processing techniques. Moreover, since the inductor element and its peripheral circuit components are fabricated on the same wafer, the CMOS image sensor has the advantage of reducing the size of the module. Thus, CMOS image sensors are now viewed from different perspectives.

In addition, a photodiode (optical signal detection area) is embedded in a conventional MOS image sensor. This is highly advantageous from the point of view of reducing noise. Therefore, it is possible to obtain high quality images.

Hereinafter, a conventional MOS image sensor including a buried photodiode will be described in detail with reference to parts (a) to (c) of FIG.

Part (a) of Figure 10 is a cross-sectional view showing a unit pixel region (one pixel) of a conventional MOS image sensor 100 including a buried photodiode. A plurality of unit pixel regions are arranged in a matrix of two dimensions in a conventional MOS image sensor.

As shown in part (a) of FIG. 10, the unit pixel region of the conventional MOS image sensor 100 includes a p-type well region 102 formed in an n-type (low concentration n-type: n-) or p-type (low concentration). P-type: p-) in the semiconductor substrate 101; a photoelectric conversion/accumulation region 103 formed of an n-type semiconductor region formed in the p-type well region 102; and a p-type (high-concentration p-type: P+) pinning layer 104, which is formed on the photoelectric conversion/accumulation region 103 on the top surface side of the semiconductor substrate 101, and each of which forms a buried photodiode. In this case, the photoelectric conversion/accumulation region 103 and the semiconductor substrate 101 are separated by the p-type well region 102. The photoelectric conversion/accumulation region 103 and the top surface of the semiconductor substrate 101 are also separated by the p-type pinned layer 104, and thus are buried in the semiconductor substrate 101.

In the unit pixel region, an insulating film 105 made of a hafnium oxide film is formed on the top surface of the semiconductor substrate 101, and a gate electrode (transfer gate electrode) 106 for transferring a MOS transistor is formed on the insulating film 105. A charge detecting region 107 formed of an n-type (high-concentration n-type: n+) semiconductor region is formed on the opposite side of the photoelectric conversion/accumulation region 103 with respect to the p-type well region 102 under the transfer gate electrode 106. The p-type well region 102 below the transfer gate electrode 106 serves as a transistor channel region.

In the MOS image sensor 100, when the photodetection signal (signal charge) accumulated in the photoelectric conversion/accumulation area 103 is read, the transfer pulse Φ _{TX is} applied to the transfer gate electrode 106, and the power supply voltage Vd is applied to Charge detection area 107. Therefore, signal charges are transferred from the photoelectric conversion/accumulation region 103 to the charge detecting region 107 via the transfer MOS transistor. The transfer pulse Φ _TX is typically supplied from a CMOS driver circuit. Therefore, the low level of the transfer pulse Φ _TX is located at the ground voltage GND, and the high level of the transfer pulse Φ _TX is located at the power supply voltage Vd. In portable electronic information machines, the supply voltage Vd is typically located at a potential of approximately 2.8 V to 3.3 V.

In addition, the element isolation region 108 is provided on both sides of the signal charge transfer path, and the signal charge transfer path extends from the photoelectric conversion/accumulation region 103 to the charge detection region 107 via the p-type well region 102.

The potential in each of the regions in the signal charge transfer path will be described in detail with reference to parts (b) and (c) of FIG. 10, and the signal charge transfer path extends from the photoelectric conversion/accumulation region 103 to the charge via the p-type well region 102. Detection area 107.

Parts (b) and (c) of Fig. 10 are each a potential distribution map in a signal charge transfer path shown by a broken line a-a' in part (a) of Fig. 10, wherein the signal charge transfer path includes a photoelectric conversion/accumulation area 103. A channel region (p-well region 102) and a charge detecting region 107 under the gate electrode 106. Part (b) of Fig. 10 shows a potential distribution diagram when the transfer pulse Φ _TX applied to the transfer gate electrode 106 is at a low level. Part (c) of Fig. 10 shows a potential distribution diagram when the transfer pulse Φ _TX applied to the transfer gate electrode 106 is at a high level.

As shown in part (b) of FIG. 10, in the conventional MOS image sensor 100 including the buried photodiode, when the transfer pulse Φ _TX applied to the transfer gate electrode 106 is at a low level, due to photoelectric conversion The accumulation/conversion region 103 is separated from the top surface of the semiconductor substrate 101 by the p-type pinning layer 104 formed at the top surface of the semiconductor substrate 101, thereby suppressing the occurrence of impurities at the interface between the semiconductor substrate 101 and the insulating film 105. The charge flows into the photoelectric conversion/accumulation region 103 to become a dark voltage component.

However, as shown in part (c) of FIG. 10, when the transfer pulse Φ _TX applied to the transfer gate electrode 106 is at a high level, the p-type pinned layer 104 formed at the top surface of the semiconductor substrate 101 affects the charge transfer path. A-a', thereby forming a potential barrier that blocks the transfer of optical signal charges from the photoelectric conversion/accumulation region 103 to the charge detecting region 107.

Due to this potential barrier, the signal charge resides in the photoelectric conversion/accumulation region 103 when the signal charge is read. Therefore, it is impossible to completely transmit the signal charge of the photodiode, or it is impossible to reduce the noise due to the occurrence of noise, thus causing a problem of image sticking.

In order to prevent this image sticking phenomenon, for example, Reference 1 discloses a method of changing the positional relationship between the transfer gate electrode 106 and the photoelectric conversion/accumulation region 103 and the high-concentration p-type pinning layer 104 on the photoelectric conversion/accumulation region 103. .

Hereinafter, a conventional MOS image sensor disclosed in Reference 1 will be described in detail with reference to parts (a) to (c) of FIG.

Part (a) of FIG. 11 is a cross-sectional view showing a unit pixel region (one pixel) of the MOS image sensor 100A, and the MOS image sensor 100A is an example of a conventional solid-state image sensor disclosed in Reference 1. A plurality of unit pixel regions are arranged in a matrix of two dimensions in the MOS image sensor 100A.

As shown in (a) of FIG. 11, the MOS image sensor 100A has an overlapping structure in which an end portion of the photoelectric conversion/accumulation region 103A extends a distance b under the transfer gate 106.

Parts (b) and (c) of Fig. 11 are each a potential distribution map in a signal charge transfer path shown by a broken line a-a' in part (a) of Fig. 11, wherein the signal charge transfer path includes a photoelectric conversion/accumulation area 103A. A channel region (p-well region 102) and a charge detecting region 107 under the transfer gate electrode 106. Part (b) of Fig. 11 shows a potential distribution diagram when the transfer pulse Φ _TX applied to the transfer gate electrode 106 is at a low level. Part (c) of Fig. 11 shows a potential distribution diagram when the transfer pulse Φ _TX applied to the transfer gate electrode 106 is at a high level.

As shown in (c) of FIG. 11, the MOS image sensor 100A having the overlapping structure in part (a) of FIG. 11 can solve the potential barrier problem shown in part (c) of FIG. 10, and it can suppress the image sticking. phenomenon.

In the MOS image sensor 100A, when the concentration of the photoelectric conversion/accumulation region 103A is increased to secure a sufficient charge capacity for accumulation, as shown in part (a) of Fig. 11, due to the tip end portion of the photoelectric conversion/accumulation region 103A The width of the tip end portion of the photoelectric conversion/accumulation region 103A extending under the transfer gate electrode 106 is large under the transfer gate electrode 106, so that the potential barrier problem is solved. As a result, as shown in part (c) of Fig. 11, a charge residue surrounded by a broken line is formed under the transfer gate electrode 106, thus causing a residual image problem.

To prevent this afterimage, the conventional MOS image sensor 100B will be described in detail with reference to parts (a) to (c) of FIG.

Part (a) of Fig. 12 is a cross-sectional view showing a unit pixel region (one pixel) of the MOS image sensor 100B, and the MOS image sensor 100B is another example of a conventional solid-state image sensor. A plurality of unit pixel regions are arranged in a matrix of two dimensions in the MOS image sensor 100B.

As shown in part (a) of Fig. 12, in the MOS image sensor 100B, the p-type pinning layer 104B is not formed on the photoelectric conversion/accumulation area 103B on the end face side of the transfer gate electrode 106. In other words, the tip end portion of the p-type pinned layer 104B is configured to be spaced apart from the end face of the transfer gate electrode 106 by a predetermined distance. In this way, the formation of the potential barrier by the p-type pinned layer 104B in the charge transfer path a-a' is suppressed.

Parts (b) and (c) of Fig. 12 are each a potential distribution map in a signal charge transfer path shown by a broken line a-a' in part (a) of Fig. 12, wherein the signal charge transfer path includes a photoelectric conversion/accumulation area 103B, a channel region (p-well region 102) under the gate electrode 106 and a charge detecting region 107. Part (b) of Fig. 12 shows a potential distribution diagram when the transfer pulse Φ _TX applied to the transfer gate electrode 106 is at a low level. Part (c) of Fig. 12 shows a potential distribution diagram when the transfer pulse Φ _TX applied to the transfer gate electrode 106 is at a high level.

In the MOS image sensor 100B, as shown in part (c) of Fig. 12, the potential level is gradually changed from the photoelectric conversion/accumulation area 103B to the charge detecting area 107 in a stepwise manner. Therefore, since the signal charge flows smoothly, it is possible to avoid the occurrence of afterimage.

Next, Reference 2 discloses a conventional solid-state imaging device in which an n-type photoelectric conversion region and a high-concentration n-type layer having an impurity concentration higher than that of the n-type photoelectric conversion region in the transport path region are formed. The signal accumulation region is arranged to form a photoelectric conversion/accumulation region of the photodiode. In the conventional solid-state imaging device, the portion having the highest potential at the photoelectric conversion region is configured to be positioned below the read gate electrode for reading signal charges to the signal scanning circuit region. In addition, a signal accumulation region is formed at the surface of the photoelectric conversion region and is separated from the p-type well region where the signal scanning circuit region is formed. According to this solid-state imaging element, only the transmission path region of the photodiode is highly concentrated, and thus it is possible to change the potential at the bottom of the photoelectric conversion region without increasing the gate voltage. Therefore, it is possible to completely transfer the photoelectrically converted signal charge to the signal scanning circuit region by low voltage driving.

Reference 1: Japanese Patent Laid-Open Application No. 11-126893 Reference No. 2: Japanese Patent Laid-Open Application No. 2006-120711

However, the above conventional solid-state imaging element has the following problems.

As described above, in the conventional MOS image sensor 100A disclosed in Reference 1, when the concentration of the photoelectric conversion/accumulation region 103A is increased to secure a sufficient charge capacity for accumulation, as shown in part (a) of FIG. As shown, the width of the tip end portion of the photoelectric conversion/accumulation region 103A extending under the transfer gate electrode 106 is large. As a result, as shown in part (c) of Fig. 11, a charge residue surrounded by a broken line is formed under the transfer gate electrode 106, thus causing a residual image problem.

In addition, as shown in part (a) of FIG. 12, in the conventional MOS image sensor 100B, the p-type pinned layer 104B is not formed on the surface of the photoelectric conversion/accumulation area 103B on the end portion of the transfer gate electrode 106, Therefore, the photoelectric conversion/accumulation region 103B is partially exposed at the surface of the semiconductor layer 101. The exposed region of the photoelectric conversion/accumulation region 103B shown in part (a) of Fig. 12 is subjected to plasma damage caused by the dry etching step at the time of forming the transfer gate electrode 106 or the like. Therefore, the interface energy density at the surface of the semiconductor substrate is high. Therefore, a large amount of noise charges are generated, and the generated noise charges flow into the photoelectric conversion/accumulation region 103B and thus the noise is prevented from being reduced.

Further, in the conventional solid-state imaging element disclosed in Reference 2, a high-concentration n-type signal accumulation region having a high impurity concentration is provided only in the transmission path region. Therefore, the area for accumulating charges therein is small, and the impurity concentration of the other n-type photoelectric conversion regions is low. Therefore, when it is desired to ensure a sufficient amount of signal charge, it is considered that afterimages will occur.

The present invention is intended to solve the above-mentioned conventional problems. The object of the present invention is to provide a solid-state imaging device capable of completely transmitting signal charges from a photoelectric conversion/accumulation region to a charge detection region, and also capable of obtaining a high-quality image with suppressed noise and afterimage. And an electronic information machine that uses a solid-state imaging element for its imaging area.

A solid-state imaging device according to the present invention includes a plurality of unit pixel regions disposed on a semiconductor substrate, wherein each of the plurality of unit pixel regions includes: a first conductivity type semiconductor region that forms a photoelectric conversion/accumulation a region for photoelectrically converting light into a signal charge and accumulating the signal charge therein; a second conductive semiconductor pinning layer for separating the photoelectric conversion/accumulation region from a top surface of the semiconductor substrate; a second conductive well region forming a channel region of the transfer transistor, capable of transferring the signal charge from the photoelectric conversion/accumulation region to a charge detection region; and a gate electrode of the transfer transistor, wherein the The second conductive type well region is formed to retreat toward the charge detecting region side with respect to one end surface of the gate electrode on the photoelectric conversion/accumulation region side, so that afterimage is suppressed, thereby achieving the above object.

Preferably, in the solid-state imaging device according to the present invention, the second conductive type well region is formed to retreat toward the charge detecting region side with respect to the photoelectric conversion/accumulation region.

Still preferably, in the solid-state imaging device according to the present invention, a tip end portion of the photoelectric conversion/accumulation region contacts the second conductive type well region under the gate electrode, or the tip end portion of the photoelectric conversion/accumulation region Located in the second conductive well region.

Still preferably, in the solid-state imaging device according to the present invention, one end portion of the photoelectric conversion/accumulation region is located under the gate electrode, and the end portion of the photoelectric conversion/accumulation region overlaps the gate in a plan view electrode.

Further preferably, in the solid-state imaging device according to the present invention, the overlap width of the photoelectric conversion/accumulation region and the gate electrode in a plan view and the end face of the second conductive type well region with respect to the gate electrode A back-off width toward the side of the charge detecting area is set such that the afterimage does not appear in a captured image.

Further preferably, in the solid-state imaging device according to the present invention, the photoelectric conversion is performed when the back-contour width of the second conductive type well region with respect to the end surface of the gate electrode toward the charge detecting region side is 0.24 μm. The overlap width of the /accumulation region and the gate electrode is set within a range between 0.06 μm (including 0.06 μm) and 0.27 μm (including 0.27 μm).

Further preferably, in the solid-state imaging device according to the present invention, the overlapping width of the photoelectric conversion/accumulation region and the gate electrode is set in a range of 0.20 μm ± 0.05 μm.

Further preferably, in the solid-state imaging device according to the present invention, when the overlapping width of the photoelectric conversion/accumulation region and the gate electrode is 0.20 μm, the second conductive type well region is opposite to the end surface of the gate electrode The back-off width toward the side of the charge detecting region is set within a range between 0.20 μm (including 0.20 μm) and 0.40 μm (including 0.40 μm).

Further preferably, in the solid-state imaging device according to the present invention, the retreat width of the second conductive type well region with respect to the end surface of the gate electrode toward the charge detecting region side is set to 0.24 μm (including 0.24 μm). ) and a range between 0.30 μm (including 0.30 μm).

Still preferably, in the solid-state imaging element according to the present invention, the second conductive type semiconductor pinning layer is formed to be offset with respect to the photoelectric conversion/accumulation area.

Further preferably, in the solid-state imaging device according to the present invention, the photoelectric conversion/accumulation region on the top surface side of the semiconductor substrate is completely covered by the second conductive type semiconductor pinning layer and the gate electrode.

Further preferably, in the solid-state imaging device according to the present invention, a position of one end portion of the second conductive type semiconductor pinning layer on the charge detecting region side and the gate electrode on the photoelectric conversion/accumulation region One of the end portions is aligned.

Further preferably, in the solid-state imaging device according to the present invention, a low concentration first conductivity type semiconductor region is disposed in the first conductivity type semiconductor region forming the photoelectric conversion/accumulation region and the second region forming the channel region Between the conductive well regions, the low concentration first conductive semiconductor region has an impurity concentration lower than that of the first conductive semiconductor region.

Further preferably, in the solid-state imaging device according to the present invention, the low-concentration first-conductivity-type semiconductor region is a first-conductivity-type semiconductor substrate region.

Further preferably, in the solid-state imaging element according to the present invention, the impurity concentration of one of the first conductive type semiconductor regions forming the photoelectric conversion/accumulation region is set to 1 × 10 ¹⁷ cm ^-3 (including 1 × 10 ¹⁷ Cm ^-3 ) to a range between 4 × 10 ¹⁷ cm ^-3 (including 4 × 10 ¹⁷ cm ^-3 ).

Further preferably, in the solid-state imaging device according to the present invention, the impurity concentration of one of the low-concentration first-conductivity-type semiconductor regions is set to 1 × 10 ¹⁴ cm ^-3 (including 1 × 10 ¹⁴ cm ^-3 ) to 1 ×10 ¹⁵ cm ^-3 (including 1 × 10 ¹⁵ cm ^-3 ) within a range.

Still preferably, in the solid-state imaging device according to the present invention, the photoelectric conversion/accumulation region is covered by the same region as the second conductive type well region forming the channel region, so that the photoelectric conversion/accumulation in a plan view The area around the area is not in contact with a component separation area for separating the pixel areas of the cells from each other.

Still preferably, in the solid-state imaging element according to the present invention, the plurality of unit pixel regions are arranged in a matrix.

Further preferably, in the solid-state imaging device according to the present invention, the unit pixel region includes the lower one as an internal circuit region of a pixel: one for reading from the transfer transistor to the charge detection a signal voltage of the region to amplify a signal and output the amplified signal of the amplified transistor; and a reset transistor capable of resetting a voltage of one of the charge detection regions to a predetermined voltage.

Still preferably, the solid-state imaging device according to the present invention further includes: a pixel selection transistor capable of reading the signal from the amplifying transistor to an output signal line as the internal circuit region in a pixel.

Further preferably, in the solid-state imaging device according to the present invention, an impurity concentration of a second conductivity type well region of a channel region of each of the transistors forming the internal circuit region of a pixel An impurity concentration of the second conductive type well region forming the channel region of the transfer transistor is different.

Further preferably, in the solid-state imaging device according to the present invention, an impurity concentration of a second conductivity type well region of a channel region of each of the transistors forming the internal circuit region of a pixel An impurity concentration of the second conductivity type well region forming the channel region of the transfer transistor is independently set and controlled.

Further preferably, in the solid-state imaging device according to the present invention, an impurity concentration of a second conductivity type well region of a channel region of each of the transistors forming the internal circuit region of a pixel Set in a range of 2 × 10 ¹⁷ cm ^-3 ± 1 × 10 ¹⁷ cm ^-3 , and an impurity concentration of the second conductive type well region forming the channel region of the transfer transistor is set at 3 × In the range of 10 ¹⁶ cm ^-3 to 1 × 10 ¹⁷ cm ^-3 .

Still preferably, in the solid-state imaging element according to the present invention, the photoelectric conversion/accumulation region is formed by a buried photodiode.

Further preferably, the solid-state imaging device according to the present invention further includes a second conductive type semiconductor layer for separating the photoelectric conversion/accumulation region from the first conductive type semiconductor substrate region, wherein the photoelectric conversion/accumulation region is formed The first conductive type semiconductor region is disposed on the second conductive type semiconductor layer, the second conductive type well region surrounding the photoelectric conversion/accumulation region in a plan view, and disposed on the photoelectric conversion/accumulation region The second conductive semiconductor pinned layer body is buried to form a buried photodiode.

Further preferably, in the solid-state imaging device according to the present invention, the first conductivity type is an n-type and the second conductivity type is a p-type, or the first conductivity type is a p-type and the second conductive The type is an n type.

Further preferably, in the solid-state imaging device according to the present invention, the retreat width of the second conductive type well region with respect to the end surface of the gate electrode toward the charge detecting region side is set to 0.45 μm (including 0.45 μm). ) within a range between 0.55 μm (including 0.55 μm).

Still preferably, in the solid-state imaging element according to the present invention, the photoelectric conversion/accumulation region includes integrally forming one of the photoelectric conversion region and a charge accumulation region, and the photoelectric conversion/accumulation region is covered in a plan view A whole light receiving area.

Further preferably, in the solid-state imaging device according to the present invention, the back-contour width of the second conductive type well region with respect to the end surface of the gate electrode toward the charge detecting region side is set such that a potential is lower than or It is equal to one of the potential barriers at which charge can be transferred during charge transfer.

The electronic information device according to the present invention uses the above-described solid-state imaging element according to the present invention for its imaging area, thereby achieving the above object.

Hereinafter, the function of the present invention having the above structure will be described.

In the solid-state imaging device according to the present invention, the second conductive type well region forming a channel region of the transfer transistor is retreated toward the charge detecting side with respect to the end face of the gate electrode on the photoelectric conversion/accumulation region side. Therefore, it is possible to prevent the charge residue originally formed in the conventional MOS image sensor, and to solve the problem of occurrence of afterimage.

Further, the end portion of the photoelectric conversion/accumulation region extends below the transfer gate electrode of the transfer transistor, and the photoelectric conversion/accumulation region overlaps the transfer gate electrode of the transfer gate. Therefore, it is possible to prevent the formation of a potential barrier in the signal charge transfer path from the photoelectric conversion/accumulation region to the charge detecting region as occurs in the conventional MOS image sensor.

Further, by setting the second conductive type well region forming the channel region of the transfer transistor to retreat toward the charge detecting side with respect to the photoelectric conversion/accumulation region, the low concentration first conductive type semiconductor region of the semiconductor substrate is formed in photoelectric conversion/accumulation Between the zone and the second conductivity type well region. With this low concentration first conductivity type semiconductor region, it is possible to reduce the overlap width of the photoelectric conversion/accumulation region and the transfer gate electrode. With this configuration, it is possible to surely prevent the charge residue originally formed in the conventional MOS image sensor shown in part (c) of Fig. 11, and it is possible to solve the cause of the occurrence of the afterimage.

Further, a second conductive type semiconductor pinning layer for separating the photoelectric conversion/accumulation region from one of the top surfaces of the semiconductor substrate is formed on the photoelectric conversion/accumulation region. Using this second conductive type semiconductor pinning layer may reduce noise.

In this case, the photoelectric conversion/accumulation region on the top surface side of the semiconductor substrate is completely covered by the second conductive type semiconductor pinning layer and the transfer gate electrode, so that the photoelectric conversion/accumulation region is not exposed to the top surface of the semiconductor substrate. . With this configuration, it is possible to suppress the problem occurring in the conventional MOS image sensor shown in Fig. 12: that is, the top surface of the photoelectric conversion/accumulation region is subjected to the dry etching step when forming the transfer gate electrode or the like The plasma damage is caused, so the energy density at the interface between the n-type semiconductor substrate and the insulating film becomes high, and in detail, a large amount of noise charges are generated, and the noise generated at the interface flows into the photoelectric conversion/accumulation. The area becomes a dark voltage component.

Further, by separating the photoelectric conversion/accumulation region from the element separation region having the interface between the semiconductor substrate and the insulating film by the second conductive type well region, the photoelectric conversion/accumulation region does not directly contact the element separation region, and may be suppressed in the semiconductor The noise generated at the interface between the substrate and the insulating film flows into the photoelectric conversion/accumulation region to become a dark voltage component.

Furthermore, by independently setting the impurity concentration of the well region of the transfer transistor and the impurity concentration of the well region forming each of the transistors of the internal circuit in the pixel, it is possible to adjust the presence of each of the transistors. Limit voltage, short channel characteristics, the size of the depletion layer of each of the channel regions, and the like. The high priority transistor required to transfer the transistor in the MOS image sensor to maximize charge transfer characteristics is to reduce the threshold voltage of the transfer transistor to approximately 0 V, and to deplete the layer when the transfer pulse is at a high level. The deeper portion of the substrate expands. The short channel feature can be achieved with a sufficiently long gate length. On the other hand, the high priority transistor features required to form internal circuitry in the pixel to meet the needs of miniaturized pixel size are to minimize the gate length to be as short as possible, in addition to ensuring short channel characteristics. Thus, it is possible to optimize each of the transistors when the high priority features of the transfer transistor and the high priority features of the transistors forming the internal circuits in the pixels are different from each other. Therefore, it is possible to implement a miniaturized solid-state imaging element with reduced image sticking.

As described above, according to the present invention, the second conductive type well region forming the channel region of the transfer transistor is formed so as to be retreated toward the charge detecting region side with respect to the end face of the gate electrode on the photoelectric conversion/accumulation region side. . Therefore, it is possible to prevent the charge residue originally formed in the conventional MOS image sensor, and to solve the problem of occurrence of afterimage.

Further, the end portion of the photoelectric conversion/accumulation region extends below the transfer gate electrode of the transfer transistor, and the photoelectric conversion/accumulation region overlaps the transfer gate electrode of the transfer gate. Therefore, it is possible to prevent the formation of a potential barrier in the signal charge transfer path from the photoelectric conversion/accumulation region to the charge detecting region as occurs in the conventional MOS image sensor.

Further, a low concentration first conductivity type semiconductor region of the semiconductor substrate is formed between the photoelectric conversion/accumulation region and the second conductivity type well region. Using the low concentration first conductivity type semiconductor region, it is possible to reduce the amount of overlapping width of the photoelectric conversion/accumulation region and the transfer gate electrode. Therefore, it is possible to more certainly prevent the charge residue formed in the conventional MOS image sensor which is originally shown in part (c) of Fig. 11, and the cause of the occurrence of the afterimage can be solved.

Further, a second conductive type semiconductor pinning layer for separating the photoelectric conversion/accumulation region from one of the top surfaces of the semiconductor substrate is formed on the photoelectric conversion/accumulation region. The noise can be reduced by the second conductive type semiconductor pinning layer.

In this case, the photoelectric conversion/accumulation region on the top surface side of the semiconductor substrate is completely covered by the second conductive type semiconductor pinning layer and the transfer gate electrode, so that the photoelectric conversion/accumulation region is not exposed at the top surface of the semiconductor substrate . Therefore, it is possible to reduce the dark voltage component in a more certain manner and obtain an image with reduced noise.

Further, by separating the photoelectric conversion/accumulation region from the element separation region having the interface between the semiconductor substrate and the insulating film by the second conductive type well region, the photoelectric conversion/accumulation region does not directly contact the element separation region, and the darkening may be reduced. The voltage component is obtained and an image with reduced noise is obtained.

Furthermore, by independently setting the impurity concentration of the well region of the transfer transistor and the impurity concentration of the well region forming each of the transistors of the internal circuits in the pixel, it is possible to not degrade the transfer characteristics of the transfer transistor. The internal circuit is miniaturized in the pixel. Therefore, it is possible to obtain a high-quality image and implement a miniaturized solid-state imaging element.

Hereinafter, Embodiments 1 to 3 of the solid-state imaging element according to the present invention applied to a MOS image sensor having a buried photodiode will be described in detail with reference to the accompanying drawings, and will be described in detail with reference to the accompanying drawings. Embodiment 4 of the electronic information machine (e.g., camera) according to the present invention uses the solid-state imaging element according to Embodiments 1 to 3 of the present invention for its imaging area. It should be noted that the solid-state imaging element according to the present invention can be applied to a CCD image sensor and a MOS image sensor.

(Example 1)

Before describing the characterization structure of the solid-state imaging device according to Embodiment 1 in detail with reference to FIGS. 2 to 6, a circuit structure of a unit pixel region according to Embodiment 1 will be described with reference to FIG. 1, in which a well of a channel region for transmitting a transistor is formed. The region is formed so as to retreat to the charge detecting side with respect to the end face of the gate electrode on the side of the photoelectric conversion/accumulation region, and also retreats to the charge detecting region side with respect to the photoelectric conversion/accumulation region.

1 is a circuit diagram showing an exemplary structure of a unit pixel region (one pixel) of a MOS image sensor 10 according to Embodiment 1 of the present invention. According to Embodiment 1, a plurality of unit pixel regions are arranged in a matrix of two tapers in the MOS image sensor 10.

As shown in FIG. 1, the unit pixel region of the MOS image sensor 10 according to Embodiment 1 includes: a buried photodiode 1 as a photoelectric conversion element for photoelectrically converting light into a signal charge and a signal a charge is accumulated therein; a transfer transistor (transfer MOS transistor) 2; an amplifying transistor 3 forming an internal circuit region in the pixel, a reset transistor 4 and a pixel selection transistor 5; an output signal line 6, It is connected to the output end of the pixel selection transistor 5; a transmission signal line 7 is connected to the control terminal of the transmission transistor 2; a reset signal line 8 is connected to the control terminal of the reset transistor 4; and a pixel A signal line 9 is selected which is connected to the control terminal of the pixel selection transistor 5.

The photodiode 1 is a buried photodiode which is a photoelectric conversion element for photoelectrically converting light into a signal charge and accumulating signal charges therein. With this configuration, it is possible to completely transfer the signal charge from the photoelectric conversion element by the transfer transistor 2, and thus it is possible to obtain a high-quality image with reduced noise.

The transfer transistor 2 transfers electrons as an example of signal charges accumulated in the photodiode 1 to the charge detection region FD side.

The amplifying transistor 3 is formed as a source follower amplifier. The amplifying transistor 3 amplifies a signal based on the amount of signal charge (signal voltage) transmitted from the transmitting transistor 2 to the charge detecting region FD side and outputs the amplified signal at a predetermined timing.

The reset transistor 4 can reset the charge detection region FD to the power supply voltage Vd at a predetermined timing.

The pixel selection transistor 5 can read the signal from the source follower amplifier to the output signal line 6 at a predetermined timing.

The output signal line 6 transmits a signal read from the amplifying transistor 3 by the pixel selecting transistor 5.

The transfer signal line 7 applies a transfer control signal to the gate electrode of the transfer transistor 2 at a predetermined timing.

The reset signal line 8 applies a reset control signal to the gate electrode of the reset transistor 4 at a predetermined timing.

The pixel selection signal line 9 applies a pixel selection control signal to the gate electrode of the pixel selection transistor 5 at a predetermined timing.

With the above configuration, first, the reset control signal applied to the gate electrode of the reset transistor 4 becomes a high level, thereby placing the reset transistor 4 in an on state. Thus, the potential at the charge detecting region FD is reset to the power source voltage Vd via the reset transistor 4.

Next, the reset control signal applied to the gate electrode of the reset transistor 4 becomes a low level, thereby placing the reset transistor 4 in an off state. The pixel selection control signal applied to the gate electrode of the pixel selection transistor 5 remains at a high level, and the pixel selection transistor 5 is in an on state. Therefore, a signal corresponding to the reset level is read from the amplifying transistor 3 to the output signal line 6 via the pixel selection transistor 5. Thus, the potential Vsig at the output signal line 6 becomes a high level.

Thereafter, the transfer control signal applied to the gate electrode of the transfer transistor 2 becomes a high level, thereby placing the transfer transistor 2 in an on state. Therefore, the signal charges accumulated in the photodiode 1 are transferred to the charge detecting region FD via the transfer transistor 2.

Next, the transfer control signal applied to the gate electrode of the transfer transistor 2 becomes a low level, thereby placing the transfer transistor 2 in an off state. Therefore, the potential at the charge detecting region FD lowers the amount of the signal charge transmitted, and the signal amplified by the amplifying transistor 3 according to the lowering potential at the charge detecting region FD is read to the output signal line via the pixel selecting transistor 5. 6.

The above operation is performed at each horizontal scanning period (1H), and thus the captured image data is obtained.

2 is a plan view showing an exemplary layout structure of a unit pixel region of the MOS image sensor 10 according to Embodiment 1. Figure 3 is a longitudinal cross-sectional view taken along line A-A' shown in Figure 2. It should be noted that the single unit pixel region 10 will be described below, while the other unit pixel regions have the same structure as the unit pixel region 10.

As shown in FIG. 2 and FIG. 3, in the MOS image sensor 10 according to Embodiment 1, for each unit pixel unit, the buried p-type semiconductor layer 12 is disposed at an n-type (low-concentration n-type: n- The predetermined depth of the top surface of the semiconductor substrate 11 (for example, about 2 μm from the top surface of the n-type semiconductor substrate 11). The n-type semiconductor region forming the photoelectric conversion/accumulation region 13 is disposed in the photodiode 1, wherein the photoelectric conversion/accumulation region 13 is formed at a top surface of the semiconductor substrate 11 as compared with the buried p-type semiconductor layer 12. The buried p-type semiconductor substrate layer 12 is divided to form a region of the photoelectric conversion/accumulation region 13 of the photodiode 1 and the underlying n-type semiconductor substrate 11.

The photoelectric conversion/accumulation region 13 includes a photoelectric conversion region and a charge accumulation region which are formed in an integrated manner. The photoelectric conversion/accumulation region 13 covers the entire light receiving region in a rectangular or square shape in plan view. A first p-type well region 14 is formed to surround the photoelectric conversion/accumulation region 13. The first p-type well region 14 separates the photoelectric conversion/accumulation region 13 from the element separation region 15. The element separation regions 15 are provided to separate the unit pixel regions 10 from each other. The element isolation region 15 forms a trench filled with an insulating material, wherein the trench is provided on the semiconductor substrate 11 by etching or the like.

Here, the impurity concentration of the n-type semiconductor substrate 11 is set to, for example, 1 × 10 ¹⁴ cm ^-3 to 1 × 10 ¹⁵ cm ^-3 (in Example 1, 1 × 10 ¹⁵ cm ^-3 ), and will be buried. The impurity concentration of the p-type semiconductor layer 12 is set to, for example, 7 × 10 ¹⁵ cm ^-3 to 2 × 10 ¹⁷ cm ^-3 (in Example 1, 8 × 10 ¹⁶ cm ^-3 ), and photoelectric conversion / The impurity concentration of the n-type semiconductor region of the accumulation region 13 is set to, for example, 1 × 10 ¹⁷ cm ^-3 to 4 × 10 ¹⁷ cm ^-3 (in Embodiment 1, 2 × 10 ¹⁷ cm ^-3 ), and The impurity concentration of a p-type well region 14 is set to, for example, 3 × 10 ¹⁶ cm ^-3 to 1 × 10 ¹⁷ cm ^-3 (in Example 1, 6 × 10 ¹⁶ cm ^-3 ).

Further, a p-type (high-concentration p-type: P+) pinning layer 16 is provided on the photoelectric conversion/accumulation region 13 on the top surface side of the n-type semiconductor substrate 11. The p-type pinning layer 16 separates the photoelectric conversion/accumulation region 13 from the top surface of the semiconductor substrate 11. The p-type pinned layer 16 is electrically connected to the buried p-type semiconductor layer 12 via the first p-type well region 14. The photoelectric conversion/accumulation region 13 is buried in the semiconductor substrate 11 while being surrounded by the p-type pinned layer 16 thereon, the first p-type well region 14 therearound, and the buried p-type semiconductor layer 12 therebelow. . In this way, the buried photodiode 1 is formed as described above. Here, the impurity concentration of the p-type pinned layer 16 is set to, for example, 1 × 10 ¹⁸ cm ^-3 .

Further, the gate electrode (transfer gate electrode) 18 of the transfer transistor 2 via the insulating film 17 made of a ruthenium oxide film; the gate electrode (reset gate electrode) 19 of the transistor 4; the gate of the amplifying transistor 3 An electrode 20 (not shown in FIG. 3); and a gate electrode 21 (not shown in FIG. 3) of the pixel selection transistor 5 are formed on the top surface of the n-type semiconductor substrate 11. For the first p-well region 14 surrounding the photoelectric conversion/accumulation region 13 in plan view, the well region below the transfer gate electrode 18 forms the channel region of the transfer transistor 2.

A second p-type well region 22 different from the first p-type well region 14 is formed in each of the gate electrode 19 of the reset transistor 4, the gate electrode 20 of the amplifying transistor 3, and the gate electrode 21 of the pixel selection transistor 5. Below one. The second p-type well region 22 forms a channel region of each of the amplifying transistor 3, the reset transistor 4, and the pixel selection transistor 5 that form an internal circuit region in the pixel. Further, the second p-type well region 22 is set so as to have an impurity concentration different from that of the first p-type well region 14 described above. The impurity concentration of each of the first p-type well region 14 and the second p-type well region 22 is independently set and controlled.

Here, the impurity concentration of the second p-type well region 22 forming the channel region of each of the amplifying transistor 3, the reset transistor 4, and the pixel selecting transistor 5 forming the internal circuit region in the pixel is set to (for example) in the range of 2 × 10 ¹⁷ cm ^-3 ± 1 × 10 ¹⁷ cm ^-3 (in Example 1, 2 × 10 ¹⁷ cm ^-3 ). The impurity concentration of the first p-type well region 14 forming the channel region of the transfer transistor 2 is set to, for example, in the range of 3 × 10 ¹⁶ cm ^-3 to 1 × 10 ¹⁷ cm ^-3 (in Embodiment 1) , 6 × 10 ¹⁶ cm ^-3 ).

An n-type semiconductor region 23 for forming the charge detecting region FD is formed on the top surface side of the n-type semiconductor substrate 11 on the first p-type well region 14 and the second p-type well region 22, wherein the n-type semiconductor region 23 is opposite The transfer gate electrode 18 is formed on the opposite side of the photoelectric conversion/accumulation region 13.

According to the MOS image sensor 10 of Embodiment 1, the tip end portion of the photoelectric conversion/accumulation region 13 overlaps the transfer gate electrode 18 in the vertical direction (in plan view), and the p-type pinned layer 16 on the charge detecting region side. The position of the end portion is aligned with the position of the end portion of the transfer gate electrode 18 of the transfer transistor 2 on the side of the photodiode 1 in plan view. Thus, the p-type pinned layer 16 is formed so as to be offset with respect to the photoelectric conversion/accumulation region 13. More specifically, the photoelectric conversion/accumulation region 13 on the top surface side of the n-type semiconductor substrate 11 is completely covered by the p-type pinned layer 16 and the transfer gate electrode 18 of the transfer transistor 2. As a result, noise can be reduced.

Further, the first p-type well region 14 under the gate electrode 18 of the transfer transistor 2 is formed so as to be retreated by a predetermined amount with respect to the photoelectric conversion/accumulation region 13 toward the charge detecting region 23 side. The back width of the first p-type well region 14 with respect to the end face of the transfer gate electrode 18 on the photoelectric conversion/accumulation region 13 side toward the charge detecting region 23 (FD) side is set such that the potential is lower than or equal to the potential barrier level. (not necessarily completely flat) so that charge can be transferred at the time of charge transfer. Further, the low concentration n-type semiconductor region 24 is disposed between the photoelectric conversion/accumulation region 13 and the first p-type well region 14. Here, the overlapping width (amount) of the photoelectric conversion/accumulation region 13 and the transfer gate electrode 18 shown by the arrow b in Fig. 3 is, for example, about 0.20 μm. The receding width of the first p-type well region 14 with respect to the end face of the transfer gate electrode 18 is, for example, about 0.24 μm as indicated by the arrow c in FIG.

Part (a) of FIG. 4 is a cross-sectional structural view of a signal charge transfer path from the photodiode 1 to the charge detecting region FD via the transfer transistor 2 in the MOS image sensor 10 according to Embodiment 1, wherein 0<b<c. Parts (b) and (c) of Fig. 4 are each a potential distribution diagram in a signal charge transfer path shown by a broken line a-a' in part (a) of Fig. 4, wherein the signal charge transfer path includes a photoelectric conversion/accumulation area 13A, a channel region under the transfer gate electrode 18 (a low concentration n-type semiconductor region 24 and a first p-type well region 14) and a charge detection region 23 (FD). Part (b) of Fig. 4 shows a potential distribution diagram when the transfer pulse Φ _TX (transfer control signal) applied to the transfer gate electrode 18 is at a low level. Part (c) of Fig. 4 shows a potential distribution diagram when the transfer pulse Φ _TX (transfer control signal) applied to the transfer gate electrode 18 is at a high level.

As shown in part (a) of FIG. 4, in the unit pixel region of the MOS image sensor 10 according to Embodiment 1, the p-type pinned layer 16 is formed such that its tip end portion is formed so as to be related to the photoelectric conversion/accumulation region 13 The tip portion is offset. The photoelectric conversion/accumulation region 13 is formed so as to extend under the transfer gate electrode 18, and the transfer gate electrode 18 is overlapped in the vertical direction (in plan view). Therefore, the formation of the potential barrier shown in part (c) of Fig. 10 is suppressed in the charge transfer path from the photoelectric conversion/accumulation region 13 to the charge detecting region 23 (FD). Further, when the photoelectric conversion/accumulation region 13 overlaps the transfer gate electrode 18, as shown in part (c) of Fig. 11, the charge residue is formed in the conventional MOS image sensor. In contrast, in the MOS image sensor 10 according to Embodiment 1, the first p-type well region 14 is formed so as to retreat toward the charge detecting region 23 (FD) side with respect to the photoelectric conversion/accumulation 13 . As a result, the low concentration n-type semiconductor region 24 of the n-type semiconductor substrate 11 is held between the photoelectric conversion/accumulation region 13 and the first p-type well region 14. Therefore, it is possible to make the overlapping width of the photoelectric conversion/accumulation region 13 and the transfer gate electrode 18 (the distance shown by the arrow b in Fig. 4) smaller than the overlap width of the conventional structure. Therefore, it is possible to avoid the formation of charge residues which occur as a conventional occurrence causing the occurrence of afterimages.

Here, in Embodiment 1, the overlapping width b of the photoelectric conversion/accumulation region 13 and the transfer gate electrode 18 and the end face of the first p-type well region 14 with respect to the transfer gate electrode 18 on the photoelectric conversion/accumulation region 13 side are set. The retreat width c toward the charge detection zone (FD) side is such that the afterimage does not appear on the captured image. The relationship between the overlap width b and the retreat width c of the first p-type well region 14 will be described with reference to FIGS. 5 and 6.

5 and 6 show the positional relationship between the occurrence of the afterimage and the photoelectric conversion/accumulation region 13 and the first p-type well region 14 (the amount of overlap between the photoelectric conversion/accumulation region 13 and the transfer gate electrode 18 (width) A diagram of the dependence of b on the relationship between the first p-type well region 14 and the back-off width c of the end face of the transfer gate electrode 18 on the side of the photoelectric conversion/accumulation region 13). The dependence is measured by the inventors of the present invention using the prototype of the MOS image sensor according to the present invention. Fig. 5 is a view showing the overlap amount b of the first p-type well region 14 when the back-off width c is fixed at 0.24 μm and the dependency of the afterimage. Fig. 6 shows a graph of the back-pitch width c of the first p-type well region 14 and the dependence of the afterimage when the overlap amount b is fixed at 0.20 μm.

In FIG. 5, the horizontal axis indicates the amount of overlap of the photoelectric conversion/accumulation region 13 and the transfer gate electrode 18 shown by the arrow b of FIG. 3, and the vertical axis indicates the measured value of the afterimage in each state (arbitrarily unit). In Fig. 5, when the amount of retreat (retraction distance) of the end face of the first p-type well region 14 shown by the arrow c in Fig. 3 with respect to the transfer gate electrode 18 on the side of the photoelectric conversion/accumulation region 13 is 0.15 μm This is indicated by a white diamond. When the back-off amount (reverse distance) is 0.24 μm, this is indicated by a black square. Herein, the criteria for determining the "measured value of the afterimage" in this case will be described. It is possible to determine whether the afterimage is present by the observer simply recognizing or not recognizing the afterimage. However, in this case, a stricter standard is used, in which after the switching mode (for example, when the mode is self-decimating to scan, the residual image may appear), then the determination of whether the observer recognizes the residual image is made (here, borrowed It is determined by the residual image upper limit specification value that the residual image does not exist).

As shown in Figure 5, the afterimage values are varied with respect to the amount of overlap shown by arrow b in Figure 3, resulting in a downward convex shape. The intermediate value reaches a minimum value. Here, when the back-off amount is 0.15 μm as indicated by the arrow c in Fig. 3, the residual image value also changes, thereby producing a downward convex shape in the pattern of Fig. 3. However, in this case, even if the value of the overlap amount b shown in FIG. 3 is changed, the lowest measured value of the afterimage is not less than or equal to the target residual upper limit specification value (when less than or equal to this value, the afterimage is not presence). In other words, the afterimage appears. When the value of the back-off amount c is shown to be 0.24 μm in Fig. 3, the value of the overlap amount b shown in Fig. 3 is in the range between 0.06 μm (including 0.06 μm) and 0.27 μm (including 0.27 μm). Therefore, the measured value of the afterimage is less than or equal to the residual image upper limit specification value. Therefore, it is possible to achieve a cross-sectional structure without image sticking (Figs. 3 and 4).

According to this result, in order to completely eliminate the afterimage from the image pickup screen, it is effective to recognize the cross-sectional structure (Figs. 3 and 4) in which the overlapping portion of the photoelectric conversion/accumulation region 13 and the transfer gate electrode 18 exists, and the low concentration n The boundary between the semiconductor region 24 and the first p-type well region 14 is retracted from the end face of the transfer gate electrode 18 on the photodiode side toward the charge detecting region 23 (FD) side with respect to the photoelectric conversion/accumulation region 13 The amount is as in the case of the MOS image sensor according to Embodiment 1.

In FIG. 6, the horizontal axis indicates the back-off width of the first p-type well region 14 shown by the arrow c of FIG. 3 with respect to the end face of the transfer gate electrode 18, and the vertical axis indicates the measurement of the afterimage in each state. Value (in arbitrary units). In Fig. 6, when the amount of overlap of the photoelectric conversion/accumulation region 13 and the transfer gate electrode 18 shown by the arrow b in Fig. 3 is 0.20 μm, this is indicated by a black square.

As shown in FIG. 6, the residual value of the back-off width of the first p-type well region 14 shown by the arrow c in FIG. 3 from the end face of the transfer gate electrode 18 is changed, thereby producing a downward convex shape. The intermediate value reaches a minimum value. Here, when the value of the overlap shown in FIG. 3 is 0.20 μm, the value of the back-pitch width c of the first p-type well region 14 shown in FIG. 3 is 0.20 μm (including 0.20 μm) and 0.40 μm (including 0.40). Within the range between μm). Therefore, the measured value of the afterimage is less than or equal to the residual image upper limit specification value. Therefore, it is possible to achieve a cross-sectional structure without image sticking.

According to this result, in order to completely eliminate the afterimage from the image pickup screen, it is recognized that the cross-sectional structure is effective in which the overlapping portion of the photoelectric conversion/accumulation region 13 and the transfer gate electrode 18 exists, and the low-concentration n-type semiconductor region 24 and the first The boundary between the p-type well regions 14 is retracted by a predetermined amount from the end face of the transfer gate electrode 18 on the photodiode side toward the charge detecting region 23 (FD) side with respect to the photoelectric conversion/accumulation region 13 as in the implementation. In the case of the MOS image sensor of Example 1.

Therefore, when the back width c of the first p-type well region 14 with respect to the end face of the transfer gate electrode toward the charge detecting region (FD) side is 0.24 μm, the overlapping width of the photoelectric conversion/accumulation region 13 and the transfer gate electrode 18 is obtained. b is set in the range between 0.06 μm (including 0.06 μm) and 0.27 μm (including 0.27 μm). In this case, the afterimage value will be less than or equal to the residual image upper limit specification value. In this case, as can be understood from Fig. 5, when the overlapping width b of the tip end portion of the photoelectric conversion/accumulation region 13 and the transfer gate electrode 18 is set to be 0.20 μm ± 0.05 μm corresponding to the minimum value of the afterimage generation In the range, the afterimage is minimized and is therefore preferred.

Similarly, when the overlapping width b of the tip end portion of the photoelectric conversion/accumulation region 13 and the transfer gate electrode 18 is 0.20 μm, the end face of the first p-type well region 14 with respect to the transfer gate electrode faces the side of the charge detecting region FD. The back width c is set to be in a range between 0.20 μm (including 0.20 μm) and 0.40 μm (including 0.40 μm). In this case, the afterimage value will be less than or equal to the residual image upper limit specification value. In this case, as can be understood from FIG. 6, when the back surface width c of the first p-type well region 14 with respect to the end face of the transfer gate electrode toward the charge detection region FD side is set to correspond to the minimum value of the afterimage generation. After the range between 0.24 μm (including 0.24 μm) and 0.30 μm (including 0.30 μm), the afterimage is minimized and is therefore preferred.

In FIG. 5, when the overlap width b and the amount of the back-pitch width c of the first p-type well region 14 are identical to each other (0.24 μm), it is possible to set the afterimage value to be less than or equal to the residual image upper limit specification value. In FIG. 6, when the overlap width b and the amount of the back-pitch width c of the first p-type well region 14 are identical to each other (0.20 μm), it is possible to set the afterimage value to be less than or equal to the afterimage limit specification value. As mentioned above, in the case of b=c or even b In the case of a, the afterimage value may be set to be less than or equal to the residual image upper limit specification value. This will be described in Embodiment 2.

(Example 2)

Embodiment 1 has been described in which the first p-type well region 14 is formed such that a predetermined amount (predetermined distance) is reversed toward the charge detecting region (FD) side with respect to the tip end portion of the photoelectric conversion/accumulation region 13, and photoelectric conversion The end portion of the accumulation region 13 extends below the transfer gate electrode 18 and overlaps the transfer gate electrode 18 in plan view. Embodiment 2 will describe a case in which the tip end portion of the photoelectric conversion/accumulation 13 contacts the interface Z of the low-concentration n-type semiconductor region 24 and the first p-type well region 14 under the transfer gate electrode 18 (in the case of b=c) ), or the tip end portion of the photoelectric conversion/accumulation region 13 extends through the interface Z with the first p-type well region 14 (in the case of b>c).

Part (a) of Fig. 7 is a cross-sectional structural view of a signal charge transfer path from the photodiode 1 to the charge detecting region FD of the transfer transistor 2 in the MOS image sensor 10A according to Embodiment 2 of the present invention. , where b c>0. Parts (b) and (c) of Fig. 7 are each a potential distribution map in a signal charge transfer path shown by a broken line a-a' in part (a) of Fig. 7, wherein the signal charge transfer path includes a photoelectric conversion/accumulation area 13A, a channel region under the transfer gate electrode 18 (first p-type well region 14) and a charge detection region 23 (FD). Part (b) of Fig. 7 shows a potential distribution diagram when the transfer pulse Φ _TX (transfer control signal) applied to the transfer gate electrode 18 is at a low level. Part (c) of Fig. 7 shows a potential distribution diagram when the transfer pulse Φ _TX (transfer control signal) applied to the transfer gate electrode 18 is at a high level.

As shown in part (a) of Fig. 7, in the unit pixel region of the MOS image sensor 10A according to Embodiment 2, the p-type pinned layer 16 is formed such that its tip end portion is formed so as to be at the tip of the photoelectric conversion/accumulation region 13A. Partial offset. The photoelectric conversion/accumulation region 13A is formed so as to extend below the transfer gate electrode 18 and overlap the transfer gate electrode 18 in the vertical direction (in plan view). Therefore, the formation of the potential barrier shown in part (c) of Fig. 10 is suppressed in the charge transfer path from the photoelectric conversion/accumulation region 13A to the charge detecting region 23 (FD). Further, when the tip end portion of the photoelectric conversion/accumulation region 13A overlaps the transfer gate electrode 18, as shown in part (c) of Fig. 11, the charge residue is formed in the conventional MOS image sensor. In the MOS image sensor 10A according to Embodiment 2, the interface Z of the first p-type well region 14 is formed such that the end face of the transfer gate electrode 18 on the side of the photoelectric conversion/accumulation region faces the charge detecting region 23 (FD) The side is backed by a predetermined amount (predetermined distance). Further, the tip end portion of the photoelectric conversion/accumulation 13A contacts the interface Z of the first p-type well region 14 below the transfer gate electrode 18 (in the case of b=c), or the tip end portion of the photoelectric conversion/accumulation region 13A extends. The interface Z with the first p-type well region 14 (extending into the first p-well region 14) (in the case of b>c). As a result, unlike the case of Embodiment 1, the low-concentration n-type semiconductor region 24 of the n-type semiconductor substrate 11 is not present between the photoelectric conversion/accumulation region 13A and the first p-type well region 14.

In this case, as shown in FIG. 5, when the back surface width of the first p-type well region 14 with respect to the transfer gate electrode toward the charge detection region (FD) side is 0.24 μm, the photoelectric conversion/accumulation region is The overlap width b of 13A and the transfer gate electrode 18 is set to be in a range between 0.24 μm (including 0.24 μm) and 0.27 μm (including 0.27 μm). In this case, the afterimage value will be less than or equal to the residual image upper limit specification value.

Similarly, when the overlapping width b of the tip end portion of the photoelectric conversion/accumulation region 13A and the transfer gate electrode 18 is 0.20 μm, the end face of the first p-type well region 14 with respect to the transfer gate electrode faces the side of the charge detecting region FD. The back width c is set to 0.20 μm. In this case, the afterimage value will be less than or equal to the residual image upper limit specification value. Therefore, it is possible to avoid the formation of charge residues which occur as a conventionally occurring cause of the afterimage.

As described above, according to Embodiments 1 and 2, the photoelectric conversion/accumulation region 13 or 13A is formed so as to have an overlapping portion with the transfer gate electrode 18, and the p-type pinned layer 16 is formed so as to be related to the MOS image sensor 10 or 10A The photoelectric conversion/accumulation area 13 or 13A in the unit pixel area is shifted. Therefore, formation of a potential barrier in the charge transfer path from the photoelectric conversion/accumulation region 13 or 13A to the charge detecting region 23 (FD) may be suppressed. Further, an interface of the first p-type well region 14 forming the channel region of the transfer transistor (MOS transistor) 2 is formed so as to face the charge detecting region 23 with respect to the end face of the transfer gate electrode 18 on the photoelectric conversion/accumulation region side. (FD) Backward predetermined value. As a result, it is possible to avoid the formation of charge residues that cause the occurrence of afterimages. Therefore, it is possible to completely transfer the signal charge from the photodiode 1 to the charge detecting region FD, and thus it is possible to obtain a high-quality image having significantly suppressed noise and afterimage.

In FIG. 5, in the case where the back end width of the first p-type well region 14 with respect to the transfer gate electrode toward the charge detection region FD side is 0.24 μm, it is impossible to place the afterimage value less than or equal to the residual. The upper limit specification value is changed even if the overlapping width b of the tip end portion of the photoelectric conversion/accumulation region 13 and the transfer gate electrode 18 is changed to be less than or equal to zero. On the other hand, in the case where the back-pitch width c of the first p-type well region 14 with respect to the end face of the transfer gate electrode toward the charge detecting region FD side significantly exceeds 0.2 μm, the image sticking or suppression may be eliminated to some extent. Even if the overlap width b of the tip end portion of the photoelectric conversion/accumulation region 13 and the transfer gate electrode 18 is "0" or a negative value as shown in FIG. 8 (in the case of b < 0; when the electric conversion/accumulation region 13 is The tip portion does not overlap the transfer gate electrode 18). This will be described in Embodiment 3.

(Example 3)

Part (a) of Fig. 8 is a cross-sectional structural view of a signal charge transfer path from the photodiode 1 to the charge detecting region FD of the transfer transistor 2 in the MOS image sensor 10B according to Embodiment 3 of the present invention. , where b<0. Parts (b) and (c) of Fig. 8 are each a potential distribution map in a signal charge transfer path shown by a broken line a-a' in part (a) of Fig. 8, wherein the signal charge transfer path includes a photoelectric conversion/accumulation area 13B, the channel region under the gate electrode 18 and the charge detection region 23 (FD). Part (b) of Fig. 8 shows a potential distribution diagram when the transfer pulse Φ _TX (transfer control signal) applied to the transfer gate electrode 18 is at a low level. Part (c) of Fig. 8 shows a potential distribution diagram when the transfer pulse Φ _TX (transfer control signal) applied to the transfer gate electrode 18 is at a high level.

As shown in part (a) of FIG. 8, in the unit pixel region of the MOS image sensor 10B according to Embodiment 3, the interface Z of the first p-type well region 14 is required to be opposite to the transfer gate on the photoelectric conversion/accumulation area side. The end face of the electrode 18 remarkably recedes (over 0.24 μm) toward the charge detecting region 23 (FD) side. In this case, the back-pitch width c of the first p-type well region 14 is set within a range between 0.45 μm (including 0.45 μm) and 0.55 μm (including 0.55 μm; the width of the electrode) to suppress image sticking, or It is set to a range between 0.50 μm (including 0.50 μm) and 0.55 μm (including 0.55 μm; width of the electrode) (in this case, the width of the transfer gate electrode 18 is greater than or equal to 0.55 μm) to eliminate the afterimage . Further, in this case, the tip end portion of the p-type pinning layer 16 is formed so as to be displaced with respect to the tip end portion of the photoelectric conversion/accumulation region 13B so that the tip end portion of the p-type pinning layer 16 is positioned on the side of the pinning layer The end faces of the transfer gate electrodes 18 are aligned so that the tip end portion of the photoelectric conversion/accumulation region 13B does not extend under the transfer gate electrode 18 (the tip end portion of the photoelectric conversion/accumulation region 13B does not overlap the transfer gate electrode in the vertical direction) 18) (in plan view), and forming the tip end portion of the photoelectric conversion/accumulation region 13B so as to retreat toward the pinned layer side with respect to the end face of the transfer gate electrode 18 on the pinned layer side (in the case where the overlap width is b<0) ). Therefore, the low-concentration n-type semiconductor region 24 of the n-type semiconductor substrate 11 exists between the photoelectric conversion/accumulation region 13B and the first p-type well region 14, wherein the low-concentration n-type semiconductor region 24 is larger than in the case of the first embodiment Low concentration n-type semiconductor region. Further, in this case, as shown in part (c) of Fig. 8, in the charge transfer path from the photoelectric conversion/accumulation region 13B to the charge detecting region 23 (FD), the potential barrier is as shown in part (c) of Fig. 10. Display formation. However, this potential barrier can be easily suppressed by signal charge and may somehow eliminate or suppress image sticking without forming the conventional MOS image sensor that is shown in part (c) of Figure 11 Residual charge.

As described above, in the unit pixel region of the MOS image sensor 10B according to Embodiment 3, the photoelectric conversion/accumulation region 13B does not overlap the transfer gate electrode 18, and forms the first p-type well of the channel region of the transfer transistor 2. The interface Z of the region 14 is formed so as to retreat by more than or equal to 0.45 μm toward the charge detecting region 23 (FD) with respect to the end face of the transfer gate electrode 18 on the side of the photoelectric conversion/accumulation region. As a result, it is possible to avoid the formation of charge residues that cause the occurrence of afterimages. Therefore, it is possible to completely transfer the signal charge from the photodiode 1 to the charge detecting region FD, and thus it is possible to obtain a high-quality image having significantly suppressed noise and afterimage.

Further, according to Embodiments 1 to 3, in the MOS image sensor 10, 10A or 10B, the photoelectric conversion/accumulation region 13, 13A or 13B and the element separation region 15 are separated by the first p-type well region 14. Therefore, it is possible to prevent the noise charge generated at the interface between the semiconductor substrate 11 and the insulating film 17 made of the ruthenium oxide film from flowing into the photoelectric conversion/accumulation region 13, 13A or 13B to become a dark voltage component.

Further, according to the MOS image sensor 10, 10A or 10B, the position of the end portion of the p-type pinning layer 16 is aligned with the position of the end portion of the transfer gate electrode 18 on the photodiode side, and thus the photoelectric conversion/accumulation region 13, 13A or 13B is not exposed at the top surface of the n-type semiconductor substrate 11. The top surface of the photoelectric conversion/accumulation region 13 is damaged by the plasma of the dry etching step or the like at the time of forming the transfer gate electrode, and thus the energy density at the interface between the n-type semiconductor substrate 11 and the insulating film 17 Become higher. Therefore, in detail, a large amount of noise charge is generated. However, by preventing the photoelectric conversion/accumulation region 13 from being exposed to the top surface of the n-type semiconductor substrate 11, the noise charge for becoming a dark voltage component does not flow into the photoelectric conversion/accumulation region 13, 13A or 13B.

In addition, according to the MOS image sensor 10, 10A or 10B, the impurity concentration of the first p-type well region 14 of the transfer transistor 2 may be different from the reset transistor 4, the amplifying transistor 3 and the internal circuit region forming the pixel. The impurity concentration of the second p-type well region 22 in each of the pixel selection transistors 5 is selected. Therefore, it is possible to implement miniaturization of internal circuits in the pixel without degrading the transfer characteristics of the transfer transistor 2.

(Example 4)

FIG. 9 is a block diagram showing an exemplary schematic configuration of an electronic information machine 70 according to Embodiment 4 of the present invention, which uses a MOS image sensor as a solid-state image pickup element including a unit pixel region according to Embodiment 1 of the present invention. In its camera area.

In FIG. 9, the electronic information machine 70 according to Embodiment 4 includes: a solid-state imaging device 30 for driving a MOS image including the unit pixel region according to Embodiment 1 (or the unit pixel region according to Embodiment 2 or 3) The sensor 10 (or 10A, 10B) to obtain an image pickup signal, and performs predetermined signal processing on the image pickup signal to obtain a high quality image signal; a memory area 40 (for example, a recording medium) for recording a video signal, the image The signal is obtained by performing predetermined signal processing on the high quality image signal from the solid-state imaging device 30 after performing predetermined signal processing for recording on the high quality image signal; a display area 50 (for example, a liquid crystal display device) for Displaying a high quality image signal on a display screen (eg, a liquid crystal display screen) after performing predetermined signal processing for display on the high quality image signal from the solid state imaging device 30; and a communication area 60 (eg, a transmission and receiver) ) for communicating high quality video signals after performing predetermined signal processing for communication on high quality video signals from the solid-state imaging device 30 .

Any of the following can be considered as an electronic information device 70: a digital camera (eg, a digital video camera, a digital still camera), an image input camera (eg, a surveillance camera, a door intercom camera, an in-vehicle camera, and Cameras for videophones) and video input machines (eg scanners, faxes and mobile phone cameras with cameras).

As described above, according to Embodiment 4, based on the high-quality image signal from the solid-state imaging device 30 having reduced noise without image sticking, it is possible to perform various data processing in an excellent manner, such as in an excellent manner. High-quality image signals are displayed on the display screen, which prints high-quality image signals on paper in an excellent way, and communicates high-quality image signals as communication materials in a wired or wireless manner in an excellent way, and performs high-quality image signals. The compression process is predetermined and stored in the memory area 40.

In addition to the electronic information machine 70 listed by Embodiment 4, the electronic information machine according to the present invention may further include a high quality image signal for printing (printing output) and outputting (printing output) from the solid-state imaging device 30. Image output area. The electronic information machine according to the present invention may include at least one of a memory area 40, a display area 50, a communication area 60, and an image output area in addition to the solid-state imaging device 30.

Further, in Embodiments 1 to 4, electrons were used as signal charges, and the first conductivity type was n-type, and the second conductivity type was p-type. However, in the present invention, in fact, the polarities of the photodiode, the MOS transistor, each of the impurity layers, the driving voltage, and the like can be reversed, and the holes can be used as signal charges.

Further, as the structure of the unit pixel region, each of the first to fourth embodiments uses a circuit configuration including the transfer transistor 2, the reset transistor 4, the amplification transistor 3, and the pixel selection transistor 5 in addition to the photodiode 1. Alternatively, a structure including an amplifying transistor 3 for amplifying a signal obtained by conversion at the photodiode 1 and a resetting transistor 4 for resetting the signal can be used for an internal circuit in a pixel. Therefore, other transistors such as the pixel selection transistor 5 can be used as necessary.

As described above, the present invention is exemplified by using the preferred embodiments 1 to 4. However, the present invention should not be construed solely based on the above-described embodiments 1 to 4. It should be understood that the scope of the invention should be construed solely on the basis of the scope of the patent application. It is also understood that those skilled in the art can implement the equivalent technical scope based on the description of the present invention and the common knowledge from the description of the detailed preferred embodiments 1 to 4 of the present invention. In addition, it is to be understood that any patents, any patent applications, and any references cited in this specification are hereby incorporated by reference in their entirety in their entirety in the same extent

Industrial applicability

According to the present invention, in the field of: a solid-state imaging device comprising a semiconductor element for performing photoelectric conversion of image light from an object and capturing an image of the object, in detail, a solid driven by a low voltage An imaging device (for example, a MOS image sensor); and an electronic information device using a solid-state imaging device as an image input device for the imaging area thereof (for example, a digital camera (digital video camera, digital still camera), and a plurality of image input cameras) , a scanner, a fax, a camera-equipped mobile phone machine, and the like), a second conductive well region forming a passage region of the transfer transistor is formed so as to face the charge detection with respect to the end face of the gate electrode on the photoelectric conversion/accumulation side The side of the survey area is back. Therefore, it is possible to prevent the charge residue originally formed in the conventional MOS image sensor, and to solve the problem of occurrence of afterimage.

Further, the end portion of the photoelectric conversion/accumulation region extends below the transfer gate electrode of the transfer transistor, and the photoelectric conversion/accumulation region overlaps the transfer gate electrode of the transfer gate. Therefore, it is possible to prevent the formation of a potential barrier in the signal charge transfer path from the photoelectric conversion/accumulation region to the charge detecting region as occurs in the conventional MOS image sensor.

Further, a low concentration first conductivity type semiconductor region of the semiconductor substrate is formed between the photoelectric conversion/accumulation region and the second conductivity type well region. Using the low concentration first conductivity type semiconductor region, it is possible to reduce the amount of overlapping width of the photoelectric conversion/accumulation region and the transfer gate electrode. Therefore, it is possible to more surely prevent the occurrence of charge residuals originally formed in the conventional MOS image sensor shown in part (c) of Fig. 11, and to solve the cause of the occurrence of afterimage.

Further, a second conductive type semiconductor pinning layer for separating the photoelectric conversion/accumulation region from the top surface of the semiconductor substrate is formed on the photoelectric conversion/accumulation region. The noise can be reduced using the second conductive type semiconductor pinning layer.

In this case, the photoelectric conversion/accumulation region on the top surface side of the semiconductor substrate is completely covered by the second conductive type semiconductor pinning layer and the transfer gate electrode, so that the photoelectric conversion/accumulation region is not exposed at the top surface of the semiconductor substrate . Therefore, it is possible to reduce the dark voltage component in a more certain manner and obtain an image with reduced noise.

Further, by separating the photoelectric conversion/accumulation region from the element separation region having the interface between the semiconductor substrate and the insulating film by the second conductive type well region, the photoelectric conversion/accumulation region does not directly contact the element separation region, and the darkening may be reduced. The voltage component is obtained and an image with reduced noise is obtained.

Furthermore, by independently setting the impurity concentration of the well region of the transfer transistor and the impurity concentration of the well region forming each of the transistors of the internal circuits in the pixel, it is possible to not degrade the transfer characteristics of the transfer transistor. The internal circuit is miniaturized in the pixel. Therefore, it is possible to obtain a high-quality image and implement a miniaturized solid-state imaging element.

1‧‧‧buried photodiode

2‧‧‧Transfer transistor

3‧‧‧Amplifying the transistor

4‧‧‧Reset the transistor

5‧‧‧Pixel selection transistor

6‧‧‧Output signal line

7‧‧‧Transmission signal line

8‧‧‧Reset signal line

9‧‧‧Pixel selection signal line

10, 10A, 10B‧‧‧ MOS image sensor

11‧‧‧Semiconductor substrate (semiconductor substrate area)

12‧‧‧ buried semiconductor layer

13, 13A, 13B‧‧‧ photoelectric conversion / accumulation area

14‧‧‧First semiconductor well area

15‧‧‧Component separation area

16‧‧‧ pinned layer

17‧‧‧Insulation film

18‧‧‧Transfer gate electrode

19‧‧‧Resetting the gate electrode of the transistor

20‧‧‧Amplifying the gate electrode of the transistor

21‧‧‧Pixel selection transistor gate electrode

twenty two. . . Second semiconductor well region

twenty three. . . Charge detection zone

twenty four. . . Low concentration semiconductor region

30. . . Solid state camera

40. . . Memory area

50. . . Display area

60. . . Communication area

70. . . Electronic information machine

1 is a circuit diagram showing an exemplary structure of a unit pixel region (one pixel) of a MOS image sensor according to Embodiment 1 of the present invention.

2 is a plan view showing an exemplary layout structure of a unit pixel region of a MOS image sensor according to Embodiment 1 of the present invention.

Figure 3 is a longitudinal cross-sectional view taken along line A-A' shown in Figure 2.

Part (a) of FIG. 4 is a cross-sectional structural view of a signal charge transfer path from a photodiode to a charge detecting region of a transfer transistor in a MOS image sensor according to Embodiment 1 of the present invention; Part (b) is a potential distribution diagram in the signal charge transfer path shown by a broken line a-a' in part (a) of Fig. 4 when the transfer pulse Φ _TX (transfer control signal) applied to the transfer gate electrode is at a low level. Part (c) of Fig. 4 is a signal charge transfer path shown by a broken line a-a' in part (a) of Fig. 4 when the transfer pulse Φ _TX (transfer control signal) applied to the transfer gate electrode is at a high level Potential distribution map.

Fig. 5 is a graph showing the dependence of the occurrence of afterimage on the positional relationship between the photoelectric conversion/accumulation region and the p-type well region.

Fig. 6 is a graph showing the dependence of the occurrence of afterimage on the positional relationship between the photoelectric conversion/accumulation region and the p-type well region.

Part (a) of FIG. 7 is a cross-sectional structural view of a signal charge transfer path from a photodiode to a charge detecting region of a transfer transistor in a MOS image sensor according to Embodiment 2 of the present invention; Part (b) is a potential distribution diagram in the signal charge transfer path shown by a broken line a-a' in part (a) of Fig. 7 when the transfer pulse Φ _TX (transfer control signal) applied to the transfer gate electrode is at a low level. Part (c) of Fig. 7 is a signal charge transfer path shown by a broken line a-a' in part (a) of Fig. 7 when the transfer pulse Φ _TX (transfer control signal) applied to the transfer gate electrode is at a high level Potential distribution map.

Part (a) of FIG. 8 is a cross-sectional structural view of a signal charge transfer path from a photodiode to a charge detecting region of a transfer transistor in a MOS image sensor according to Embodiment 3 of the present invention; Part (b) is a potential distribution diagram in the signal charge transfer path shown by a broken line a-a' in part (a) of Fig. 8 when the transfer pulse Φ _TX (transfer control signal) applied to the transfer gate electrode is at a low level. Part (c) of Fig. 8 is a signal charge transfer path shown by a broken line a-a' in part (a) of Fig. 8 when the transfer pulse Φ _TX (transfer control signal) applied to the transfer gate electrode is at a high level Potential distribution map.

9 is a block diagram showing an exemplary schematic configuration of an electronic information machine according to Embodiment 4 of the present invention, which uses a MOS image sensor as a solid-state image pickup element including a unit pixel region according to Embodiment 1 of the present invention.

Part (a) of FIG. 10 is a cross-sectional structural view of a unit pixel region (one pixel) of a conventional MOS image sensor; part (b) of FIG. 10 is when the transfer pulse Φ _TX applied to the transfer gate electrode is at a low level The potential distribution map in the signal charge transfer path shown by the broken line a-a' in part (a) of Fig. 10; part (c) of Fig. 10 is when the transfer pulse Φ _TX applied to the transfer gate electrode is at a high level The potential distribution map in the signal charge transfer path shown by the broken line a-a' in part (a) of Fig. 10.

Part (a) of FIG. 11 is a cross-sectional structural view of a unit pixel region (one pixel) of the MOS image sensor, and the MOS image sensor is an example of a conventional solid-state imaging device disclosed in Reference 1; b) a potential distribution map in the signal charge transfer path shown by a broken line a-a' in part (a) of Fig. 11 when the transfer pulse Φ _TX applied to the transfer gate electrode is at a low level; part of Fig. 11 (c) The potential distribution map in the signal charge transfer path shown by the broken line a-a' in the portion (a) of Fig. 11 when the transfer pulse Φ _TX applied to the transfer gate electrode is at the high level.

Part (a) of FIG. 12 is a cross-sectional structural view of a unit pixel region (one pixel) of the MOS image sensor, and the MOS image sensor is another example of a conventional solid-state imaging device; part (b) of FIG. 12 is The transfer pattern Φ _TX applied to the transfer gate electrode is at a low level, and the potential distribution pattern in the signal charge transfer path shown by a broken line a-a' in part (a) of Fig. 12; part (c) of Fig. 12 is when applied The potential distribution map in the signal charge transfer path shown by the broken line a-a' in the portion (a) of Fig. 12 at the high level of the transfer pulse Φ _TX to the transfer gate electrode.

1. . . Buried photodiode

2. . . Transfer transistor

3. . . Amplifying the transistor

4. . . Reset transistor

5. . . Pixel selection transistor

6. . . Output signal line

7. . . Transmission signal line

8. . . Reset signal line

9. . . Pixel selection signal line

10, 10A, 10B. . . MOS image sensor

Claims (29)

A solid-state imaging device includes a plurality of unit pixel regions disposed on a semiconductor substrate, wherein each of the plurality of unit pixel regions includes: a first conductivity type semiconductor region that forms a photoelectric conversion/accumulation region For photoelectrically converting light into signal charge and accumulating the signal charge therein; a second conductive type semiconductor pinning layer for separating the photoelectric conversion/accumulation region and one of the semiconductor substrates a second conductive well region forming a channel region of the transfer transistor, capable of transmitting the signal charge from the photoelectric conversion/accumulation region to a charge detection region; and a gate electrode of the transfer transistor The second conductive type well region is formed to retreat toward the charge detecting region side with respect to an end surface of the gate electrode on the photoelectric conversion/accumulation region side; wherein a low concentration first conductive type semiconductor region is disposed Between the first conductive type semiconductor region forming the photoelectric conversion/accumulation region and the second conductive type well region forming the channel region, and the low concentration first conductive A semiconductor region having the first conductivity type is lower than the impurity concentration of the semiconductor region impurity concentration; wherein the low-concentration semiconductor region of a first conductivity type extends a predetermined distance greater than zero to below the gate electrode of, to obtain A residual value that is less than the specification value. The solid-state imaging device of claim 1, wherein the second conductive type well region is formed to retreat toward the charge detecting region side with respect to the photoelectric conversion/accumulation region. The solid-state imaging device of claim 1, wherein a tip end portion of the photoelectric conversion/accumulation region contacts the second conductive type well region under the gate electrode, or the tip end portion of the photoelectric conversion/accumulation region is located at the second conductive region In the well area. The solid-state imaging device according to any one of claims 1 to 3, wherein one end portion of the photoelectric conversion/accumulation region is located under the gate electrode, and the end portion of the photoelectric conversion/accumulation region overlaps in a plan view Gate electrode. The solid-state imaging device of claim 4, wherein an overlap width of the photoelectric conversion/accumulation region and the gate electrode is set in a plan view and the second conductive type well region faces the charge detector with respect to the end face of the gate electrode The back width of the measurement area side so that the afterimage does not appear on the captured image. The solid-state imaging device of claim 4, wherein the photoelectric conversion/accumulation region and the gate are when the second conductivity type well region has a back-off width of 0.24 μm with respect to the charge detection region side of the gate electrode The overlap width of the electrodes was set in a range between 0.06 μm (including 0.06 μm) and 0.27 μm (including 0.27 μm). The solid-state imaging device of claim 6, wherein the overlap width of the photoelectric conversion/accumulation region and the gate electrode is set to be in a range of 0.20 μm ± 0.05 μm. The solid-state imaging device of claim 4, wherein the photoelectric conversion/accumulation region When the overlap width with the gate electrode is 0.20 μm, the back-contour width of the second conductive type well region with respect to the gate electrode toward the charge detecting region side is set to 0.20 μm (including 0.20 μm) and 0.40 μm. Within the range (including 0.40 μm). The solid-state imaging device of claim 8, wherein the second conductive type well region is set to 0.24 μm (including 0.24 μm) and 0.30 μm with respect to the back width of the end surface of the gate electrode facing the charge detecting region side. Includes a range between 0.30 μm). A solid-state imaging device according to claim 1, wherein the second conductive type semiconductor pinning layer is formed to be offset with respect to the photoelectric conversion/accumulation region. The solid-state imaging device of claim 1 or 10, wherein the photoelectric conversion/accumulation region on the top side of the semiconductor substrate is completely covered by the second conductive type semiconductor pinning layer and the gate electrode. The solid-state imaging device of claim 1 or 10, wherein a position of one end portion of the second conductive type semiconductor pinning layer on the charge detecting region side and one end of the gate electrode on the photoelectric conversion/accumulation region One of the parts is aligned. The solid-state imaging device of claim 1, wherein the low-concentration first-conductivity-type semiconductor region is a first-conductivity-type semiconductor substrate region. A solid-state imaging device according to claim 1, wherein an impurity concentration of one of the first conductive type semiconductor regions forming the photoelectric conversion/accumulation region is set to 1 × 10 ¹⁷ cm ^-3 (including 1 × 10 ¹⁷ cm ^-3 ) to Within the range between 4 × 10 ¹⁷ cm ^-3 (including 4 × 10 ¹⁷ cm ^-3 ). The solid-state imaging device of claim 1, wherein an impurity concentration of one of the low-concentration first-conductivity-type semiconductor regions is set to 1 × 10 ¹⁴ cm ^-3 (including 1 × 10 ¹⁴ cm ^-3 ) to 1 × 10 ¹⁵ cm ^{- 3} (including 1 × 10 ¹⁵ cm ^-3 ) in the range between. The solid-state imaging device of claim 1, wherein the photoelectric conversion/accumulation region is covered by the same region as the second conductive type well region forming the channel region such that the photoelectric conversion/accumulation region is not in contact with each other in plan view An element separation area for separating unit pixel regions from each other. The solid-state imaging device of claim 1, wherein the plurality of unit pixel regions are configured as a matrix. The solid-state imaging device of claim 1 or 17, wherein each of the plurality of unit pixel regions includes the lower one as an internal circuit region of a pixel: an amplifying transistor for transmitting power according to the one The crystal reads the signal voltage to the charge detection region, amplifies a signal and outputs the amplified signal, and resets the transistor to reset the voltage of one of the charge detection regions to a predetermined voltage. The solid-state imaging device of claim 18, further comprising: a pixel selection transistor capable of reading the signal from the amplifying transistor to an output signal line as the internal circuit region in a pixel. The solid-state imaging device of claim 18, wherein an impurity concentration of a second conductivity type well region of a channel region of each of the transistors forming the internal circuit region of a pixel and forming the transmission transistor The second conductivity type well region of the channel region has a different impurity concentration. The solid-state imaging device of claim 18, wherein an impurity concentration of a second conductivity type well region of a channel region of each of the transistors forming the internal circuit region of a pixel and forming the transmission transistor The impurity concentration of the second conductive well region in the channel region is independently set and controlled. The solid-state imaging device of claim 18, wherein an impurity concentration of the second conductivity type well region of one of the transistors forming one of the transistors in the internal circuit region of the pixel is set to 2 × 10 ^{In the range of 17} cm ^-3 ± 1 × 10 ¹⁷ cm ^-3 , the impurity concentration of the second conductivity type well region forming the channel region of the transfer transistor is set to 3 × 10 ¹⁶ cm ^-3 to 1 × Within the range of 10 ¹⁷ cm ^-3 . The solid-state imaging device according to any one of claims 1 to 3, wherein the photoelectric conversion/accumulation region is formed by a buried photodiode. The solid-state imaging device according to any one of claims 1 to 3, further comprising a second conductive type semiconductor layer for separating the photoelectric conversion/accumulation region from the first conductive type semiconductor substrate region, wherein the photoelectric conversion is formed/ The first conductive type semiconductor region of the accumulation region is provided by the second conductive type semiconductor layer, the second conductive type well region disposed around the photoelectric conversion/accumulation region in plan view, and disposed on the photoelectric conversion/accumulation The second conductive semiconductor pinned layer on the region is buried to form a buried photodiode. The solid-state imaging device of claim 1, wherein the first conductivity type is an n-type and the second conductivity type is a p-type, or the first conductivity type is a p-type and the The second conductivity type is an n-type. The solid-state imaging device of claim 1, wherein the second conductive type well region has a back-off width of the end face of the second electrode facing the charge detecting region side of 0.45 μm (including 0.45 μm) and 0.55 μm (including Within the range between 0.55 μm). The solid-state imaging device of claim 1, wherein the photoelectric conversion/accumulation region comprises one of a photoelectric conversion region and a charge accumulation region formed integrally, and the photoelectric conversion/accumulation region covers an entire light-receiving region in a plan view. The solid-state imaging device of claim 1, wherein a back-off width of the second conductive type well region with respect to the gate electrode toward the charge detecting region side is set such that a potential is lower than or equal to that at the time of charge transfer One of the potential barriers of the charge transferable. An electronic information machine using the solid-state imaging device of claim 1 for an imaging area thereof.