JP5319965B2 - Amplification type solid-state imaging device and electronic information device - Google Patents

Description

  The present invention relates to an amplification type solid-state imaging device having a readout circuit that amplifies each signal charge from a plurality of light receiving elements (photoelectric conversion elements) that photoelectrically convert image light from a subject and captures it as pixel data. And, for example, a digital camera such as a digital video camera and a digital still camera, an image input camera, a scanner device, a facsimile device, a camera-equipped mobile phone device, etc. using the amplification type solid-state imaging device as an image input device in an imaging unit Relates to electronic information equipment.

  As a conventional amplifying solid-state imaging device, there has been proposed an amplifying solid-state imaging device having a pixel portion having an amplifying function and a scanning circuit around the pixel portion and reading out pixel data by the scanning circuit. .

  In particular, there is known an APS (Active PIXEL Sensor) type image sensor constituted by CMOS (Complementary Metal Oxide Semiconductor) which is advantageous for integrating a pixel configuration with a peripheral driving circuit and a signal processing circuit. High sensitivity, single power supply drive and low power consumption.

  However, with the reduction in the size of the pixel portion, a phenomenon such as so-called color mixing or crosstalk, in which signal charges photoelectrically converted inside the substrate leak to the adjacent pixel portion, is a serious problem.

  In order to solve this problem, Patent Document 1 discloses an invention in which a semiconductor substrate is changed from a P-type substrate to an N-type substrate. This N-type substrate configuration is shown in FIGS.

  FIG. 14 is a horizontal longitudinal sectional view illustrating an example of a main part configuration of a pixel portion in a solid-state imaging device having a conventional N-type substrate configuration disclosed in Patent Document 1. In FIG. FIG. 15 is a vertical cross-sectional view in the vertical direction showing a configuration example of a main part of a pixel unit in a conventional solid-state imaging device having an N-type substrate configuration disclosed in Patent Document 1. 14 may be a vertical cross section in the vertical direction, and FIG. 15 may be a vertical cross section in the horizontal direction.

  14 and 15, in the solid-state imaging device 100 having the conventional N-type substrate configuration, the N-type embedded photodiode 101 includes a P-type surface high-concentration diffusion layer 102 on the surface side for reducing dark current, It is surrounded by a low concentration P-well 104 on the N-type substrate 103 side.

  The reason why the P-well 104 has a low concentration is to increase the sensitivity by expanding the depletion layer region between the N type buried photodiode 101 and the P-well 104. The signal charge photoelectrically converted by the embedded photodiode 101 is completely transferred to the charge storage unit 106 (floating diffusion FD) through the semiconductor layer under the gate 105a of the transfer transistor 105 during the read operation, and connected to the source. An imaging signal is output from an amplifier (not shown) such as a follower circuit.

  After the imaging signal is output, the charge accumulation unit 106 (floating diffusion FD) is reset to the power supply voltage (Vdd) from the drain region 108 to which the power supply voltage (Vdd) is applied, through the semiconductor region under the gate 107a of the reset transistor 107. The Each transistor is isolated by an element isolation oxide film STI. However, the element isolation oxide film STI is not particularly required between the photodiodes 101, and an element isolation layer such as a P-type reverse injection layer is sufficient. It is. These gates 105a and 107a are provided via a surface oxide film 109 on the substrate surface.

  Below the P-well 104 is an N-type N-type substrate 103. This is mainly because N-type substrate 103 is made N-type in order to prevent signal charges obtained by photoelectrically converting long-wavelength light inside the substrate from leaking into the adjacent pixel portion (photodiode 101). The purpose is to sweep out photoelectric charges to the substrate 103 side and prevent leakage of signal charges to the adjacent pixel portion (crosstalk).

  However, the following problem occurs in the conventional example. That is, the signal charge photoelectrically converted inside the N-type substrate 103 is swept out to the N-type substrate 103, but the signal charge photoelectrically converted by the light of the medium and long wavelength with the light incident inside the P-well 104. However, it cannot be completely prevented from diffusing inside the P-well 104 as a minority carrier and leaking to the adjacent pixel portion, and color mixing and crosstalk cannot be avoided.

  This is because leakage into the adjacent pixel portion is more noticeable particularly in the vertical direction where the distance from the photodiode 101 is shorter than in the horizontal direction. When the P-well 104 is made high in concentration, the diffusion distance of minority carriers is shortened, but the depletion layer region is narrowed as a side effect, and a decrease in light receiving sensitivity is inevitable.

  In order to solve this problem, Patent Document 2 discloses a method of separating a P-well by a semiconductor layer of an N-type substrate for each unit pixel portion.

  FIG. 16 is a vertical cross-sectional view in the vertical direction showing a configuration example of a main part of a pixel portion in a solid-state imaging device having a conventional N-type substrate configuration disclosed in Patent Document 2.

In FIG. 16, in a solid-state imaging device 200 having a conventional N-type substrate configuration, an N-type embedded photodiode 201 includes a P-type surface high-concentration diffusion layer 202 on the surface side for reducing dark current, and an N-type substrate. It is surrounded by a low concentration P-well 204 on the 203 side. For each unit pixel portion, a P-well 204 is separated by an N semiconductor layer 203 a of an N-type substrate 203. A surface oxide film 209 is provided on the entire surface of the substrate.
JP 2000-150848 A JP 2006-196729 A

  In the configuration of Patent Document 2, the pixel portions are isolated from each other by the N semiconductor layer 203a of the N-type substrate 203. Therefore, the signal charges photoelectrically converted in the P-well 204 are diffused as minority carriers and adjacent to each other. Although it does not leak into the pixel portion, an extra vertical separation region for each pixel portion (embedded photodiode 201) is required, which reduces the planar view area in the substrate surface direction (horizontal direction) of each pixel portion. Is disadvantageous.

  The present invention solves the above-described conventional problems, and further enables the pixel size to be further reduced, and an amplification type solid-state imaging device capable of obtaining a high-quality image without color mixing or loss of talk, and the amplification type solid-state imaging device. An object of the present invention is to provide an electronic information device such as a camera-equipped mobile phone device used as an image input device in an imaging unit.

An amplification type solid-state imaging device according to the present invention is a solid-state imaging device that includes a plurality of unit pixel units that perform photoelectric conversion two-dimensionally, and includes a first conductivity type photoelectric conversion device and a first conductivity type substrate of the unit pixel unit. A second conductivity type well is provided between the first conductivity type well, the second conductivity type well is completely depleted, and the potential potential of the fully depleted second conductivity type well is deeper than the ground potential. In a mountain-shaped curve that allows minority carriers to move to the first conductivity type photoelectric conversion element side or the first conductivity type substrate side with respect to the valley portion of the potential potential of the first conductivity type photoelectric conversion element. A charge transfer transistor for transferring a signal charge from the first conductivity type photoelectric conversion element to a charge voltage conversion unit for amplification is provided adjacent to the first conductivity type photoelectric conversion element; When the charge transfer transistor is off The potential level of the bottom is set deeper than the depletion potential potential of the second conductivity type well, the charge transfer transistors are those which are transistors of depletion mode, the objects can be achieved.

Constant DC potential to the first conductivity type substrate in the amplification type solid-state imaging device of the present invention is applied.

  Further preferably, the signal charge from one of the first conductivity type photoelectric conversion elements is amplified and read out as pixel data between the first conductivity type photoelectric conversion elements adjacent to each other in the amplification type solid-state imaging element of the present invention. A readout circuit is arranged, and the readout circuit converts the signal charge transferred to the charge-voltage converter by the charge transfer transistor, and converts the signal amplified by the amplification transistor according to the conversion voltage to the pixel unit It reads out to a signal line as every imaging signal. Preferably, a signal charge from one of the first conductivity type photoelectric conversion elements is amplified and read out as pixel data between the first conductivity type photoelectric conversion elements adjacent to each other in the amplification type solid-state imaging device of the present invention. A second conductivity type well is formed between the first conductivity type substrate and the region under the gate of each transistor constituting the read circuit and the first conductivity type substrate. It is formed shallower than the second conductivity type well between the one conductivity type photoelectric conversion element.

  Further preferably, in the readout circuit in the amplification type solid-state imaging device of the present invention, before the signal charge is transferred to the charge-voltage converter by the charge transfer transistor, the potential of the charge-voltage converter is set to a predetermined potential. There is further provided a reset transistor for resetting to. Preferably, in the readout circuit in the amplification type solid-state imaging device of the present invention, the signal charge transferred by the charge transfer transistor to the charge voltage conversion unit is voltage-converted for each of the first conductivity type photoelectric conversion elements. The signal amplified by the amplification transistor in accordance with the converted voltage is read out to the signal line as an imaging signal for each pixel unit.

The potential potential under the gate of the charge transfer transistor in the amplification type solid-state imaging device of the present invention is applied to the first conductivity type substrate so as to be deeper than the depletion potential potential of the second conductivity type well. The potential is set during the shipping test process.

  In this case, preferably, in the amplification type solid-state imaging device of the present invention, the potential applied to the first conductivity type substrate is set in parallel to each of the plurality of divided resistors connected in series, and the fuse element or the switch element is respectively set. It is connected, and the fuse element or the switch element is opened and closed.

  Further preferably, in the amplification type solid-state imaging device of the present invention, the first conductivity type substrate is an N type substrate, the first conductivity type photoelectric conversion device is an N type photoelectric conversion device, and the second conductivity type well is P-type well.

  Furthermore, preferably, the first conductive photoelectric conversion element in the amplification type solid-state imaging device of the present invention includes a second conductive type surface high-concentration diffusion layer provided on the surface side of the first conductive type photoelectric conversion element, It is composed of a buried photodiode surrounded by a second conductivity type well provided on the first conductivity type substrate side of the first conductivity type photoelectric conversion element.

  The electronic information device of the present invention uses the amplification type solid-state imaging device of the present invention as an image input device in an imaging unit, thereby achieving the above object.

  With the above configuration, the operation of the present invention will be described below.

  In the present invention, the second conductivity type well between the first conductivity type photoelectric conversion element of the unit pixel portion and the first conductivity type substrate is completely depleted.

  As a result, the potential potential of the fully-depleted second conductivity type well is deeper than the ground potential, and minority carriers are present in the first conductivity type photoelectric photoelectric transducer with respect to the valley portion of the potential potential of the first conductivity type photoelectric conversion element. Since it is a mountain-shaped curve that can be moved to the conversion element side or the first conductivity type substrate side, either the embedded type photodiode side or the N-type substrate side is used as the decimal carrier in which incident light is photoelectrically converted. To move quickly. This prevents minority carriers from leaking into adjacent pixel portions, and it is possible to obtain a high-quality image free from color mixing or loss of talk. In this case, the vertical separation region of each pixel portion according to the prior art becomes unnecessary, and the pixel size can be further reduced.

  As described above, according to the present invention, the potential potential of the fully-depleted second conductivity type well is deeper than the ground potential, and minority carriers with respect to the valley portion of the potential potential of the first conductivity type photoelectric conversion element. Is a mountain-shaped curve that can move to the first conductivity type photoelectric conversion element side or the first conductivity type substrate side, so that leakage of minority carriers into the adjacent pixel portion can be prevented, The pixel size can be further reduced, and a high-quality image free from color mixing or loss of talk can be obtained.

  Hereinafter, for example, a camera-equipped mobile phone device in which any one of Embodiments 1 to 3 of the amplification type solid-state imaging device of the present invention and Embodiments 1 to 3 of the amplification type solid-state imaging device is used as an image input device in an imaging unit. Embodiment 4 of an electronic information device such as the above will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a plan view showing an exemplary layout configuration of a main part of a pixel portion in an amplification type solid-state imaging device having an N-type substrate configuration according to Embodiment 1 of the present invention. 2 is a vertical sectional view taken along the line XX ′ of the amplification type solid-state imaging device of FIG. 1, and FIG. 3 is a vertical sectional view taken along the line YY ′ of the amplification type solid-state imaging device of FIG. FIG. 2 may be a vertical cross section in the vertical direction, and FIG. 3 may be a vertical cross section in the horizontal direction.

  1 to 3, in the solid-state image pickup device 10 that is an amplification type solid-state image pickup device having an N-type substrate configuration according to the first embodiment, the N-type embedded photodiode 1 includes P on the surface side for dark current reduction. It is surrounded by a high concentration diffusion layer 2 of the type and a depleted low concentration P-well 4 on the N-type substrate 3 side. The characteristic configuration of the solid-state imaging device 10 having the N-type substrate configuration of the first embodiment is that the region of the P-well 4 formed between the N-type embedded photodiode 1 and the N-type N-type substrate 3 is completely. This is a depleted low-concentration P-well region that is depleted.

  The reason why the depleted low-concentration P-well 4 has a low concentration is that, as described above, the depletion layer region between the N-type buried photodiode 1 and the P-well 4 is expanded to increase the light receiving sensitivity. Because. The signal charge photoelectrically converted by the embedded photodiode 1 is completely transferred and connected to the charge storage unit 6 (floating diffusion FD) through the semiconductor layer 4a under the gate 5a of the transfer transistor 5 during the read operation. An image pickup signal is output from an amplifier (not shown) such as a source follower circuit.

The potential potential below the gate 5a when the transfer transistor 5 is off is set deeper than the depletion potential potential of the depleted low concentration P-well 4. The concentration of ion concentration 1 × ^{10 -16} atoms / cm depleted low concentration P- well 4 with respect to the ^third semiconductor layer 4a is a low concentration of ion concentration 1 × ^{10 -15} atoms / cm ^3.

  After the imaging signal is output, the charge storage unit 6 (floating diffusion FD) is supplied from the drain region 7 to which the power supply voltage (Vdd) is applied through the semiconductor region 4b below the gate 8a of the reset transistor 8 to the power supply voltage (Vdd) -transistor. It is reset to the voltage value of the threshold voltage. Each transistor is isolated by an element isolation oxide film STI. However, the element isolation oxide film STI is not particularly required between the photodiodes 1, and an element isolation layer such as a P-type reverse injection layer is sufficient. It is. These gates 5a and 8a are provided through a surface oxide film 9 on the surface of the substrate.

  Thus, the electrical isolation of the pixels requires the isolation of the transistors in the horizontal direction, and thus the isolation is performed by a thick element isolation oxide film such as STI, but the isolation in the vertical direction is only for the photodiode 1. Separation is performed only by ion implantation.

  Below the depleted low concentration P-well 4 is an N-type N-type substrate 3. This is mainly because N-type substrate 3 is made N-type in order to prevent signal charges obtained by photoelectrically converting long-wavelength light inside the substrate from leaking into the adjacent pixel portion (photodiode 1). The purpose is to sweep out photoelectric charges to the substrate 3 side and prevent leakage of signal charges to adjacent pixel portions.

  In this way, the N-type N-type substrate 3 sweeps out signal charges photoelectrically converted inside the N-type substrate 3 by long-wavelength light to the N-type substrate 3 side. Since the signal charge due to the light of medium wavelength converted photoelectrically on the depleted low concentration P-well 4 is completely depleted in the P-region of the depleted low concentration P-well 4, there is no neutral region. It does not diffuse as minority carriers, and immediately flows into the N-type embedded photodiode 1 and accumulates as signal charges by the electric field effect due to the potential gradient, or is swept out to the N-type N-type substrate 3 side. Thus, minority carriers do not leak into the adjacent pixel portion.

  In addition, in order to prevent leakage of signal charges to the adjacent pixel portion, it is not necessary to newly form a pixel separation region in which an N region is formed in the vertical direction as in the prior art, which is advantageous for downsizing the pixel portion. . In order to show this effect, the solid line in FIG. 4 indicates the potential potential of the A-A ′ line portion in FIG. 2.

  The fact that the region of the P-well 4 of the first embodiment is completely depleted can further reduce the pixel size and obtain a high-quality image free from color mixing or loss of talk. This will be described in more detail.

  As shown in FIG. 4, the P-well 4 region is completely depleted. When the neutral region with a flat ground potential is spread, the P-well 4 is not depleted, and the potential potential is deeper than the ground potential. (The weir is low and the depth of the valley portion is shallow), and the valley shape of the embedded photodiode 1 is a mountain-shaped curve. The accumulated charge amount stored in the valley portion of the potential potential of the embedded photodiode 1 is reduced by a portion deeper than the neutral region of the ground potential, and the accumulated charge amount in the valley portion of the embedded photodiode 1 is small. The relationship between the carrier leaking into the adjacent pixel portion is a trade-off relationship.

  If it is not depleted, incident light is photoelectrically converted to become minority carriers and diffuses in a flat neutral region without being defined, and minority carriers leak into adjacent pixels, but depleted low concentration When the potential potential of the P-well 4 is depleted with a mountain-shaped curve, the fractional carriers obtained by photoelectric conversion of incident light are on the embedded photodiode 1 side along the mountain-shaped curve of the potential potential or It moves quickly to one of the N-type substrate 3 side. This prevents minority carriers from leaking into adjacent pixel portions, and a high-quality image free from color mixing or loss of talk can be obtained.

  The case where the region of the P-well 4 is completely depleted as in the first embodiment and the case of the prior art of FIG. 16 in which the pixel portions are isolated by the N semiconductor layer 203a of the N-type substrate 203 described above. Compared to the above, the vertical separation region of each pixel portion of the prior art of FIG. 16 is not required, and the method of the first embodiment can further reduce the pixel size.

  In the case of such a fully depleted low-concentration P-well 4, as described above, the amount of charge that can be accumulated in the N type buried photodiode 1 is reduced. This is because in the process of gradually accumulating photoelectric charges in the embedded photodiode 1, if the amount of accumulated charges increases, the peak of the potential curve of the depleted P-well 4 exceeds the top of the mountain-shaped curve, and the N-type substrate 3. This is because the signal charge flows out to the side.

  In order to prevent this, the type of the charge transfer transistor 5 is changed from the enhancement type to the depletion type, and the potential under the gate 5a when the charge transfer transistor 5 is off is deeper than the depletion potential of the P-well 4. . As a result, when the amount of signal charge increases, the signal charge is swept out to the charge detection unit 6 through the gate 5a of the charge transfer transistor 5 before exceeding the depleted P-well 4. This potential diagram is indicated by a broken line in FIG. 4 and the B-B ′ potential potential in FIG. 2.

  FIG. 5 is a potential diagram of a pixel portion that compares the potential of the charge transfer transistor 5 of FIG. 2 under the enhancement type and depletion type gates.

  Since the depletion type is deeper than the enhancement type when the charge transfer transistor is on, the charge that can be accumulated in the N type buried photodiode 1 by increasing the N type ion implantation amount of the buried type photodiode 1. A decrease in the amount can be prevented.

  As described above, according to the first embodiment, the potential potential of the fully depleted depleted low-concentration P-well 4 is deeper than the ground potential, and the embedded photodiode 1 as the first conductivity type photoelectric conversion element. Is a mountain-shaped curve that allows minority carriers to move to the embedded photodiode 1 side or the N-type substrate 3 side with respect to the valley portion of the potential potential of the sub-carrier. Quickly moves to either the embedded photodiode 1 side or the N-type substrate 3 side along a mountain-shaped curve of the potential potential. This prevents minority carriers from leaking into adjacent pixel portions, and a high-quality image free from color mixing or loss of talk can be obtained. In this case, the vertical separation region of each pixel portion according to the prior art becomes unnecessary, and the pixel size can be further reduced.

  Thus, by completely depleting the P-well 4 formed between the N-type buried photodiode 1 and the N-type N-type substrate 3, the pixel size can be reduced, color mixing, A high-quality image without crosstalk can be obtained. Further, the charge transfer transistor 5 can be made a depletion type, and at the same time, the N type ion implantation amount of the embedded photodiode 1 can be increased to prevent the maximum charge accumulation amount from decreasing.

  In the first embodiment, a signal readout circuit that amplifies a signal charge from one of the embedded photodiodes 1 and reads it out as pixel data is disposed between the embedded photodiodes 1 adjacent to each other. This signal readout circuit includes a reset transistor 8 that resets the potential of the charge-voltage conversion unit 6 to a predetermined potential before the signal charge is transferred to the charge-voltage conversion unit 6 by the charge transfer transistor 5 for each pixel unit, The signal charge transferred to the charge-voltage conversion unit 6 by the charge transfer transistor 5 is converted into a voltage, and an amplification transistor (not shown) that amplifies the signal in accordance with the converted voltage is provided for each pixel unit. The image signal is read out to a signal line (not shown).

(Embodiment 2)
In the first embodiment, the P-well 4 between the N-type substrate 3 and the N-type embedded photodiode 1 of the unit pixel is completely depleted, and the transfer transistor 5 is a depletion type. Although the case where the potential potential under the gate 5a when the transistor 5 is off is deeper than the depletion potential potential of the P-well 4 has been described, the second embodiment will be described later under the gate 5a when the transfer transistor 5 is off. The case where the P-well 4A to be formed is formed shallower than the P-well 4 between the N-type substrate 3 and the N-type buried photodiode 1 will be described.

  FIG. 6 is a horizontal cross-sectional view along the X-X ′ line in the horizontal direction of the amplification type solid-state imaging device having the N-type substrate configuration according to the second embodiment of the present invention. FIG. 7 is a vertical cross-sectional view along the Y-Y ′ line in the vertical direction of the amplification type solid-state imaging device having the N-type substrate configuration according to the second embodiment of the present invention. 6 may be a vertical cross section in the vertical direction, and FIG. 7 may be a vertical cross section in the horizontal direction.

  6 and 7, in the solid-state image pickup device 10A that is an amplification type solid-state image pickup device having an N-type substrate configuration according to the second embodiment, the N-type embedded photodiode 1 includes a P on the surface side for dark current reduction. The surface type high concentration diffusion layer 2 of the type and the depleted low concentration P-well 4 and P well 4A on the N-type substrate 3 side are surrounded.

  The characteristic configuration of the solid-state imaging device 10 of the N-type substrate configuration of the second embodiment is that the region of the P-well 4 formed between the N-type embedded photodiode 1 and the N-type N-type substrate 3 is completely This is the same in that it is a depleted low-concentration P-well region that is depleted. The difference from the first embodiment is that, in the first embodiment, the depleted low-concentration P-well 4 has a single P-well structure, but in the second embodiment, the buried photodiode 1 The structure is characterized by maintaining the configuration of a depleted low-concentration P-well 4 in the periphery, and a shallow P-well structure (P-well 4A) mainly under each gate of the signal readout circuit section other than the periphery of the embedded photodiode 1. It is a configuration.

  The depth of the depleted low-concentration P-well 4 is 2 to 3 μm, the depth of the P-well 4A is 1 to 2 μm, and the N-type substrate 3 between the adjacent depleted low-concentration P-wells 4 is N-type. A semiconductor layer is interposed. In short, the P well 4A under the gate 5a of the transfer transistor 5 is formed with a substrate depth shallower than the bottom of the depleted low concentration P − well 4 between the N type substrate 3 and the N type buried photodiode 1. Has been. The impurity concentration of the P well 4A is higher than that of the depleted low concentration P-well 4.

  In general, color mixing and crosstalk are likely to occur in the vertical direction (YY ′ line direction in FIG. 1) close to the adjacent embedded photodiode 1, but slightly in the horizontal direction (XX ′ line direction in FIG. 1). Occur.

  In the potential potential between BB ′ in the first embodiment, since the neutral region remains in the P− region, the signal charge photoelectrically converted by the medium-long wavelength light obliquely incident on this region is If it flows into the adjacent pixel portion due to diffusion of minority carriers, color mixing or crosstalk occurs.

  On the other hand, FIG. 8 shows a potential diagram of the pixel portion of the second embodiment, as in the case of the first embodiment, but compared with the case of the first embodiment in FIGS. In FIG. 8, the neutral region of the depleted low-concentration P-well 4 is decreased, and the N-type substrate region is increased. As a result, it is possible to reduce color mixing and crosstalk generated in the P-well 4A due to diffusion in the P-well 4A due to oblique light of medium to long wavelength, which is generated in the horizontal direction.

(Embodiment 3)
In the third embodiment, the potential VD applied to the N-type substrate 3 so that the potential potential under the gate 5a when the transfer transistor 5 is off becomes deeper than the depletion potential potential of the depleted low concentration P-well 4. Will be described for each manufacture during the shipping test process.

  FIG. 9 is a horizontal cross-sectional view along the X-X ′ line in the horizontal direction of the amplification type solid-state imaging device having the N-type substrate configuration according to the third embodiment of the present invention. FIG. 10 is a vertical cross-sectional view along the Y-Y ′ line in the vertical direction of the amplification type solid-state imaging device having the N-type substrate configuration according to the third embodiment of the present invention. 9 may be a vertical cross section in the vertical direction, and FIG. 10 may be a vertical cross section in the horizontal direction.

  9 and 10, in the solid-state image pickup device 10B that is an amplification type solid-state image pickup device having an N-type substrate configuration according to the third embodiment, the N-type embedded photodiode 1 includes a P on the surface side for dark current reduction. It is surrounded by a high concentration diffusion layer 2 of the type and a depleted low concentration P-well 4 on the N-type substrate 3 side.

  The characteristic configuration of the solid-state imaging device 10B of the N-type substrate configuration of the third embodiment is that the region of the P-well 4 formed between the N-type embedded photodiode 1 and the N-type N-type substrate 3 is completely This is the same in that the depleted low concentration P-well 4 is depleted. The difference from the first embodiment is that the potential applied to the N-type substrate 3 is not always a constant VDD (power supply potential) but an optimum potential VD is applied every time a semiconductor is manufactured.

  The charge transfer transistor 5 can be of a depletion type, and at the same time, the N-type ion implantation amount of the embedded photodiode 1 can be increased to prevent a decrease in the maximum charge accumulation amount. Since the potential potential below 5a varies during manufacturing, and the P-well depletion potential potential also varies during manufacturing, the condition described in the first embodiment may not be satisfied. In the third embodiment, the potential VD applied to the N-type substrate 3 is adjusted to an optimum value according to manufacturing fluctuations.

  In this case, the potential applied to the N-type substrate 3 is set in parallel with each of the plurality of divided resistors connected in series, although not shown, a fuse element or a switch element is connected. This is done by opening and closing.

  FIG. 11 shows a potential diagram showing the potential potential of the A-A ′ line portion and the potential potential of the B-B ′ line portion of the solid-state imaging device 10B having the N-type substrate configuration according to the third embodiment.

  FIG. 12 is a diagram showing the maximum charge accumulation amount and crosstalk characteristics with respect to the potential VD applied to the N-type substrate 3 of FIG.

  The maximum charge accumulation amount does not change when the potential VD applied to the N-type substrate 3 is low, but is not changed because it is limited by the potential potential under the gate 5a of the charge transfer transistor 5, but the potential VD applied to the N-type substrate 3 is high. In this region, the maximum charge accumulation amount decreases as the potential VD increases. Therefore, in terms of the maximum charge accumulation amount, the potential VD should be low.

On the other hand, the crosstalk worsens when the potential VD applied to the N-type substrate 3 is low and the P-well 4 is not completely depleted and the neutral region remains, but the P-well 4 is depleted. The interval has good characteristics as described above. Therefore, VDmin and VDmax in FIG. 12 are VDmin: When P-well potential is 0V
VDmax: represents the time when the P-well potential is the same as the potential under the gate of the charge transfer transistor.

  Here, since the charge transfer transistor 5 is a depletion type, the potential potential under the gate 5a is 0 V or more, and a solution exists. From these two characteristics, the optimum potential range of the VD potential can be obtained. In FIG. 12, a region between VDmin and VDmax is a region where the maximum charge accumulation amount is limited by the potential potential under the gate 5a of the charge transfer transistor 5 while the P-well 4 is completely depleted.

These are the potentials applied to the N-type substrate 3 from the maximum accumulated charge amount and the crosstalk characteristics while scanning the potential VD applied to the N-type substrate 3 during the wafer test after the manufacture of the two-dimensional solid-state imaging device 10B. The optimum value of VD is obtained and stored in a memory circuit (such as a fuse circuit or flash memory), and the obtained potential is applied to the N-type substrate 3.
(Embodiment 4)
FIG. 13: is a block diagram which shows the schematic structural example of the electronic information apparatus which used the solid-state imaging device containing the solid-state imaging device in any one of Embodiment 1-3 of this invention for the imaging part as Embodiment 4 of this invention. is there.

  In FIG. 13, the electronic information device 90 according to the fourth embodiment performs solid-state imaging to obtain a color image signal by performing various signal processing on the imaging signal from the solid-state imaging device 10, 10 </ b> A, or 10 </ b> B according to any of the first to third embodiments. A device 91, a memory unit 92 such as a recording medium capable of recording data after a predetermined signal processing is performed on the color image signal from the solid-state imaging device 91, and the color image signal from the solid-state imaging device 91 is displayed. Display means 93 such as a liquid crystal display device which can be displayed on a display screen such as a liquid crystal display screen after predetermined signal processing for use, and color signal signals from the solid-state imaging device 91 are subjected to predetermined signal processing for communication. And a communication means 94 such as a transmission / reception device that enables communication processing after the communication. The electronic information device 90 is not limited to this, and in addition to the solid-state imaging device 91, at least one of a memory unit 92, a display unit 93, a communication unit 94, and an image output device 95 such as a printer. You may have.

  As described above, the electronic information device 90 includes, for example, a digital camera such as a digital video camera and a digital still camera, an in-vehicle camera such as a surveillance camera, a door phone camera, and an in-vehicle rear surveillance camera, and a video phone camera. An electronic device having an image input device such as an image input camera, a scanner device, a facsimile device, a camera-equipped mobile phone device, and a portable terminal device (PDA) is conceivable.

  Therefore, according to the fourth embodiment, on the basis of the color image signal from the solid-state imaging device 91, it is displayed on the display screen, or is printed out on the paper by the image output device 95. (Printing), communicating this as communication data in a wired or wireless manner, performing a predetermined data compression process in the memory unit 92 and storing it in a good manner, or performing various data processings satisfactorily Can do.

  Although not described briefly in the first to third embodiments, the depleted low-concentration P-well 4 provided between the embedded photodiode 1 and the N-type substrate 3 in the unit pixel portion is completely formed. By being depleted, it is possible to achieve the object of the present invention that can further reduce the pixel size and obtain a high-quality image free from color mixing or loss of talk.

  As mentioned above, although this invention has been illustrated using preferable Embodiment 1-4 of this invention, this invention should not be limited and limited to this Embodiment 1-4. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range from the description of specific preferred embodiments 1 to 4 of the present invention based on the description of the present invention and the common general technical knowledge. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention relates to a solid-state imaging device configured by a semiconductor element that photoelectrically converts image light from a subject to capture an image, and, for example, a digital video camera and a digital still camera using the solid-state imaging device as an image input device in an imaging unit In the field of electronic information equipment such as digital cameras, image input cameras, scanner devices, facsimile devices, and camera-equipped mobile phone devices, the potential potential of the fully-depleted second conductivity type well is higher than the ground potential. Further, it becomes a mountain-like curve that allows minority carriers to move to the first conductive type photoelectric conversion element side or the first conductive type substrate side with respect to the valley portion of the potential potential of the first conductive type photoelectric conversion element. Therefore, it is possible to prevent the minority carrier from leaking into the adjacent pixel portion, and to further reduce the pixel size. Both can be obtained a high-quality image free from color mixture or Surosutoku.

It is a top view which shows the principal part layout structural example of the pixel part in the amplification type solid-state image sensor of N type board | substrate structure which concerns on Embodiment 1 of this invention. FIG. 2 is a vertical cross-sectional view along the X-X ′ line in the horizontal direction of the amplification type solid-state imaging device of FIG. 1. FIG. 2 is a vertical cross-sectional view along the Y-Y ′ line in the vertical direction of the amplification type solid-state imaging device of FIG. 1. FIG. 3 is a potential diagram showing a potential potential of an A-A ′ line portion and a potential potential of a B-B ′ line portion of FIG. 2. FIG. 3 is a potential diagram of a pixel portion for comparing potentials under an enhancement type and depletion type gate of the charge transfer transistor 5 of FIG. 2. It is a X-X 'line longitudinal cross-sectional view of the horizontal direction of the amplification type solid-state image sensor of N type substrate composition concerning Embodiment 2 of the present invention. It is the Y-Y 'line longitudinal cross-sectional view of the orthogonal | vertical direction of the amplification type solid-state image sensor of N type board | substrate structure which concerns on Embodiment 2 of this invention. FIG. 7 is a potential diagram showing a potential potential of an A-A ′ line portion and a potential potential of a B-B ′ line portion of FIG. 6. It is a X-X 'line longitudinal cross-sectional view of the horizontal direction of the amplification type solid-state image sensor of N type substrate composition concerning Embodiment 3 of the present invention. It is the Y-Y 'line longitudinal cross-sectional view of the orthogonal | vertical direction of the amplification type solid-state image sensor of N type board | substrate structure which concerns on Embodiment 3 of this invention. FIG. 10 is a potential diagram showing the potential potential of the A-A ′ line portion and the potential potential of the B-B ′ line portion of FIG. 9. FIG. 10 is a diagram showing a maximum charge accumulation amount and crosstalk characteristics with respect to a potential VD applied to the N-type substrate of FIG. 9. It is a block diagram which shows the example of schematic structure of the electronic information apparatus which used the solid-state imaging device containing the solid-state image sensor in any one of Embodiments 1-3 of this invention for Embodiment 4 as an imaging part. It is a longitudinal cross-sectional view of the horizontal direction which shows the example of a principal part structure of the pixel part in the solid-state image sensor of the conventional N type board | substrate structure. It is a longitudinal cross-sectional view of the perpendicular direction which shows the example of a principal part structure of the pixel part in the solid-state image sensor of the conventional N type board | substrate structure. FIG. 10 is a vertical sectional view in the vertical direction showing an example of a main part configuration of a pixel portion in a conventional solid-state imaging device having an N-type substrate configuration disclosed in Patent Document 2.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Embedded type photodiode 2 Surface high concentration diffusion layer 3 N type substrate 4 Depletion low concentration P-well 4A P-well 5 Transfer transistor 5a Gate 6 Charge storage part 6 (floating diffusion FD)
7 Drain region 8 Reset transistor 8a Gate 9 Surface oxide film 10, 10A, 10B Solid-state imaging device (amplification type solid-state imaging device)
DESCRIPTION OF SYMBOLS 90 Electronic information equipment 91 Solid-state imaging device 92 Memory part 93 Display means 94 Communication means 95 Image output device

Claims (9)

In a solid-state imaging device that two-dimensionally includes a plurality of unit pixel units that perform photoelectric conversion,
A second conductivity type well is provided between the first conductivity type photoelectric conversion element of the unit pixel portion and the first conductivity type substrate, and the second conductivity type well is completely depleted,
The potential potential of the fully-depleted second conductivity type well is deeper than the ground potential, so that minority carriers are present in the first conductivity type photoelectric conversion with respect to the valley portion of the potential potential of the first conductivity type photoelectric conversion element. It is a mountain-shaped curve that can be moved to the conversion element side or the first conductivity type substrate side,
A charge transfer transistor for transferring signal charges from the first conductivity type photoelectric conversion element to a charge voltage converter for amplification is provided adjacent to the first conductivity type photoelectric conversion element. An amplification type solid-state imaging device in which the potential potential under the gate at the time of OFF is set deeper than the depletion potential potential of the second conductivity type well , and the charge transfer transistor is a depletion type transistor .   The amplification type solid-state imaging device according to claim 1, wherein a constant DC potential is applied to the first conductive type substrate. Between the first conductivity type photoelectric conversion elements adjacent to each other,
A readout circuit that amplifies the signal charge from one of the first conductivity type photoelectric conversion elements and reads it out as pixel data is disposed,
The readout circuit is
The signal charge transferred to the charge-voltage conversion unit by the charge transfer transistor is voltage-converted, and a signal amplified by the amplification transistor according to the conversion voltage is read out to a signal line as an imaging signal for each pixel unit. 2. The amplification type solid-state imaging device according to 1. The readout circuit includes
4. The amplification type according to claim 3 , further comprising a reset transistor that resets a potential of the charge-voltage conversion unit to a predetermined potential before the signal charge is transferred to the charge-voltage conversion unit by the charge transfer transistor. Solid-state image sensor.   The potential applied to the first conductivity type substrate is set at the time of the shipping test process so that the potential potential under the gate when the charge transfer transistor is off is deeper than the depletion potential potential of the second conductivity type well. The amplification type solid-state imaging device according to claim 1. In setting the potential to be applied to the first conductive type substrate, a fuse element or a switch element is connected in parallel to each of a plurality of series-connected divided resistors, and the fuse element or the switch element is opened / closed. The amplification type solid-state imaging device according to claim 5 , wherein the amplification type solid-state imaging device is performed.   2. The amplification type according to claim 1, wherein the first conductivity type substrate is an N type substrate, the first conductivity type photoelectric conversion element is an N type photoelectric conversion element, and the second conductivity type well is a P type well. Solid-state image sensor. The first conductivity type photoelectric conversion element is:
A second conductivity type surface high-concentration diffusion layer provided on the surface side of the first conductivity type photoelectric conversion element, and a second conductivity type well provided on the first conductivity type substrate side of the first conductivity type photoelectric conversion element. The amplification type solid-state imaging device according to claim 1, comprising an embedded photodiode surrounded by Electronic information device using the imaging unit the amplification type solid-state image pickup device as an image input device according to any one of claims 1-8.

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