TWI420474B - Source driver - Google Patents

Description

Source driver

The present invention relates to a source driver, and more particularly to a source driver for adjusting the slew rate of an output signal.

The source driver is an important component in a liquid crystal display (LCD), which converts digital video data into a plurality of voltage signals, and transmits the converted voltage signal to a pixel on the display panel to display an image. Picture. The source driver typically has multiple output buffers to enhance the voltage signals described above. Due to differences in electronic component characteristics and process variations, the voltage signals output from these output buffers may not have the same slew rate when driving pixels. As a result, the display screen is unstable due to the difference in time required for the liquid crystal orientation.

Generally, in a liquid crystal display device, the polarity of a voltage signal transmitted to a pixel must be periodically changed to avoid polarization of the liquid crystal and cause image sticking. There are three ways to drive the display panel with polarity inversion, namely frame inversion, column inversion, and dot inversion. Taking dot inversion as an example, adjacent pixels in a picture are driven by driving voltages of opposite polarities, and pixels of the same position in two consecutive pictures are also driven by driving voltages of opposite polarities. Generally, the driving voltage of the positive polarity is greater than the common voltage coupled to the liquid crystal, and the driving voltage of the negative polarity is less than the common voltage.

Since the driving voltages of opposite polarities have different voltage levels, the output buffers that respectively enhance the driving voltages of different polarities may be composed of different electronic components. For example, an output buffer suitable for enhancing the driving voltage of the positive polarity may include an N-Type Differential Pair for receiving a driving voltage of a high level and controlling the operation of the output buffer. Conversely, an output buffer suitable for enhancing the drive voltage of the negative polarity may include a P-Type Differential Pair for receiving a low level drive voltage and controlling the operation of the output buffer. As described above, due to the difference in characteristics of the electronic components and variations in the process, the voltage signals output by the source drivers are likely to have different slew rates.

Obviously, the difference in the slew rate of the voltage signal causes the difference in the orientation time of the liquid crystal driven by the voltage signal. Therefore, when the polarity inversion is performed, the gray scale display of the displayed image is uneven, and the flickering of the screen perceived by the human eye is more serious, resulting in deterioration of display quality. Here, an appropriate source driver needs to be designed to solve the above problem.

The present invention provides a source driver that can adjust the slew rate of pixel signals generated by different output buffers. Thereby, the present invention can avoid flickering of the screen in the display panel and further improve the quality of the display panel.

The invention provides a source driver suitable for driving a display panel having a plurality of data lines. The source driver includes a first output buffer, and a second An output buffer, a multiplexer, and a first adjustment unit. The first input end of the first output buffer receives a first pixel signal, and the second input end is coupled to the output end thereof for enhancing the transmission strength of the first pixel signal. Similarly, the first input end of the second output buffer receives a second pixel signal, and the second input end is coupled to the output end thereof for enhancing the transmission strength of the second pixel signal. The first adjusting unit is coupled to the output end of the first output buffer and the first input end of the multiplexer. The first adjusting unit adjusts the slew rate of the first pixel signal output by the first output buffer to match the slew rate of the second pixel signal output by the second output buffer, and transmits the first pixel signal At most work. The multiplexer is coupled to the output ends of the first output buffer and the second output buffer for respectively transmitting the first pixel signal and the second pixel signal to an odd data line and an even data line thereof according to the control signal Or respectively transmitting the first pixel signal and the second pixel signal to one of the even data lines and one of the odd data lines.

In an embodiment of the invention, the source driver further includes a second adjustment unit. The second adjusting unit is coupled between the output end of the second output buffer and the multiplexer for adjusting the slew rate of the second pixel signal outputted by the second output buffer to the first output buffer The slew rate of the output first pixel signal matches, and the second pixel signal is transmitted to the multiplexer.

In an embodiment of the invention, the first pixel signal and the second pixel signal have complementary polarities.

Based on the above, the source driver of the present invention uses the adjustment unit to adjust the slew rate of the pixel signals outputted by the different output buffers. In addition, Through the operation of the adjustment unit, the rise time and fall time of the pixel signal outputted by the same output buffer can be made symmetric, that is, the charging capacity and the discharge capacity of the output buffer are symmetrical to avoid the image when the image is displayed. flicker.

The above described features and advantages of the present invention will be more apparent from the following description.

The embodiments of the present invention are described in detail below with reference to the accompanying drawings, in which FIG.

1 is a circuit diagram of a source driver in accordance with an embodiment of the present invention. Referring to FIG. 1, the source driver 100 is adapted to drive a plurality of data lines on the display panel, that is, data lines D1 and D2, wherein the display panel is, for example, a liquid crystal display panel or a germanium-based liquid crystal panel. The data line includes a plurality of odd data lines (ie, data lines D1) and a plurality of even data lines (ie, data lines D2) are alternately arranged on the display panel. The source driver 100 includes output buffers 111 and 112, a multiplexer 120, and adjustment units 131 and 132. When a scan line is enabled, the source driver 100 enhances the transmission strengths of the pixel signals VP1 and VP2 via the output buffers 111 and 112, respectively, and then transmits the pixel signals VP1 and VP2 to the data lines D1 and D2 to display an image. Those skilled in the art should be able to understand the basic operation of the source driver 100 of the present embodiment, and therefore will not be described again.

It is assumed that the output buffers 111 and 112 are respectively responsible for enhancing the complementary polarity. The pixel signals VP1 and VP2 are positive polarity and negative polarity. The first input end of the output buffer 111 (ie, the non-inverting terminal "+") receives the positive polarity pixel signal VP1, and the second input end of the output buffer 111 (ie, the inverting terminal "-") is coupled to the output. The output terminal OUT1 of the buffer 111. Similarly, the first input terminal of the output buffer 112 (ie, the non-inverting terminal "+") receives the negative polarity pixel signal VP2, and the second input terminal of the output buffer 112 (ie, the inverting terminal "-") The output terminal OUT2 of the output buffer 112 is coupled.

The adjusting unit 131 is coupled between the output terminal OUT1 of the output buffer 111 and the first input end I1 of the multiplexer 120 for adjusting the slew rate of the pixel signal VP1 outputted by the output buffer 111. Similarly, the adjustment unit 132 is coupled between the output terminal OUT2 of the output buffer 112 and the second input terminal I2 of the multiplexer 120 for adjusting the slew rate of the pixel signal VP2 outputted by the output buffer 112. The first output terminal O1 and the second output terminal O2 of the multiplexer 120 are coupled to the odd data line D1 and the even data line D2, respectively. The multiplexer 120 transmits the pixel signals VP1 and VP2 having complementary polarities to the odd data line D1 and the even data line D2 according to the control signal CON, or respectively transmits the pixel signals VP1 and VP2 to the even data line D2 and the odd data lines. D1 for point polarity inversion.

In general, the slew rate of an electronic circuit is defined as the maximum rate at which the output signal changes. Due to the load effect and the charge and discharge operation of the output buffer, the slew rate of the pixel signal outputted by the output buffer may be slow, and even if the pixel signal output by the same output buffer is up, the rising slew rate and the falling slew are reversed. The rate will also be asymmetrical. The slower the slew rate of the pixel signal, the more time the pixel signal needs to reach the predetermined voltage level to drive the liquid crystal. Pixel The asymmetry of the signal's rising slew rate and falling slew rate can also cause unwanted flickering. In addition, if the slew rate of the pixel signals output by different output buffers does not match, the display of the displayed image will be uneven.

Therefore, in the embodiment of the present invention, the adjustment units 131 and 132 respectively adjust the slew rates of the pixel signals VP1 and VP2 outputted by the output buffers 111 and 112 to solve the above problem. Referring to FIG. 1, in the embodiment, the adjusting units 131 and 132 are respectively implemented by variable resistors VR1 and VR2 for adjusting the slew rate of the pixel signals VP1 and VP2 outputted by the output buffers 111 and 112. match. The variable resistor VR1 is coupled between the output terminal OUT1 of the output buffer 111 and the multiplexer 120 to adjust the resistance between the two. The variable resistor VR2 is coupled between the output terminal OUT2 of the output buffer 112 and the multiplexer 120 to adjust the resistance between the two.

When the slew rate of the pixel signal VP1 is smaller than the slew rate of the pixel signal VP2, the variable resistor VR1 is controlled to adjust the signal T1 and lower its resistance value to increase the slew rate of the pixel signal VP1, so that the pixel signal VP1 The slew rate matches the slew rate of the pixel signal VP2. On the other hand, the variable resistor VR2 is controlled to adjust the signal T2 to increase its resistance value to reduce the slew rate of the pixel signal VP2, so that the slew rate of the pixel signal VP2 matches the slew rate of the pixel signal VP1. In a preferred embodiment, the variable resistors VR1 and VR2 are respectively controlled by adjusting the signals T1 and T2 to lower the resistance values of the two, thereby increasing the slew rate of the pixel signals VP1 and VP2 to a preset value. The slew rates of the pixel signals VP1 and VP2 can match and match each other. In addition, by adjusting the operation of the unit, the rising and falling slew rates of the pixel signals outputted by the same output buffer can be symmetric, so that the charging energy of each output buffer can be The symmetry between force and discharge capability is increased to avoid flickering.

Referring to FIG. 1, the multiplexer 120 is controlled by a control signal CON, which receives the pixel signals VP1 and VP2 respectively adjusted by the adjusting units 131 and 132 to selectively transmit the pixel signals VP1 and VP2 to the odd The data line D1 and the even data line D2, or the pixel signals VP1 and VP2 to the even data line D2 and the odd data line D1, respectively. 2 is a circuit diagram of the multiplexer 120 of FIG. 1 according to an embodiment of the present invention. Referring to FIG. 2, the multiplexer 120 includes switches W1 to W4. The switch W1 turns on the first input end I1 of the multiplexer 120 to the first output end O1 according to the first signal CON1 of the control signal CON, and the switch W3 turns on the multiplexer 120 according to the second signal CON2 of the control signal CON. The two input terminals I2 to the second output terminal O2. Therefore, the multiplexer 120 can transmit VP1 and VP2 to the odd data line D1 and the even data line D2, respectively. The switch W2 turns on the first input terminal I1 to the second output terminal O2 of the multiplexer 120 according to the first inversion signal CON1' of the control signal CON, and the switch W4 is turned on according to the second inversion signal CON2' of the control signal CON. The second input terminal I2 of the multiplexer 120 is to the first output terminal O1. The first inverted signal CON1' and the second inverted signal CON2' are obtained by inverting the first signal CON1 and the second signal CON2, respectively. Thereby, the multiplexer 120 can transmit the pixel signals VP1 and VP2 to the even data line D2 and the odd data line D1, respectively.

The circuit diagrams shown in Figures 1 and 2 are illustrated by way of example only to enable those skilled in the art to practice the invention, and are not intended to limit the invention. To enable the present invention to be readily implemented by those skilled in the art, the operation of the adjustment units 131 and 132 will be described in detail below with other embodiments.

3 is a circuit diagram of an adjustment unit in the source driver 100 in accordance with an embodiment of the present invention. Referring to FIG. 3, taking the adjustment unit 131 as an example, the adjustment unit 131 in FIG. 3 includes resistors RE_1~RE_N, and switches SW_1~SW_N-1, where N is a positive integer. The resistors RE_1~RE_N are connected in series, and the first end and the second end of the series resistors RE_1~RE_N are respectively coupled to the output terminal OUT1 and the ground GND of the output buffer 111. In the switches SW_1~SW_N-1, each switch is coupled between the corresponding resistor and the first input terminal I1 of the multiplexer 120, and turns on the output terminal OUT1 of the output buffer 111 to the multiplexer 120 according to the adjustment signal T1. The circuit between the first input I1. The resistors RE_1~RE_N and the switches SW_1~SW_N-1 operate in an equivalent manner as a variable resistor to adjust the slew rate of the pixel signal VP1.

For example, assume that the adjustment signal T1 has N-1 bits, and the bit signals of the adjustment signal T1 respectively control the on/off states of the switches SW_1~SW_N-1. If the switch SW_1 is turned on, the equivalent resistance between the output terminal OUT1 of the output buffer 111 and the first input terminal I1 of the multiplexer 120 is the resistor RE_1. Similarly, if the switch SW_2 is turned on, the equivalent resistance between the output terminal OUT1 of the output buffer 111 and the first input terminal I1 of the multiplexer 120 is the sum of the resistor RE_1 and the resistor RE_2. Therefore, the adjusting unit 131 shown in FIG. 3 can adjust the slew rate of the pixel signal VP1 by increasing or decreasing the equivalent resistance.

4 is a circuit diagram of an adjustment unit in the source driver 100 in accordance with another embodiment of the present invention. Referring to FIG. 4 , taking the adjustment unit 131 as an example, the adjustment unit 131 includes switches S1 S S2 and a capacitor C1 . As shown in Figure 4, open The switch S1 has one end coupled to the output terminal OUT1 of the output buffer 111, and the other end coupled to one end of the capacitor C1 and one end of the switch S2. In addition, the other end of the capacitor C1 is coupled to the ground voltage GND, and the other end of the switch S2 is coupled to the first input end I1 of the multiplexer 120.

The adjustment unit 131 generates an equivalent resistance by alternately turning on the switches S1 and S2. The equivalent resistance value generated by the adjusting unit 131 is related to the switching frequency of the switches S1 and S2 alternately, that is, R=1/(C×f), where R is the effective resistance value, C is the capacitance value of the capacitor C1 and f is the switching frequency. Therefore, the adjusting unit 131 shown in FIG. 4 can adjust the slew rate of the pixel signal VP1 by increasing or decreasing the effective resistance value generated by the adjusting unit 131.

As described above, the adjustment unit 132 in the source driver 100 can also be implemented by the circuits shown in FIG. 3 and FIG. 4, and thus will not be further described herein.

In summary, the source driver of the above embodiment uses the adjustment unit to adjust the slew rate of the pixel signals output by the different output buffers to match each other. In addition, through the adjustment unit, the slew rate of the rise and fall of the pixel signal can also be adjusted to be symmetrical. In this way, the time required for the liquid crystal orientation on the display panel can be nearly the same to improve the display quality, and the symmetry between the charging capability and the discharging capability of the output buffer can also be improved to avoid flickering of the screen.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Source Driver

111~112‧‧‧Output buffer

120‧‧‧Multiplexer

131~132‧‧‧Adjustment unit

OUT1~OUT2‧‧‧ output

T1~T2‧‧‧ adjustment signal

VP1~VP2‧‧‧ pixel signal

VR1~VR2‧‧‧Variable resistor

I1‧‧‧ first input

I2‧‧‧ second input

O1‧‧‧ first output

O2‧‧‧ second output

D1‧‧‧Unusual data line

D2‧‧‧ even data line

CON‧‧‧ control signal

CON1‧‧‧ first signal

CON2‧‧‧second signal

RE_1~RE_N‧‧‧Resistors

W1~W4, SW_1~SW_N-1, S1, S2‧‧‧ switch

GND‧‧‧ Grounding voltage

C1‧‧‧ capacitor

1 is a circuit diagram of a source driver in accordance with an embodiment of the present invention.

2 is a circuit diagram of the multiplexer of FIG. 1 according to an embodiment of the present invention.

3 is a circuit diagram of an adjustment unit in a source driver according to an embodiment of the present invention.

4 is a circuit diagram of an adjustment unit in a source driver according to another embodiment of the present invention.

100‧‧‧Source Driver

111~112‧‧‧Output buffer

120‧‧‧Multiplexer

131~132‧‧‧Adjustment unit

OUT1~OUT2‧‧‧ output

T1~T2‧‧‧ adjustment signal

VP1~VP2‧‧‧ pixel signal

VR1~VR2‧‧‧Variable resistor

I1‧‧‧ first input

I2‧‧‧ second input

O1‧‧‧ first output

O2‧‧‧ second output

D1‧‧‧Unusual data line

D2‧‧‧ even data line

CON‧‧‧ control signal

Claims (12)

A source driver for driving a display panel, wherein the display panel has a plurality of data lines, and the data lines include a plurality of odd data lines and a plurality of even data lines alternately disposed on the display panel, the source The driver includes: a first output buffer, the first input end receives a first pixel signal, and the second input end is coupled to the output end thereof for enhancing the transmission strength of the first pixel signal; a second output buffer, the first input end receives a second pixel signal, and the second input end is coupled to the output end thereof for enhancing the transmission strength of the second pixel signal; a multiplexer, the first An input end is coupled to the output end of the first output buffer, and a second input end is coupled to the output end of the second output buffer, and the first output end is coupled to the odd data lines, and the first The two output terminals are coupled to the one of the even data lines for transmitting the first pixel signal and the second pixel signal to the odd data lines and the even data lines according to a control signal. First, or respectively transmitting the first pixel signal and the first a pixel signal to the one of the even data lines and one of the odd data lines; and a first adjusting unit coupled to the output end of the first output buffer and the first input end of the multiplexer And adjusting a slew rate of the first pixel signal output by the first output buffer to match a slew rate of the second pixel signal output by the second output buffer, and transmitting the The first pixel signal is sent to the multiplexer. The source driver as described in claim 1 of the patent scope, The second adjusting unit is coupled to the output end of the second output buffer and the second input end of the multiplexer for adjusting the second pixel signal output by the second output buffer The slew rate is matched to the slew rate of the first pixel signal output by the first output buffer, and the second pixel signal is transmitted to the multiplexer. The source driver of claim 2, wherein the second adjustment unit comprises: a variable resistor, the first end of which is coupled to the output end of the second output buffer, and the second end is coupled The second input end of the multiplexer is configured to adjust a resistance value passed by the second pixel signal according to an adjustment signal. The source driver of claim 2, wherein the second adjustment unit comprises: a plurality of resistors coupled together in series, wherein the resistors connected in series have a first end and a second end coupled respectively An output of the second output buffer and a voltage; and a plurality of switches, each of the switches being coupled between the corresponding resistor and the second input of the multiplexer for turning on the adjustment signal The output of the second output buffer is to the second input of the multiplexer. The source driver of claim 2, wherein the second adjustment unit comprises: a first switch, the first end of which is coupled to the output end of the second output buffer; a first capacitor, the first One end is coupled to the second end of the first switch, and The second end of the multiplexer is coupled to the second end of the first switch, and the second end is coupled to the second end of the multiplexer, wherein the second end is coupled to the second end of the multiplexer A switch and the second switch are alternately turned on. The source driver of claim 1, wherein the first adjustment unit comprises: a variable resistor having a first end coupled to the output end of the first output buffer and a second end coupled The first input end of the multiplexer is configured to adjust a resistance value passed by the second pixel signal according to an adjustment signal. The source driver of claim 1, wherein the first adjustment unit comprises: a plurality of resistors coupled together in series, wherein the resistors connected in series have a first end and a second end coupled respectively An output of the first output buffer and a voltage; and a plurality of switches, each of the switches being coupled between the corresponding one of the resistor and the first input of the multiplexer for turning on the adjustment signal according to an adjustment signal The output of the first output buffer is to the first input of the multiplexer. The source driver of claim 1, wherein the first adjustment unit comprises: a first switch, the first end of which is coupled to the output end of the first output buffer; a first capacitor, the first One end is coupled to the second end of the first switch, and the second end is coupled to a voltage; and a second switch is coupled to the second end of the first switch, The second end is coupled to the first input end of the multiplexer, wherein the first switch and the second switch are alternately turned on. The source driver of claim 1, wherein the multiplexer includes: a first switch having a first end coupled to the output end of the first output buffer and a second end coupled to the source One of the odd data lines is configured to transmit the first pixel signal to the one of the odd data lines according to the first signal of the control signal; and the second switch has a first end coupled to the first switch The first end, and the second end of the control signal is coupled to the first data line, and the first pixel signal is transmitted to the even data lines according to the first reverse signal of the control signal; The first switch is coupled to the output end of the second output buffer, and the second end is coupled to the one of the even data lines, and the second picture is transmitted according to the second signal of the control signal The first signal is coupled to the first end of the third switch, and the second end is coupled to the singular data lines, according to the control A second inverted signal of the signal transmits the second pixel signal to one of the odd data lines. The source driver of claim 1, wherein the first pixel signal and the second pixel signal have complementary polarities. The source driver of claim 1, wherein the display panel is a liquid crystal display panel. The source driver of claim 1, wherein the display panel is a germanium-based liquid crystal panel.