CN106328086B - Drive circuit and drive method of liquid crystal display device - Google Patents

Drive circuit and drive method of liquid crystal display device Download PDF

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CN106328086B
CN106328086B CN201610928230.3A CN201610928230A CN106328086B CN 106328086 B CN106328086 B CN 106328086B CN 201610928230 A CN201610928230 A CN 201610928230A CN 106328086 B CN106328086 B CN 106328086B
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polarity
signal
jitter
data output
liquid crystal
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CN106328086A (en
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熊志
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00Control of display operating conditions
    • G09G2320/02Improving the quality of display appearance
    • G09G2320/0257Reduction of after-image effects

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
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  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

The embodiment of the invention provides a driving circuit and a driving method of liquid crystal display equipment, wherein the driving circuit comprises a time schedule controller and a source driver, and the time schedule controller comprises a gamma curve adjusting module, a time schedule control module and a polarity control module; the gamma curve adjusting module is used for acquiring a jitter data output period in the frame rate control process according to a preset jitter control table; the timing control module is used for providing a polarity inversion control signal, is connected between the timing control module and the source driver, and is used for controlling the polarity inversion control signal to be inverted between two adjacent jitter data output periods according to a preset reference signal; and the source driver is used for outputting data voltage with corresponding polarity to the liquid crystal panel according to the polarity inversion control signal. The driving circuit can enable the data voltage on the liquid crystal panel to have balanced direct current bias voltage in any two adjacent jitter data output periods.

Description

Drive circuit and drive method of liquid crystal display device
Technical Field
The invention relates to the field of liquid crystal display, in particular to a driving circuit and a driving method of liquid crystal display equipment.
Background
In the field of liquid crystal panel design, the voltage-transmittance curves of red, green and blue colors through liquid crystal are different due to different wavelengths of the red, green and blue colors. The different voltage-transmittance curves of red, green and blue lead to different brightness of red, green and blue transmitting liquid crystal under the same gray scale, so that the color displayed by the TFT-LCD is distorted. In order to ensure that the color display of the liquid crystal panel is not distorted, a direct current bias voltage can be applied to the liquid crystal pixels through Digital Gamma Control (DGC) in a time sequence controller TCON during the design of a liquid crystal panel driving circuit, so that three colors of red, green and blue are respectively adjusted to solve the problem of color distortion. However, when the screen keeps a still picture for a long time, if the liquid crystal molecules are applied with a dc bias for a long time, the polarization of the liquid crystal molecules cannot be deflected normally, and even if the content of the displayed picture IS changed, the screen still can see the trace of the previous still image, which IS called Image Sticking (IS), and this IS directly affects the display quality of the liquid crystal panel, and may even cause that the product cannot be produced normally in batch or a large number of products with poor display quality are produced, which increases the cost of the liquid crystal panel.
Disclosure of Invention
The embodiment of the invention provides a driving circuit and a driving method of liquid crystal display equipment, which are used for controlling direct current bias on a liquid crystal panel of the liquid crystal display equipment to enable the direct current bias on the liquid crystal panel to keep a self-balancing state in a certain period, thereby eliminating image residue and improving the display quality of the liquid crystal panel.
A drive circuit of a liquid crystal display device comprises a time schedule controller and a source electrode driver, wherein the time schedule controller is electrically connected with the source electrode driver;
the time sequence controller comprises a gamma curve adjusting module, a time sequence control module and a polarity control module;
the gamma curve adjusting module is used for acquiring a jitter data output period in the frame rate control process according to a preset jitter control table;
the timing control module is used for providing a polarity inversion control signal, is connected between the timing control module and the source driver, and is used for controlling the polarity inversion control signal to be inverted between any two adjacent jitter data output periods according to a preset reference signal;
the source driver is used for outputting data voltage with corresponding polarity to the liquid crystal panel under the control of the polarity inversion control signal, so that the data voltage on the liquid crystal panel has balanced direct current bias voltage in any two adjacent jitter data output periods.
The preset reference signal comprises an enable signal and a disable signal, the preset reference signal alternates between the enable signal and the disable signal between any two adjacent jitter data output periods, if the preset reference signal is the enable signal, the polarity control module is enabled, the polarity inversion control signal is inverted when passing through the polarity control module, if the preset reference signal is the disable signal, the polarity control module is disabled, and the phase of the polarity inversion control signal is kept unchanged when passing through the polarity control module.
Wherein if the phase of the polarity inversion control signal is kept unchanged, the polarity of the data voltage output by the source driver changes following the change of the polarity inversion control signal, if the polarity inversion control signal is inverted, the polarity of the data voltage output by the source driver changes following the change of the polarity of the inverted polarity inversion control signal, and the phases of the data voltages output by the source driver are opposite in any two adjacent jitter data output periods.
The shaking data output period in the frame rate control process comprises a plurality of frame periods, and the data voltages of the last frame period of the current shaking data output period and the first frame period of the next shaking data output period have the same column inversion polarity arrangement.
The gamma curve adjusting module is further used for generating a modified jitter control table according to the preset jitter control table and outputting jitter data voltage to the liquid crystal panel according to the modified jitter control table; wherein the modified jitter control table has opposite phases of jitter data in any two adjacent output periods of jitter data.
A driving method of a liquid crystal display device, comprising:
acquiring a jitter data output period in the frame rate control process according to a preset jitter control table;
acquiring a polarity inversion control signal provided by a time schedule controller for a source electrode driver, and controlling the polarity inversion control signal to be inverted between any two adjacent jitter data output periods according to a preset reference signal;
and outputting the data voltage with the corresponding polarity to the liquid crystal panel according to the polarity inversion control signal so that the data voltage on the liquid crystal panel has balanced direct current bias voltage in any two adjacent jitter data output periods.
The preset reference signal comprises an enable signal and a disable signal, and the control of the polarity inversion control signal to reverse between any two adjacent jitter data output periods according to the preset reference signal comprises:
if the preset reference signal is an enable signal, the polarity control module is enabled, and the polarity inversion control signal is inverted when passing through the polarity control module;
if the preset reference signal is a prohibition signal, the polarity control module is prohibited, and the phase of the polarity inversion control signal is kept unchanged when the polarity inversion control signal passes through the polarity control module;
wherein the preset reference signal alternates between the enable signal and the disable signal between any two adjacent jitter data output periods.
If the phase of the polarity inversion control signal is kept unchanged, the polarity of the data voltage output by the source driver changes along with the change of the polarity inversion control signal;
if the polarity inversion control signal is inverted, the polarity of the data voltage output by the source driver is changed following the change of the polarity of the inverted polarity inversion control signal;
in any two adjacent jitter data output periods, the phases of the data voltages output by the source driver are opposite.
The shaking data output period in the frame rate control process comprises a plurality of frame periods, and the data voltages of the last frame period of the current shaking data output period and the first frame period of the next shaking data output period have the same column inversion polarity arrangement.
After acquiring the jitter data output period in the frame rate control process according to the preset jitter control table, the method further includes:
generating a modified jitter control table according to the preset jitter control table;
outputting a dithering data voltage to the liquid crystal panel according to the modified dithering control table;
wherein the modified jitter control table has opposite phases of jitter data in any two adjacent output periods of jitter data.
The driving circuit and the driving method of the liquid crystal display device control the polarity inversion control signal to be inverted between any two adjacent jitter data output periods by acquiring the jitter data output period in the frame rate control process, so that the data voltage on the liquid crystal panel of the liquid crystal display device has balanced direct current bias in any two adjacent jitter data output periods, namely the direct current bias on the liquid crystal panel keeps a self-balancing state in a plurality of frame periods corresponding to any two adjacent jitter periods, thereby effectively eliminating image retention caused by the direct current bias existing in the liquid crystal panel for a long time and further improving the display quality of the liquid crystal panel.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a driving circuit of a liquid crystal display device according to an embodiment of the present invention;
FIG. 2 is a data polarity distribution diagram of a preset jitter control table applied to the driving circuit shown in FIG. 1;
FIG. 3 is a first waveform diagram of a polarity inversion control signal of the driving circuit shown in FIG. 1;
FIG. 4 is a diagram of a first waveform of a data voltage of the driving circuit shown in FIG. 1;
FIG. 5 is a diagram illustrating a second waveform of a polarity inversion control signal of the driving circuit shown in FIG. 1;
FIG. 6 is a diagram of a second waveform of the data voltage of the driving circuit shown in FIG. 1;
FIG. 7 is a data polarity profile of a modified dither control table applied to the drive circuit of FIG. 1;
fig. 8 is a flowchart illustrating a driving method of a liquid crystal display device according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Spatially relative terms such as "below …", "below …", "below", "above …", "above", and the like may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present.
It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Further, the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Referring to fig. 1, in an embodiment of the present invention, a driving circuit 100 of a liquid crystal display device is provided, including a timing controller 110 and a source driver 130, wherein the timing controller 110 is electrically connected to the source driver 130.
The timing controller 110 includes an LVDS receiving interface module 111, a gamma curve adjusting module 112, a processing module 113, a mini-LVDX transmitting interface module 115, a timing control module 117, and a polarity control module 119. The LVDS receiving interface module 111 is configured to receive a Low Voltage Differential Signaling (LVDS) input signal including image or video information, where the low voltage differential input signal is processed by the gamma curve adjusting module 112 to perform gamma correction and the processing module 113 to perform gray-scale modulation, and then generates a corresponding data signal and a clock signal, and is further sent to the source driver 130 by the mini-LVDX sending interface module 115, so as to control the source driver 130 to output a corresponding data voltage according to the clock signal to drive a liquid crystal panel of the liquid crystal display device to perform image or video display. In this embodiment, the Gamma curve adjusting module 113 performs Gamma curve adjustment on three colors of red, green and blue through Temporal Dithering (Temporal Dithering) and Spatial Dithering (Spatial Dithering) of Frame Rate Control (FRC), and obtains a Dithering data output period in a Frame Rate Control process according to a preset Dithering Control table.
The timing control module 117 is configured to provide a polarity inversion control signal POL for controlling the source driver 130 to output a data voltage with inverted polarity and a source driving enable signal TP for enabling a data output function of the source driver 130. The polarity control module 119 is connected between the timing control module 117 and the source driver 130, and configured to control the polarity inversion control signal to invert between any two adjacent jitter data output periods according to a preset reference signal. The source driver 130 is configured to output a data voltage with a corresponding polarity to the liquid crystal panel under the control of the polarity inversion control signal, so that the data voltage on the liquid crystal panel has a balanced dc bias voltage in any two adjacent jittered data output periods.
Specifically, as shown in fig. 2, it is assumed that the preset jitter control Table is a 2 × 2 jitter control Table (dither Table), the LVDS receiving interface module 111 receives an 8-bit input signal, and the mini-LVDX sending interface module 115 outputs an 8-bit output signal.
Since the voltage-transmittance curves of the three colors of red, green and blue are not consistent, if the timing controller 110 receives an input signal of 127 gray scales, the output data of the three colors of red, green and blue need to be adjusted to solve the problem of color distortion. In the present embodiment, it is assumed that the gray levels of the output data of three colors of red, green and blue are 127.25, 127.75 and 127.5, respectively. The 8-bit input signal and the 8-bit output signal determine that the data volume input and output by the timing controller 110 is the same, and in order to obtain the non-integer gray scale output signals of 127.25, 127.75 and 127.5, the timing controller 110 adopts FRC to realize that the liquid crystal panel can output the non-integer gray scale at any time through spatialDither; meanwhile, in order to solve the problem that the data of different positions of the liquid crystal panel in a whole picture is different due to the fact that Spatial heat forms a gray scale picture, the Temporal heat is simultaneously used by the timing controller 110.
In this embodiment, 127.25 gray-scale output is taken as an example for explanation. As can be seen from the preset jitter control table shown in fig. 2, the 127.25 gray level output uses the LSB1(Least significant bit) jitter control table to output jitter data to the source driver 130 in a period of 4 frames. Referring to the pixel row 2 and pixel column 2 positions in the preset dither control table shown in fig. 2, the dither data of LSB1 is 0, 1, and is output in a period of 4 frames. Assuming that the liquid crystal panel Inversion driving method is Column Inversion (Column Inversion), and the waveforms of the corresponding polarity Inversion control signals are as shown in fig. 3, the polarities of the pixel row 2 and Column 2 positions are negative, positive, negative, and positive …, the jitter data are 0, and 1, and the period of 4 frames of the screen is taken as a cycle. The waveform of the data voltage outputted by the source driver 130 is shown in fig. 4, where Vcom is a common voltage.
As can be seen from fig. 4, the output of the source driver 130 has the same voltage amplitude and the opposite polarity in the frame F _ N and the frame F _ N +1, the opposite polarity in the frame F _ N +2 and the frame F _ N +3, and the negative polarity amplitude in the frame F _ N +2 is smaller than the positive polarity in the frame F _ N + 3; the frame F _ N +4 has the same voltage amplitude as the frame F _ N +5, the frame F _ N +6 has the same polarity as the frame F _ N +7, and the frame F _ N +6 has a negative polarity amplitude smaller than the positive polarity of the frame F _ N +7, i.e. there is a forward dc bias voltage in the data voltage output by the source driver 130. If a forward bias is applied to the pixel electrode of the liquid crystal panel, i.e. the liquid crystal, for a long time, the liquid crystal will be degraded to form image sticking, and the image display quality of the liquid crystal panel will be reduced. In order to solve the problems of image retention and reduction of the display quality of the liquid crystal panel caused by the existence of the direct current bias voltage, the embodiment of the invention controls the polarity inversion control signal to be inverted between any two adjacent jitter data output periods by acquiring the jitter data output period in the frame rate control process, so that the direct current bias voltage on the liquid crystal panel keeps a self-balancing state in a plurality of frame periods corresponding to any two adjacent jitter periods, thereby effectively eliminating the image retention caused by the long-time existence of the direct current bias voltage in the liquid crystal panel and further improving the display quality of the liquid crystal panel.
Specifically, before sending the polarity inversion control signal to the source driver 130, the timing control module 117 performs polarity processing through the polarity control module 119 connected between the timing control module 117 and the source driver 130, so that the polarity inversion control signal is inverted between any two adjacent jitter data output periods. If the polarity inversion control signal input to the polarity control module 119 is denoted as POL _ input, the polarity inversion control signal Output by the polarity control module 119 is denoted as POL _ Output, the preset reference signal of the polarity control module 119 is denoted as POL _ C, and POL _ C includes an enable signal (e.g., a low level signal L) and a disable signal (e.g., a high level signal H), then:
when POL _ C is the disable signal, the polarity control module 119 controls the POL _ Output signal to be consistent with the POL _ input signal, that is, the polarity control module 119 is disabled, and the phase of the polarity inversion control signal is kept unchanged when the polarity inversion control signal passes through the polarity control module 119.
When POL _ C is an enable signal, the polarity control module 119 controls the POL _ Ouput signal to perform phase inversion with POL _ Input, that is, the polarity control module 119 is enabled, and the polarity inversion control signal is inverted when passing through the polarity control module 119.
It is to be understood that, in order to invert the polarity inversion control signal between any two adjacent shaking data output periods, the preset reference signal alternates between the enable signal and the disable signal between any two adjacent shaking data output periods. In this embodiment, the switching of the preset reference signal takes 4 frames of picture time as a period, and in one 4 frames of picture time, the preset reference signal is an inhibit signal, and the polarity control module 119 controls the POL _ Output signal to be consistent with the POL _ input signal; in the next 4-frame picture time, the preset reference signal is an enable signal, and the polarity control module 119 controls the POL _ Ouput signal and the POL _ Input to perform phase inversion.
It is understood that the control logic of the polarity control module 119 may also be: when the POL _ C is an inhibit signal (e.g., a high level signal H), the polarity control module 119 is inhibited, and the phase of the polarity inversion control signal is kept unchanged when the polarity inversion control signal passes through the polarity control module 119, i.e., the polarity control module 119 controls the POL _ Output signal to be consistent with the POL _ input signal; when the POL _ C is an enable signal (e.g., a low level signal L), the polarity control module 119 is enabled, the polarity control module 119 controls the POL _ Output signal to alternate between keeping the POL _ input signal consistent and inverting the phase of the POL _ input signal with a period of 4 frame picture time, and a specific control logic is shown in table 1, where F _ N, F _ N +1, …, and F _ N +7 represent 8 consecutive frame periods.
TABLE 1 control logic for polarity control module 119
Figure BDA0001137396490000081
The waveform of the polarity inversion control signal processed by the polarity control module 119 is shown in fig. 5, and as can be seen from fig. 5, the phases of the polarity inversion control signal in the first four frame periods are opposite to those in the last four frame periods. Accordingly, if the phase of the polarity inversion control signal is maintained, the polarity of the data voltage output from the source driver 130 changes in accordance with the change in the polarity of the polarity inversion control signal, and if the polarity inversion control signal is inverted, the polarity of the data voltage output from the source driver 130 changes in accordance with the change in the polarity of the inverted polarity inversion control signal, and the phases of the data voltages output from the source driver are inverted in any two adjacent dither data output periods.
In this embodiment, the output voltage waveform of the source driver 130 is shown in fig. 6, where Vcom is a common voltage. Specifically, the output of the source driver 130 has opposite polarity and same voltage amplitude as F _ N +1 at F _ N, F _ N +2 has opposite polarity to F _ N +3, and F _ N +2 has negative polarity amplitude smaller than F _ N +3 positive polarity; f _ N +4 and F _ N +5 have opposite polarities and the same voltage amplitude, F _ N +6 and F _ N +7 have opposite polarities, and the positive polarity amplitude of F _ N +6 is smaller than the negative polarity of F _ N + 7. Therefore, the direct current bias voltage of the liquid crystal voltage on the liquid crystal panel is self-balanced in every 8 frame periods (namely any two adjacent jitter data output periods), so that the liquid crystal can be prevented from being applied with the direct current bias voltage for a long time, the image retention caused by the direct current bias voltage existing in the liquid crystal panel for a long time can be effectively eliminated, and the display quality of the liquid crystal panel is improved.
It can be understood that, since the polarity inversion control signal is inverted between any two adjacent output periods of the dithering data, the dithering control table of the gamma curve adjusting module 113 during the gamma curve adjustment through the frame rate control needs to be modified correspondingly on the basis of the preset dithering control table shown in fig. 2, and the modified dithering control table is shown in fig. 7. As can be seen from fig. 7, the shaking data output period in the frame rate control process includes a plurality of frame periods (4 frame periods in the present embodiment), and the data voltages of the last frame period of the current shaking data output period and the first frame period of the next shaking data output period have the same column inversion polarity arrangement, while the shaking data phases in any two adjacent shaking data output periods of the modified shaking control table are opposite. After generating a modified dithering control table according to the preset dithering control table, the gamma curve adjusting module 113 further outputs a dithering data voltage to the liquid crystal panel according to the modified dithering control table, thereby implementing gamma curve adjustment.
Referring to fig. 8, in an embodiment of the present invention, a method for driving a liquid crystal display device is provided, including:
step 801: acquiring a jitter data output period in the frame rate control process according to a preset jitter control table;
step 802: acquiring a polarity inversion control signal provided by a time schedule controller for a source electrode driver, and controlling the polarity inversion control signal to be inverted between any two adjacent jitter data output periods according to a preset reference signal;
step 803: and outputting the data voltage with the corresponding polarity to the liquid crystal panel according to the polarity inversion control signal so that the data voltage on the liquid crystal panel has balanced direct current bias voltage in any two adjacent jitter data output periods.
The preset reference signal comprises an enable signal and a disable signal, and the control of the polarity inversion control signal to reverse between any two adjacent jitter data output periods according to the preset reference signal comprises:
if the preset reference signal is an enable signal, the polarity control module is enabled, and the polarity inversion control signal is inverted when passing through the polarity control module;
if the preset reference signal is a prohibition signal, the polarity control module is prohibited, and the phase of the polarity inversion control signal is kept unchanged when the polarity inversion control signal passes through the polarity control module;
wherein the preset reference signal alternates between the enable signal and the disable signal between any two adjacent jitter data output periods.
If the phase of the polarity inversion control signal is kept unchanged, the polarity of the data voltage output by the source driver changes along with the change of the polarity inversion control signal;
if the polarity inversion control signal is inverted, the polarity of the data voltage output by the source driver is changed following the change of the polarity of the inverted polarity inversion control signal;
in any two adjacent jitter data output periods, the phases of the data voltages output by the source driver are opposite.
The shaking data output period in the frame rate control process comprises a plurality of frame periods, and the data voltages of the last frame period of the current shaking data output period and the first frame period of the next shaking data output period have the same column inversion polarity arrangement.
After acquiring the jitter data output period in the frame rate control process according to the preset jitter control table, the method further includes:
generating a modified jitter control table according to the preset jitter control table;
outputting a dithering data voltage to the liquid crystal panel according to the modified dithering control table;
wherein the modified jitter control table has opposite phases of jitter data in any two adjacent output periods of jitter data.
It can be understood that specific implementation of each step in the driving method of the liquid crystal display device may also refer to related description in the embodiments of the driving circuit shown in fig. 1 to fig. 7, and details are not described here again.
The driving circuit and the driving method of the liquid crystal display device control the polarity inversion control signal to be inverted between any two adjacent jitter data output periods by acquiring the jitter data output period in the frame rate control process, so that the data voltage on the liquid crystal panel of the liquid crystal display device has balanced direct current bias in any two adjacent jitter data output periods, namely the direct current bias on the liquid crystal panel keeps a self-balancing state in a plurality of frame periods corresponding to any two adjacent jitter periods, thereby effectively eliminating image retention caused by the direct current bias existing in the liquid crystal panel for a long time and further improving the display quality of the liquid crystal panel.
It should be understood that the above-described embodiments are merely exemplary of the present invention, and should not be construed as limiting the scope of the present invention, but rather as embodying all or part of the above-described embodiments and equivalents thereof as may be made by those skilled in the art, and still fall within the scope of the invention as claimed.

Claims (8)

1. The driving circuit of the liquid crystal display device is characterized by comprising a time schedule controller and a source electrode driver, wherein the time schedule controller is electrically connected with the source electrode driver;
the time sequence controller comprises a gamma curve adjusting module, a time sequence control module and a polarity control module;
the gamma curve adjusting module is used for acquiring a jitter data output period in the frame rate control process according to a preset jitter control table;
the timing control module is used for providing a polarity inversion control signal, is connected between the timing control module and the source driver, and is used for controlling the polarity inversion control signal to be inverted between any two adjacent jitter data output periods according to a preset reference signal;
the source driver is used for outputting data voltage with corresponding polarity to the liquid crystal panel under the control of the polarity inversion control signal, so that the data voltage on the liquid crystal panel has balanced direct current bias voltage in any two adjacent jitter data output periods;
the preset reference signal comprises an enable signal and a disable signal, the preset reference signal alternates between the enable signal and the disable signal between any two adjacent jitter data output periods, if the preset reference signal is the enable signal, the polarity control module is enabled, the polarity inversion control signal is inverted when passing through the polarity control module, if the preset reference signal is the disable signal, the polarity control module is disabled, and the phase of the polarity inversion control signal is kept unchanged when passing through the polarity control module.
2. The driving circuit according to claim 1, wherein if the phase of the polarity inversion control signal is kept constant, the polarity of the data voltage outputted from the source driver changes in accordance with the change in the polarity of the polarity inversion control signal, and if the polarity inversion control signal is inverted, the polarity of the data voltage outputted from the source driver changes in accordance with the change in the polarity of the inverted polarity inversion control signal, and the phases of the data voltages outputted from the source driver are opposite in any two adjacent dither data output periods.
3. The drive circuit according to claim 1, wherein the shaking data output period in the frame rate control process includes a plurality of frame periods, and the data voltages of the last frame period of the current shaking data output period and the first frame period of the next shaking data output period have the same column inversion polarity arrangement.
4. The driving circuit of claim 1, wherein the gamma curve adjustment module is further configured to generate a modified dithering control table according to the preset dithering control table, and output a dithering data voltage to the liquid crystal panel according to the modified dithering control table; wherein the modified jitter control table has opposite phases of jitter data in any two adjacent output periods of jitter data.
5. A driving method of a liquid crystal display device, comprising:
acquiring a jitter data output period in the frame rate control process according to a preset jitter control table;
acquiring a polarity inversion control signal provided by a time schedule controller for a source electrode driver, and controlling the polarity inversion control signal to be inverted between any two adjacent jitter data output periods according to a preset reference signal;
outputting data voltage with corresponding polarity to the liquid crystal panel according to the polarity inversion control signal so that the data voltage on the liquid crystal panel has balanced direct current bias voltage in any two adjacent jitter data output periods;
the preset reference signal comprises an enable signal and a disable signal, and the control of the polarity inversion control signal to reverse phase between any two adjacent jitter data output periods according to the preset reference signal comprises:
if the preset reference signal is an enabling signal, the polarity control module is enabled, and the polarity inversion control signal is inverted when passing through the polarity control module;
if the preset reference signal is a prohibition signal, the polarity control module is prohibited, and the phase of the polarity inversion control signal is kept unchanged when the polarity inversion control signal passes through the polarity control module;
wherein the preset reference signal alternates between the enable signal and the disable signal between any two adjacent jitter data output periods.
6. The method of claim 5, wherein if the phase of the polarity inversion control signal remains unchanged, the polarity of the data voltage output by the source driver changes following the change of the polarity inversion control signal;
if the polarity inversion control signal is inverted, the polarity of the data voltage output by the source driver is changed following the change of the polarity of the inverted polarity inversion control signal;
in any two adjacent jitter data output periods, the phases of the data voltages output by the source driver are opposite.
7. The method of claim 5, wherein the shaking data output period in the frame rate control process includes a plurality of frame periods, and the data voltages of the last frame period of the current shaking data output period and the first frame period of the next shaking data output period have the same column inversion polarity arrangement.
8. The method of claim 5, wherein after acquiring the jitter data output period in the frame rate control process according to the preset jitter control table, the method further comprises:
generating a modified jitter control table according to the preset jitter control table;
outputting a dithering data voltage to the liquid crystal panel according to the modified dithering control table;
wherein the modified jitter control table has opposite phases of jitter data in any two adjacent output periods of jitter data.
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