TWI417867B - Liquid crystal display device - Google Patents

Description

LCD Monitor

The present invention relates to a liquid crystal display, and more particularly to a liquid crystal display capable of improving the phenomenon of shutdown afterimage, a liquid crystal display capable of improving the phenomenon of starting image sticking, and a liquid crystal display capable of improving the phenomenon of turning on the afterimage and turning off the image after shutdown.

Due to its small size, light weight, thin thickness, low power consumption, no flicker, and low radiation, liquid crystal displays have been widely used in electronic devices such as televisions, notebook computers, mobile phones, and personal digital assistants.

However, in the liquid crystal display and related products, when the external power source is turned on, since the source driver of the liquid crystal display does not reach the voltage during normal operation, the logic function inside the source driver does not function, and the source driver internal The data latch randomly captures the image data, and the image data is converted into a data voltage accordingly. Because the image data captured by the source driver is random, the data voltage corresponding to the output is also random, and the data voltage of the liquid crystal panel outputted to the liquid crystal display is inconsistent. The picture displayed by the liquid crystal panel driven by the data voltage may appear as a vertical bright line, that is, the phenomenon of booting afterimage.

In addition, when the external power source is turned off, a large amount of residual charge in the liquid crystal panel cannot be released in time, and there is still residual image on the liquid crystal panel after the shutdown, that is, the phenomenon of shutdown and afterimage. The phenomenon of power-on afterimage or/and the phenomenon of the after-image of the shutdown affect the display quality of the liquid crystal display.

In view of this, it is necessary to provide a liquid crystal display capable of effectively improving the phenomenon of shutdown afterimage.

In view of this, it is necessary to provide a liquid crystal display capable of effectively improving the phenomenon of booting afterimage.

In view of this, it is necessary to provide a liquid crystal display capable of effectively improving the phenomenon of burn-in afterimage and the phenomenon of shutdown afterimage.

A liquid crystal display comprising: a liquid crystal panel comprising a common electrode, a plurality of pixel electrodes, and liquid crystal molecules sandwiched between the plurality of pixel electrodes and the common electrode; and a timing controller that receives the image signal and according to the figure The signal driver generates a timing signal and a data signal; the data driver receives the timing signal and the data signal to form a plurality of data voltages; and the power circuit provides a power voltage to the data driver and the timing controller; the liquid crystal display is normal When displayed, the data driver provides the data voltage to the plurality of pixel electrodes. When the liquid crystal display is turned off, the data driver provides a predetermined voltage to the plurality of pixel electrodes to display the same grayscale image.

A liquid crystal display comprising: a liquid crystal panel comprising a common electrode, a plurality of pixel electrodes, and liquid crystal molecules sandwiched between the plurality of pixel electrodes and the common electrode; and a timing controller that receives the image signal and according to the figure The signal driver generates a timing signal and a data signal; the data driver receives the timing signal and the data signal to form a plurality of data voltages; and the power circuit provides a power voltage to the data driver and the timing controller; and the liquid crystal display is powered on The data driver provides a predetermined voltage to the plurality of pixel electrodes to display the same grayscale picture in an instant until the timing controller provides the timing signal and the data signal to the data driver.

A liquid crystal display comprising: a liquid crystal panel comprising a common electrode, a plurality of pixel electrodes, and liquid crystal molecules sandwiched between the plurality of pixel electrodes and the common electrode; and a timing controller that receives the image signal and according to the figure The signal driver generates a timing signal and a data signal; the data driver receives the timing signal and the data signal to form a plurality of data voltages; and the power circuit provides a power voltage to the data driver and the timing controller; and the liquid crystal display is powered on Instantly until the timing controller begins to provide the timing signal and the data signal to the data driver, the data driver provides a first preset voltage to the plurality of pixel electrodes to display the same grayscale picture; When the display is turned off, the data driver provides a second preset voltage to the plurality of pixel electrodes to display the same grayscale picture.

Compared with the prior art, the data driver of the liquid crystal display of the present invention supplies the preset voltage to the plurality of pixel electrodes when the power is turned off, so that the clamping pressure of the liquid crystal molecules is the same, and accordingly, the liquid crystal display is turned off. The same grayscale picture is displayed until the residual charge in the liquid crystal panel is released. Further, the shutdown phenomenon of the liquid crystal display is solved.

Compared with the prior art, since the data driver supplies the preset voltage to the plurality of pixel electrodes before the timing controller outputs the timing signal and the data signal to the data driver, the data driver can avoid the data. The driver outputs a random grabped data voltage to the complex pixel electrode. Correspondingly, the clamping of the two ends of the liquid crystal molecules is the same, and the liquid crystal display displays the same gray scale picture when it is turned on. Further, the phenomenon of booting afterimage of the liquid crystal display is solved.

Compared with the prior art, the data driver provides a first preset voltage to the plurality of pictures during the period from the start of the liquid crystal display to the time when the timing controller starts to provide the timing signal and the data signal to the data driver. The pixel electrode displays the same gray scale picture, so that the data driver can prevent the data driver from outputting the randomly grabbed data voltage to the plurality of pixel electrodes; further, when the liquid crystal display is turned off, the data driver provides a second preset voltage to The plurality of pixel electrodes display the same grayscale image until The residual charge remaining in the liquid crystal panel is released. Furthermore, the phenomenon of the afterimage of the liquid crystal display and the phenomenon of shutdown afterimage are solved.

Please refer to FIG. 1. FIG. 1 is a schematic structural view of a first embodiment of a liquid crystal display according to the present invention. The liquid crystal display 100 is a normally black liquid crystal display including a liquid crystal panel 110, a driving circuit 130 for driving the liquid crystal panel 110, a power supply circuit 150 for supplying the operating power to the driving circuit 130, and a A common voltage generating circuit 170 for supplying a common voltage to the liquid crystal panel 110.

The liquid crystal panel 110 includes a plurality of parallel scan lines 102, a plurality of data lines 104 parallel to each other and insulated from the complex scan lines 102, and a plurality of thin film transistors 108 and a plurality of traces at the intersection of the scan lines 102 and the data lines 104. The pixel electrode 111, the plurality of common electrodes 112, and the plurality of storage capacitors 116. The pixel electrode 111, the common electrode 112, and liquid crystal molecules (not shown) therebetween constitute a plurality of liquid crystal capacitors 114. The liquid crystal capacitor 114 is connected in parallel with the storage capacitor 116. A gate (not labeled) of the thin film transistor 108 is coupled to the scan line 102, a source (not labeled) is coupled to the data line 104, and a gate (not labeled) is coupled to the pixel electrode 111. The common electrode 112 is connected to the common voltage generating circuit 170. The minimum area surrounded by the scan line 102 and the data line 104 is defined as a pixel 106.

The driving circuit 130 includes a timing controller 132, a scan driver 134 and a data driver 136. The common voltage generating circuit 170 is also coupled to the data driver 136 to provide the common voltage to the data driver 136. The timing controller 132 is configured to receive an image data provided by an external circuit 115, and generate a timing signal and a data signal (eg, an RGB signal) according to the image data, and provide the timing signal to the data driver 136 and the The scan driver 134 controls the operation timing of the data driver 136 and the scan driver 134, and provides the data signal to the data driver 136. The scan driver 134 receives the timing signal and outputs the sequence A series of scan pulses are applied to the scan line 102. The data driver 136 receives the common voltage, the data signal and the timing signal, and converts the data signal into a plurality of data voltages. Before the liquid crystal display 100 is turned off, the data driver 136 selects an output data voltage according to the timing signal to the pixel electrode 111; when the liquid crystal display 100 is turned off, the data driver 136 selects to output a common voltage to the pixel electrode 111.

Please refer to FIG. 2. FIG. 2 is a partial structural diagram of the data driver 136 of the liquid crystal display device 100 of FIG. The data driver 136 includes a data processing circuit 120, a control circuit 121, a voltage processing circuit 123, a signal input terminal 124, a first voltage input terminal 125, a second voltage input terminal 126, and a voltage output terminal 127. The data processing circuit 120 is electrically connected to the signal input terminal 124 and the control circuit 121, respectively. The voltage processing circuit 123 is electrically connected to the second voltage input terminal 126 and the control circuit 121, respectively. The control circuit 121 is further electrically connected to the first voltage input terminal 125 and the voltage output terminal 127 to cooperate with the voltage processing circuit 123 to control the output of the data driver 136 before and during shutdown of the liquid crystal display device 100. status. The control circuit 121 includes a first switch 128 and a second switch 129. The first switch 128 is electrically connected to the data processing circuit 120 and the voltage output terminal 127, respectively. The second switch 129 is electrically connected to the first voltage input terminal 125 and the voltage output terminal 127, respectively.

The data processing circuit 120 receives the data signal and the timing signal outputted by the timing controller 132 by the signal input terminal 124, converts the data signal into a data voltage, and outputs the data voltage to the control circuit 121 according to the timing signal. The common voltage generated by the common voltage generating circuit 170 is transmitted to the control circuit 121 via the first voltage input terminal 125. The power supply voltage Vcc supplied from the power circuit 150 to the data driver 136 is transmitted to the voltage processing circuit 123 via the second voltage input terminal 126. The voltage processing circuit 123 correspondingly outputs different control signals to the control circuit 121 according to the magnitude of the received power supply voltage Vcc. The control circuit 121 The first switch 128 and the second switch 129 are controlled to be turned on or off according to the corresponding control signal received, thereby controlling whether the data driver 136 outputs the data voltage or outputs the common voltage to the voltage output terminal 127.

Please refer to FIG. 3. FIG. 3 is a schematic structural diagram of an embodiment of a voltage processing circuit 123 of the data driver 136 of FIG. The voltage processing circuit 123 includes a comparator 141 and a reference voltage generating circuit 142. The comparator 141 includes a positive phase input terminal 143, a negative phase input terminal 144 and an output terminal 145. The positive phase input terminal 143 is coupled to the power supply circuit 150. The negative phase input terminal 144 is coupled to the reference voltage generating circuit 142, and the output terminal 145 is coupled to the control circuit 121. When the liquid crystal display 100 is operating normally, the reference voltage generating circuit 142 outputs a reference voltage REF to the negative phase input terminal 144, and the power supply circuit 150 outputs the power supply voltage Vcc to the positive phase input terminal 143. The comparator 141 outputs a first control signal C1 and a second control signal C2 by comparing the power supply voltage Vcc with the reference voltage REF. When the power supply voltage Vcc is greater than the reference voltage REF, the output 145 of the comparator 141 outputs the second control signal C2. When the power supply voltage Vcc is equal to or less than the reference voltage REF, the output terminal 145 of the comparator 141 outputs the first control signal C1.

The reference voltage generating circuit 142 includes a first resistor 146, a second resistor 147, a capacitor 148, and a diode 149. The anode of the diode 149 is coupled to an external DC power source 105, the cathode of which is coupled to the negative phase input terminal 144 by the first resistor 146. The second resistor 147 is connected in parallel with the capacitor 148 between the diode 149 and the ground. This capacitor 148 is used for voltage regulation. The diode 149 has only a forward conduction function to prevent voltage backflow. The DC voltage outputted by the external DC power source 105 is generated by the diode 149 and the first resistor 146 to generate the reference voltage REF, and is output to the negative phase input terminal 144.

By appropriately setting the resistance values of the first and second resistors 146 and 147, and selecting a capacitor 148 having a large capacitance value (for example, 20 microfarads), it is required to provide a significantly smaller than that required for the data driver 136 to operate normally. Power supply voltage The reference voltage REF of Vcc, such as the reference voltage REF, is eighty percent of the power supply voltage Vcc required for the data driver 136 to operate normally. Before the liquid crystal display 100 is turned off, the power supply voltage Vcc is greater than the reference voltage REF. Accordingly, the comparator 141 outputs the second control signal C2 to the control circuit 121 to control the second switch 129 to be turned on. The first switch 128 is turned off, so that the data voltage is output to the complex pixel electrode 111 via the voltage output terminal 127. When the liquid crystal display 100 is turned off, the power supply voltage Vcc is powered off faster, and since the capacitance 148 having a larger capacitance value stores more charge, the diode 149 has only a forward conduction function. When the liquid crystal display is turned off, the power supply voltage Vcc is rapidly decreased to be equal to and rapidly lower than the reference voltage REF, and the comparator 141 outputs the first control signal C1 to the control circuit 121 to control the first switch 128 to be turned on. The second switch 129 is turned off, so that the common voltage is output to the complex pixel electrode 111 via the voltage output terminal 127, and the voltage of the pixel electrode 111 and the common electrode 112 are the same, thereby causing the liquid crystal display 100 to display when the power is turned off. Black screen.

Further, in order to better understand the implementation of the present invention, the working principle of the liquid crystal display 100 will be described below with reference to FIGS. 1-3 as follows: When the liquid crystal display device 100 is in a normal working period, the power supply circuit 150 first supplies a power supply voltage Vcc to the timing controller 132, the data driver 136, and the scan driver 134 to the timing controller 132, the data driver 136, and The scan driver 134 is powered. The common voltage generating circuit 170 provides a common voltage to the data driver 136 and the common electrode 112. The external DC power source 105 provides a DC power supply to the reference voltage generating circuit 142. The external circuit 115 then provides image data to the timing controller 132.

The timing controller 132 generates a timing signal and a data signal according to the image data, and supplies the timing signal to the data driver 136 and the scan driver 134 to control the working timing of the data driver 136 and the scan driver 134, and The data signal is provided to the data driver 136 Data processing circuit 120. The data processing circuit 120 converts the received data signal into a corresponding data voltage, and outputs the data voltage to the control circuit 121. The common voltage supplied from the common voltage generating circuit 170 to the data driver 136 is also output to the control circuit 121.

After the DC voltage is supplied to the reference voltage generating circuit 142, the diode 149 is turned on. Further, the DC voltage charges the capacitor 148, and is divided by the first resistor 146 to output a reference voltage REF to the negative voltage. Phase input 144. The power supply circuit 150 supplies the power supply voltage Vcc to the data driver 136 to the positive phase input terminal 143. At this time, the power supply voltage Vcc is greater than the reference voltage REF, and the comparator 141 outputs a second control signal C2 to the Control circuit 121. The control circuit 121 controls the second switch 129 to be turned on according to the second control signal C2, and controls the first switch 128 to be turned off, so that the control circuit 121 outputs the data voltage, and the data voltage is output to the Multiple data lines 104. When the scan driver 134 outputs a scan pulse to the scan line 102 to turn on the thin film transistor 108, the data voltage on the complex data line 104 is output to the complex pixel electrode 111 by the thin film transistor 108. Further, the liquid crystal panel 110 displays a normal screen.

When the user presses the power on/off button of the liquid crystal display 100 to select to turn off the liquid crystal display 100, the image signal outputted by the external circuit 115 to the timing controller 132 is first cut off, and the power circuit 150, the The external DC power source 105 and the common voltage generating circuit 170 store a certain amount of energy because the internal energy storage device includes a plurality of energy storage devices. Therefore, the power circuit 150, the external DC power source 105, and the common voltage generating circuit 170 do not immediately stop working. When the liquid crystal display 100 is turned off, the reference voltage REF remains substantially unchanged, and the power supply voltage Vcc drops sharply to be equal to and rapidly smaller than the reference voltage REF. Further, the comparator 141 outputs a first control signal C1 to the control. Circuit 121. The control circuit 121 receives the first control signal C1, and controls the first switch 128 to be turned on according to the first control signal C1, and controls the second switch 129 to be turned off, thereby, the control The circuit 121 stops outputting the data voltage and switches to output the common voltage, and the common voltage is output to the complex data line 104 via the voltage output terminal 127. On the other hand, the scan driver 134 outputs a scan pulse to the scan line 102 under the control of a gate full-on signal, and the common voltage on the complex data line 104 is loaded to the complex pixel electrode 111 via the plurality of thin film transistors 108. . Since the common electrode 112 is also loaded with a common voltage at this time, when the liquid crystal display 100 is turned off, the clamping of the liquid crystal molecules at both ends is 0 volts, so that the liquid crystal display 100 always displays a black image until the complex pixel 106 The charge on the top is released.

Since the data driver 136 can provide a common voltage to the plurality of pixels 106 of the liquid crystal panel 110 when the liquid crystal display device 100 is turned off, so that the potentials of the two ends of the plurality of pixels 106 are the same, both of which are 0 volts, the liquid crystal display device 100 The black screen is displayed until the charge on the plurality of pixels 106 of the liquid crystal panel 110 is released, thereby improving the shutdown phenomenon of the liquid crystal display 100.

Further, since the nip of the liquid crystal molecules of the liquid crystal display 100 is 0 volt, the problem of aging of the liquid crystal molecules can be prevented to the utmost.

Further, the voltage processing circuit 123 of the liquid crystal display 100 shown in FIG. 3 can also be replaced with the structure of the voltage processing circuit 223 as shown in FIG. Please refer to FIG. 4. FIG. 4 is a schematic structural diagram of the voltage processing circuit 223. The liquid crystal display 100 having the voltage processing circuit 223 can further improve the phenomenon of booting after the opening, in addition to effectively improving the afterimage of the shutdown.

The voltage processing circuit 223 includes a reset die 224 and a delay circuit 225 coupled to the reset die 224. The reset chip 224 is further connected to the power circuit 150 and the control circuit 121, and can respectively output a first control signal C1 and a second control signal C2 according to the condition of the power supply voltage Vcc. The reset chip 224 is provided with a first reference voltage level and a second reference voltage level. The reset wafer 224 is selected during the startup of the liquid crystal display 100 until the liquid crystal display is in normal operation. The first reference voltage level is used as a reference standard, and when the liquid crystal display 100 is turned off, the reset wafer 224 selects the second reference voltage level as a reference standard. When the liquid crystal display 100 is turned on, the power supply voltage Vcc outputted by the power circuit 150 gradually rises. When the reset chip 224 detects that the power supply voltage Vcc rises to the first reference voltage level, the reset wafer 224 has a certain delay time. The first control signal C1 outputted is then switched to the second control signal C2. The power circuit 150 also charges the delay circuit 225 by the reset chip 224. The delay time of the reset chip 224 is determined by the charging time of the delay circuit 225. When the liquid crystal display 100 is turned off, the power supply voltage Vcc is fast due to the power-down speed. Therefore, the power supply voltage Vcc rapidly drops to the second reference voltage level, and the reset chip 224 corresponds to the second control signal C2 to be output. Switching to the first control signal C1. When the reset chip 224 outputs the first control signal C1, the control circuit 121 receives the first control signal C1 and correspondingly outputs the common voltage to the pixel electrode 111; and when the reset chip 224 outputs the second control signal At C2, the control circuit 121 receives the second control signal C2 and correspondingly outputs the data voltage to the pixel electrode 111. The first reference voltage level is generally greater than the second reference voltage level and is less than the power supply voltage Vcc.

The delay circuit 225 includes a resistor 226 and a capacitor 227. The resistor 226 is connected in series with the capacitor 227 between the reset wafer 224 and the ground. The power circuit charges the capacitor 227 by the reset wafer 224 and the resistor 226 to determine the delay time of the reset wafer 224. The user first measures the time required from the moment when the liquid crystal display 100 is turned on until the timing controller 132 starts outputting the timing signal and the data signal, and measures that the power voltage Vcc rises from 0 volts to the first voltage level. The time required to define the time required for the timing controller 132 to output the timing signal and the data signal from the moment when the liquid crystal display 100 is turned on is the first time interval, and the power supply voltage Vcc is defined to rise from 0 volts to the first time. The time required for the voltage level is the second time interval. In fact, the power supply The time required for the voltage Vcc to rise from 0 volts to the first voltage level is shorter, and the first time interval is significantly greater than the second time interval. Then, the user performs a subtraction operation on the first time interval and the second time interval, and the difference is the delay time of the reset wafer 224. Further, the user can set the delay time required for the reset wafer 224 by adjusting the component parameters of the delay circuit 225. This delay time is preferably 10 microseconds.

The working principle of the liquid crystal display 100 including the voltage processing circuit 223 will be specifically described below with reference to FIG. 1 , FIG. 2 and FIG. 4 : When the user presses the power on/off button of the liquid crystal display 100 to select to turn on the liquid crystal display 100, first, the power circuit 150 provides a power voltage Vcc to the timing controller 132, the data driver 136, and the scan driver 134. And supplying power to the timing controller 132, the data driver 136, and the scan driver 134. The common voltage generating circuit 170 provides a common voltage to the data driver 136 and the common electrode 112. The external circuit 115 then provides image data to the timing controller 132. After the power supply voltage Vcc rises from 0 volts to the first reference voltage level set in the reset wafer 224, the power supply voltage Vcc charges the capacitor 227 by the reset chip 224 and the resistor 226 until the capacitor 227 is charged. Before the completion, the reset chip 224 outputs a first control signal C1 to the control circuit 121. In addition, during this period, the timing controller 132 does not output any signals to the scan driver 134 and the data driver 136. The control circuit 121 controls the first switch 128 to be turned on according to the first control signal C1, and controls the second switch 129 to be turned off. Further, the common voltage is sequentially output to the first switch 128 and the voltage output terminal 127. Multiple data lines 104. The scan driver 134 outputs a scan voltage to the scan line 102. The common voltage applied to the data line 104 is output to the pixel electrode 111 by the thin film transistor 108. Since the voltage on the common electrode 112 is also a common voltage during this period, the clamping of the liquid crystal molecules at both ends is 0 volts, and the liquid crystal display 100 displays a black image. The first control signal C1 is a low voltage, for example, 0 volts.

When the capacitor 227 is fully charged, the timing controller 132 starts outputting the timing signal to the scan driver 134 and the data driver 136, and outputs a data signal to the data driver 136. Further, the liquid crystal display 100 starts to work normally. The data processing circuit 120 receives the data signal and converts the data signal to a corresponding data voltage. At the same time, after the delay time, the reset chip 224 outputs a second control signal C2 to the control circuit 121. The control circuit 121 controls the second switch 129 to be turned on according to the second control signal C2, and controls the first A switch 128 is turned off. Further, the data processing circuit 120 outputs a data voltage to the complex data line 104. The scan driver 134 outputs a scan voltage to the scan line 102. The data voltage on the data line 104 is output to the pixel electrode 111 by the thin film transistor 108. Thereby, the liquid crystal panel 110 displays a normal picture. The second control signal C2 is the power supply voltage Vcc.

When the user presses the power on/off button of the liquid crystal display 100 to select to turn off the liquid crystal display 100, the image signal provided by the external circuit 115 to the timing controller 132 is first cut off, and then the power circuit 150 outputs to the The power supply voltage Vcc of the reset wafer 224 begins to decrease and rapidly drops to the second reference voltage level. The reset wafer 224 again outputs the first control signal C1 to the control circuit 121. The control circuit 121 is configured according to the first The control signal C1 again controls the first switch 128 to be turned on, and controls the second switch 129 to be turned off. Further, the common voltage is again output to the complex data line 104 by the first switch 128 and the voltage output terminal 127, and The thin film transistor 108 is loaded to the pixel electrode 111. Therefore, the voltage on the common electrode 112 is the same as the voltage on the pixel electrode 111, and the clamping of the liquid crystal molecules is 0 volts, so that the liquid crystal display 100 displays a black screen until the plural of the liquid crystal panel 110 The charge on the pixel 106 is released. The second reference voltage level is preferably the reference voltage REF.

Therefore, when the liquid crystal display 100 enters the shutdown period, the data driver 136 supplies a common voltage to the complex pixel electrode 111, so that the liquid The crystal display 100 also displays a black screen when it is turned off until the charge on the plurality of pixels 106 of the liquid crystal panel 110 is released. Thereby, the shutdown phenomenon of the liquid crystal display 100 is improved.

Further, the data driver 136 selects an output during the period from the start of the liquid crystal display 100 to the completion of the charging of the capacitor 227, that is, before the timing controller 132 outputs the normal data signal to the data driver 136. The common voltage is applied to the complex pixel electrode 111 to avoid outputting the data voltage that is randomly captured to the complex pixel electrode 111. Since the nip of the liquid crystal molecules of the liquid crystal display 100 is 0 volts during this period, the liquid crystal display 100 displays a black screen. Thereby, the phenomenon of turning on the image of the liquid crystal display 100 is further improved.

In addition, the liquid crystal display device 100 selects to output a common voltage to the pixel 106 during the startup period until the power supply voltage Vcc reaches a constant value, and when the liquid crystal display device 100 is turned off, so that the liquid crystal molecules are terminated. The nip is 0 volts, thereby maximally preventing the aging of the liquid crystal molecules.

Referring to FIG. 5, the voltage processing circuit 123 can also be replaced with the structure of the voltage processing circuit 323 as shown in FIG.

The voltage processing circuit 323 includes a comparator 324, a reset transistor 325, a delay circuit 326, and a reference voltage generating circuit 327. The comparator 324 includes a positive phase input terminal 328, a negative phase input terminal 329, and an output terminal 330. The power circuit 150 is coupled to the non-inverting input 328 by the reset die 325. The reference voltage generating circuit 327 is connected to the negative phase input terminal 329. The output 330 of the comparator 324 is coupled to the control circuit 121. The delay circuit 326 is coupled between the reset wafer 325 and ground. The structure and function of the reset chip 325 and the delay circuit 326 are substantially the same as the structure and function of the reset chip 224 and the delay circuit 225. The structure and function of the reference voltage generating circuit 327 and the structure of the reference voltage generating circuit 142 and The functions are basically the same.

The liquid crystal display 100 is charged to the delay circuit 326 at the moment of power on. After completion, and when the liquid crystal display 100 is turned off, the reset wafer 325 outputs a low level (eg, 0 volts) to the non-inverting input terminal 328, and the 0 volt voltage is less than the output of the reference voltage generating circuit 327 to the negative phase. The reference voltage REF at input 329. The comparator 324 outputs a first control signal C1 to the control circuit 121 via its output terminal 330. The control circuit 121 controls the first switch 128 to be turned on according to the first control signal C1, and controls the second switch 129 to be turned off. Thus, the control circuit 121 outputs a common voltage which is output to the pixel electrode 111 by the voltage output terminal 127. Further, the liquid crystal display 100 displays a black screen at the time of power-on until the delay circuit 326 is charged and when it is turned off.

When the liquid crystal display device 100 is in normal operation, the reset chip 325 outputs the power supply voltage Vcc to the non-inverting input terminal 328. The power supply voltage Vcc is greater than the reference voltage REF. Accordingly, the comparator 324 outputs a second control signal C2. To the control circuit 121. The control circuit 121 controls the first switch 128 to be turned off according to the second control signal C2, and controls the second switch 129 to be turned on. Therefore, the control circuit 121 outputs a data voltage which is output to the pixel electrode 111 by the voltage output terminal 127. Further, the liquid crystal display 100 displays a normal picture.

Since the second control signal C2 outputted by the reset chip 224 is the power supply voltage Vcc, the maximum value of the power supply voltage Vcc is usually 3.3 volts, and the voltage thereof is small. Therefore, the second control signal C2 outputted by the reset chip 224 is difficult. The control circuit 121 is controlled to turn on or off the two switches 128 and 129. However, the voltage corresponding to the second control signal C2 outputted by the comparator 324 is relatively large. Therefore, the second control signal C2 output by the comparator 324 can control the control circuit 121 relatively easily, and the two switches 128 and 129 can be implemented. Turn on or off. Therefore, the liquid crystal display 100 having the voltage processing circuit 323 has higher operational accuracy.

Please refer to FIG. 6 and FIG. 7. FIG. 6 is a schematic structural view of a second embodiment of the liquid crystal display of the present invention. 7 is a partial structural schematic view of a data driver of the liquid crystal display shown in FIG. 6. The liquid crystal display 400 is also a A normally black liquid crystal display is substantially the same as the liquid crystal display 100 of the first embodiment, and the main difference is that, firstly, the liquid crystal display 400 further includes a preset voltage generating circuit 480, and the preset voltage generating circuit 480 is connected. The data driver 436 is configured to provide a first preset voltage and a second preset voltage to the data driver 436. The common voltage generating circuit 470 is not connected to the data driver 436. Second, the data driver 436 further includes a third voltage input 430. The control circuit 421 of the data driver 436 further includes a third switch 431 connected between the third voltage input terminal 430 and the voltage output terminal 427. The voltage processing circuit 423 is different from the voltage processing circuits 123, 223 and 323. During the time when the liquid crystal display 400 is turned on until the timing controller 432 starts to provide the timing signal and the data signal to the data driver 436, the time is The voltage processing circuit 423 of the data driver 436 can output a third control signal C3 instead of outputting the first control signal C1 to the control circuit 421.

The working principle of the liquid crystal display 400 is basically the same as that of the liquid crystal display 100. Therefore, the working principle of the liquid crystal display 400 is briefly described as follows: when the liquid crystal display 400 is turned on, the timing controller 432 starts to provide timing signals and data. During the period before the signal driver 436, when the control circuit 421 receives the third control signal C3, the control circuit 421 controls the third switch 431 to be turned on, and controls the first switch 428 and the second switch. The first preset voltage outputted by the preset voltage generating circuit 480 is output to the complex pixel electrode 411 via the third voltage input terminal 430, the third switch 431, and the voltage output terminal 427. Thus, the liquid crystal display 400 displays the same grayscale picture.

When the timing controller 432 provides timing signals and data signals to the data driver 436, the liquid crystal display 400 begins to operate normally. At this time, the voltage processing circuit 423 switches the third control signal C3 to the second control signal C2, and outputs the second control signal C2 to the control circuit 421. The control circuit 421 controls the second switch 429 to be turned on according to the received second control signal C2, and controls the first switch 428 and the third switch 431 to be turned off, and the data voltage output by the data processing circuit 420 is thereby The second switch 429 and the voltage output terminal 427 are output to the complex pixel electrode 411. Thus, the liquid crystal display 400 displays a normal picture.

When the liquid crystal display 400 is turned off, the voltage processing circuit 423 switches the second control signal C2 to the first control signal C1, and outputs the first control signal C1 to the control circuit 421. The control circuit 421 controls the first switch 428 to be turned on according to the first control signal C1, and controls the second switch 429 and the third switch 431 to be turned off. Furthermore, the second preset voltage output by the preset voltage generating circuit 480 is applied to the complex pixel electrode 411 by the first voltage input terminal 425, the first switch 428 and the voltage output terminal 427. Thus, the liquid crystal display 400 displays the same grayscale picture until the charge on the plurality of pixels 406 of the liquid crystal panel 410 is released. The first preset voltage is different from the second preset voltage.

Since the control circuit 421 of the data driver 436 has three switches, and corresponding to different working periods of the liquid crystal display 400, the voltage processing circuit 423 can provide three different control signals C1, C2, and C3 to the control circuit 121, Correspondingly, one of the three switches is turned on, and the other two switches are turned off. Therefore, the data driver 436 can start to provide the timing signal and the data signal to the data driver 436 when the liquid crystal display 400 is turned on. The first preset voltage is output to the complex pixel electrode 411 during the previous period, and when the liquid crystal display 400 is turned off, the data driver 436 correspondingly outputs the second preset voltage to the plurality of pixel electrodes 411. Therefore, the liquid crystal display 400 can display two different times during the period from the start of the liquid crystal display 400 to the time before the timing controller 432 starts to provide the timing signal and the data signal to the data driver 436, and when the liquid crystal display 400 is turned off. Grayscale picture.

The present invention is not limited to the above embodiment, for example, the first preset power The voltage is the same as the second predetermined voltage and is different from the common voltage. In addition, the first preset voltage and the second preset voltage may also be the same as the common voltage.

The liquid crystal display 100 further includes a circuit board electrically connected to the liquid crystal panel 110. The reset wafers 224 and 325 and the delay circuits 225 and 326 may also be disposed on the circuit board instead of being integrated in the data driver 136.

The liquid crystal display 400 can also be a normally white liquid crystal display. For a normally white liquid crystal display, preferably, the first and second predetermined voltages applied to the plurality of pixel electrodes 411 can be selected to enable the liquid crystal display 400 to be displayed. Black screen.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100,400‧‧‧LCD display

110, 410‧‧‧ LCD panel

130‧‧‧Drive circuit

150‧‧‧Power circuit

170, 470‧‧‧Common voltage generating circuit

102‧‧‧ scan line

104‧‧‧Information line

108‧‧‧film transistor

111,411‧‧‧ pixel electrodes

112‧‧‧Common electrode

114‧‧‧Liquid Crystal Capacitor

116‧‧‧ Storage Capacitor

106, 406‧‧ ‧ pixels

132, 432‧‧‧ timing controller

134‧‧‧ scan driver

136, 436‧‧‧ data drive

115‧‧‧External Circuit

120, 420‧‧‧ data processing circuit

121, 421‧‧‧ control circuit

123, 223, 323, 423‧‧‧ voltage processing circuits

124‧‧‧Signal input

125, 425‧‧‧ first voltage input

126‧‧‧second voltage input

430‧‧‧ third voltage input

127, 427‧‧‧ voltage output

128, 428‧‧‧ first switch

129, 429‧‧‧ second switch

431‧‧‧third switch

141, 324‧‧‧ comparator

142, 327‧‧‧ reference voltage generation circuit

143, 328‧‧‧ positive phase input

144, 329‧‧‧ negative phase input

145, 330‧‧‧ output

224, 325‧‧‧Reset wafer

225, 326‧‧‧ delay circuit

146‧‧‧First resistance

147‧‧‧second resistance

226‧‧‧resistance

148, 227‧‧‧ capacitor

149‧‧‧ diode

105‧‧‧External DC power supply

1 is a schematic view showing the structure of a first embodiment of a liquid crystal display of the present invention.

2 is a partial structural schematic view of a data driver of the liquid crystal display shown in FIG. 1.

3 is a block diagram showing an embodiment of a voltage processing circuit of the data driver shown in FIG. 2.

4 is a schematic structural view of a first alternative embodiment of a voltage processing circuit of the data driver shown in FIG. 2.

FIG. 5 is a schematic structural view of a second alternative embodiment of a voltage processing circuit of the data driver shown in FIG.

Figure 6 is a schematic view showing the structure of a second embodiment of the liquid crystal display of the present invention.

7 is a partial structural schematic view of a data driver of the liquid crystal display shown in FIG. 6.

100‧‧‧LCD display

110‧‧‧LCD panel

130‧‧‧Drive circuit

150‧‧‧Power circuit

170‧‧‧Common voltage generating circuit

102‧‧‧ scan line

104‧‧‧Information line

106‧‧‧ pixels

108‧‧‧film transistor

111‧‧‧ pixel electrodes

112‧‧‧Common electrode

114‧‧‧Liquid Crystal Capacitor

115‧‧‧External Circuit

116‧‧‧ Storage Capacitor

132‧‧‧Timing controller

134‧‧‧ scan driver

136‧‧‧Data Drive

Claims (3)

A liquid crystal display comprising: a liquid crystal panel comprising a common electrode, a plurality of pixel electrodes, and liquid crystal molecules sandwiched between the plurality of pixel electrodes and the common electrode; and a timing controller that receives the image signal and according to the figure The signal driver generates the timing signal and the data signal; the data driver receives the timing signal and the data signal to form a plurality of data voltages; and the power circuit provides a power voltage to the data driver and the timing controller; wherein the data driver The control circuit and the voltage processing circuit include a comparator and a reference voltage generating circuit, the comparator includes a positive phase input terminal, an inverting input terminal and an output terminal, the power circuit is connected to the comparison a positive phase input terminal, the reference voltage generating circuit is connected to the negative phase input end of the comparator, the output end of the comparator is connected to the control circuit, and the voltage processing circuit receives and analyzes the power supply voltage to determine the liquid crystal display a state, when the voltage processing circuit determines that the liquid crystal display is in a shutdown state, The voltage processing circuit provides a first control signal to the control circuit, the power supply voltage is equal to or less than the reference voltage, the comparator outputs the first control signal, and the data driver provides a preset voltage according to the first control signal to the plurality The pixel electrode displays the same gray scale picture. When the voltage processing circuit determines the normal display state of the liquid crystal display, the voltage processing circuit provides a second control signal to the control circuit, and the power supply circuit outputs a power supply voltage greater than the reference voltage. a reference voltage of the circuit output, the output end of the comparator outputs the second control signal, the control circuit outputs the complex data voltage to the plurality of pixel electrodes according to the second control signal, and the control circuit outputs the first control signal according to the first control signal The preset voltage is applied to the plurality of pixel electrodes. The liquid crystal display of claim 1, wherein the liquid crystal display further comprises a common voltage generating circuit that supplies a common voltage to the common electrode. The liquid crystal display of claim 2, wherein the public The common voltage is used as a preset voltage provided by the data driver when the liquid crystal display is turned off.