201201188 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明涉及一種液晶顯示器，尤其涉及一種能夠改善關 機殘影現象之液晶顯示器、一種能夠改善開機殘影現象 之液晶顯示器以及一種能夠改善開機殘影現象及關機殘 影現象之液晶顯示器。 【先前技術】 [0002] 液晶顯示器因具有體積小、品質輕、厚度薄、耗電低、 不閃爍、輻射少等特點，已廣泛應用於電視、筆記本電 腦、手機、個人數位助理等電子設備。 [0003] 惟，在液晶顯示器及其相關產品中，當外部電源打開時 ，由於液晶顯示器之源極驅動器沒有達到正常工作時之 電壓，該源極驅動器内部之邏輯功能沒有起到作用，該 源極驅動器内部之資料鎖存器就會隨機性抓取圖像資料 ，該圖像資料經相應轉換成為資料電壓。因為該源極驅 動器所抓取之圖像資料具有隨機性，故，其對應輸出之 資料電壓亦具有隨機性，導致其輸出至該液晶顯示器之 液晶面板之貧料電壓就會不一致。該液晶面板在該資料 電壓之驅動下所顯示之畫面則會出現如垂直亮線等現象 ，即開機殘影現象。 [0004] 另外，當該外部電源關閉時，由於該液晶面板内會有大 量之殘留電荷無法及時釋放，導致關機後該液晶面板上 還有殘留影像，即關機殘影現象。該開機殘影現象或/及 該關機殘影現象影響了該液晶顯示器之顯示品質。 【發明内容】 099120564 表單編號A0101 第4頁/共40頁 0992036324-0 201201188 [0005] [0006] [0007] [0008] Ο201201188 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to a liquid crystal display, and more particularly to a liquid crystal display capable of improving the phenomenon of shutdown afterimage, a liquid crystal display capable of improving the image sticking phenomenon and an improvement The liquid crystal display with the phenomenon of booting afterimage and the phenomenon of turning off the afterimage. [Prior Art] [0002] Liquid crystal displays have been widely used in televisions, notebook computers, mobile phones, personal digital assistants and other electronic devices because of their small size, light weight, thin thickness, low power consumption, no flicker, and low radiation. [0003] However, in the liquid crystal display and related products, when the external power source is turned on, since the source driver of the liquid crystal display does not reach the voltage during normal operation, the logic function inside the source driver does not function, the source The data latch inside the polar driver randomly captures the image data, and the image data is converted into a data voltage accordingly. Because the image data captured by the source driver is random, the data voltage of the corresponding output is also random, and the poor voltage of the liquid crystal panel outputted to the liquid crystal display is inconsistent. The screen displayed by the liquid crystal panel driven by the data voltage will appear as a vertical bright line, that is, the phenomenon of booting afterimage. [0004] In addition, when the external power source is turned off, a large amount of residual charge in the liquid crystal panel cannot be released in time, and there is still residual image on the liquid crystal panel after the shutdown, that is, the phenomenon of shutdown image sticking. The phenomenon of booting afterimage or/and the phenomenon of the afterimage of the shutdown affect the display quality of the liquid crystal display. SUMMARY OF THE INVENTION 099120564 Form No. A0101 Page 4 of 40 0992036324-0 201201188 [0005] [0006] [0007] [0008]
[0009] 有鑑於此，有必要提供一種能夠有效改善關機殘影現象 之液晶顯示器。 有鑑於此，有必要提供一種能夠有效改善開機殘影現象 之液晶顯不。 有鑑於此，有必要提供一種能夠有效改善開機殘影現象 及關機殘影現象之液晶顯示器。 一種液晶顯示器，其包括：液晶面板，其包括公共電極 、複數晝素電極及夾於該複數畫素電極與該公共電極之 間之液晶分子；時序控制器，其接收圖像訊號並根據該 圖像訊號生成時序訊號及資料訊號；資料驅動器，其接 收該時序訊號及該資料訊號以形成複數資料電壓；及電 源電路，其提供電源電壓至該資料驅動器及該時序控制 器；在該液晶顯示器正常顯示時，該資料驅動器提供該 資料電壓至該複數畫素電極，在該液晶顯示器關機時， 該資料驅動器提供一預設電壓至該複數畫素電極以顯示 同一灰階畫面。 一種液晶顯示器，其包括：液晶面板，其包括公共電極 、複數畫素電極及夾於該複數畫素電極與該公共電極之 間之液晶分子；時序控制器，其接收圖像訊號並根據該 圖像訊號生成時序訊號及資料訊號；資料驅動器，其接 收該時序訊號及該資料訊號以形成複數資料電壓；及電 源電路，其提供電源電壓至該資料驅動器及該時序控制 器；在該液晶顯示器開機瞬間至該時序控制器提供該時 序訊號及該資料訊號至該資料驅動器之前之時段内，該 099120564 表單編號Α0101 第5頁/共40頁 0992036324-0 201201188 資料驅動器提供一預設電壓至該複數畫素電極以顯示同 一灰階畫面。 [0010] 一種液晶顯示器，其包括：液晶面板，其包括公共電極 、複數畫素電極及夾於該複數畫素電極與該公共電極之 間之液晶分子；時序控制器，其接收圖像訊號並根據該 圖像訊號生成時序訊號及資料訊號；資料驅動器，其接 收該時序訊號及該資料訊號以形成複數資料電壓；及電 源電路，其提供電源電壓至該資料驅動器及該時序控制 器；在該液晶顯示器開機瞬間至該時序控制器開始提供 該時序訊號及該資料訊號至該資料驅動器之前之時段内 ，該資料驅動器提供一第一預設電壓至該複數畫素電極 以顯示同一灰階畫面；在該液晶顯示器關機時，該資料 驅動器提供一第二預設電壓至該複數畫素電極以顯示同 一灰階畫面。 [0011] 相較於先前技術，本發明液晶顯示器之資料驅動器在關 機時提供該預設電壓至該複數畫素電極，因此，該液晶 分子二端之夾壓都相同，相應地，該液晶顯示器在關機 時顯示同一灰階畫面，直至該液晶面板内殘留之電荷釋 放完畢。進而，解決該液晶顯示器之關機殘影現象。 [0012] 相較於先前技術，由於在該液晶顯示器開機瞬間至該時 序控制器輸出時序訊號及資料訊號至該資料驅動器之前 ，該資料驅動器提供該預設電壓至該複數晝素電極，從 而可以避免該資料驅動器輸出隨機抓取之資料電壓至該 複數畫素電極。相應地，該液晶分子二端之夾壓都相同 ，該液晶顯示器在開機時顯示同一灰階畫面。進而，解 099120564 表單編號A0101 第6頁/共40頁 0992036324-0 201201188 [0013] Ο [0014] ❹ [0015] 決該液晶顯示器之開機殘影現象。 相較於先前技術，由於在該液晶顯示器開機瞬間至該時 序控制器開始提供該時序訊號及該資料訊號至該資料驅 動器之前之時段内，該資料驅動器提供一第一預設電壓 至該複數畫素電極以顯示同一灰階晝面’從而可以避免 該資料驅動器輸出隨機抓取之資料電壓至該複數晝素電 極，進一步地，在該液晶顯不器關機時’該S料驅動器 提供一第二預設電壓至該複數晝素電極以顯示同一灰階 畫面，直至該液晶面板内殘留之電荷釋放完畢。進而， 解決該液晶顯示器之聞機殘影現象與關機殘影現象。 【實施方式】 請參閱圖1，圖1是本發明液晶顯示器第一實施方式之結 構示意圖。該液晶顯示器100是一常黑型液晶顯示器，其 包括一液晶面板110、一用於驅動該液晶面板110之驅動 電路130、一用於為該驅動電路130提供工作電源之電琢 1 電路150、Θ及一用於為該液晶面板110提供公共電壓 公共電壓產生電路170。 該液晶面板110包括複數相互平行之掃描線1〇2、複數相 互平行且與該複數掃描線丨〇2絕緣相交之資料線丨〇4、複 數位於該掃描線102與該資料線丨〇4交叉處之薄膜電晶體 108及複數畫素電極m、複數公共電極112及複數存儲 電容116。該晝素電極lu、該公共電極112及位於其間 之液晶分子（未標示）構成複數液晶電容1 1 4。該液晶電容 114與該存儲電容116並聯連接^該薄膜電晶體1〇8之閘 極（未標不）連接至該掃描線1〇2，源極（未標示）連接至該 099120564 表單編號A0101 第7頁/共40頁 0992036324-0 201201188 資料線104，閘極（未標示）連接至該畫素電極⑴。該公 共電極112連接至該公共電麼產生電路…。該掃描線 102及該資料線1〇4所圍之最小區域定義為一畫素⑽。 [0016] [0017] 該驅動電路130包括-時序控制器132、一掃描驅動器 134及一資料驅動器136。該公共電壓產生電路17〇還連 接至該資料驅動器i 36 ’提供該公共電壓給該:#料驅動器 136。β玄時序控制器132用於接收一外部電路115提供之 圖像資料，且根據該圖像資料產生時序訊號及資料訊號（ 如，RGB訊號），並將該時序訊號提供給該資料驅動器 及該掃描驅動器13 4以控制該資料驅動器丨3 6及該掃描驅 動器134之工作時序，以及將該資料訊號提供給該資料驅 動器136。該掃描驅動器丨34接收該時序訊號並依序輸出 一系列掃描脈衝至該掃描線1〇2。該資料驅動器136接收 該公共電壓、該資料訊號及時序訊號，並轉換該資料訊 號為複數資料電壓《在該液晶顯示器1〇〇關機之前該資 料驅動器136根據該時序訊號選擇輸出資料電壓至該畫素 電極111 ;在該液晶顯示器1〇〇關機時，該資料驅動器 136選擇輸出公共電壓至該畫素電極lu。 請參閱圖2，圖2為圖1所示液晶顯示器1〇〇之資料驅動器 136之局部結構示意圖。該資料驅動器136包括一資料處 理電路120、一控制電路121、一電壓處理電路123、一 讯號輸入端124、一第一電壓輸入端125、一第二電壓輸 入端126及一電壓輸出端127。該資料處理電路丨2〇分別 電性連接該訊號輸入端1 2 4及該控制電路121。該電壓處 理電路123分別電性連接該第二電壓輸入端126及該控制 099120564 表單編號A0101 第8頁/共40頁 0992036324-0 201201188 電路121。該控制電路121還分別電性連接該第一電壓輸 入端125及該電壓輸出端127，以與該電壓處理電路123 相配合以控制該資料驅動器136在該液晶顯示器100關機 前與關機時之輸出狀態。其中，該控制電路121包括一第 一開關128及一第二開關129。該第一開關128分別電性 連接該資料處理電路120及該電壓輸出端127。該第二開 關129分別電性連接該第一電壓輸入端125及該電壓輸出 端 127。 [0018] 該資料處理電路120藉由該訊號輸入端124接收該時序控 制器132輸出之資料訊號及時序訊號，轉換該資料訊號為 資料電壓，並根據該時序訊號輸出該資料電壓至該控制 電路121。該公共電壓產生電路170產生之公共電壓藉由 該第一電壓輸入端125傳輸至該控制電路121。該電源電 路150提供給該資料驅動器136之電源電壓Vcc藉由該第 二電壓輸入端126傳輸至該電壓處理電路1^3。該電壓處 理電路123根據接收到之該電源電壓Vcc之大小，對應輸 出不同之控制訊號至該控制電路121。該控制電路121根 據接收到之相應之控制訊號對應控制該第一開關128與該 第二開關129之導通或截止，進而控制該資料驅動器136 是輸出資料電壓還是輸出公共電壓至該電壓輸出端127。 [0019] 請參閱圖3，圖3是圖2所示資料驅動器136之電壓處理電 路123—實施方式之結構示意圖。該電壓處理電路123包 括一比較器141及一參考電壓產生電路142。該比較器 141包括一正相輸入端143、一負相輸入端144及一輸出 端145。該正相輸入端143連接該電源電路150，該負相 099120564 表單編號A0101 第9頁/共40頁 0992036324-0 201201188 輸入端144連接該參考電壓產生電路142，該輸出端145 連接至該控制電路121。當該液晶顯示器ι〇〇正常工作時 ’該參考電壓產生電路142輸出一參考電壓rEF至該負相 輸入端144，該電源電路150輸出該電源電壓Vcc：至該正 相輸入端143。該比較器141藉由比較該電源電壓Vcc與 δ亥參考電壓REF之大小，相應輸出一第一控制訊號[I及一 第二控制訊號C2。當該電源電壓Vcc大於該參考電壓ref 時，該比較器141之輸出端145輸出該第二控制訊號C2。 當該電源電壓Vcc等於或小於該參考電壓時，該比較 器141之輸出端145輸出該第一控制訊號u。 [0020] [0021] 該參考電壓產生電路142包括一第一電阻146、一第二電 阻147 ' —電容148及一二極體149。該二極體149之陽極 連接至一外部直流電源，其陰極藉由該第一電阻ι46 連接至該負相輸入端144。該第二電阻147與該電容148 並聯連接於該二極體149與地之間。該電容丨“用於穩壓 。該二極體149僅具有正嚮導通作用，防止電壓反灌該 外部直流電源1 〇 5輸出之直流電壓經該二極體丨4 9及該第 電阻146後產生該參考電壓REF，並輸出至該負相輸入 端 144。 藉由適當設定該第-、第二電阻146、147之阻值，並選 擇具有較大電容值（如：20微法）之電容148，以提供一明 顯小於该資料駆動器！ 36正常工作時所需之電源電壓Vcc 之 > 考電壓REF ’如該參考電壓REF為該資料驅動器136 正常工作所需之電源電壓Vcc之百分之八十。在該液晶顯 不益100關機前，由於該電源電射ccA於該參考電壓 099120564 表單編號A0101 第10頁/共40頁 0992036324-0 201201188 Ο [0022] [0023]In view of the above, it is necessary to provide a liquid crystal display capable of effectively improving the phenomenon of shutdown afterimage. In view of this, it is necessary to provide a liquid crystal display which can effectively improve the phenomenon of sticking on the boot. In view of this, it is necessary to provide a liquid crystal display capable of effectively improving the phenomenon of burn-in afterimage and the phenomenon of shutdown afterimage. A liquid crystal display comprising: a liquid crystal panel comprising a common electrode, a plurality of halogen electrodes, and liquid crystal molecules sandwiched between the plurality of pixel electrodes and the common electrode; and a timing controller that receives the image signal and according to the figure The signal driver generates a timing signal and a data signal; the data driver receives the timing signal and the data signal to form a plurality of data voltages; and the power circuit provides a power voltage to the data driver and the timing controller; the liquid crystal display is normal When displayed, the data driver provides the data voltage to the plurality of pixel electrodes. When the liquid crystal display is turned off, the data driver provides a predetermined voltage to the plurality of pixel electrodes to display the same grayscale image. A liquid crystal display comprising: a liquid crystal panel comprising a common electrode, a plurality of pixel electrodes, and liquid crystal molecules sandwiched between the plurality of pixel electrodes and the common electrode; and a timing controller that receives the image signal and according to the figure The signal driver generates a timing signal and a data signal; the data driver receives the timing signal and the data signal to form a plurality of data voltages; and the power circuit provides a power voltage to the data driver and the timing controller; and the liquid crystal display is powered on The data driver provides a preset voltage to the complex picture during the period until the timing controller provides the timing signal and the data signal to the data driver. The 099120564 form number Α0101 5th page/total 40 page 0992036324-0 201201188 Prime electrodes to display the same grayscale picture. [0010] A liquid crystal display comprising: a liquid crystal panel comprising a common electrode, a plurality of pixel electrodes, and liquid crystal molecules sandwiched between the plurality of pixel electrodes and the common electrode; and a timing controller that receives the image signal and Generating a timing signal and a data signal according to the image signal; a data driver receiving the timing signal and the data signal to form a plurality of data voltages; and a power supply circuit for supplying a power voltage to the data driver and the timing controller; The data driver provides a first preset voltage to the plurality of pixel electrodes to display the same grayscale picture during a period when the liquid crystal display is turned on until the timing controller starts to provide the timing signal and the data signal to the data driver; When the liquid crystal display is turned off, the data driver provides a second preset voltage to the plurality of pixel electrodes to display the same grayscale picture. [0011] Compared with the prior art, the data driver of the liquid crystal display of the present invention supplies the preset voltage to the plurality of pixel electrodes when the power is turned off, so that the clamping of the liquid crystal molecules is the same, and accordingly, the liquid crystal display The same grayscale screen is displayed when the power is turned off until the residual charge in the liquid crystal panel is released. Further, the shutdown phenomenon of the liquid crystal display is solved. [0012] Compared with the prior art, the data driver provides the preset voltage to the plurality of pixel electrodes before the timing controller outputs the timing signal and the data signal to the data driver. The data driver is prevented from outputting the randomly grabbed data voltage to the complex pixel electrode. Correspondingly, the clamping of the two ends of the liquid crystal molecules is the same, and the liquid crystal display displays the same gray scale picture when turned on. Further, the solution 099120564 Form No. A0101 Page 6 / Total 40 pages 0992036324-0 201201188 [0013] ❹ [0015] The liquid crystal display is turned on. Compared with the prior art, the data driver provides a first preset voltage to the plurality of pictures during the period from the start of the liquid crystal display to the time when the timing controller starts to provide the timing signal and the data signal to the data driver. The pixel electrode displays the same gray-scale surface to prevent the data driver from outputting the randomly grabbed data voltage to the plurality of pixel electrodes, and further, when the liquid crystal display is turned off, the S material driver provides a second The voltage is preset to the plurality of halogen electrodes to display the same gray scale picture until the residual charge in the liquid crystal panel is released. Further, the image sticking phenomenon and the shutdown phenomenon of the liquid crystal display are solved. [Embodiment] Please refer to Fig. 1. Fig. 1 is a schematic view showing the structure of a first embodiment of a liquid crystal display according to the present invention. The liquid crystal display 100 is a normally black liquid crystal display, and includes a liquid crystal panel 110, a driving circuit 130 for driving the liquid crystal panel 110, and an electric circuit 1 for supplying power to the driving circuit 130. And a common voltage common voltage generating circuit 170 for supplying the liquid crystal panel 110. The liquid crystal panel 110 includes a plurality of mutually parallel scan lines 1 and 2, and a plurality of data lines 平行4 which are parallel to each other and insulated from the plurality of scan lines 丨〇2, and the plurality of lines are located at the intersection of the scan lines 102 and the data lines 丨〇4. The thin film transistor 108 and the plurality of pixel electrodes m, the plurality of common electrodes 112, and the plurality of storage capacitors 116. The halogen electrode lu, the common electrode 112, and liquid crystal molecules (not shown) therebetween constitute a plurality of liquid crystal capacitors 1 14 . The liquid crystal capacitor 114 is connected in parallel with the storage capacitor 116. The gate of the thin film transistor 1〇8 is connected to the scan line 1〇2, and the source (not labeled) is connected to the 099120564 form number A0101. 7 pages/total 40 pages 0992036324-0 201201188 The data line 104, the gate (not shown) is connected to the pixel electrode (1). The common electrode 112 is connected to the common electric generating circuit. The minimum area surrounded by the scan line 102 and the data line 1〇4 is defined as a pixel (10). [0017] The driving circuit 130 includes a timing controller 132, a scan driver 134, and a data driver 136. The common voltage generating circuit 17 is also connected to the data driver i 36 ' to supply the common voltage to the #料 driver 136. The β-thin timing controller 132 is configured to receive an image data provided by an external circuit 115, and generate a timing signal and a data signal (eg, an RGB signal) according to the image data, and provide the timing signal to the data driver and the The scan driver 13 4 controls the operation timing of the data driver 丨36 and the scan driver 134, and supplies the data signal to the data driver 136. The scan driver 丨34 receives the timing signal and sequentially outputs a series of scan pulses to the scan line 1〇2. The data driver 136 receives the common voltage, the data signal and the timing signal, and converts the data signal into a plurality of data voltages. Before the liquid crystal display is turned off, the data driver 136 selects the output data voltage according to the timing signal to the picture. The element electrode 111; when the liquid crystal display 1 is turned off, the data driver 136 selects to output a common voltage to the pixel electrode lu. Please refer to FIG. 2. FIG. 2 is a partial structural diagram of the data driver 136 of the liquid crystal display device of FIG. The data driver 136 includes a data processing circuit 120, a control circuit 121, a voltage processing circuit 123, a signal input terminal 124, a first voltage input terminal 125, a second voltage input terminal 126, and a voltage output terminal 127. . The data processing circuit 丨2〇 is electrically connected to the signal input terminal 1 24 and the control circuit 121, respectively. The voltage processing circuit 123 is electrically connected to the second voltage input terminal 126 and the control 099120564 Form No. A0101 Page 8 / Total 40 page 0992036324-0 201201188 Circuit 121. The control circuit 121 is further electrically connected to the first voltage input terminal 125 and the voltage output terminal 127 to cooperate with the voltage processing circuit 123 to control the output of the data driver 136 before and during shutdown of the liquid crystal display device 100. status. The control circuit 121 includes a first switch 128 and a second switch 129. The first switch 128 is electrically connected to the data processing circuit 120 and the voltage output terminal 127, respectively. The second switch 129 is electrically connected to the first voltage input terminal 125 and the voltage output terminal 127, respectively. The data processing circuit 120 receives the data signal and the timing signal output by the timing controller 132 by the signal input terminal 124, converts the data signal into a data voltage, and outputs the data voltage to the control circuit according to the timing signal. 121. The common voltage generated by the common voltage generating circuit 170 is transmitted to the control circuit 121 via the first voltage input terminal 125. The power supply voltage Vcc supplied from the power supply circuit 150 to the data driver 136 is transmitted to the voltage processing circuit 1^3 via the second voltage input terminal 126. The voltage processing circuit 123 correspondingly outputs different control signals to the control circuit 121 according to the magnitude of the received power supply voltage Vcc. The control circuit 121 controls the first switch 128 and the second switch 129 to be turned on or off according to the corresponding control signal received, thereby controlling whether the data driver 136 outputs the data voltage or outputs the common voltage to the voltage output terminal 127. . Please refer to FIG. 3. FIG. 3 is a schematic structural diagram of a voltage processing circuit 123 of the data driver 136 of FIG. The voltage processing circuit 123 includes a comparator 141 and a reference voltage generating circuit 142. The comparator 141 includes a non-inverting input 143, a negative input 144 and an output 145. The positive phase input terminal 143 is connected to the power supply circuit 150. The negative phase 099120564 is shown in the form number A0101. The input terminal 144 is connected to the reference voltage generating circuit 142, and the output terminal 145 is connected to the control circuit. 121. When the liquid crystal display ι is operating normally, the reference voltage generating circuit 142 outputs a reference voltage rEF to the negative phase input terminal 144, and the power supply circuit 150 outputs the power supply voltage Vcc: to the positive phase input terminal 143. The comparator 141 outputs a first control signal [I and a second control signal C2] by comparing the magnitudes of the power supply voltage Vcc and the δ reference voltage REF. When the power supply voltage Vcc is greater than the reference voltage ref, the output 145 of the comparator 141 outputs the second control signal C2. When the power supply voltage Vcc is equal to or smaller than the reference voltage, the output terminal 145 of the comparator 141 outputs the first control signal u. [0021] The reference voltage generating circuit 142 includes a first resistor 146, a second resistor 147', a capacitor 148, and a diode 149. The anode of the diode 149 is coupled to an external DC power source, the cathode of which is coupled to the negative phase input terminal 144 by the first resistor ι46. The second resistor 147 is connected in parallel with the capacitor 148 between the diode 149 and the ground. The capacitor 丨 is used for voltage regulation. The diode 149 has only a forward conduction function, and prevents the voltage from being reversed by the DC voltage output from the external DC power source 1 〇 5 through the diode 丨 49 and the first resistor 146. The reference voltage REF is generated and output to the negative phase input terminal 144. By appropriately setting the resistance values of the first and second resistors 146 and 147, and selecting a capacitor having a large capacitance value (for example, 20 microfarad) 148, to provide a power supply voltage Vcc required for the normal operation of the device 36! The reference voltage REF ' is the percentage of the power supply voltage Vcc required for the data driver 136 to operate normally. Eighty. Before the LCD display is disabled, the power supply ccA is at the reference voltage 099120564 Form No. A0101 Page 10 / Total 40 Page 0992036324-0 201201188 Ο [00223] [0023]
[0024] 099120564 REF，相應地，該比較器141輸出該第二控制訊號C2至該 控制電路121，以控制該第二開關129導通，控制該第一 開關128截止，從而該資料電壓經由該電壓輸出端127輸 出至該複數畫素電極111。而當該液晶顯示器100關機時 ，該電源電壓Vcc掉電速度較快，且由於電容值較大之電 容148存儲之電荷量較多，該二極體149又僅具有正嚮導 通作用，因此，在該液晶顯示器關機時，該電源電壓Vcc 迅速下降等於並迅速小於該參考電壓REF，該比較器141 對應輸出該第一控制訊號C1至該i控制電路121，以控制該 第一開關128導通，該第二開關129截止，從而該公共電 壓經由該電壓輸出端127輸出至該複數畫素電極111，則 該晝素電極111與該公共電極112之電壓相同，進而使得 該液晶顯示器100在關機時顯示黑畫面。 進一步地，為更好地理解本案之實施方式，以下結合圖 1-3說明該液晶顯示器100之工作原理如下： 當該液晶顯示器100處於正常工作時段，該電源電路150 首先提供一電源電壓Vcc至該時序控钊器132、該資料驅 動器136及該掃描驅動器134，以向該時序控制器1.32、 該資料驅動器136及該掃描驅動器134供電。該公共電壓 產生電路170提供一公共電壓至該資料驅動器136及該公 共電極112。該外部直流電源105提供一直流電源至該參 考電壓產生電路142。然後，該外部電路115提供圖像資 料至該時序控制器132。 該時序控制器132根據該圖像資料產生時序訊號及資料訊 號，並將該時序訊號提供給該資料驅動器136及該掃描驅 表單編號A0101 第11頁/共40頁 0992036324-0 201201188 動器134以控制該資料驅動器136及該掃描驅動器134之 工作時序’以及將該資料訊號提供給該資料驅動器136之 資料處理電路120。該資料處理電路12〇轉換接收到資料 訊號為相應之資料電壓’並輸出該資料電壓至該控制電 路121。該公共電壓產生電路170提供給該資料驅動器 136之公共電壓也輸出至該控制電路121。 [0025] 該直流電壓提供至該參考電壓產生電路142後，該二極體 149導通，進而’該直流電壓對該電容148進行充電，並 經該第一電阻146分壓後輸出一參考電壓ref至該負相輸 入端144。該電源電路150提供袷該資料驅動器136之電 源電壓Vcc輸出至該正相輸入端143，此時，該電源電壓 Vcc大於該參考電壓REF，該比較器141對應輸出一第二 控制訊號C2至該控制電路121。該控制電路121根據該第 一控制訊號C2控制該第二開關129導通，控制該第一開關 128截止’從而’該控制電路121輸出該資料電壓，該資 料電壓經由該電壓輸出端127輸出至該複數資料線104。 當該掃描驅動器134輸出掃描脈衝至該掃描線1〇2導通該 薄膜電晶體108時，該複數資料線1〇4上之資料電壓藉由 該薄膜電晶體108輸出至該複數畫素電極iU。進而，該 液晶面板110顯示正常之畫面。 [0026] 當使用者按下該液晶顯示器1〇〇之開機/關機按鈕，選擇 關閉該液晶顯示器1 〇 〇時’該外部電路11 5輸出至該時序 控制器132之圖像訊號首先被切斷，而該電源電路15〇、 該外部直流電源105及該公共電壓產生電路no由於内部 包括複數儲能元件儲存有一定能量，因此該電源電路15〇 099120564 表單編號A0101 第】2頁/共40頁 0992036324-0 201201188 Ο 、該外部直流電源1 0 5及該公共電壓產生電路1 7 0並不會 立即停止工作。在該液晶顯示器100關機瞬間，該參考電 壓REF基本保持不變，而該電源電壓Vcc急劇下降以等於 並迅速小於該參考電壓REF，進而，該比較器141輸出一 第一控制訊號C1至該控制電路121。該控制電路121接收 該第一控制訊號C1，並根據該第一控制訊號C1控制該第 一開關128導通，控制該第二開關129截止，從而，該控 制電路121停止輸出該資料電壓，而切換為輸出該公共電 壓，該公共電壓經由該電壓輸出端127輸出至該複數資料 線104。另一方面，該掃描驅動器134則在一閘極全開訊 號之控制下輸出掃描脈衝至掃描線102，該複數資料線 104上之公共電壓經由該複數薄膜電晶體108加載至該複 數晝素電極111。由於該公共電極112此時亦加載公共電 壓，因此，在該液晶顯示器100關機時，液晶分子二端之 夾壓為0伏，從而，該液晶顯示器100—直顯示黑畫面， 直至該複數晝素106上之電荷釋放完畢。 Q [0027] 由於液晶顯示器100在關機時，該資料驅動器136能夠提 供公共電壓至該液晶面板110之複數畫素106，使該複數 畫素106二端之電勢相同，均為0伏，則該液晶顯示器100 一直顯示黑畫面，直至該液晶面板110之複數晝素106上 之電荷釋放完畢，改善該液晶顯示器100之關機殘影現象 〇 [0028] 另外，由於該液晶顯示器100之液晶分子之二端之夾壓為 0伏，因此，也能夠最大限度地防止液晶分子老化之問題 099120564 表單編號A0101 第13頁/共40頁 0992036324-0 201201188 [0029] 進一步地，圖3中所示之該液晶顯示器100之電壓處理電 路123也可被替換為如圖4中所示之電壓處理電路223之結 構。請參閲圖4，圖4是該電壓處理電路223之結構示意圖 。具有該電壓處理電路223之液晶顯示器100除能夠有效 改善關機殘影外，還能進一步改善開機殘影現象。 [0030] 該電壓處理電路223包括一復位晶片224及一與該復位晶 片224相連接之延時電路225。該復位晶片224還分別與 該電源電路150及該控制電路121連接，其能夠根據電源 電壓Vcc之狀況，相應輸出一第一控制訊號C1及一第二控 制訊號C2。該復位晶片224内設有一第一參考電壓準位及 一第二參考電壓準位。在該液晶顯示器100開機瞬間至該 液晶顯示器正常工作期間内，該復位晶片224選擇以該第 一參考電壓準位為參考標準，而在該液晶顯示器100關機 時，該復位晶片224選擇以該第二參考電壓準位為參考標 準。在該液晶顯示器100開機瞬間，該電源電路150輸出 之電源電壓Vcc逐漸上升，當該復位晶片224檢測到該電 源電壓Vcc上升至該第一參考電壓準位時，該復位晶片 2 2 4經一定延時時間後將輸出之該第一控制訊號C1切換為 該第二控制訊號C2。該電源電路150還藉由該復位晶片 224對該延時電路225進行充電，該復位晶片224之延時 時間由該延時電路225之充電時間決定。在該液晶顯示器 1 0 0關機時，該電源電壓V c c由於掉電速度較快，因此， 該電源電壓Vcc迅速下降至該第二參考電壓準位，該復位 晶片2 2 4對應將輸出之該第二控制訊號C 2切換為該第一控 制訊號C1。當該復位晶片224輸出該第一控制訊號C1時， 099120564 表單編號A0101 第14頁/共40頁 0992036324-0 201201188 [0031] Ο ❹ [0032] 099120564 邊控制電路121接收該第一控制訊號π並對應輸出該公共 電壓至該晝素電極lu ;而當該復位晶片224輸出該第二 控制訊號C2時’該控制電路121接收該第二控制訊號以並 對應輸出該資料電壓至該畫素電極ηι。其中，該第一參 考電壓準位通常大於該第二參考電壓準位，且均小於該 電源電壓Vcc。 該延時電路225包括-電阻226及一電容227。該電阻226 與該電容227串聯連接於該復位晶片224與地之間。該電 源電路藉由該復位晶片224、該電阻226對該電容m進 行充電，進而決定該復位晶片224之延時時間。使用者首 先預先量測從該液晶顯示器1〇〇開機辑間益該時序控制器 132開始輪出時序訊號及資料訊號所需之時間，以及量測 該電源電壓從〇伏上升至該第―電齡位所需之時間 丄其中’定義從該液晶顯示器100開機瞬間至該時序控制 益開始輸出時序訊號及資料訊號所需之時間為第一時 間間隔，定義該電源電壓Vce從〇佚上升至該第—電壓準 位所需之時間為第二時間間隔。實際上，該電源電壓— 從〇伏上升至該第-電壓準位所需之時間較短，該第一時 間間隔明顯大於該第二時間間隔。接著，使用者對該第 一時間間隔與該第二時間間隔做減法運算，得到之差/值 即為該復位晶片224之延時時間。進一步地，使用者藉由 調整該延時電路225之元件參數，即可設定該復位晶片曰 224所需之延時時間。該延時時間優選為微秒。 下面結合圖1、圖2及圖4 ’具體說明具備該電壓處理電路 223之該碎晶顯示器之工作原理·· 表單編號A0I01 第15頁/共40頁 0992036324-0 201201188 [0033]當使用者按下該液晶顯示器1 〇〇之開機/關機按鈕，選擇 開啟該液晶顯示器1〇〇時，首先，該電源電路15〇提供一 電源電壓Vcc至該時序控制器132、該資料驅動器】36及 該掃描驅動器134，以向該時序控制器132 '該資料驅動 器136及該掃描驅動器134供電。該公共電壓產生電路 170提供一公共電壓至該資料驅動器136及該公共電極 112。然後，該外部電路u 5提供圖像資料至該時序控制 器132。該電源電壓vcc從〇伏上升至該復位晶片224内設 之第一參考電壓準位後，該電源電壓Vcc藉由該復位晶片 224及該電阻226對該電容227進行充電，直至該電容227 充電完畢之前，該復位晶片224都對應輸出一第一控制訊 號C1至該控制電路121。另外，在此時段，該時序控制器 132未輸出任何訊號至該掃描驅動器134及該資料驅動器 136。該控制電路121根據該第一控制訊號C1對應控制該 第一開關128導通，控制該第二開關129截止，進而，該 公共電壓依次藉由該第一開關128及該電壓輸出端127輸 出至該複數資料線104 »該掃描驅動器134輸出掃描電壓 至β玄掃描線1〇2。該資料線1〇4上加載之公共電壓藉由該 薄膜電晶體108輸出至該晝素電極lu。由於此時段内， 該公共電極112上之電壓亦為公共電壓，因此，該液晶分 子二端之夾壓為0伏，該液晶顯示器100顯示黑畫面。其 中，該第一控制訊號C1為一低電廢，例如〇伏。 [0034]當該電容227充電完畢時’該時序控制器132開始輸出時 序訊號至該掃描驅動器134及該資料驅動器136，並輸出 貢料訊號至該資料驅動器136 ’進而’該液晶顯示器1〇〇 099120564 表單編號A0101 第16頁/共40頁 0992036324-0 201201188[0024] 099120564 REF, correspondingly, the comparator 141 outputs the second control signal C2 to the control circuit 121 to control the second switch 129 to be turned on, and the first switch 128 is controlled to be turned off, so that the data voltage passes through the voltage. The output terminal 127 is output to the complex pixel electrode 111. When the liquid crystal display 100 is turned off, the power supply voltage Vcc is powered off faster, and since the capacitance 148 having a larger capacitance value stores more charge, the diode 149 has only a forward conduction function. When the liquid crystal display is turned off, the power supply voltage Vcc is rapidly decreased to be equal to and rapidly lower than the reference voltage REF, and the comparator 141 outputs the first control signal C1 to the i control circuit 121 to control the first switch 128 to be turned on. The second switch 129 is turned off, so that the common voltage is output to the complex pixel electrode 111 via the voltage output terminal 127, and the voltage of the pixel electrode 111 and the common electrode 112 are the same, thereby causing the liquid crystal display device 100 to be turned off. A black screen is displayed. Further, in order to better understand the implementation of the present invention, the working principle of the liquid crystal display 100 is as follows with reference to FIGS. 1-3: When the liquid crystal display 100 is in a normal working period, the power supply circuit 150 first provides a power supply voltage Vcc to The timing controller 132, the data driver 136, and the scan driver 134 supply power to the timing controller 1.32, the data driver 136, and the scan driver 134. The common voltage generating circuit 170 supplies a common voltage to the data driver 136 and the common electrode 112. The external DC power source 105 supplies a DC power supply to the reference voltage generating circuit 142. The external circuit 115 then provides image data to the timing controller 132. The timing controller 132 generates a timing signal and a data signal according to the image data, and supplies the timing signal to the data driver 136 and the scan drive form number A0101 page 11 / total page 4092036324-0 201201188 actuator 134 The working sequence of the data driver 136 and the scan driver 134 is controlled and the data signal is supplied to the data processing circuit 120 of the data driver 136. The data processing circuit 12 converts the received data signal to the corresponding data voltage ' and outputs the data voltage to the control circuit 121. The common voltage supplied from the common voltage generating circuit 170 to the data driver 136 is also output to the control circuit 121. [0025] After the DC voltage is supplied to the reference voltage generating circuit 142, the diode 149 is turned on, and the DC voltage charges the capacitor 148, and is divided by the first resistor 146 to output a reference voltage ref. To the negative phase input 144. The power supply circuit 150 provides a power supply voltage Vcc of the data driver 136 to the positive phase input terminal 143. At this time, the power supply voltage Vcc is greater than the reference voltage REF, and the comparator 141 outputs a second control signal C2 to the Control circuit 121. The control circuit 121 controls the second switch 129 to be turned on according to the first control signal C2, and controls the first switch 128 to turn off and thus the control circuit 121 outputs the data voltage, and the data voltage is output to the Multiple data lines 104. When the scan driver 134 outputs a scan pulse to the scan line 1〇2 to turn on the thin film transistor 108, the data voltage on the complex data line 1〇4 is output to the complex pixel electrode iU through the thin film transistor 108. Further, the liquid crystal panel 110 displays a normal picture. [0026] When the user presses the power on/off button of the liquid crystal display and selects to turn off the liquid crystal display 1 ', the image signal outputted to the timing controller 132 by the external circuit 11 is first cut off. The power supply circuit 15A, the external DC power supply 105, and the common voltage generation circuit no have a certain amount of energy stored in the internal energy storage device, so the power supply circuit 15〇099120564 Form No. A0101 Page 2 of 40 0992036324-0 201201188 、 The external DC power supply 1 0 5 and the common voltage generating circuit 170 will not stop working immediately. When the liquid crystal display 100 is turned off, the reference voltage REF remains substantially unchanged, and the power supply voltage Vcc drops sharply to be equal to and rapidly smaller than the reference voltage REF. Further, the comparator 141 outputs a first control signal C1 to the control. Circuit 121. The control circuit 121 receives the first control signal C1, and controls the first switch 128 to be turned on according to the first control signal C1, and controls the second switch 129 to be turned off, so that the control circuit 121 stops outputting the data voltage, and switches. To output the common voltage, the common voltage is output to the complex data line 104 via the voltage output terminal 127. On the other hand, the scan driver 134 outputs a scan pulse to the scan line 102 under the control of a gate full-on signal, and the common voltage on the complex data line 104 is loaded to the plurality of pixel electrodes 111 via the plurality of thin film transistors 108. . Since the common electrode 112 is also loaded with a common voltage at this time, when the liquid crystal display 100 is turned off, the clamping of the liquid crystal molecules is 0 volts, so that the liquid crystal display 100 directly displays a black image until the plurality of pixels The charge on 106 is released. [0027] Since the data driver 136 is capable of providing a common voltage to the plurality of pixels 106 of the liquid crystal panel 110 when the liquid crystal display device 100 is turned off, the potentials of the two ends of the plurality of pixels 106 are the same, both being 0 volts. The liquid crystal display 100 always displays a black screen until the charge on the plurality of pixels 106 of the liquid crystal panel 110 is released, thereby improving the shutdown phenomenon of the liquid crystal display 100. [0028] In addition, since the liquid crystal molecules of the liquid crystal display 100 are The clamping force at the end is 0 volt, therefore, the problem of aging of the liquid crystal molecules can be prevented to the utmost. 099120564 Form No. A0101 Page 13 / Total 40 Page 0992036324-0 201201188 [0029] Further, the liquid crystal shown in FIG. The voltage processing circuit 123 of the display 100 can also be replaced with the structure of the voltage processing circuit 223 as shown in FIG. Please refer to FIG. 4. FIG. 4 is a schematic structural diagram of the voltage processing circuit 223. The liquid crystal display 100 having the voltage processing circuit 223 can further improve the phenomenon of power-on residual image, in addition to effectively improving the after-effect of the shutdown. The voltage processing circuit 223 includes a reset wafer 224 and a delay circuit 225 coupled to the reset transistor 224. The reset chip 224 is further connected to the power circuit 150 and the control circuit 121, and can respectively output a first control signal C1 and a second control signal C2 according to the condition of the power voltage Vcc. The reset wafer 224 is provided with a first reference voltage level and a second reference voltage level. During the startup of the liquid crystal display 100 to the normal operation of the liquid crystal display, the reset wafer 224 selects the first reference voltage level as a reference standard, and when the liquid crystal display 100 is turned off, the reset wafer 224 selects the first The two reference voltage levels are reference standards. When the liquid crystal display 100 is turned on, the power supply voltage Vcc outputted by the power supply circuit 150 gradually rises. When the reset wafer 224 detects that the power supply voltage Vcc rises to the first reference voltage level, the reset wafer 2 2 4 is fixed. After the delay time, the first control signal C1 outputted is switched to the second control signal C2. The power circuit 150 also charges the delay circuit 225 by the reset chip 224. The delay time of the reset chip 224 is determined by the charging time of the delay circuit 225. When the liquid crystal display 100 is turned off, the power supply voltage V cc is faster due to the power-down speed. Therefore, the power supply voltage Vcc rapidly drops to the second reference voltage level, and the reset wafer 2 24 corresponds to the output. The second control signal C 2 is switched to the first control signal C1. When the reset chip 224 outputs the first control signal C1, 099120564 Form No. A0101 Page 14 / Total 40 Page 0992036324-0 201201188 [0031] 003 ❹ [0032] 099120564 The edge control circuit 121 receives the first control signal π and Correspondingly outputting the common voltage to the pixel electrode lu; and when the reset chip 224 outputs the second control signal C2, the control circuit 121 receives the second control signal and correspondingly outputs the data voltage to the pixel electrode ηι . The first reference voltage level is generally greater than the second reference voltage level and is less than the power supply voltage Vcc. The delay circuit 225 includes a resistor 226 and a capacitor 227. The resistor 226 is connected in series with the capacitor 227 between the reset wafer 224 and ground. The power circuit charges the capacitor m by the reset wafer 224 and the resistor 226 to determine the delay time of the reset wafer 224. The user first measures the time required for the timing controller 132 to start the rotation of the timing signal and the data signal from the liquid crystal display, and measures the power supply voltage from the stagnation to the first The time required for the age group, wherein the time required to output the timing signal and the data signal from the moment when the liquid crystal display 100 is turned on to the timing control is started is a first time interval, and the power supply voltage Vce is defined to rise from 〇佚 to The time required for the first voltage level is the second time interval. In effect, the supply voltage - the time required to rise from the stagnation to the first - voltage level is shorter, the first time interval being significantly greater than the second time interval. Then, the user performs a subtraction operation on the first time interval and the second time interval, and the difference/value is the delay time of the reset wafer 224. Further, the user can set the delay time required to reset the chip 224 by adjusting the component parameters of the delay circuit 225. The delay time is preferably microseconds. The working principle of the broken crystal display provided with the voltage processing circuit 223 will be specifically described below with reference to FIG. 1, FIG. 2 and FIG. 4'. Form No. A0I01 Page 15 / Total 40 Page 0992036324-0 201201188 [0033] When the user presses When the liquid crystal display 1 is turned on and off, when the liquid crystal display is turned on, first, the power circuit 15 provides a power voltage Vcc to the timing controller 132, the data driver, and the scan. The driver 134 is configured to supply power to the timing controller 132' the data driver 136 and the scan driver 134. The common voltage generating circuit 170 supplies a common voltage to the data driver 136 and the common electrode 112. The external circuit u 5 then supplies the image data to the timing controller 132. After the power supply voltage vcc rises from the sag to the first reference voltage level in the reset chip 224, the power supply voltage Vcc charges the capacitor 227 by the reset chip 224 and the resistor 226 until the capacitor 227 is charged. Before the completion, the reset chip 224 outputs a first control signal C1 to the control circuit 121. Additionally, during this time period, the timing controller 132 does not output any signals to the scan driver 134 and the data driver 136. The control circuit 121 controls the first switch 128 to be turned on according to the first control signal C1, and controls the second switch 129 to be turned off. Further, the common voltage is sequentially output to the first switch 128 and the voltage output terminal 127. The complex data line 104 » The scan driver 134 outputs a scan voltage to the β-mystery line 1〇2. The common voltage applied to the data line 111 is outputted to the halogen electrode lu by the thin film transistor 108. Since the voltage on the common electrode 112 is also a common voltage during this period, the nip of the liquid crystal molecules is 0 volts, and the liquid crystal display 100 displays a black screen. The first control signal C1 is a low-power waste, such as a crouch. When the capacitor 227 is fully charged, the timing controller 132 starts outputting the timing signal to the scan driver 134 and the data driver 136, and outputs a tribute signal to the data driver 136 'and thus' the liquid crystal display 1〇〇 099120564 Form No. A0101 Page 16 / Total 40 Page 0992036324-0 201201188
[0035] ❹ 開始正常工作。該資料處理電路120接收該資料訊號並轉 換該資料訊號為相應之資料電壓。同時，該復位晶片224 經該延時時間之後，其對應輸出一第二控制訊號C2至該 控制電路121，該控制電路121根據該第二控制訊號C2對 應控制該第二開關129導通，控制該第一開關128截止， 進而，該資料處理電路120輸出資料電壓至該複數資料線 104。該掃描驅動器134輸出掃描電壓至該掃描線102。 該資料線104上之資料電壓藉由該薄膜電晶體108輸出至 該畫素電極111。從而，該液晶面板110顯示正常之畫面 。其中，該第二控制訊號C2為該電源電壓Vcc。 當使用者按下該液晶顯示器100之開機/關機按鈕，選擇 關閉該液晶顯示器100，該外部電路115提供給該時序控 制器132之圖像訊號首先被切斷，接著，該電源電路150 輸出至該復位晶片224之電源電壓Vcc開始下降，並迅速 下降至該第二參考電壓準位，該復位晶片224再次對應輸 出該第一控制訊號C1至該控制電路121，該控制電路121 根據該第一控制訊號C1再次控制該第一開關128導通，控 制該第二開關129截止，進而，該公共電壓再次藉由該第 一開關128及該電壓輸出端127輸出至該複數資料線104 ，並藉由該薄膜電晶體108加載至該畫素電極111。因此 ，該公共電極112上之電壓與該晝素電極111上之電壓大 小相同，該液晶分子二端之夾壓為0伏，從而，該液晶顯 示器100顯示黑畫面，直至該液晶面板110之複數畫素 106上之電荷釋放完畢。其中，該第二參考電壓準位優選 為該參考電壓REF。 099120564 表單編號A0101 第17頁/共40頁 0992036324-0 201201188 [0036] 因此，當該液晶顯示器1 0 0進入關機時段時，該資料驅動 器136提供公共電壓至該複數晝素電極111，使得該液晶 顯示器100在關機時也顯示黑畫面，直至該液晶面板Π〇 之複數畫素106上之電荷釋放完畢。從而，改善該液晶顯 示器100之關機殘影現象。 [0037] 進一步地，該資料驅動器136在該液晶顯示器100開機瞬 間至該電容227充電完畢期間内，也即在該時序控制器 132未輸出正常之資料訊號至該資料驅動器136之前，該 資料驅動器136選擇輸出公共電壓至該複數晝素電極111 ，避免輸出其隨機抓取之資料電壓至該複數畫素電極Π1 。由於在此時段内，該液晶顯示器100之液晶分子二端之 夾壓為0伏，該液晶顯示器100顯示黑畫面。從而，進一 步改善該液晶顯示器100之開機殘影現象。 [0038] 另外，該液晶顯示器100在開機瞬間至該電源電壓Vcc達 到定值期間内、以及在該液晶顯示器100關機時，該資料 驅動器136均選擇輸出公共電壓至該畫素106，使得該液 晶分子二端之夾壓為〇伏，從而，能夠最大限度地防止液 晶分子老化之問題。 [0039] 請參閱圖5，該電壓處理電路123也可被替換為如圖5所示 之電壓處理電路323之結構。 [0040] 該電壓處理電路323包括一比較器324、一復位晶片325 、一延時電路326及一參考電壓產生電路327。該比較器 324包括·一正相輸入端328、一負相輸入端329及一輸出 端330。該電源電路150藉由該復位晶片325連接至該正 099120564 表單編號A0101 第18頁/共40頁 0992036324-0 201201188 相輪入端328。該參考電壓產生電路327連接至該負相輸 入端329。該比較器324之輸出端330連接至該控制電路 121 ^該延時電路326連接於該復位晶片325與地之間。 該復位晶片325與該延時電路326之結構及功能與該復位 晶片224及該延時電路225之結構及功能基本相同，該參 考電壓產生電路327之結構及功能與該參考電壓產生電路 14 2之結構及功能基本相同。 [0041] ❹ 該液晶顯示器在開機瞬間至該延時電路326充電完畢 、以及在該液晶顯示器100關機時，該復位晶片325都輸 出一低電平（如〇伏）至該真相輪入端328，該0伏電壓小於 該參考電壓產生電路327輸出至該負相輸入端329之參考 電壓REF。該比較器324藉由其輸出端33〇對應輸出一第 一控制訊號C1至該控制電路121。該控制.電.路121根據該 第一控制訊號C1對應控制該第一開關128導通，控制該第 二開關12 9截止。從而，該控制電路1 21輸出公共電壓， Ο [0042] 該公共電壓藉由該電壓輸出端127輸出至該畫素電極111 。進而，該液晶顯示器100在開機瞬間至該延時電路326 充電完畢、以及在關機時都顯示黑畫面。 在該液晶顯示器100正常工作時，該復位晶片325輸出該 電源電壓Vcc至該正相輸入端328，該電源電壓Vcc大於 該參考電壓REF，相應地，該比較器324輸出一第二控制 訊號C2至該控制電路121。該控制電路121根據該第二控 制訊號C2對應控制該第一開關128截止，控制該第二開關 129導通。從而，該控制電路121輸出資料電壓，該資料 電壓藉由該電壓輸出端127輪出至該晝素電極1H。進而 099120564 表單編號A0101 第19頁/共40頁 0992036324-0 201201188 ，該液晶顯示器10 0顯示正常之畫面。 [0043] 由於該復位晶片224輸出之第二控制訊號C2為電源電壓 Vcc，該電源電壓Vcc之最大值通常為3. 3伏，其電壓較 小，因此，由該復位晶片224輸出之第二控制訊號C2較難 控制該控制電路121，實現該二開關128、129之導通或 ,截止。然而，該比較器324輸出之第二控制訊號C2對應之 電壓較大，因此，該比較器324輸出之第二控制訊號C2能 夠較容易之控制該控制電路121，實現該二開關128、 129之導通或截止。因此，具備該電壓處理電路323之液 晶顯示器100之工作準確性更高。 [0044] 請一併參閱圖6與圖7,圖6是本發明液晶顯示器第二實施 方式之結構示意圖。圖7是圖6所示液晶顯示器之資料驅 動器之局部結構示意圖。該液晶顯示器400也是一常黑型 液晶顯示器，其與第一實施方式之液晶顯示器100之結構 大致相同，其主要差別在於：首先，該液晶顯示器400進 一步包括一預設電壓產生電路480，該預設電壓產生電路 480連接至該資料驅動器436，用於提供一第一預設電壓 及一第二預設電壓至該資料驅動器436。該公共電壓產生 電路470與該資料驅動器436無連接。其次，該資料驅動 器436進一步包括一第三電壓輸入端430。該資料驅動器 436之控制電路421進一步包括一連接於該第三電壓輸入 端430與該電壓輸出端427之間之第三開關431。該電壓 處理電路423與該電壓處理電路123、223及323均不相同 ，在該液晶顯示器400開機瞬間至該時序控制器432開始 提供時序訊號及資料訊號至該資料驅動器436之前之時段 099120564 表單編號A0101 第20頁/共40頁 0992036324-0 201201188 内，該資料驅動器436之電壓處理電路423能夠輸出一第 三控制訊號C3代替輸出第一控制訊號C1至該控制電路421 〇 [0045] 該液晶顯示器400之工作原理與該液晶顯示器100之工作 原理基本相同，因此，該液晶顯示器400之工作原理簡述 如下：[0035] ❹ Start working normally. The data processing circuit 120 receives the data signal and converts the data signal to a corresponding data voltage. At the same time, after the delay time, the reset chip 224 outputs a second control signal C2 to the control circuit 121. The control circuit 121 controls the second switch 129 to be turned on according to the second control signal C2, and controls the first A switch 128 is turned off, and further, the data processing circuit 120 outputs a data voltage to the complex data line 104. The scan driver 134 outputs a scan voltage to the scan line 102. The data voltage on the data line 104 is output to the pixel electrode 111 by the thin film transistor 108. Thereby, the liquid crystal panel 110 displays a normal picture. The second control signal C2 is the power supply voltage Vcc. When the user presses the power on/off button of the liquid crystal display 100 to select to turn off the liquid crystal display 100, the image signal provided by the external circuit 115 to the timing controller 132 is first cut off, and then the power circuit 150 outputs to the The power supply voltage Vcc of the reset wafer 224 begins to decrease and rapidly drops to the second reference voltage level. The reset wafer 224 again outputs the first control signal C1 to the control circuit 121. The control circuit 121 is based on the first The control signal C1 again controls the first switch 128 to be turned on, and controls the second switch 129 to be turned off. Further, the common voltage is again output to the complex data line 104 by the first switch 128 and the voltage output terminal 127, and The thin film transistor 108 is loaded to the pixel electrode 111. Therefore, the voltage on the common electrode 112 is the same as the voltage on the halogen electrode 111, and the clamping of the liquid crystal molecules is 0 volts, so that the liquid crystal display 100 displays a black screen until the plural of the liquid crystal panel 110 The charge on the pixel 106 is released. The second reference voltage level is preferably the reference voltage REF. 099120564 Form No. A0101 Page 17 / Total 40 Page 0992036324-0 201201188 [0036] Therefore, when the liquid crystal display 100 enters the shutdown period, the data driver 136 supplies a common voltage to the plurality of pixel electrodes 111, so that the liquid crystal The display 100 also displays a black screen when it is turned off until the charge on the plurality of pixels 106 of the liquid crystal panel is released. Thereby, the shutdown phenomenon of the liquid crystal display 100 is improved. [0037] Further, the data driver 136 is in the period when the liquid crystal display 100 is turned on until the capacitor 227 is charged, that is, before the timing controller 132 outputs the normal data signal to the data driver 136, the data driver 136 selects to output a common voltage to the plurality of pixel electrodes 111, and avoids outputting the randomly grabbed data voltage to the plurality of pixel electrodes Π1. Since the pinch of the liquid crystal molecules of the liquid crystal display 100 is 0 volt during this period, the liquid crystal display 100 displays a black screen. Thereby, the phenomenon of turning on the image of the liquid crystal display 100 is further improved. [0038] In addition, the liquid crystal display device 100 selects to output a common voltage to the pixel 106 during the startup period until the power supply voltage Vcc reaches a fixed value period, and when the liquid crystal display device 100 is turned off, so that the liquid crystal display unit 100 The pinch of the two ends of the molecule is crouched, thereby maximally preventing the aging of the liquid crystal molecules. Referring to FIG. 5, the voltage processing circuit 123 can also be replaced with the structure of the voltage processing circuit 323 as shown in FIG. The voltage processing circuit 323 includes a comparator 324, a reset transistor 325, a delay circuit 326, and a reference voltage generating circuit 327. The comparator 324 includes a positive phase input terminal 328, a negative phase input terminal 329, and an output terminal 330. The power supply circuit 150 is connected to the positive 099120564 form number A0101 page 18/40 page 0992036324-0 201201188 phase wheel 328 by the reset chip 325. The reference voltage generating circuit 327 is connected to the negative phase input terminal 329. The output 330 of the comparator 324 is coupled to the control circuit 121. The delay circuit 326 is coupled between the reset die 325 and ground. The structure and function of the reset chip 325 and the delay circuit 326 are substantially the same as those of the reset chip 224 and the delay circuit 225. The structure and function of the reference voltage generating circuit 327 and the structure of the reference voltage generating circuit 14 2 And the function is basically the same. [0041] ❹ the liquid crystal display is charged to the delay circuit 326 after the power-on instant, and when the liquid crystal display 100 is turned off, the reset wafer 325 outputs a low level (eg, crouching) to the truth wheel 328. The 0 volt voltage is less than the reference voltage REF that the reference voltage generating circuit 327 outputs to the negative phase input terminal 329. The comparator 324 outputs a first control signal C1 to the control circuit 121 via its output terminal 33. The control circuit 202 controls the first switch 128 to be turned on according to the first control signal C1, and controls the second switch 12 to be turned off. Thus, the control circuit 211 outputs a common voltage, Ο [0042] the common voltage is output to the pixel electrode 111 by the voltage output terminal 127. Further, the liquid crystal display 100 displays a black screen at the time of power-on until the delay circuit 326 is charged and when it is turned off. When the liquid crystal display device 100 is in normal operation, the reset chip 325 outputs the power supply voltage Vcc to the non-inverting input terminal 328. The power supply voltage Vcc is greater than the reference voltage REF. Accordingly, the comparator 324 outputs a second control signal C2. To the control circuit 121. The control circuit 121 controls the first switch 128 to be turned off according to the second control signal C2, and controls the second switch 129 to be turned on. Thus, the control circuit 121 outputs a data voltage which is outputted to the halogen electrode 1H by the voltage output terminal 127. Further, 099120564 Form No. A0101 Page 19 of 40 0992036324-0 201201188 , the liquid crystal display 10 0 displays a normal picture. [0043] Since the second control signal C2 outputted by the reset chip 224 is the power supply voltage Vcc, the maximum value of the power supply voltage Vcc is usually 3.3 volts, and the voltage thereof is small, and therefore, the second output by the reset wafer 224 The control signal C2 is more difficult to control the control circuit 121, and the two switches 128, 129 are turned on or off. However, the voltage corresponding to the second control signal C2 outputted by the comparator 324 is relatively large. Therefore, the second control signal C2 output by the comparator 324 can control the control circuit 121 relatively easily, and the two switches 128 and 129 can be implemented. Turn on or off. Therefore, the liquid crystal display 100 having the voltage processing circuit 323 has higher operational accuracy. Referring to FIG. 6 and FIG. 7, FIG. 6 is a schematic structural view of a second embodiment of the liquid crystal display of the present invention. Fig. 7 is a partial structural view showing the data drive of the liquid crystal display shown in Fig. 6. The liquid crystal display 400 is also a normally black liquid crystal display, which is substantially the same as the liquid crystal display 100 of the first embodiment. The main difference is that, firstly, the liquid crystal display 400 further includes a preset voltage generating circuit 480. The voltage generating circuit 480 is connected to the data driver 436 for providing a first predetermined voltage and a second predetermined voltage to the data driver 436. The common voltage generating circuit 470 is not connected to the data driver 436. Second, the data driver 436 further includes a third voltage input 430. The control circuit 421 of the data driver 436 further includes a third switch 431 coupled between the third voltage input terminal 430 and the voltage output terminal 427. The voltage processing circuit 423 and the voltage processing circuits 123, 223 and 323 are different, and the form number is 099120564 when the liquid crystal display 400 is turned on until the timing controller 432 starts to provide the timing signal and the data signal to the data driver 436. A0101, page 20 of 40, 0992036324-0 201201188, the voltage processing circuit 423 of the data driver 436 can output a third control signal C3 instead of outputting the first control signal C1 to the control circuit 421 〇 [0045] the liquid crystal display The working principle of the liquid crystal display 100 is basically the same as that of the liquid crystal display 100. Therefore, the working principle of the liquid crystal display 400 is briefly described as follows:
[0046] G 在該液晶顯示器400開機瞬間至該時序控制器432開始提 供時序訊號及資料訊號至該資料驅動器436之前之時段内 ，當該控制電路421接收到該第三控制訊號C3時，該控制 電路421控制該第三開關431導通，並控制該第一開關 428與該第二開關429截止，該預設電壓產生電路480輸 出之第一預設電壓藉由該第三電壓輸入端430、該第三開 關431及該電壓輸出端427輸出至該複數畫素電極411。 從而，該液晶顯示器400顯示同一灰階畫面。 [0047] ❹ 當該時序控制器432提供時序訊號及資料訊號至該資料驅 動器436時，該液晶顯示器40 0開始正常工作。此時，該 電壓處理電路423切換該第三控制訊號C3為該第二控制訊 號C2，並輸出該第二控制訊號C2至該控制電路421。該控 制電路421根據接收到之該第二控制訊號C2控制該第二開 關429導通，並控制該第一開關428與該第三開關431截 止，進而該資料處理電路420輸出之資料電壓藉由該第二 開關429及該電壓輸出端427輸出至該複數畫素電極411 。從而，該液晶顯示器400顯示正常之畫面。 [0048] 當該液晶顯示器400關機時，該電壓處理電路423切換該 099120564 表單編號A0101 第21頁/共40頁 0992036324-0 201201188 第一控制訊號C 2為該第一控制訊號C1，並輸出該第一控 制訊號C1至該控制電路421。該控制電路421根據該第一 控制訊號C1對應控制該第一開關428導通，並控制該第二 開關429及該第三開關431截止。進而，該預設電壓產生 電路480輸出之第二預設電壓藉由該第一電壓輸入端425 、該第一開關428及該電壓輸出端427施加至該複數畫素 電極411。從而’該液晶顯示器400顯示同一灰階晝面， 直至該液晶面板410之複數畫素406上之電荷釋放完畢。 其中，該第一預設電壓與該第二預設電壓不同。 [0049] 由於該資料驅動器436之控制電路421具有三個開關，且 對應該液晶顯示器4 0 0之不同工作時段’:該電壓處理電路 423能夠對應提供三個不同之控制訊號ci、C2及C3至該 控制電路121，進而對應控制該三個開關中一個開關導通 ，另外兩個開關截止’從而，該資料驅動器436能夠在該 液晶顯示器40 0開機瞬間至該時序控制器432開始提供時 序訊號及資料訊號至該資嵙驅動器436之前之時段内輸出 該第一預設電堡至該複數畫素電極411，而在該液晶顯示 器400關機時，該資料驅動器436對應輸出該第二預設電 壓至該複數畫素電極411。因此，在該液晶顯示器4〇〇開 機瞬間至該時序控制器432開始提供時序訊號及資料訊號 至該資料驅動器436之前之時段内、及在該液晶顯示器 400關機時，該液晶顯示器400可以顯示二不同之灰階晝 面。 本發明並不限於上述實施方式’例如，該第一預設電壓 與s亥第一預6又電壓相同，且與該公共電麼不同。另外， 099120564 表單編號A0101 第22頁/共40頁 0992036324-0 [0050] 201201188 =-預設電壓與該第二預設電壓亦可以與該公共電壓 [0051] 該液晶顯示器100進一步包括一與該液晶面板ΐι〇電連接 之電路板，該復位晶片224、325與該延時電路奶 '^可以設置於該電路板上，而非集成於該資料驅動器136 [0052] ❹ 該液晶顯示器400也可以為一常白型液晶顯示器 白=顯示器’優選地’選擇施加至該複數畫素電極 親=1^、第二預設電壓能约使得該液晶顧示器彻 [0053] 雖然本發明已以實施例揭露如上，然其並非用以限定本 發明’任何所屬技術領域中具有通常知識者，在不脱離 本發明之精神和範圍内，當可作些許之更動與潤飾，故 本發明之賴當視後社中料鄕_界定者為 準。 G 【圖式簡單說明】 [0054] 圖1是本發明液晶顯示器第-實施方式之結構示意圖。 [0055] 圖2是圖i所示液晶顯示器之資料驅動器之局部結構示意 圖。 L0056] 圖3是圖2所示資料驅動器之電壓處理電路一實施方式之 結構示意圖》 [0057] 圖4是圖2所示資料驅動器之電壓處理電路第一替換實施 方式之結構示意圖。 099120564 表單編號A0101 第23頁/共40頁 0992036324-0 201201188 [0058] 圖5是圖2所示資料驅動器之電壓處理電路第二替換實施 方式之結構示意圖。 [0059] 圖6是本發明液晶顯示器第二實施方式之結構示意圖。 [0060] 圖7是圖6所示液晶顯示器之資料驅動器之局部結構示意 圖。 【主要元件符號說明】 [0061] 液晶顯不為 100、400 [0062] 液晶面板 110 ' 410 [0063] 驅動電路 130 [0064] 電源電路 150 [0065] 公共電壓產生電路 170、470 [0066] 掃描線 102 [0067] 資料線 104 [0068] 薄膜電晶體 108 [0069] 晝素電極 111 、 411 [0070] 公共電極 112 [0071] 液晶電容 114 [0072] 存儲電容 116 [0073] 畫素 106、406 [0074] 時序控制器 132 ' 432 099120564 表單編號 A0101 第 24 頁/共 40 頁 0992036324-0 201201188 [0075] 掃描驅動器 134 [0076] 貢料驅動益 136 ' 436 [0077] 外部電路 115 [0078] 資料處理電路 120 ' 420 [0079] 控制電路 121 、 421 [0080] 電壓處理電路 123 ' 223 ' 323、423 [0081] 訊號輸入端 124 〇 [0082] 第一電壓輸入端 125 ' 425 [0083] 第二電壓輸入端 126 [0084] 第三電壓輸入端 430 [0085] 電壓輸出端 127 ' 427 [0086] 第一開關 128 ' 428 [0087] 第二開關 129、 429 [0088] 第三開關 431 [0089] 比較器 141 、 324 [0090] 參考電壓產生電路 142 、 327 [0091] 正相輸入端 143 、 328 [0092] 負相輸入端 144 、 329 [0093] 輸出端 145 ' 330 099120564 表單編號A0101 第25頁/共40頁 0992036324-0 201201188 [0094] 復位晶片 224 ' 325 [0095] 延時電路 225 ' 326 [0096] 第一電阻 146 [0097] 第二電阻 147 [0098] 電阻 226 [0099] 電容 148 ' 227 [0100] 二極體 149 [0101] 外部直流電源 105 099120564 表單編號 A0101 第 26 頁/共 40 頁 0992036324-0[0046] G, when the liquid crystal display 400 is turned on until the timing controller 432 starts to provide the timing signal and the data signal to the data driver 436, when the control circuit 421 receives the third control signal C3, The control circuit 421 controls the third switch 431 to be turned on, and controls the first switch 428 and the second switch 429 to be turned off. The first preset voltage output by the preset voltage generating circuit 480 is passed through the third voltage input terminal 430. The third switch 431 and the voltage output terminal 427 are output to the complex pixel electrode 411. Thus, the liquid crystal display 400 displays the same grayscale picture. [0047] When the timing controller 432 provides the timing signal and the data signal to the data driver 436, the liquid crystal display 40 starts normal operation. At this time, the voltage processing circuit 423 switches the third control signal C3 to the second control signal C2, and outputs the second control signal C2 to the control circuit 421. The control circuit 421 controls the second switch 429 to be turned on according to the received second control signal C2, and controls the first switch 428 and the third switch 431 to be turned off, and the data voltage output by the data processing circuit 420 is thereby The second switch 429 and the voltage output terminal 427 are output to the complex pixel electrode 411. Thus, the liquid crystal display 400 displays a normal picture. [0048] When the liquid crystal display 400 is turned off, the voltage processing circuit 423 switches the 099120564 Form No. A0101 Page 21 / Total 40 Page 0992036324-0 201201188 The first control signal C 2 is the first control signal C1, and outputs the The first control signal C1 is to the control circuit 421. The control circuit 421 controls the first switch 428 to be turned on according to the first control signal C1, and controls the second switch 429 and the third switch 431 to be turned off. Further, the second preset voltage output by the preset voltage generating circuit 480 is applied to the complex pixel electrode 411 by the first voltage input terminal 425, the first switch 428, and the voltage output terminal 427. Thus, the liquid crystal display 400 displays the same grayscale surface until the charge on the plurality of pixels 406 of the liquid crystal panel 410 is released. The first preset voltage is different from the second preset voltage. [0049] Since the control circuit 421 of the data driver 436 has three switches and corresponds to different working periods of the liquid crystal display 400: the voltage processing circuit 423 can provide three different control signals ci, C2 and C3 correspondingly. Up to the control circuit 121, correspondingly controlling one of the three switches to be turned on, and the other two switches are turned off. Thus, the data driver 436 can start to provide timing signals to the timing controller 432 when the liquid crystal display 40 is turned on. The first preset electric bunker is outputted to the plurality of pixel electrodes 411 during a period before the data signal is sent to the resource driver 436, and when the liquid crystal display 400 is turned off, the data driver 436 correspondingly outputs the second preset voltage to The complex pixel electrode 411. Therefore, the liquid crystal display 400 can display two times during the period from the start of the liquid crystal display 4 to the time when the timing controller 432 starts to provide the timing signal and the data signal to the data driver 436, and when the liquid crystal display 400 is turned off. Different gray scales. The present invention is not limited to the above embodiment. For example, the first predetermined voltage is the same as the first pre-6 voltage and is different from the common electric power. In addition, 099120564 Form No. A0101 Page 22 / Total 40 Page 0992036324-0 [0050] 201201188 = - The preset voltage and the second preset voltage can also be combined with the common voltage [0051] The liquid crystal display 100 further includes a The liquid crystal panel is electrically connected to the circuit board, and the reset wafers 224, 325 and the delay circuit milk can be disposed on the circuit board instead of being integrated in the data driver 136. [0052] The liquid crystal display 400 can also be A normally white type liquid crystal display white = display 'preferably' is selectively applied to the plurality of pixel electrodes =1, the second predetermined voltage energy is approximately such that the liquid crystal display is clear [0053] although the present invention has been The disclosure of the present invention is not intended to limit the invention, and it is intended to be a matter of ordinary skill in the art, and the invention may be modified and modified without departing from the spirit and scope of the invention. The latter is subject to the definition of _ _. G [Simple Description of the Drawings] [0054] Fig. 1 is a schematic view showing the structure of a liquid crystal display according to a first embodiment of the present invention. 2 is a partial structural schematic view of a data driver of the liquid crystal display shown in FIG. 3 is a schematic structural view of an embodiment of a voltage processing circuit of the data driver shown in FIG. 2. [0057] FIG. 4 is a schematic structural view showing a first alternative embodiment of a voltage processing circuit of the data driver shown in FIG. 2. 099120564 Form No. A0101 Page 23 of 40 0992036324-0 201201188 [0058] FIG. 5 is a block diagram showing a second alternative embodiment of the voltage processing circuit of the data driver shown in FIG. 2. 6 is a schematic structural view of a second embodiment of a liquid crystal display according to the present invention. 7 is a partial structural schematic view of a data driver of the liquid crystal display shown in FIG. 6. [Main component symbol description] [0061] Liquid crystal display is not 100, 400 [0062] Liquid crystal panel 110 '410 [0063] Drive circuit 130 [0064] Power supply circuit 150 [0065] Common voltage generation circuit 170, 470 [0066] Scanning Line 102 [0067] Data Line 104 [0068] Thin Film Transistor 108 [0069] Alizarin Electrode 111, 411 [0070] Common Electrode 112 [0071] Liquid Crystal Capacitor 114 [0072] Storage Capacitor 116 [0073] Pixels 106, 406 [0074] Timing Controller 132 ' 432 099120564 Form No. A0101 Page 24 of 40 0992036324-0 201201188 [0075] Scan Driver 134 [0076] tributary drive benefit 136 ' 436 [0078] External circuit 115 [0078] Processing circuit 120 420 [0079] Control circuit 121, 421 [0080] Voltage processing circuit 123 '223' 323, 423 [0081] Signal input 124 〇 [0082] First voltage input 125 ' 425 [0083] Voltage Input 126 [0084] Third Voltage Input 430 [0085] Voltage Output 127 ' 427 [0086] First Switch 128 ' 428 [0087] Second Switch 129, 429 [0088] Third Switch 431 [0089] Comparators 141, 32 4 [0090] Reference voltage generating circuit 142, 327 [0091] Positive phase input terminals 143, 328 [0092] Negative phase input terminals 144, 329 [0093] Output terminal 145 '330 099120564 Form number A0101 Page 25 of 40 0992036324-0 201201188 [0094] Reset Wafer 224 ' 325 [0095] Delay Circuit 225 ' 326 [0096] First Resistor 146 [0097] Second Resistor 147 [0098] Resistor 226 [0099] Capacitor 148 '227 [0100] Polar Body 149 [0101] External DC Power Supply 105 099120564 Form No. A0101 Page 26 of 40 0992036324-0