TWI416735B - A thin film transistor (tft) array substrate and method for manufacturing the same - Google Patents

Abstract

The present invention provides a thin film transistor (TFT) array substrate and a method for manufacturing the same. The TFT array substrate comprises a substrate, a first metal layer, an insulating layer, a semiconductor layer, asecond metal layer, a passivation layer and a transparent electrode layer sequently formed on the substrate. Wherein the first metal layer comprises at least three layers of aluminum(Al) thin film, otherwise the second metal layer may comprise at least the three layers of Al thin film as well. In addition, the aforesaid three layers of Al thin film may have different film density which is formed by different sputter parameter. Therefore, the present invention having at least the three layers Al thin film can not only have the characteristic of low resist, but also prevent Al from hillock growth during the process of high temperature sputter.

Description

Thin film transistor array substrate and manufacturing method thereof

The present invention relates to a liquid crystal display thin film transistor array substrate and a method of fabricating the same, and more particularly to a method for forming a metal layer of a thin film transistor array substrate.

At present, the use of liquid crystal displays (LCDs) has become a trend. Liquid crystal displays have superior features such as high image quality, better space utilization, low power consumption, and no radiation. With the maturity of liquid crystal display technology, liquid crystal displays are also widely used. Application to various fields. Generally, a liquid crystal display is composed of a thin film transistor array substrate, a color filter substrate, and a liquid crystal layer sandwiched between the two substrates. The thin film transistor array substrate mainly comprises a substrate and a pixel structure arranged on the substrate in an array manner. The pixel structure described above is mainly composed of a scanning line, a data line, a Thin Film Transistor (TFT), a pixel electrode, and a common electrode line. The scan line and the data line are respectively used for transmitting the scan signal and the data signal. In order to prevent the signal from being distorted during the transmission process, a metal or a metal alloy with good conductivity is generally used as the material of the scan line and the data line.

Moreover, in the conventional liquid crystal display technology, the scan lines and data lines on the thin film transistor array substrate have a double layer structure of molybdenum (Mo) and aluminum lanthanum (AlNd), and the molybdenum (Mo) and aluminum lanthanum (AlNd) double layers. The structure has been disclosed in the Chinese published patent CN101392375. Fig. 1 is a schematic view showing the structure of a thin film transistor array substrate having a double layer structure of the molybdenum (Mo) and aluminum lanthanum (AlNd). As shown in FIG. 1, on the substrate 10, the scanning line 11 and the data line 12 are vertically arranged to each other to define a pixel structure 13, the pixel electrode 14 is disposed on the pixel structure 13, and the pixel electrode 14 is electrically connected to the pixel. The crystals 15 are connected to the scanning lines 11 and the data lines 12, respectively. Fig. 2 is a cross-sectional view of the pixel structure of the thin film transistor array substrate taken along line A-A in Fig. 1. Referring to FIG. 1 and FIG. 2 together, the thin film transistor 15 includes a gate 151, a source 152 and a drain 153. The gate 151 is connected to the scanning line 11, and the source 152 is connected to the data line 12, The pole 153 is connected to the pixel electrode 13; the first metal layer 22 is disposed on the substrate 21, and the gate 151 and the scan line 11 are both formed by the first metal layer 22, and the first metal layer 22 is made of an aluminum alloy ( The AlNd) layer 221 and a molybdenum (Mo) metal layer 222 are formed in two layers, and an aluminum (AlNd) layer 221 is disposed on the substrate 21, and a molybdenum (Mo) metal layer 222 is disposed on the AlNd layer 221; 23 is disposed on the molybdenum (Mo) metal layer 222, the semiconductor layer 24 is disposed on the insulating layer 23, and the second metal layer 25 is located over the semiconductor layer 24 and partially covers the semiconductor layer 24, wherein the source 152, the drain 153 and the data The wires 12 are all formed by the second metal layer 25, the passivation layer 26 is overlaid on the second metal layer 25 and the passivation layer 26 has a contact hole 261 exposing a portion of the second metal layer 25 such that it is disposed over the passivation layer 26. The transparent electrode layer 27 is connected to the exposed portion of the second metal layer 25 through the contact hole 261, wherein the pixel electrode 14 is formed of the transparent electrode layer 27.

In the above pixel structure, the gate has a two-layer structure of a molybdenum (Mo) metal layer and an aluminum lanthanum (AlNd) layer, although aluminum lanthanum (AlNd) has better temperature stability than aluminum (Al) metal. It can prevent the problem of hillock growth caused by excessive extrusion stress between aluminum atom grains during high temperature film formation, but aluminum lanthanum (AlNd) has higher resistivity than aluminum (Al) metal. Shortcomings.

Considering the increasing trend of LCD size, the length of the scan line and the data line will increase along with the increase of the LCD size, so that the increased scan line and data line increase the resistance value with the length, thus generating signal delay ( RC Delay), so a material with low resistivity is needed to solve the above problem.

Although aluminum (Al) metal has the advantages of low resistivity and low cost compared with aluminum lanthanum (AlNd), the conventional aluminum (Al) metal process is prone to hillocks due to excessive compressive stress between aluminum atoms at high temperature film formation. The problem of (hillock) growth, and thus easy to induce the occurrence of short circuit between the gate of the thin film transistor and the source and the drain.

In view of the above problems, it is currently desired in the industry to obtain a method for manufacturing a thin film transistor array substrate, which can apply a low resistivity material in the prior art while at the same time being able to overcome the small occurrence of such a material at high temperature film formation. Hillock problem.

The object of the present invention is to provide a thin film transistor array substrate and a manufacturing method thereof, wherein the first metal layer on the thin film transistor array substrate has at least three aluminum thin film structures, and the three-layer aluminum thin film structure of the present invention and the foregoing Compared with the gate formed by aluminum lanthanum (AlNd) mentioned in the art, the three-layer aluminum thin film structure of the present invention can have a lower resistivity and can effectively overcome the problem of inducing hillock growth when the metal layer is formed at a high temperature.

In order to achieve the above object, the present invention provides a thin film transistor array substrate comprising a substrate, forming a first metal layer on the substrate, forming an insulating layer on the substrate to cover the first metal layer, and forming a semiconductor on the insulating layer. a layer, a second metal layer is disposed on a portion of the semiconductor layer, a passivation layer is formed on the second metal layer and the semiconductor layer and covers the second metal layer and the semiconductor layer, and the transparent electrode layer is on the passivation layer and covers the passivation layer; The metal layer is a multi-layer film structure, and has at least three aluminum film, the first aluminum film, the second aluminum film and the third aluminum film, wherein the second aluminum film is covered in the first On the aluminum film, the second aluminum film is sandwiched between the first aluminum film and the third aluminum film.

An embodiment of the present invention provides a thin film transistor array substrate including a substrate, a first metal layer formed on the substrate, an insulating layer formed on the substrate to cover the first metal layer, and a semiconductor layer formed on the insulating layer. Providing a second metal layer on a portion of the semiconductor layer, forming a passivation layer on the second metal layer and the semiconductor layer and covering the second metal layer and the semiconductor layer, the transparent electrode layer being on the passivation layer and covering the passivation layer; wherein the second layer The metal layer is a multilayer film structure having at least three layers of aluminum film.

An embodiment of the present invention provides a thin film transistor array substrate including a substrate, a first metal layer formed on the substrate, an insulating layer formed on the substrate to cover the first metal layer, and a semiconductor layer formed on the insulating layer. Providing a second metal layer on a portion of the semiconductor layer, forming a passivation layer on the second metal layer and the semiconductor layer and covering the second metal layer and the semiconductor layer, the transparent electrode layer being on the passivation layer and covering the passivation layer; wherein the first layer The metal layer and the second metal layer are both a multilayer film structure having at least three aluminum film, the first aluminum film, the second aluminum film and the third aluminum film, wherein the second aluminum film The first aluminum film is covered on the first aluminum film, and the second aluminum film is sandwiched between the first aluminum film and the third aluminum film.

In order to achieve the above object, the present invention further provides a method for fabricating a thin film transistor array substrate, the method for manufacturing the thin film transistor array substrate, comprising: first providing a substrate, and then forming a first metal layer on the substrate, and then Forming an insulating layer on the first metal layer and covering the first metal layer on the substrate, depositing a semiconductor layer on the insulating layer, and depositing a second metal layer on the semiconductor layer and the insulating layer. And forming a passivation layer on the insulating layer, the semiconductor layer and the second metal layer, and finally forming a transparent electrode layer on the passivation layer; wherein the first metal layer further comprises at least three aluminum films Coating, wherein an aluminum target and the substrate are first placed in a coating chamber, and deposited on the substrate at a coating pressure of 0.03 Pa to 0.4 Pa, a coating power of not more than 53 kw, and a coating time of not more than 10 s. a first aluminum film is deposited on the first aluminum film at a coating pressure of 0.03 Pa to 0.4 Pa, a coating power of not more than 85 kw, and a coating time of not more than 26 s. Then, a third aluminum film is deposited on the second aluminum film at a coating pressure of 0.03 Pa to 0.4 Pa, a coating power of not more than 53 kw, and a coating time of not more than 12 s.

The above-described features and advantages of the present invention will be more apparent from the following detailed description of the embodiments.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described more fully hereinafter with reference to the accompanying drawings in which preferred embodiments of the invention are illustrated. However, the invention may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. However, the embodiments are provided so that this disclosure will be more fully described and the scope of the invention will be fully disclosed.

In the figures, the thickness of layers, films, and regions are shown exaggerated for clarity. The same reference numerals are used to refer to the same elements. It is also understood that when an element such as a layer, a film, a region or a substrate is referred to as being "on" another element, it may be directly on the other element or the intervening element may be present.

Hereinafter, a thin film transistor array substrate and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily implement the present invention.

In order to enable the present invention to be easily implemented by those skilled in the relevant art, please refer to FIGS. 3, 4a and 4b, wherein FIG. 3 is a schematic diagram of the structure of the thin film transistor array substrate of the present invention, and FIG. 4a is a diagram In Fig. 3, the thin film transistor array substrate in the BB' direction has a three-layer aluminum (Al) structure, and Fig. 4b is a partial enlarged view of Fig. 4a. As shown in FIG. 3, on the substrate 30, scan lines 32 and data lines 33 are disposed and vertically intersected with each other, thereby defining a pixel structure 31, and the pixel electrodes 34 are disposed in the pixel structure 31, and The pixel electrodes 34 are respectively connected to the scan line 32 and the data line 33 through the thin film transistor 35. The thin film transistor 35 includes a gate 351, a source 352 and a drain 353, and the gate 351 is connected to the scan line 32. The pole 352 is connected to the data line 33, and the drain 353 is connected to the pixel electrode 34. Referring to FIG. 4a and FIG. 4b simultaneously, the first metal layer 41 is disposed on the substrate 40, and the gate 351 and the scan line 32 are both formed by the first metal layer 41, and the first metal layer 41 thereof. The three-layer aluminum film is composed of a first aluminum film 411, a second aluminum film 412 and a third aluminum film 413. The structural relationship between the films of the first metal layer 41 is described in detail. The first aluminum film 411 is disposed on the substrate 40, the second aluminum film 412 is disposed on the first aluminum film 411 and covers the first aluminum film 411, and the third aluminum film 413 is disposed on the second aluminum film 412. And covering the second aluminum film 412, wherein the second aluminum film 412 is interposed between the first aluminum film 411 and the third aluminum film 413, and the first aluminum film 411, the second aluminum film 412 and the third aluminum film The 413 series is formed by different coating parameters, and thus has different film qualities; wherein the first aluminum film 411 and the third aluminum film 413 adopt low-power coating parameters, and the surface of the coated aluminum film is relatively smooth, and the aluminum film is aluminum. The gap between the metal grains is small, thus making it The film is formed as a film-like dense aluminum film; the second aluminum film 412 adopts high-power coating parameters, and the surface of the coated aluminum film is rough, and the gap between the aluminum metal grains in the film is large, so that the aluminum film is rendered. It is a film-like loose aluminum film; continued, the insulating layer 42 is located on the first metal layer 41 and covers the substrate 40 and the first metal layer 41, and the semiconductor layer 43 is disposed on the insulating layer 42, and the second metal layer 44 is located in the semiconductor Above the layer 43 and partially covering the semiconductor layer 43, wherein the source 352, the drain 353 and the data line 33 are formed by the second metal layer 44, the passivation layer 45 is disposed over the second metal layer 44, and the passivation layer 45 The second metal layer 44 having a contact hole 451 exposed portion is such that the transparent electrode layer 46 disposed on the passivation layer 45 is connected to a portion of the second metal layer 44 through the contact hole 451, wherein the pixel electrode 34 is composed of a transparent electrode layer 46 is formed.

5 is a flow chart of a method for fabricating a thin film transistor array substrate according to an embodiment of the present invention, as shown in FIG. 5, and referring to FIGS. 3, 4a and 4b, the flow of the method for manufacturing the thin film transistor array substrate. The following steps are as follows: firstly, a substrate (S51) is provided, the substrate and the aluminum target are disposed in a coating cavity, and then the aluminum target is sputtered on the substrate by magnetron sputtering in the coating cavity to form a substrate. a first metal layer (S52), wherein the first metal layer is composed of a three-layer aluminum film, and the three-layer aluminum film is first set to a coating pressure of 0.03 Pa to 0.4 Pa, and a coating film is applied. The power is not more than 53kw, the coating time is not more than 10s, and then the aluminum target is sputtered on the substrate by magnetron sputtering to deposit a first aluminum film (S521), and then the coating cavity is coated. The control parameter is set to a coating pressure of 0.03 Pa to 0.4 Pa, a coating power of not more than 85 kw, and a coating time of not more than 26 s, and then a sputtering target is used to deposit an aluminum target on the first aluminum film to deposit a second. Aluminum film (S522), and then the plating The coating control parameter of the cavity is set to a coating pressure of 0.03 Pa to 0.4 Pa, a coating power of not more than 53 kw, and a coating time of not more than 12 s, and then the aluminum target is sputtered onto the second aluminum film by magnetron sputtering. Depositing a third aluminum film (S523), after performing the above operation, applying, exposing, developing and etching the three-layer aluminum film through the plate making process and etching process to form the first metal layer to form a plurality of scan lines and gates Extremely, the above-mentioned plate making works mainly include coating, exposure, development and the like.

Then, an insulating layer is formed on the first metal layer by chemical vapor deposition, and the insulating layer completely covers the first metal layer (S53), and then the semiconductor layer is deposited on the insulating layer (S54) After the insulating layer and the semiconductor layer are deposited, the semiconductor layer is smeared, exposed, developed, and etched to form a thin film transistor through a plate-making process and an etching process, wherein the insulating layer is usually tantalum nitride. It is also possible to use ruthenium oxide and ruthenium oxynitride.

Then, an aluminum target is sputtered on the insulating layer and the semiconductor layer by magnetron sputtering in the coating chamber to form a second metal layer (S55), and the second metal layer is smeared and exposed through a plate making process and an etching process. And developing and etching to form a plurality of data lines and a source and a drain of the plurality of thin film transistors; forming a passivation layer (S56) on the insulating layer, the semiconductor layer and the second metal layer, and the passivation layer Etching to form a contact hole, the exposed portion of the contact hole is a drain portion of the second metal layer; finally, a transparent electrode layer (S57) is formed on the passivation layer, and transparent to the plate making process and etching process The electrode layer is smeared, exposed, developed, and etched to form a plurality of pixel electrodes. The material of the transparent electrode layer is one of indium tin oxide (ITO) or indium zinc oxide (IZO), but may be other transparent conductive materials.

In the above method for manufacturing a thin film transistor array substrate, wherein the first metal layer is composed of a three-layer aluminum film, and the coating control parameter of the first aluminum film of the three-layer aluminum film in the coating cavity is set to a pressure of 0.03 Pa. ～0.4 Pa, coating power is not more than 53kw, coating time is not more than 10s, and then the first aluminum film is sputtered on the substrate by magnetron sputtering, and the coating control parameter setting can be A membranous dense first aluminum film is obtained.

In the above method for manufacturing a thin film transistor array substrate, wherein the first metal layer is composed of a three-layer aluminum film, and the coating control parameter of the second aluminum film of the three-layer aluminum film in the coating cavity is set to a pressure of 0.03. Pa ~ 0.4 Pa, coating power is not more than 85kw, coating time is not more than 26s, and then the second aluminum film is sputtered on the first aluminum film by magnetron sputtering, and the coating is controlled. A second aluminum film with a loose film can be obtained under the parameter setting.

In the above method for manufacturing a thin film transistor array substrate, wherein the first metal layer is composed of a three-layer aluminum film, and the coating control parameter of the third aluminum film of the three-layer aluminum film in the coating cavity is set to a pressure of 0.03. Pa~0.4 Pa, coating power is not more than 53kw, coating time is not more than 12s, and then the aluminum target is sputter-deposited by magnetron sputtering to deposit the third aluminum film on the second aluminum film. A membranous dense third aluminum film can be obtained under the control parameter setting.

In the above method for manufacturing a thin film transistor array substrate, in the case where the first aluminum thin film of the first metal layer is formed, the plating power is set to be an optimum coating power in the coating control parameter of 30 kw to 53 kw.

In the method for manufacturing a thin film transistor array substrate, in which the second aluminum thin film of the first metal layer is formed, the coating power is set to 50 kw to 85 kw in the coating control parameter, and the coating time is set to 16 s to 26 s. And coating time.

In the method for manufacturing a thin film transistor array substrate, in which the third aluminum thin film of the first metal layer is formed, the coating power is set to 30 kw to 53 kw in the coating control parameter, and the coating time is set to 2 s to 12 s. And coating time.

Fig. 6a is a cross-sectional view of the thin film transistor array substrate in the B-B' direction in Fig. 3 having a Mo-Al structure, and Fig. 6b is a partially enlarged view of Fig. 6a. In the following description, please refer to the figures 3, 6a, and 6b. As shown in FIG. 3, the scanning line 32 and the data line 33 are disposed on the substrate 30 and are vertically arranged to intersect each other, thereby defining the pixel structure 31. The pixel electrode 34 is disposed in the pixel structure 31, and the pixel electrode 34 is connected to the scan line 32 and the data line 33 through the thin film transistor 35, wherein the thin film transistor 35 includes a gate 351, a source 352, and The drain 353 has a gate 351 connected to the scan line 32, a source 352 connected to the data line 33, and a drain 353 connected to the pixel electrode 34. Referring to the above, while referring to FIGS. 6a and 6b, the first metal layer 61 is disposed on the substrate 60, and the gate 351 and the scan line 32 are both formed by the first metal layer 61, and the first metal layer 61 thereof. A three-layer aluminum film and a first molybdenum film 614 are included, wherein the three aluminum films are respectively composed of a first aluminum film 611, a second aluminum film 612, and a third aluminum film 613, and the first metal layer 61 is described in detail herein. The structural relationship between the layers of the film is: the first aluminum film 611 is disposed on the substrate 60, the second aluminum film 612 is disposed on the first aluminum film 611 and covers the first aluminum film 611, and the third aluminum film 613 is disposed. The second aluminum film 612 is over the second aluminum film 612, and finally the first molybdenum film 614 is disposed on the third aluminum film 613 and covers the third aluminum film 613. The first molybdenum film 614 is covered. A molybdenum-aluminum structure is formed on the three-layer aluminum film to enhance the compactness of the first metal layer to reduce hillock generation, and the first aluminum film 611, the second aluminum film 612 and the third layer Aluminum film 613 is formed by different coating parameters, so they are different Membrane; wherein the first aluminum film 611 and the third aluminum film 613 adopt low-power coating parameters, the surface of the coated aluminum film is relatively smooth, and the gap between the aluminum metal grains in the aluminum film is small, so that the aluminum is made The film is formed as a film-like dense aluminum film; the second aluminum film 612 adopts high-power coating parameters, and the surface of the coated aluminum film is rough, and the gap between the aluminum metal grains in the film is large, so that the aluminum film is rendered. It is a film-like loose aluminum film; continued, the insulating layer 62 is located on the first metal layer 61 and covers the substrate 60 and the first metal layer 61, and the semiconductor 63 layer is disposed on the insulating layer 62, and the second metal layer 64 is located in the semiconductor Above the layer 63 and partially covering the semiconductor layer 63, wherein the source 352, the drain 353 and the data line 33 are formed by the second metal layer 64, the passivation layer 65 is disposed over the second metal layer 64, and the passivation layer 65 The second metal layer 64 having a contact hole 651 exposed portion is such that the transparent electrode layer 66 disposed on the passivation layer 65 is connected to a portion of the second metal layer 64 through the contact hole 651, wherein the pixel electrode 34 is composed of a transparent electrode layer Form 66 .

FIG. 7 is a flow chart of a method for fabricating a thin film transistor array substrate according to another embodiment of the present invention. As shown in FIG. 7, and referring to FIGS. 3, 6a and 6b at the same time, the flow of the method for manufacturing the thin film transistor array substrate is as follows: first, a substrate (S71) is provided, and the substrate and the aluminum target are disposed. In a coating chamber, an aluminum target is sputtered on the substrate in a magnetron sputtering manner to form a first metal layer (S72), wherein the first metal layer is composed of a three-layer aluminum film. And a layer of molybdenum film, the three-layer aluminum film and the first molybdenum film firstly set the coating control parameter of the coating cavity to a coating pressure of 0.03 Pa to 0.4 Pa, a coating power of not more than 53 kw, and a coating time of not more than After 10s, the aluminum target was sputtered on the substrate by magnetron sputtering to deposit a first aluminum film (S721), and then the coating control parameters of the coating cavity were set to a coating pressure of 0.03 Pa to 0.4. Pa, the coating power is not more than 85kw, the coating time is not more than 26s, and then the aluminum target is sputtered on the first aluminum film by magnetron sputtering to deposit a second aluminum film (S722), and then Coating control parameters of the coating chamber are set to coating The force of 0.03 Pa~0.4 Pa, the coating power is not more than 53kw, the coating time is not more than 12s, and the aluminum target is sputtered on the second aluminum film by magnetron sputtering to deposit a third aluminum film (S723) And depositing a first molybdenum film (S724) on the third aluminum film, and performing the above operation, then applying, exposing, developing, and etching the three-layer aluminum film and the first molybdenum film through a plate-making process and an etching process. The first metal layer is formed into a plurality of scan lines and gates, and the plate-making process mainly includes engineering, exposure, development, and the like.

Then, an insulating layer is continuously formed on the first metal layer by chemical vapor deposition, and the insulating layer completely covers the first metal layer (S73), and then the semiconductor layer is deposited on the insulating layer ( S74), after the insulating layer and the semiconductor layer are deposited, the semiconductor layer is smeared, exposed, developed, and etched through a plate-making process and an etching process to form a channel of the thin film transistor, wherein the material of the insulating layer is usually nitrided. Helium, bismuth oxide and bismuth oxynitride can also be used.

Then, an aluminum target is sputtered on the insulating layer and the semiconductor layer by magnetron sputtering in the coating chamber to form a second metal layer (S75), and the second metal layer is smeared and exposed through a plate making process and an etching process. And developing and etching to form a plurality of data lines and a source and a drain of the plurality of thin film transistors; forming a passivation layer (S76) on the insulating layer, the semiconductor layer and the second metal layer, and the passivation layer Dry etching is performed to form a contact hole, the exposed portion of the contact hole is a drain portion of the second metal layer; finally, a transparent electrode layer (S77) is formed on the passivation layer, and the transparent electrode is subjected to plate making engineering and etching engineering The layer is smeared, exposed, developed, and etched to form a plurality of pixel electrodes, wherein the transparent electrode layer is made of indium tin oxide (ITO) or indium zinc oxide (IZO), but may be other transparent conductive materials.

In the above method for manufacturing a thin film transistor array substrate, wherein the first metal layer is composed of a three-layer aluminum film, and the coating control parameter of the first aluminum film of the three-layer aluminum film in the coating cavity is set to a coating pressure of 0.03. Pa ~ 0.4 Pa, coating power is not more than 53kw, coating time is not more than 10s, and then the aluminum target is sputter deposited on the substrate by magnetron sputtering, under the coating control parameter setting A membranous dense first aluminum film can be obtained.

In the above method for fabricating a thin film transistor array substrate, wherein the first metal layer is composed of a three-layer aluminum film, and the coating control parameter of the second aluminum film of the three-layer aluminum film in the coating cavity is set to a coating pressure. 0.03 Pa~0.4 Pa, coating power is not more than 85kw, coating time is not more than 26s, and then the second aluminum film is sputtered on the first aluminum film by magnetron sputtering. A second aluminum film with a loose film can be obtained under the control parameter setting.

In the above method for manufacturing a thin film transistor array substrate, wherein the first metal layer is composed of a three-layer aluminum film, and the coating control parameter of the third aluminum film of the three-layer aluminum film in the coating cavity is set to a coating pressure. 0.03 Pa～0.4 Pa, coating power is not more than 53kw, coating time is not more than 12s, and then the aluminum target is sputter-deposited by magnetron sputtering to deposit the third aluminum film on the second aluminum film. A thin film of the third aluminum film can be obtained under the control of the coating control parameters.

In the above method for manufacturing a thin film transistor array substrate, in the case where the first aluminum thin film of the first metal layer is formed, the plating power is set to be an optimum coating power in the coating control parameter of 30 kw to 53 kw.

In the method for manufacturing a thin film transistor array substrate, in which the second aluminum thin film of the first metal layer is formed, the coating power is set to 50 kw to 85 kw in the coating control parameter, and the coating time is set to 16 s to 26 s. And coating time.

In the method for manufacturing a thin film transistor array substrate, in which the third aluminum thin film of the first metal layer is formed, the coating power is set to 30 kw to 53 kw in the coating control parameter, and the coating time is set to 2 s to 12 s. And coating time.

The thin film transistor array substrate of the present invention and the method of manufacturing the same, wherein the first molybdenum film may be replaced by a molybdenum alloy or other materials; and the thin film transistor array substrate of the present invention and the method of manufacturing the same, wherein the first molybdenum The film is covered on the three-layer aluminum film, which not only can relieve the hillock of the three-layer aluminum film after high temperature, but also can prevent the three-layer aluminum film from interfering with the insulating layer.

Fig. 8a is a cross-sectional view of the thin film transistor array substrate in the B-B' direction in Fig. 3 having a Mo-Al-Mo structure, and Fig. 8b is a partially enlarged view of Fig. 8a. In the following description, please refer to FIGS. 3, 8a and 8b. As shown in FIG. 3, on the substrate 30, scan lines 32 and data lines 33 are disposed and arranged perpendicularly to each other, thereby defining a pixel structure. 31, the pixel electrode 34 is disposed in the pixel structure 31, and the pixel electrode 34 is connected to the scan line 32 and the data line 33 through the thin film transistor 35, wherein the thin film transistor 35 includes a gate 351 and a source 352. The gate 351 is connected to the scan line 32, the source 352 is connected to the data line 33, and the drain 353 is connected to the pixel electrode 34. Referring to FIG. 8a and FIG. 8b simultaneously, the first metal layer 81 is disposed on the substrate 80 (not shown), and the gate 351 and the scan line 32 are both formed by the first metal layer 81. The first metal layer 81 comprises a three-layer aluminum film, a first molybdenum film 815 and a second molybdenum film 811, and the three-layer aluminum film is composed of a first aluminum film 812, a second aluminum film 813 and a third aluminum film 814, respectively. The structural relationship between the layers of the first metal layer 81 is described in this detail: the second molybdenum film 811 is disposed on the substrate 80, and the first aluminum film 812 is disposed on the second molybdenum film 811 and covers the second The molybdenum aluminum film 811 is disposed on the first aluminum film 812 and covers the first aluminum film 812. The third aluminum film 814 is disposed on the second aluminum film 813 and covers the second aluminum film 813. The first molybdenum film 815 is disposed on the third aluminum film 814 and covers the third aluminum film 814. The three aluminum film is sandwiched between the first molybdenum film 815 and the second molybdenum film 811 to form a molybdenum-aluminum-molybdenum structure to enhance the compactness of the first metal layer to reduce hillock The production. The first aluminum film 812, the second aluminum film 813 and the third aluminum film 814 are formed by different coating parameters, and thus have different film qualities respectively; wherein the first aluminum film 812 and the third aluminum film 814 have low power. With the coating parameters, the surface of the coated aluminum film is relatively smooth, and the gap between the aluminum metal grains in the aluminum film is small, so that the aluminum film is formed as a film-like dense aluminum film; the second aluminum film 813 is high in power. With the coating parameters, the surface of the coated aluminum film is rough, and the gap between the aluminum metal grains in the film is large, so that the aluminum film is formed as a film-like aluminum film; continued, the insulating layer 82 is on the first metal. Above the layer 41 and covering the substrate 80 and the first metal layer 81, the semiconductor layer 83 is disposed on the insulating layer 82, and the second metal layer 84 is over the semiconductor layer 83 and partially covers the semiconductor layer 83, wherein the source 352, 汲The pole 353 and the data line 33 are formed by the second metal layer 84, the passivation layer 85 is disposed over the second metal layer 84, and the passivation layer 85 has a second metal layer 84 exposing a portion of the contact hole 851, so that Passivation layer 8 The transparent electrode layer 86 on 5 is connected to a portion of the second metal layer 84 through the contact hole 851, wherein the pixel electrode 34 is formed by the transparent electrode layer 86.

FIG. 9 is a flow chart showing a method of manufacturing a thin film transistor array substrate according to another embodiment of the present invention. As shown in FIG. 9, and referring to FIGS. 3, 8a and 8b, the flow of the method for manufacturing the thin film transistor array substrate includes the following steps: first providing a substrate (S91), and the substrate and the aluminum target And disposed in a coating cavity, and then sputtering a metal target on the substrate by magnetron sputtering to form a first metal layer (S92), wherein the first metal layer is composed of three layers of aluminum a film, a first layer of molybdenum film and a second molybdenum film, wherein the three layers of aluminum film, the first layer of molybdenum film and the second molybdenum film are first deposited on the substrate (S921), and then the film is coated The coating control parameter of the cavity is set to a coating pressure of 0.03 Pa to 0.4 Pa, a coating power of not more than 53 kw, and a coating time of not more than 10 s, and then the aluminum target is sputtered on the second molybdenum film by magnetron sputtering. Depositing a first aluminum film (S922), and then setting the coating control parameter of the coating cavity to a plating pressure of 0.03 Pa to 0.4 Pa, a coating power of not more than 85 kw, and a coating time of not more than 26 s, and then using magnetic control Sputtering the aluminum target to the first Depositing and covering a second aluminum film (S923) on the film, and then setting the coating control parameter of the coating cavity to a plating pressure of 0.03 Pa to 0.4 Pa, a coating power of not more than 53 kw, and a coating time of not more than 12 s. The aluminum target is sputtered on the second aluminum film by magnetron sputtering to cover and cover a third aluminum film (S924), and then a first molybdenum film (S925) is deposited on the third aluminum film. After the above operation, the three-layer aluminum film, the first molybdenum film and the second molybdenum film are smeared, exposed, developed and etched to form a plurality of scan lines and gates through a plate-making process and an etching process. The above-mentioned plate-making engineering mainly includes engineering, exposure, development and the like.

Then, an insulating layer is continuously formed on the first metal layer by chemical vapor deposition, and the insulating layer completely covers the first metal layer (S93), and then the semiconductor layer is deposited on the insulating layer ( S94), after the insulating layer and the semiconductor layer are deposited, the semiconductor layer is smeared, exposed, developed, and etched through a plate-making process and an etching process to form a channel of the thin film transistor, wherein the material of the insulating layer is usually nitrided. Helium, bismuth oxide and bismuth oxynitride can also be used.

Then, an aluminum target is sputtered on the insulating layer and the semiconductor layer by magnetron sputtering in the coating chamber to form a second metal layer (S95), and the second metal layer is smeared and exposed through a plate making process and an etching process. And developing and etching to form a plurality of data lines and a source and a drain of the plurality of thin film transistors; forming a passivation layer (S96) on the insulating layer, the semiconductor layer and the second metal layer, and the passivation layer Dry etching is performed to form a contact hole, the exposed portion of the contact hole is a drain portion of the second metal layer; finally, a transparent electrode layer (S97) is formed on the passivation layer, and the transparent electrode is subjected to plate making engineering and etching engineering The layer is smeared, exposed, developed, and etched to form a plurality of pixel electrodes, wherein the transparent electrode layer is made of indium tin oxide (ITO) or indium zinc oxide (IZO), but may be other transparent conductive materials.

In the above method for manufacturing a thin film transistor array substrate, wherein the first metal layer is composed of a three-layer aluminum film, and the coating control parameter of the first aluminum film of the three-layer aluminum film in the coating cavity is set to a coating pressure of 0.03. Pa ~ 0.4 Pa, coating power is not more than 53kw, coating time is not more than 10s, and then the first aluminum film is deposited on the second molybdenum film by sputtering the aluminum target by magnetron sputtering. A membranous dense first aluminum film can be obtained by parameter setting.

In the above method for fabricating a thin film transistor array substrate, wherein the first metal layer is composed of a three-layer aluminum film, and the coating control parameter of the second aluminum film of the three-layer aluminum film in the coating cavity is set to a coating pressure. 0.03 Pa~0.4 Pa, coating power is not more than 85kw, coating time is not more than 26s, and then the second aluminum film is sputtered on the first aluminum film by magnetron sputtering. A second aluminum film with a loose film can be obtained under the control parameter setting.

In the above method for manufacturing a thin film transistor array substrate, wherein the first metal layer is composed of a three-layer aluminum film, and the coating control parameter of the third aluminum film of the three-layer aluminum film in the coating cavity is set to a coating pressure. 0.03 Pa～0.4 Pa, coating power is not more than 53kw, coating time is not more than 12s, and then the aluminum target is sputter-deposited by magnetron sputtering to deposit the third aluminum film on the second aluminum film. A thin film of the third aluminum film can be obtained under the control of the coating control parameters.

In the above method for manufacturing a thin film transistor array substrate, in the case where the first aluminum thin film of the first metal layer is formed, the plating power is set to be an optimum coating power in the coating control parameter of 30 kw to 53 kw.

In the method for manufacturing a thin film transistor array substrate, in which the second aluminum thin film of the first metal layer is formed, the coating power is set to 50 kw to 85 kw in the coating control parameter, and the coating time is set to 16 s to 26 s. And coating time.

In the method for manufacturing a thin film transistor array substrate, in which the third aluminum thin film of the first metal layer is formed, the coating power is set to 30 kw to 53 kw in the coating control parameter, and the coating time is set to 2 s to 12 s. And coating time.

The thin film transistor array substrate of the present invention and the method of manufacturing the same, wherein the first molybdenum film and the second molybdenum film may be replaced by a molybdenum alloy or other materials; and the thin film transistor array substrate of the present invention and a method of manufacturing the same, The first molybdenum film is covered on the three-layer aluminum film, which not only can relieve the hillock of the three-layer aluminum film after high temperature, but also can prevent the three-layer aluminum film from interdifing with the insulating layer.

According to the above embodiment of the present invention, the first metal layer of the thin film transistor array substrate and the method of manufacturing the same according to the present invention includes a structure of a three-layer aluminum film, and the first aluminum film and the third aluminum film are coated with a low power film. The surface of the coated aluminum film is relatively smooth, the gap between the aluminum metal grains in the aluminum film is small, and the second aluminum film adopts high power and other coating parameters, and the surface of the coated aluminum film is rough, and the film is thin. The gap between the crystal grains of the aluminum alloy is large, and the difference in the gap between the crystal grains can give a space for the stress release at a high temperature, so that the hillock can be effectively suppressed, and the aluminum (Al) metal and the aluminum crucible Since (AlNd) has a lower resistivity, the present invention can improve the quality of the liquid crystal display and obtain a better picture display effect.

Figures 10a and 10b are photographs of an aluminum thin film scanning electron microscope (SEM) showing the case of an aluminum film plated at different coating powers. Figure 10a is a scanning electron micrograph of an aluminum film plated at a coating power of 40kw and a coating pressure of 0.1Pa. Figure 10b shows a scanning of an aluminum film plated at a coating pressure of 0.1kPa and a coating pressure of 0.1Pa. Electron micrograph, it can be seen that the surface of the aluminum film coated by the coating power of 40kw is relatively smooth, and the gap between the aluminum metal grains in the aluminum film is small, so that the aluminum film is made into a dense film of aluminum. The film; the surface of the aluminum film plated at a coating power of 65kw to 70kw is rough, and the gap between the aluminum metal grains in the film is large, so that the aluminum film is formed as a film-like aluminum film.

Figure 11 is a scanning electron microscope (SEM) photograph of the first metal layer being a single-layer aluminum film and the first metal layer being a three-layer aluminum film. Sample 1 is a single-layer aluminum film with a single-layer aluminum film using a coating parameter of 70 KW, 0.1 Pa, and a scanning electron microscope (SEM) after annealing at 360 ° C, 8 m, and 230 ° C, 60 m twice (Anneal). Photo 2; sample 2 is a first metal layer is a three-layer aluminum film by the three-layer coating method of the present invention, after 360 ° C, 8 m and 230 ° C, 60 m two annealing (Anneal) after scanning electron microscope (SEM) The photo; it can be clearly found that the sample 1 has a hillock after annealing, while the sample 2 has no hillock after annealing.

In another embodiment of the thin film transistor array substrate and the method of fabricating the same, the second metal layer comprises a structure of a third molybdenum film, a fourth molybdenum film and a three-layer aluminum film, wherein the structure of the three-layer aluminum film and the above implementation In the example, the three-layer aluminum film of the first metal layer has the same structure, the third molybdenum film is disposed on the semiconductor layer, the fourth molybdenum film is coated on the three-layer aluminum film, and the three-layer aluminum film is sandwiched between the third molybdenum film. A molybdenum-aluminum-molybdenum structure is formed between the fourth molybdenum film to enhance the compactness of the second metal layer to reduce the generation of hillocks.

In a method of fabricating a thin film transistor array substrate according to another embodiment of the present invention, the method of forming the second metal layer is the same as the method of forming the first metal layer having the molybdenum-aluminum-molybdenum structure in the above embodiment. No longer.

In the thin film transistor array substrate of the present invention and the method of manufacturing the same, the second metal layer comprises a structure of three layers of aluminum thin film, and the coating power of the coating power of the three-layer aluminum film is different, and the plating parameter is coated with a coating property such as a low coating power. The film surface is smooth, the gap between the crystal grains is small, and the film surface coated by the coating parameters such as high coating power is rough, and the gap between the crystal grains is large. The difference in the gap between the crystal grains can be given. The space generated by the stress generated at a high temperature can effectively suppress the generation of hillock, and the aluminum (Al) metal has a lower resistivity than the aluminum lanthanum (AlNd), so the present invention can improve the quality of the liquid crystal display. Get a better picture display.

Of course, in the thin film transistor array substrate of the present invention and the method of fabricating the same, the first metal layer and the second metal layer may be simultaneously provided as a multilayer film structure, and have at least three aluminum film; and at least three aluminum films are produced. The method of the first metal layer and the second metal layer has been disclosed in detail in the above embodiments, and details are not described herein.

It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not limited thereto; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that The technical solutions described in the foregoing embodiments are modified, or the equivalents of the technical features are replaced. The modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

30, 40, 60, 80. . . Substrate

31. . . Pixel structure

32. . . Scanning line

33. . . Data line

34. . . Pixel electrode

35. . . Thin film transistor

351. . . Gate

352. . . Source

353. . . Bungee

41, 61, 81. . . First metal layer

411, 611, 812. . . First aluminum film

412, 612, 813. . . Second aluminum film

413, 613, 814. . . Third aluminum film

614, 815. . . Molybdenum film

811. . . Molybdenum film

42, 62, 82. . . Insulation

43, 63, 83. . . Semiconductor layer

44, 64, 84. . . Second metal layer

45, 65, 85. . . Passivation layer

451, 651, 851. . . Contact hole

46, 66, 86. . . Transparent electrode layer

1 is a schematic view showing the structure of a pixel of a conventional thin film transistor array substrate;

2 is a cross-sectional view of the thin film transistor array substrate along the A-A' direction in FIG. 1 having a Mo-AlNd structure;

3 is a schematic view showing the structure of a thin film transistor array substrate of the present invention;

4a is a cross-sectional view of the thin film transistor array substrate along the B-B' direction in FIG. 3 having a three-layer aluminum (Al) structure;

Figure 4b is a partial enlarged view of Figure 4a;

5 is a flow chart of a method for fabricating a thin film transistor array substrate according to an embodiment of the invention;

6a is a cross-sectional view of the thin film transistor array substrate along the B-B' direction in FIG. 3 having a Mo-Al structure;

Figure 6b is a partial enlarged view of Figure 6a;

7 is a flow chart of a method for fabricating a thin film transistor array substrate according to another embodiment of the present invention;

Figure 8a is a cross-sectional view of the thin film transistor array substrate in the B-B' direction of Figure 3 having a Mo-Al-Mo structure;

Figure 8b is a partial enlarged view of Figure 8a;

FIG. 9 is a flow chart showing a method of manufacturing a thin film transistor array substrate according to another embodiment of the present invention.

Figures 10a and 10b are photographs of an aluminum thin film scanning electron microscope (SEM).

Figure 11 is a scanning electron microscope (SEM) photograph of the first metal layer being a single-layer aluminum film and the first metal layer being a three-layer aluminum film.

40. . . Substrate

41. . . First metal layer

42. . . Insulation

43. . . Semiconductor layer

44. . . Second metal layer

45. . . Passivation layer

451. . . Contact hole

46. . . Transparent electrode layer

Claims (14)

A thin film transistor array substrate includes a substrate, a first metal layer is formed on the substrate, and an insulating layer is formed on the substrate to cover the first metal layer, and a semiconductor layer is formed on the insulating layer. a second metal layer is formed on a portion of the semiconductor layer, and the second metal layer and the semiconductor layer are covered by a passivation layer, and a transparent electrode layer is formed on the passivation layer and covered, wherein: the first The metal layer is a multi-layer film structure having at least three aluminum film, the first aluminum film, the second aluminum film and the third aluminum film, wherein the second aluminum film covers the first aluminum film On the film, the second aluminum film is sandwiched between the first aluminum film and the third aluminum film. The thin film transistor array substrate of claim 1, wherein the first aluminum film and the third aluminum film of the three-layer aluminum film are film-densified aluminum films. The thin film transistor array substrate of claim 1, wherein the second aluminum film of the three-layer aluminum film is a film-like aluminum film. The thin film transistor array substrate of claim 1, wherein the first metal layer further comprises the first molybdenum film covering a three-layer aluminum film to form a molybdenum-aluminum structure, thereby reinforcing the first The density of the metal layer to reduce the generation of hillocks. The thin film transistor array substrate of claim 1, wherein the first metal layer further comprises a first molybdenum film and a second molybdenum film, and the second molybdenum film covers the substrate. The first molybdenum film is coated on the three-layer aluminum film, and the three-layer aluminum film is sandwiched between the first molybdenum film and the second molybdenum film to form a molybdenum-aluminum-molybdenum structure, thereby reinforcing the first metal The density of the layers to reduce the production of hillocks. The thin film transistor array substrate of claim 1, wherein the second metal layer comprises a third molybdenum film, a fourth molybdenum film and a three-layer aluminum film, the third molybdenum film covering the semiconductor layer The fourth molybdenum film is coated on the three-layer aluminum film, and the three-layer aluminum film is sandwiched between the third molybdenum film and the fourth molybdenum film to form a molybdenum-aluminum-molybdenum structure, thereby strengthening The density of the second metal layer to reduce the generation of hillocks. A method for fabricating a thin film transistor array substrate, comprising: first providing a substrate, forming a first metal layer on the substrate, and then forming an insulating layer on the first metal layer and covering the first metal layer The substrate is further deposited on the insulating layer by a semiconductor layer, and a second metal layer is deposited on the semiconductor layer and the insulating layer, and a passivation is formed on the insulating layer, the semiconductor layer and the second metal layer. Forming and covering the layer, and finally forming a transparent electrode layer on the passivation layer, wherein the first metal layer further comprises at least three layers of aluminum thin film coating, wherein an aluminum target and the substrate are first placed In the coating cavity, a first aluminum film is deposited on the substrate at a coating pressure of 0.03 Pa to 0.4 Pa, a coating power of not more than 53 kw, and a coating time of not more than 10 s, and the coating pressure is 0.03 Pa to 0.4. Depositing a second aluminum film on the first aluminum film at a time when the coating power is not more than 85 kw and the coating time is not more than 26 s, and then the coating pressure is 0.03 Pa to 0.4 Pa, and the coating power is not more than 53 kw. The time the film deposition time of less than 12s a third aluminum thin film on the second Al film. The method for manufacturing a thin film transistor array substrate according to claim 7, wherein a deposition power of the first aluminum thin film is from 30 kw to 53 kw, and a plating time is from 2 s to 10 s. The method for manufacturing a thin film transistor array substrate according to claim 7, wherein the deposition power of the second aluminum thin film is from 50 to 85 kw, and the coating time is from 16 to 26 s. The method for manufacturing a thin film transistor array substrate according to claim 7, wherein the deposition power of the third aluminum thin film is from 30 kw to 53 kw, and the plating time is from 2 s to 12 s. The method for manufacturing a thin film transistor array substrate according to claim 7, wherein the first aluminum film and the third aluminum film of the three-layer aluminum film are film-densified aluminum films. The method for manufacturing a thin film transistor array substrate according to claim 7, wherein the second aluminum film of the three-layer aluminum film is a film-like aluminum film. The method for manufacturing a thin film transistor array substrate according to claim 7, wherein the first metal layer further comprises a first molybdenum film deposited on the three after the formation of the three-layer aluminum film. On the third aluminum film of the aluminum film. The method for manufacturing a thin film transistor array substrate according to claim 7, wherein the first metal layer further comprises a first molybdenum film and a second molybdenum film, two layers of molybdenum film, before the three-layer aluminum film Depositing the second molybdenum film, depositing the first molybdenum film on the third aluminum film of the three-layer aluminum film after the three-layer aluminum film.