WO2020093458A1

WO2020093458A1 - Array substrate and preparation method therefor, liquid crystal display panel, and display device

Info

Publication number: WO2020093458A1
Application number: PCT/CN2018/116840
Authority: WO
Inventors: 周星宇
Original assignee: 深圳市华星光电半导体显示技术有限公司
Priority date: 2018-11-06
Filing date: 2018-11-22
Publication date: 2020-05-14
Also published as: CN109473448A

Abstract

An array substrate and a preparation method therefor, a liquid crystal display panel, and a display device. A second semiconductor region (4042) and a second pixel electrode region (4072) in a transparent capacitor region (430) are made of transparent conductive materials, so that the capacitor region (430) of the array substrate can transmit light. Changing the original non-transparent capacitor region into the transparent capacitor region (430) improves the light transmittance of the array substrate, and increase the aperture ratio of the liquid crystal display panel or the display device prepared by means of the array substrate.

Description

Array substrate and preparation method thereof, liquid crystal display panel, and display device

Technical field

The invention relates to the technical field of semiconductor materials, in particular to an array substrate and a preparation method thereof, a liquid crystal display panel, and a display device.

Background technique

Liquid crystal display (Liquid Crystal Display, LCD) has the advantages of thin body, low power consumption, small radiation and soft screen display, etc., and has a wide range of applications. Transmittance Ratio) is an important indicator of the display quality of the liquid crystal display panel. Increasing the penetration rate of the liquid crystal display can reduce the backlight energy consumption and reduce the cost. In the case of the same backlight, greater brightness can be achieved, and gray levels can be adjusted more clearly. Several major factors that generally affect the transmittance of a liquid crystal display panel include: polarizers, liquid crystal efficiency, film absorption of the array substrate and color filter substrate, and the aperture ratio of the liquid crystal display panel. Liquid crystal efficiency refers to the transmittance of the liquid crystal display panel at the same aperture ratio.

technical problem

One of the main problems of the large-sized transparent display panel is to solve the problem of the aperture ratio, that is, the thin film transistor (TFT) and the capacitor area should be accounted for as little as possible to increase the area of the transmission area, but the capacitor and TFT need certain The size guarantees function, so the reduction is limited.

Technical solution

Embodiments of the present invention provide an array substrate and a preparation method thereof, a liquid crystal display panel, and a display device, which improve the light transmittance of the array substrate and increase the aperture ratio of the liquid crystal display panel or display device prepared by the array substrate.

In a first aspect, the present application provides a method for preparing an array substrate, the method comprising:

Depositing a buffer layer, a gate metal layer, a gate insulating layer and a semiconductor layer in sequence on the glass substrate, the semiconductor layer including a first semiconductor region and a second semiconductor region;

Defining the position where the gate insulating layer needs to be opened, while exposing the second semiconductor region;

Performing a dry etching process on the glass substrate and each layer deposited on the glass substrate, and performing plasma treatment after the etching is completed, so that the second semiconductor region becomes conductive, and the first semiconductor region is photoresisted protection;

The source-drain metal layer, the passivation layer and the pixel electrode layer are sequentially manufactured to form the TFT area, the gate wiring area and the transparent capacitance area of the array substrate respectively;

Wherein the pixel electrode layer includes a first pixel electrode area and a second pixel electrode area, the transparent capacitance area includes the second semiconductor area and the second pixel electrode area, the second semiconductor area and the The second pixel electrode area is made of transparent conductive material.

Further, the step of sequentially depositing a buffer layer, a gate metal layer, a gate insulating layer and a semiconductor layer on the glass substrate includes:

Cleaning the glass substrate, and depositing a buffer layer on the glass substrate;

Depositing a gate metal layer on the buffer layer and etching the pattern;

Depositing a gate insulating layer on the gate metal layer;

A semiconductor layer is deposited and patterned on the gate insulating layer.

Further, the step of depositing a buffer layer on the glass substrate includes:

A SiO layer, a SiN layer or a mixed layer of SiO layer and SiN is deposited on the glass substrate as a buffer layer.

Further, the step of depositing a gate metal layer on the buffer layer includes:

A metal material is deposited on the buffer layer, and a first gate region and a second gate region are formed on the buffer layer, respectively.

Further, the metal material is a single metal of Mo, Al, Cu or Ti, or the metal material is an alloy metal layer of at least two of Mo, Al, Cu and Ti.

Further, the step of depositing a gate insulating layer on the gate metal layer includes:

A layer of SiOx or SiNx or a thin film is deposited on the gate metal layer as a gate insulating layer, or a multilayer structure of SiOx and SiNx is deposited on the gate metal layer as a gate insulating layer.

Further, the thickness of the gate insulating layer is 1000-5000 angstroms.

Further, the step of depositing a semiconductor layer on the gate insulating layer includes:

Depositing a layer of metal oxide semiconductor material on the gate insulating layer to form the first semiconductor region and the second semiconductor region;

Wherein the first semiconductor region is above the first gate region, and the second semiconductor region is on the right side of the second gate region.

Further, the metal oxide semiconductor material is indium gallium zinc oxide IGZO, indium zinc tin oxide IZTO or indium gallium zinc tin oxide IGZTO.

Further, the thickness of the semiconductor layer is 100-1000 angstroms.

Further, the steps of sequentially manufacturing the source-drain metal layer, the passivation layer and the pixel electrode layer to respectively form the TFT region, the gate wiring region and the transparent capacitor region of the array substrate include:

Deposit the source-drain metal layer and etch the pattern;

Making a passivation layer on the source-drain metal layer;

A pixel electrode layer is formed on the passivation layer, and a pattern is defined to form a TFT area, a gate wiring area and a transparent capacitance area of the array substrate, respectively.

Further, the step of depositing the source-drain metal layer includes:

Depositing a metal layer, so that a source metal region and a drain metal region are deposited on the left and right sides of the first semiconductor region, respectively, and a source drain metal region is formed above the second gate region.

Further, the source metal region, the drain metal region and the source-drain metal region are single metal layers of Mo, Al, Cu or Ti, or the source metal region and the drain metal The region and the source-drain metal region are alloy metal layers of at least two of Mo, Al, Cu and Ti.

Further, a pixel electrode layer is formed on the passivation layer, and a pattern is defined to form a TFT area, a gate wiring area, and a transparent capacitance area of the array substrate, respectively, including:

Forming a first pixel electrode region on the passivation layer and defining a pattern, the first pixel electrode region covering the source metal region, the drain metal region, and the source-drain metal region;

Making a second pixel electrode region on the passivation layer using a transparent conductive material, the second pixel electrode region being above the second semiconductor region;

The area corresponding to the first gate area forms a TFT area of the array substrate, the area corresponding to the second gate area forms the gate wiring area of the array substrate, and the area corresponding to the second semiconductor area forms an array The transparent capacitor area of the substrate.

Further, the transparent conductive material is indium tin oxide ITO or indium zinc oxide IZO.

In a second aspect, the present application provides an array substrate including, from left to right, a TFT region, a gate wiring region, and a transparent transparent capacitor region.

Further, the array substrate includes:

glass substrate;

A gate metal layer, prepared on the surface of the glass substrate, includes a first gate region and a second gate region;

A gate insulating layer prepared on the surface of the glass substrate and covering the gate metal layer;

A semiconductor layer, prepared on the surface of the gate insulating layer, including a first semiconductor region and a second semiconductor region;

A source-drain metal layer, prepared on the surfaces of the gate insulating layer and the semiconductor layer, including a source metal region, a drain metal region, and a source-drain metal region;

A passivation layer surrounding the source-drain metal layer;

The pixel electrode layer, prepared on the surface of the passivation layer, includes a first pixel electrode area and a second pixel electrode area;

Wherein, a channel region is formed between the source metal region and the drain metal region, the source metal region and the drain metal region are on the left and right sides of the first semiconductor region, and the source and drain metals The region is above the second gate region, the first semiconductor region is above the first gate region, the second semiconductor region is to the right of the second gate region, and the transparent capacitor region includes The second semiconductor region and the second pixel electrode region, the second semiconductor region and the second pixel electrode region are made of a transparent conductive material.

Further, the glass substrate, the first gate region, the gate insulating layer, the first semiconductor region, the source metal region, the drain metal region, the passivation layer and The first pixel electrode region constitutes an array of TFT regions, the glass substrate, the second gate region, the gate insulating layer, the source-drain metal region, the passivation layer and the first The pixel electrode area constitutes a gate wiring area, and the glass substrate, the second semiconductor area, the passivation layer, and the second pixel electrode area constitute a transparent capacitance area.

In a third aspect, the present application provides a liquid crystal display panel, including the array substrate according to any one of the second aspect.

According to a fourth aspect, the present application provides a display device including the liquid crystal display panel according to any one of the third aspect.

Beneficial effect

In the method of the embodiment of the present invention, a buffer layer, a gate metal layer, a gate insulating layer and a semiconductor layer are sequentially deposited on the glass substrate. The semiconductor layer includes a first semiconductor region and a second semiconductor region; defining the gate insulating layer requires openings At the same time, the second semiconductor region is exposed at the same time; a dry etching process is performed on the glass substrate and each layer deposited on the glass substrate, and plasma treatment is performed after the etching is completed, so that the second semiconductor region becomes conductive, the first semiconductor region It is protected by a photoresist; the source-drain metal layer, the passivation layer and the pixel electrode layer are sequentially manufactured to form the TFT area, the gate wiring area and the transparent capacitance area of the array substrate, respectively. Since the transparent capacitor region includes a second semiconductor region and the second pixel electrode region, the second semiconductor region and the second pixel electrode region are made of a transparent conductive material, so that the capacitor region of the array substrate itself can transmit light, The original non-transparent capacitor area becomes a transparent capacitor area, which improves the light transmittance of the array substrate and increases the aperture ratio of the liquid crystal display panel or display device prepared by the array substrate.

BRIEF DESCRIPTION

In order to more clearly explain the technical solutions in the embodiments of the present invention, the drawings required in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, without paying any creative work, other drawings can be obtained based on these drawings.

1 is a schematic flowchart of an embodiment of a method for preparing an array substrate provided by an embodiment of the present invention;

2 is a schematic flowchart of an embodiment of step S101 in the embodiment shown in FIG. 1;

3 is a schematic flowchart of an embodiment of step S104 in the embodiment shown in FIG. 1;

4 is a schematic structural view of a buffer layer, a gate metal layer, a gate insulating layer, and a semiconductor layer sequentially deposited on a glass substrate in an embodiment of the present invention;

FIG. 5 is a schematic structural view after defining the position where the gate insulating layer needs to be opened in the embodiment of the present invention, while exposing the second semiconductor region;

FIG. 6 is a schematic diagram of a structure in which a dry etching process is performed on a glass substrate and each layer deposited on the glass substrate in an embodiment of the present invention, and after plasma etching is completed;

7 is a schematic structural diagram of an embodiment of an array substrate in an embodiment of the present invention.

Embodiments of the invention

The technical solutions in the embodiments of the present invention will be described clearly and completely in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present invention.

As shown in FIG. 1, it is a schematic diagram of an embodiment of a method for preparing an array substrate in an embodiment of the present invention. The method includes:

S101. Deposit a buffer layer, a gate metal layer, a gate insulating layer, and a semiconductor layer in sequence on the glass substrate.

Wherein, the semiconductor layer includes a first semiconductor region and a second semiconductor region. As shown in FIG. 2, the step of sequentially depositing a buffer layer, a gate metal layer, a gate insulating layer and a semiconductor layer on the glass substrate may further include:

S1011: Clean the glass substrate, and deposit a buffer layer on the glass substrate.

Specifically, the step of depositing a buffer layer on the glass substrate may include: depositing a SiO layer, a SiN layer, or a mixed layer of SiO layer and SiN on the glass substrate as a buffer layer, and the thickness of the buffer layer may be 500-5000 angstroms .

S1012. Deposit a gate metal layer on the buffer layer and etch the pattern.

Specifically, the step of depositing the gate metal layer on the buffer layer may include: depositing a metal material on the buffer layer, and forming a first gate region and a second gate region on the buffer layer, respectively. Wherein, the metal material may be a single metal of Mo, Al, Cu or Ti, or the metal material may be an alloy metal layer of at least two of Mo, Al, Cu and Ti. Further, the thickness of the gate metal layer is 2000-10000 angstroms.

S1013. Deposit a gate insulating layer on the gate metal layer.

The gate insulating layer refers to the GI layer. The GI layer is formed by a process in an LTPS called GI Deposition, which is the deposition of the GI layer. GI is the insulating layer between the gate metal and the semiconductor layer in TFT, usually SiNx / SiOx, called Gate Insulator (gate insulating layer). In the embodiment of the present invention, the step of depositing a gate insulating layer on the gate metal layer may include: depositing a layer of SiOx or SiNx or a thin film on the gate metal layer as the gate insulating layer, Or a SiOx and SiNx multilayer structure film is deposited on the gate metal layer as a gate insulating layer. The thickness of the gate insulating layer is 1000-5000 angstroms.

S1014. Deposit and pattern a semiconductor layer on the gate insulating layer.

Specifically, the step of depositing a semiconductor layer on the gate insulating layer includes: depositing a layer of metal oxide semiconductor material on the gate insulating layer to form a first semiconductor region and a second semiconductor region; wherein, the first semiconductor region Above the first gate region, the second semiconductor region is to the right of the second gate region. Further, the metal oxide semiconductor material may be indium gallium zinc oxide (Indium Gallium Zinc Oxide (IGZO), Indium Zinc Tin Oxide (IZTO) or Indium Gallium Zinc Tin Oxide (IGZTO).

The thickness of the semiconductor layer may be 100-1000 angstroms, and the thickness of the first semiconductor region and the second semiconductor region may be kept the same, for example, the thickness is 500 angstroms.

As shown in FIG. 4, it is a schematic structural view after sequentially depositing a buffer layer, a gate metal layer, a gate insulating layer, and a semiconductor layer on a glass substrate, in which a buffer layer (not shown) is deposited on the glass substrate 401 Out), the gate metal layer (including the first gate region 4021 and the second gate region 4022), the gate insulating layer 403 and the semiconductor layer (including the first semiconductor region 4041 and the second semiconductor region 4042).

S102. Define a position where the gate insulating layer needs to be opened, and at the same time expose the second semiconductor region.

In the embodiment of the present invention, the step of defining the position where the gate insulating layer needs to be opened and exposing the second semiconductor region at the same time may be: performing a yellow light process to define the position where the gate insulating layer needs to be opened while being exposed Out of the second semiconductor region. Specifically, as shown in FIG. 5, a photoresist 408 is coated on the semiconductor layer, the photoresist 408 covers the first semiconductor region 4041, and at the same time, the photoresist is defined in the position where the gate insulating layer needs to be opened The covering area avoids covering the position of the opening (for example, the opening area between the two photoresists on the left side in FIG. 5). In addition, it is ensured that the photoresist 408 does not cover the second semiconductor region 4042, that is, the second semiconductor is exposed Area 4042.

S103. Perform a dry etching process on the glass substrate and each layer deposited on the glass substrate, and perform plasma treatment after the etching is completed, so that the second semiconductor region becomes conductive, and the first semiconductor region is protected by the photoresist.

Specifically, a dry etching process is performed on the glass substrate and each layer deposited on the glass substrate, and after the etching is completed, a plasma treatment is performed, so that the second semiconductor region becomes conductive, and the first semiconductor region is protected by a photoresist It may include: performing a dry etching process, adding some plasma treatment after the dry etching is completed, can make the second semiconductor region become conductive, the resistance value is greatly reduced, and is more suitable as a capacitor plate, the first channel region The semiconductor region is protected by photoresist, and still maintains semiconductor characteristics, so as to form a thin film transistor (Thin-film) transistor, TFT) area. As shown in FIG. 6, after the dry etching process and the plasma treatment are performed, the photoresist on the gate insulating layer 403 and the semiconductor layer is removed. Due to the dry etching process, the first semiconductor region 4041 has photoresist Protection, the second semiconductor region 4042 is not protected by photoresist (also called photoresist), which can make the second semiconductor region 4042 become conductive, the resistance value is greatly reduced, and it is more suitable as a capacitor plate, while the first semiconductor region 4041 Protected by photoresist, it still maintains semiconductor characteristics. At the same time, the position where the gate insulating layer needs to be opened is etched because there is no photoresist protection.

S104. Manufacture the source-drain metal layer, the passivation layer, and the pixel electrode layer in sequence to form the TFT region, the gate wiring region, and the transparent capacitor region of the array substrate, respectively.

The first semiconductor region may be located in the TFT region of the array substrate, and the second semiconductor region may be located in the transparent capacitor region of the array substrate.

In some embodiments of the present invention, as shown in FIG. 3, the source-drain metal layer, the passivation layer and the pixel electrode layer are sequentially formed to form the TFT region, the gate wiring region and the transparent capacitor region of the array substrate The steps may further include:

S1041, a source-drain metal layer is deposited, and the pattern is etched.

Specifically, depositing a source-drain metal layer, and the etching pattern may further include: depositing a metal layer, so that a source metal region and a drain metal region are deposited on the left and right sides of the first semiconductor region, respectively, above the second gate region Source and drain metal regions are formed. Wherein, the source metal region, drain metal region and source-drain metal region are single metal layers of Mo, Al, Cu or Ti, or the source metal region, drain metal region and source-drain metal region are Mo, Al, At least two alloy metal layers of Cu and Ti.

S1042, forming a passivation layer on the source-drain metal layer.

S1043, forming a pixel electrode layer on the passivation layer, and defining a pattern, respectively forming a TFT region, a gate wiring region and a transparent capacitor region of the array substrate.

Forming a pixel electrode layer on the passivation layer and defining a pattern, respectively forming a TFT area, a gate wiring area and a transparent capacitance area of the array substrate, including: forming a first pixel electrode area on the passivation layer, and A pattern is defined. The first pixel electrode area covers the source metal area, the drain metal area, and the source and drain metal area; a second pixel electrode area is formed on the passivation layer using a transparent conductive material. Above the two semiconductor regions; wherein the region corresponding to the first gate region forms the TFT region of the array substrate, the region corresponding to the second gate region forms the gate wiring region of the array substrate, and the second semiconductor region corresponds to The area forms a transparent capacitance area of the array substrate. Further, the transparent conductive material is indium tin oxide ITO or indium zinc oxide IZO.

As shown in FIG. 7, at this time, the glass substrate 401, first gate region 4021, gate insulating layer 403, first semiconductor region 4041, source metal region 4051, drain metal region 4052, passivation layer 406 and The first pixel electrode region 4071 constitutes an array of TFT regions 410, the glass substrate 401, the second gate region 4022, the gate insulating layer 403, the source-drain metal region 4053, the passivation layer 406, and the first pixel electrode region 4071 constitute the gate The wiring area 420, the glass substrate 401, the second semiconductor area 4042, the passivation layer 406, and the second pixel electrode area 4072 constitute a transparent capacitance area 430.

An array substrate has also been provided in an embodiment of the present invention. As shown in FIG. 7, the array substrate includes a TFT region 410, a gate wiring region 420, and a transparent transparent capacitor region 430 from left to right. Since the capacitance area of the array substrate can transmit light itself, the original non-transparent capacitance area becomes a transparent capacitance area, which increases the aperture ratio of the display or device prepared by the array substrate.

Specifically, as shown in FIG. 7, the array substrate may include:

Glass substrate 401;

The gate metal layer, prepared on the surface of the glass substrate 401, includes a first gate region 4021 and a second gate region 4022;

The gate insulating layer 403 is prepared on the surface of the glass substrate 401 and covers the gate metal layer;

The semiconductor layer, prepared on the surface of the gate insulating layer 403, includes a first semiconductor region 4041 and a second semiconductor region 4042;

The source-drain metal layer, prepared on the surfaces of the gate insulating layer 403 and the semiconductor layer, includes a source metal region 4051, a drain metal region 4052, and a source-drain metal region 4053;

A passivation layer 406, surrounding the source-drain metal layer;

The pixel electrode layer, prepared on the surface of the passivation layer 406, includes a first pixel electrode region 4071 and a second pixel electrode region 4072;

A channel region is formed between the source metal region 4051 and the drain metal region 4052, the source metal region 4051 and the drain metal region 4052 are on the left and right sides of the first semiconductor region 4041, and the source and drain metal region 4053 are in the second Above the gate region 4022, the first semiconductor region 4041 is above the first gate region 4021, the second semiconductor region 4042 is to the right of the second gate region 4022, and the transparent capacitor region 430 includes the second semiconductor region 4042 and the second pixel electrode The region 4072, the second semiconductor region 4042 and the second pixel electrode region 4072 are made of transparent conductive material. Further, the transparent conductive material is indium tin oxide ITO or indium zinc oxide IZO.

Further, the glass substrate 401, the first gate region 4021, the gate insulating layer 403, the first semiconductor region 4041, the source metal region 4051, the drain metal region 4052, the passivation layer 406 and the first pixel electrode region 4071 The array of TFT regions 410, the glass substrate 401, the second gate region 4022, the gate insulating layer 403, the source-drain metal region 4053, the passivation layer 406 and the first pixel electrode region 4071 constitute the gate wiring region 420, glass The substrate 401, the second semiconductor region 4042, the passivation layer 406, and the second pixel electrode region 4072 constitute a transparent capacitance region 430.

An embodiment of the present invention also provides a liquid crystal display panel, including the array substrate described in any of the above embodiments.

An embodiment of the present invention further provides a display device, including the array substrate described in any of the above embodiments.

During specific implementation, the above units can be implemented as independent entities, or they can be combined in any combination and implemented as the same or several entities. For the specific implementation of the above units, please refer to the previous method embodiments, such as the thickness of each layer Wait, I won't repeat them here.

The above describes an array substrate, a method for manufacturing the same, a liquid crystal display panel, and a display device provided in the embodiments of the present invention. Specific examples are used to explain the principles and implementation modes of the present invention. The description is only used to help understand the method of the present invention and its core idea; at the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation and application scope, in summary, The contents of this description should not be construed as limiting the invention.

Claims

A method for preparing an array substrate, wherein the method includes:

Depositing a buffer layer, a gate metal layer, a gate insulating layer and a semiconductor layer in sequence on the glass substrate, the semiconductor layer including a first semiconductor region and a second semiconductor region;

Defining the position where the gate insulating layer needs to be opened, while exposing the second semiconductor region;

Performing a dry etching process on the glass substrate and each layer deposited on the glass substrate, and performing plasma treatment after the etching is completed, so that the second semiconductor region becomes conductive, and the first semiconductor region is photoresisted protection;

The source-drain metal layer, the passivation layer and the pixel electrode layer are sequentially manufactured to form the TFT area, the gate wiring area and the transparent capacitance area of the array substrate respectively;

Wherein the pixel electrode layer includes a first pixel electrode area and a second pixel electrode area, the transparent capacitance area includes the second semiconductor area and the second pixel electrode area, the second semiconductor area and the The second pixel electrode area is made of transparent conductive material.
The method for preparing an array substrate according to claim 1, wherein the step of sequentially depositing a buffer layer, a gate metal layer, a gate insulating layer and a semiconductor layer on the glass substrate includes:

Cleaning the glass substrate, and depositing a buffer layer on the glass substrate;

Depositing a gate metal layer on the buffer layer and etching the pattern;

Depositing a gate insulating layer on the gate metal layer;

A semiconductor layer is deposited and patterned on the gate insulating layer.
The method for manufacturing an array substrate according to claim 2, wherein the step of depositing a buffer layer on the glass substrate includes:

A SiO layer, a SiN layer or a mixed layer of SiO layer and SiN is deposited on the glass substrate as a buffer layer.
The method for manufacturing an array substrate according to claim 2, wherein the step of depositing a gate metal layer on the buffer layer comprises:

A metal material is deposited on the buffer layer, and a first gate region and a second gate region are formed on the buffer layer, respectively.
The method for manufacturing an array substrate according to claim 4, wherein the metal material is a single metal of Mo, Al, Cu or Ti, or the metal material is an alloy of at least two of Mo, Al, Cu and Ti Metal layer.
The method for manufacturing an array substrate according to claim 2, wherein the step of depositing a gate insulating layer on the gate metal layer includes:

A layer of SiOx or SiNx or a thin film is deposited on the gate metal layer as a gate insulating layer, or a multilayer structure of SiOx and SiNx is deposited on the gate metal layer as a gate insulating layer.
The method for manufacturing an array substrate according to claim 6, wherein the thickness of the gate insulating layer is 1000-5000 angstroms.
The method for manufacturing an array substrate according to claim 4, wherein the step of depositing a semiconductor layer over the gate insulating layer includes:

Depositing a layer of metal oxide semiconductor material on the gate insulating layer to form the first semiconductor region and the second semiconductor region;

Wherein the first semiconductor region is above the first gate region, and the second semiconductor region is on the right side of the second gate region.
The method for manufacturing an array substrate according to claim 8, wherein the metal oxide semiconductor material is indium gallium zinc oxide IGZO, indium zinc tin oxide IZTO or indium gallium zinc tin oxide IGZTO.
The method for manufacturing an array substrate according to claim 9, wherein the thickness of the semiconductor layer is 100-1000 angstroms.
The method for manufacturing an array substrate according to claim 8, wherein the source-drain metal layer, the passivation layer and the pixel electrode layer are sequentially formed to form a TFT region, a gate wiring region and a transparent capacitor of the array substrate The steps of the district include:

Deposit the source-drain metal layer and etch the pattern;

Making a passivation layer on the source-drain metal layer;

A pixel electrode layer is formed on the passivation layer, and a pattern is defined to form a TFT area, a gate wiring area and a transparent capacitance area of the array substrate, respectively.
The method for manufacturing an array substrate according to claim 11, wherein the step of depositing the source-drain metal layer includes:

Depositing a metal layer, so that a source metal region and a drain metal region are deposited on the left and right sides of the first semiconductor region, respectively, and a source drain metal region is formed above the second gate region.
The method for manufacturing an array substrate according to claim 12, wherein the source metal region, the drain metal region, and the source-drain metal region are single metal layers of Mo, Al, Cu, or Ti, or, The source metal region, the drain metal region, and the source-drain metal region are alloy metal layers of at least two of Mo, Al, Cu, and Ti.
The method for manufacturing an array substrate according to claim 11, wherein a pixel electrode layer is formed on the passivation layer, and a pattern is defined to form a TFT region, a gate wiring region and a transparent capacitor region of the array substrate ,include:

Forming a first pixel electrode region on the passivation layer and defining a pattern, the first pixel electrode region covering the source metal region, the drain metal region, and the source-drain metal region;

Making a second pixel electrode region on the passivation layer using a transparent conductive material, the second pixel electrode region being above the second semiconductor region;

The area corresponding to the first gate area forms a TFT area of the array substrate, the area corresponding to the second gate area forms the gate wiring area of the array substrate, and the area corresponding to the second semiconductor area forms an array The transparent capacitor area of the substrate.
The method for manufacturing an array substrate according to claim 14, wherein the transparent conductive material is indium tin oxide ITO or indium zinc oxide IZO.
An array substrate, wherein the array substrate includes, in order from left to right, a TFT region, a gate wiring region and a transparent transparent capacitor region.
The array substrate according to claim 16, wherein the array substrate comprises:

glass substrate;

A gate metal layer, prepared on the surface of the glass substrate, includes a first gate region and a second gate region;

A gate insulating layer prepared on the surface of the glass substrate and covering the gate metal layer;

A semiconductor layer, prepared on the surface of the gate insulating layer, including a first semiconductor region and a second semiconductor region;

A source-drain metal layer, prepared on the surfaces of the gate insulating layer and the semiconductor layer, including a source metal region, a drain metal region, and a source-drain metal region;

A passivation layer surrounding the source-drain metal layer;

The pixel electrode layer, prepared on the surface of the passivation layer, includes a first pixel electrode area and a second pixel electrode area;

Wherein, a channel region is formed between the source metal region and the drain metal region, the source metal region and the drain metal region are on the left and right sides of the first semiconductor region, and the source and drain metals The region is above the second gate region, the first semiconductor region is above the first gate region, the second semiconductor region is to the right of the second gate region, and the transparent capacitor region includes The second semiconductor region and the second pixel electrode region, the second semiconductor region and the second pixel electrode region are made of a transparent conductive material.
The array substrate according to claim 17, wherein the glass substrate, the first gate region, the gate insulating layer, the first semiconductor region, the source metal region, and the drain The metal region, the passivation layer and the first pixel electrode region constitute an array of TFT regions, the glass substrate, the second gate region, the gate insulating layer, the source-drain metal region, and the The passivation layer and the first pixel electrode area constitute a gate wiring area, and the glass substrate, the second semiconductor area, the passivation layer, and the second pixel electrode area constitute a transparent capacitance area.
A liquid crystal display panel comprising the array substrate as claimed in claim 16.
A display device comprising the liquid crystal display panel according to claim 19.