TWI413326B - Power protection circuit - Google Patents

Power protection circuit Download PDF

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TWI413326B
TWI413326B TW99126968A TW99126968A TWI413326B TW I413326 B TWI413326 B TW I413326B TW 99126968 A TW99126968 A TW 99126968A TW 99126968 A TW99126968 A TW 99126968A TW I413326 B TWI413326 B TW I413326B
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Taiwan
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transistor
circuit
voltage
voltage converter
power supply
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TW99126968A
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Chinese (zh)
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TW201208222A (en
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Hsiao Jen Tsai
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Hon Hai Prec Ind Co Ltd
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Publication of TWI413326B publication Critical patent/TWI413326B/en

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Abstract

The present invention relates to a power protection circuit including a power providing unit, a first voltage converter, a second voltage converter, a first switch, a second switch, a first voltage detecting circuit, a second voltage detecting circuit, a first alarming circuit, and a second alarming circuit. The first and second switches are respectively connected to the power providing unit and the first voltage converters, or the power providing unit and the first and second voltage converters. The first and second voltage detecting circuits are respectively connected to the first and second voltage converters. The first and second alarming circuits are respectively connected to the first and second voltage detecting circuits. When the input voltage of the first or the second voltage detecting circuit becomes lower, the first switch cuts off the first voltage converter and actuates the first alarming circuit alarming, or the second switch cuts off the second voltage converter and actuates the second alarming circuit alarming.

Description

電源保護電路 Power protection circuit

本發明涉及一種電源保護電路。 The invention relates to a power protection circuit.

電路板有時會發生負載故障,當負載發生故障時,輸出電流往往會增大,甚至短路。由於未設置報警和保護裝置,當發生故障時,一方面可能導致觸電或其他事故,不安全;另一方面不能知道發生故障之元件或線路,為了檢查和排除出現之故障,往往需要切斷主機器之整個供電系統並檢查整個電路板,因而耗時耗力。 The board sometimes has a load failure. When the load fails, the output current tends to increase or even short. Since the alarm and protection device are not set, when a fault occurs, on the one hand, it may cause electric shock or other accidents, and it is unsafe. On the other hand, it is impossible to know the faulty component or line. In order to check and eliminate the fault, it is often necessary to cut off the main fault. The entire power supply system of the machine checks the entire board and is time consuming and labor intensive.

有鑒於此,有必要提供一種當負載發生異常,可發出報警保護訊號之電源保護電路。 In view of this, it is necessary to provide a power protection circuit that can issue an alarm protection signal when an abnormality occurs in the load.

一種電源保護電路,其包括一電源供應單元、一第一電壓轉換器、一第二電壓轉換器、一第一開關電路、一第二開關電路。所述第一開關電路連接在所述電源供應單元及所述第一電壓轉換器之間。所述第二開關電路連接在所述電源供應單元及所述第二電壓轉換器之間。所述電源供應單元用於為所述第一、第二電壓轉換器提供電壓源。所述電源保護電路進一步包括一第一電壓偵測電路、一第二電壓偵測電路及一第一報警電路及一第二報警電路。所述第一電壓偵測電路連接至所述第一電壓轉換器。所述第二電 壓偵測電路連接至所述第二電壓轉換器。所述第一報警電路連接至所述第一電壓偵測電路。所述第二報警電路連接至所述第二電壓偵測電路。當所述第一電壓偵測電路之輸入電壓降低時,所述第一開關電路切斷所述第一電壓轉換器,同時所述電源供應單元驅動第一報警電路發出報警訊號。當所述第二電壓偵測電路之輸入電壓降低時,所述第二開關電路切斷所述第二電壓轉換器,同時所述電源供應單元驅動第二報警電路發出報警訊號。 A power protection circuit includes a power supply unit, a first voltage converter, a second voltage converter, a first switching circuit, and a second switching circuit. The first switch circuit is connected between the power supply unit and the first voltage converter. The second switch circuit is connected between the power supply unit and the second voltage converter. The power supply unit is configured to provide a voltage source for the first and second voltage converters. The power protection circuit further includes a first voltage detecting circuit, a second voltage detecting circuit, a first alarm circuit and a second alarm circuit. The first voltage detecting circuit is connected to the first voltage converter. The second electricity A voltage detection circuit is coupled to the second voltage converter. The first alarm circuit is connected to the first voltage detecting circuit. The second alarm circuit is connected to the second voltage detecting circuit. When the input voltage of the first voltage detecting circuit decreases, the first switching circuit cuts off the first voltage converter, and the power supply unit drives the first alarm circuit to send an alarm signal. When the input voltage of the second voltage detecting circuit decreases, the second switching circuit cuts off the second voltage converter, and the power supply unit drives the second alarm circuit to send an alarm signal.

相較於先前技術,當所述第一電壓偵測電路偵測到第一電壓轉換器有故障發生時,所述第一開關電路切斷所述第一電壓轉換器,同時驅動第一報警電路發出相應之報警訊號,提醒人員注意第一電壓轉換器有故障。當所述第二電壓偵測電路偵測到第二電壓轉換器有故障發生時,所述第二開關電路切斷所述第二電壓轉換器,同時驅動第二報警電路發出相應之報警訊號,提醒人員注意第二電壓轉換器有故障。如此可以及時有效地查出故障之原因且避免了可能出現之各種事故。 Compared with the prior art, when the first voltage detecting circuit detects that a fault occurs in the first voltage converter, the first switching circuit cuts off the first voltage converter and simultaneously drives the first alarm circuit. A corresponding alarm signal is sent to remind the person that the first voltage converter is faulty. When the second voltage detecting circuit detects that a fault occurs in the second voltage converter, the second switching circuit cuts off the second voltage converter, and simultaneously drives the second alarm circuit to issue a corresponding alarm signal. Remind the person that the second voltage converter is faulty. In this way, the cause of the fault can be detected in a timely and effective manner and various accidents that may occur are avoided.

100‧‧‧電源保護電路 100‧‧‧Power protection circuit

10‧‧‧電源供應單元 10‧‧‧Power supply unit

21‧‧‧第一電壓轉換器 21‧‧‧First voltage converter

22‧‧‧第二電壓轉換器 22‧‧‧Second voltage converter

211、221‧‧‧輸入端 211, 221‧‧‧ input

212、222‧‧‧輸出端 212, 222‧‧‧ output

31‧‧‧第一開關電路 31‧‧‧First switch circuit

32‧‧‧第二開關電路 32‧‧‧Second switch circuit

Q1‧‧‧第一電晶體 Q1‧‧‧First transistor

Q2‧‧‧第二電晶體 Q2‧‧‧Second transistor

D‧‧‧漏極 D‧‧‧Drain

S‧‧‧源極 S‧‧‧ source

G‧‧‧柵極 G‧‧‧Gate

C1、C2‧‧‧延時電容 C1, C2‧‧‧ time delay capacitor

41‧‧‧第一電壓偵測電路 41‧‧‧First voltage detection circuit

42‧‧‧第二電壓偵測電路 42‧‧‧Second voltage detection circuit

Q3‧‧‧第三電晶體 Q3‧‧‧ Third transistor

Q4‧‧‧第四電晶體 Q4‧‧‧4th transistor

R1-R24‧‧‧電阻 R1-R24‧‧‧ resistance

B‧‧‧基極 B‧‧‧ base

C‧‧‧集電極 C‧‧‧ Collector

E‧‧‧發射極 E‧‧‧ emitter

Q5‧‧‧第五電晶體 Q5‧‧‧ fifth transistor

Q6‧‧‧第六電晶體 Q6‧‧‧ sixth transistor

51‧‧‧第一報警電路 51‧‧‧First alarm circuit

52‧‧‧第二報警電路 52‧‧‧Second alarm circuit

Q7‧‧‧第七電晶體 Q7‧‧‧ seventh transistor

Q8‧‧‧第八電晶體 Q8‧‧‧ eighth transistor

Q9‧‧‧第九電晶體 Q9‧‧‧Ninth transistor

D1‧‧‧第一發光二極體 D1‧‧‧First Light Emitting Diode

Q10‧‧‧第十電晶體 Q10‧‧‧10th transistor

Q11‧‧‧第十一電晶體 Q11‧‧‧Eleventh transistor

Q12‧‧‧第十二電晶體 Q12‧‧‧12th transistor

D2‧‧‧第二發光二極體 D2‧‧‧Second light-emitting diode

圖1為本發明實施方式提供之電源保護電路之功能模組圖;圖2為圖1之電源保護電路之電路圖。 1 is a functional block diagram of a power protection circuit according to an embodiment of the present invention; and FIG. 2 is a circuit diagram of the power protection circuit of FIG.

下面將結合附圖對本發明實施方式作進一步之詳細說明。 The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

請參閱圖1,本發明提供之電源保護電路100,其包括一電源供應單元10、一第一電壓轉換器21、一第二電壓轉換器22、一第一開關電路31、一第二開關電路32、一第一電壓偵測電路41、一第二 電壓偵測電路42、一第一報警電路51及一第二報警電路52。所述電源供應單元10用於為所述第一電壓轉換器21及第二電壓轉換器22提供電壓源。所述第一開關電路31連接在所述電源供應單元10及第一電壓轉換器21之間。所述第二開關電路32連接在所述電源供應單元10及第二電壓轉換器22之間。所述第一電壓偵測電路41連接至第一電壓轉換器21,用於偵測所述第一電壓轉換器21是否有故障發生。所述第二電壓偵測電路42連接至第二電壓轉換器22,用於偵測所述第二電壓轉換器22是否有故障發生。所述第一報警電路51連接至所述第一電壓偵測電路41。所述第二報警電路52連接至所述第二電壓偵測電路42。當所述第一電壓偵測電路41偵測到第一電壓轉換器21有故障發生時,所述第一開關電路31切斷所述第一電壓轉換器21,同時所述電源供應單元10驅動所述第一報警電路51發出相應之報警訊號。當所述第二電壓偵測電路42偵測到第二電壓轉換器22有故障發生時,所述第二開關電路32切斷所述第二電壓轉換器22,同時所述電源供應單元10驅動所述第二報警電路52發出相應之報警訊號。 Referring to FIG. 1 , the power protection circuit 100 of the present invention includes a power supply unit 10 , a first voltage converter 21 , a second voltage converter 22 , a first switch circuit 31 , and a second switch circuit . 32. A first voltage detecting circuit 41 and a second The voltage detecting circuit 42 , a first alarm circuit 51 and a second alarm circuit 52 . The power supply unit 10 is configured to provide a voltage source for the first voltage converter 21 and the second voltage converter 22. The first switch circuit 31 is connected between the power supply unit 10 and the first voltage converter 21. The second switch circuit 32 is connected between the power supply unit 10 and the second voltage converter 22. The first voltage detecting circuit 41 is connected to the first voltage converter 21 for detecting whether the first voltage converter 21 has a fault. The second voltage detecting circuit 42 is connected to the second voltage converter 22 for detecting whether the second voltage converter 22 has a fault. The first alarm circuit 51 is connected to the first voltage detecting circuit 41. The second alarm circuit 52 is connected to the second voltage detecting circuit 42. When the first voltage detecting circuit 41 detects that a fault occurs in the first voltage converter 21, the first switching circuit 31 cuts off the first voltage converter 21 while the power supply unit 10 drives The first alarm circuit 51 sends a corresponding alarm signal. When the second voltage detecting circuit 42 detects that a fault occurs in the second voltage converter 22, the second switching circuit 32 cuts off the second voltage converter 22 while the power supply unit 10 drives The second alarm circuit 52 sends a corresponding alarm signal.

可以理解之係,除本實施方式外,根據上述原理還可分別設置三個或三個以上之電壓轉換器、開關電路、電壓偵測電路及報警電路,並不限於本實施方式。 It can be understood that, in addition to the present embodiment, three or more voltage converters, switching circuits, voltage detecting circuits, and alarm circuits may be separately provided according to the above principles, and are not limited to the embodiment.

請一併參閱圖2,本實施方式中,所述電源供應單元10用於輸出12V電壓,所述第一電壓轉換器21用於將所述電源供應單元10輸出之12V電壓轉換為5V,所述第二電壓轉換器22用於將所述電源供應單元10輸出之12V電壓轉換為3.3V。所述第一電壓轉換器21 之輸出端212連接至一負載(圖未示)。所述第二電壓轉換器22之輸出端222連接至另一負載(圖未示)。 Referring to FIG. 2, in the embodiment, the power supply unit 10 is configured to output a voltage of 12V, and the first voltage converter 21 is configured to convert a voltage of 12V output by the power supply unit 10 into 5V. The second voltage converter 22 is configured to convert the 12V voltage output by the power supply unit 10 to 3.3V. The first voltage converter 21 The output 212 is coupled to a load (not shown). The output 222 of the second voltage converter 22 is coupled to another load (not shown).

所述第一開關電路31為一第一電晶體Q1,所述第二開關電路32為一第二電晶體Q2。本實施方式中,所述第一電晶體Q1與第二電晶體Q2均為P-MOS電晶管,該第一電晶體Q1之漏極D連接至第一電壓轉換器21之輸入端211,所述第一電晶體Q1之柵極G連接至所述電壓偵測電路40且經過一延時電容C1連接至地。所述第一電晶體Q1之源極S連接至所述電源供應單元10。所述第二電晶體Q2之漏極D連接至第二電壓轉換器22之輸入端221,所述第二電晶體Q2之柵極G連接至所述電壓偵測電路40且經過一延時電容C2連接至地。所述第二電晶體Q2之源極S連接至所述電源供應單元10。同時,所述第二電晶體Q2之柵極G連接至所述電壓偵測電路40。 The first switch circuit 31 is a first transistor Q1, and the second switch circuit 32 is a second transistor Q2. In this embodiment, the first transistor Q1 and the second transistor Q2 are both P-MOS transistors, and the drain D of the first transistor Q1 is connected to the input terminal 211 of the first voltage converter 21, The gate G of the first transistor Q1 is connected to the voltage detecting circuit 40 and connected to the ground via a delay capacitor C1. The source S of the first transistor Q1 is connected to the power supply unit 10. The drain D of the second transistor Q2 is connected to the input terminal 221 of the second voltage converter 22, and the gate G of the second transistor Q2 is connected to the voltage detecting circuit 40 and passes through a delay capacitor C2. Connect to the ground. The source S of the second transistor Q2 is connected to the power supply unit 10. At the same time, the gate G of the second transistor Q2 is connected to the voltage detecting circuit 40.

所述第一電壓偵測電路41包括一第三電晶體Q3及一第四電晶體Q4。本實施方式中,所述第三電晶體Q3及第四電晶體Q4均為NPN型電晶體。所述第三電晶體Q3之集電極C藉由一電阻R2連接至所述第一電晶體Q1之柵極G。所述第三電晶體Q3之發射極E藉由一電阻R1連接至地。所述第三電晶體Q3之基極B藉由一電阻R3連接至所述第一電壓轉換器21之輸出端212。所述第四電晶體Q4之集電極C藉由一電阻R4連接至所述電源供應單元10。所述第四電晶體Q4之發射極E藉由一電阻R5接地。所述第四電晶體Q4之基極B藉由兩個電阻R6、R7連接至所述電源供應單元10。所述第三電晶體Q3之集電極C與第四電晶體Q4之集電極C之間串聯有一電阻R8。所述電阻R6與地之間串聯有一電阻R9。 The first voltage detecting circuit 41 includes a third transistor Q3 and a fourth transistor Q4. In this embodiment, the third transistor Q3 and the fourth transistor Q4 are both NPN type transistors. The collector C of the third transistor Q3 is connected to the gate G of the first transistor Q1 via a resistor R2. The emitter E of the third transistor Q3 is connected to the ground by a resistor R1. The base B of the third transistor Q3 is connected to the output terminal 212 of the first voltage converter 21 via a resistor R3. The collector C of the fourth transistor Q4 is connected to the power supply unit 10 by a resistor R4. The emitter E of the fourth transistor Q4 is grounded via a resistor R5. The base B of the fourth transistor Q4 is connected to the power supply unit 10 by two resistors R6, R7. A resistor R8 is connected in series between the collector C of the third transistor Q3 and the collector C of the fourth transistor Q4. A resistor R9 is connected in series between the resistor R6 and the ground.

所述第二電壓偵測電路42包括一第五電晶體Q5及一第六電晶體Q6。本實施方式中,所述第五電晶體Q5及第六電晶體Q6均為NPN型電晶體。所述第五電晶體Q5之集電極C藉由一電阻R10連接至所述第二電晶體Q2之柵極G。所述第五電晶體Q5之發射極E藉由一分壓電阻R11連接至地。所述第五電晶體Q5之基極B藉由一電阻R12連接至所述第二電壓轉換器22之輸出端222。所述第六電晶體Q6之集電極C藉由一電阻R13連接至所述電源供應單元10。所述第六電晶體Q6之發射極E藉由一電阻R14接地。所述第六電晶體Q6之基極B藉由兩個電阻R15、R16連接至所述電源供應單元10。所述第五電晶體Q5之集電極C與第六電晶體Q6之集電極C之間串聯有一電阻R17。所述電阻R15與地之間串聯有一電阻R18。 The second voltage detecting circuit 42 includes a fifth transistor Q5 and a sixth transistor Q6. In the present embodiment, the fifth transistor Q5 and the sixth transistor Q6 are both NPN type transistors. The collector C of the fifth transistor Q5 is connected to the gate G of the second transistor Q2 by a resistor R10. The emitter E of the fifth transistor Q5 is connected to the ground by a voltage dividing resistor R11. The base B of the fifth transistor Q5 is connected to the output terminal 222 of the second voltage converter 22 by a resistor R12. The collector C of the sixth transistor Q6 is connected to the power supply unit 10 by a resistor R13. The emitter E of the sixth transistor Q6 is grounded via a resistor R14. The base B of the sixth transistor Q6 is connected to the power supply unit 10 by two resistors R15, R16. A resistor R17 is connected in series between the collector C of the fifth transistor Q5 and the collector C of the sixth transistor Q6. A resistor R18 is connected in series between the resistor R15 and the ground.

所述第一報警電路51包括一第七電晶體Q7、一第八電晶體Q8、一第九電晶體Q9及一第一發光二極體D1。本實施方式中,所述第七電晶體Q7為一NPN型電晶體。第八電晶體Q8與第九電晶體Q9均為N-MOS電晶管。該第七電晶體Q7之基極B連接至第三電晶體Q3之集電極C,第七電晶體Q7之集電極C藉由一電阻R19連接至所述電源供應單元10,第七電晶體Q7之發射極E藉由一電阻R20連接至所述第四電晶體Q4之集電極C。所述第八電晶體Q8與第九電晶體Q9之柵極G均連接至第四電晶體Q4之集電極C。所述第八電晶體Q8之源極S連接至所述第九電晶體Q9之漏極D。所述第九電晶體Q9之源極S接地。所述第八電晶體Q8之漏極D連接第一發光二極體D1之陰極。所述第一發光二極體D1之陽極藉由一電阻R21連接至所述電源供應單元10。 The first alarm circuit 51 includes a seventh transistor Q7, an eighth transistor Q8, a ninth transistor Q9, and a first LED diode D1. In this embodiment, the seventh transistor Q7 is an NPN type transistor. The eighth transistor Q8 and the ninth transistor Q9 are both N-MOS transistors. The base B of the seventh transistor Q7 is connected to the collector C of the third transistor Q3, and the collector C of the seventh transistor Q7 is connected to the power supply unit 10 by a resistor R19, and the seventh transistor Q7 The emitter E is connected to the collector C of the fourth transistor Q4 by a resistor R20. The gates G of the eighth transistor Q8 and the ninth transistor Q9 are both connected to the collector C of the fourth transistor Q4. The source S of the eighth transistor Q8 is connected to the drain D of the ninth transistor Q9. The source S of the ninth transistor Q9 is grounded. The drain D of the eighth transistor Q8 is connected to the cathode of the first LED D1. The anode of the first LED D1 is connected to the power supply unit 10 by a resistor R21.

所述第二報警電路52包括一第十電晶體Q10、一第十一電晶體Q11、一第十二電晶體Q12及一第二發光二極體D2。本實施方式中,所述第十電晶體Q10為一NPN型電晶體。第十一電晶體Q11與第十二電晶體Q12均為N-MOS電晶管。該第十電晶體Q10之基極B連接至第五電晶體Q5之集電極C,第十電晶體Q10之集電極C藉由一電阻R22連接至所述電源供應單元10,第十電晶體Q10之發射極E藉由一電阻R23連接至所述第六電晶體Q6之集電極C。所述第十一電晶體Q11與第十二電晶體Q12之柵極G均連接至所述第八電晶體Q8之源極S與第九電晶體Q9之漏極D之間。所述第十一電晶體Q11之源極S連接至所述第十二電晶體Q12之漏極D。所述第十二電晶體Q12之源極S接地。所述第十一電晶體Q11之漏極D連接至所述第二發光二極體D2之陰極。所述第二發光二極體D2之陽極藉由一電阻R24連接至所述電源供應單元10。 The second alarm circuit 52 includes a tenth transistor Q10, an eleventh transistor Q11, a twelfth transistor Q12, and a second LED Dipole D2. In this embodiment, the tenth transistor Q10 is an NPN type transistor. The eleventh transistor Q11 and the twelfth transistor Q12 are both N-MOS electrowinning tubes. The base B of the tenth transistor Q10 is connected to the collector C of the fifth transistor Q5, and the collector C of the tenth transistor Q10 is connected to the power supply unit 10 by a resistor R22, and the tenth transistor Q10 The emitter E is connected to the collector C of the sixth transistor Q6 via a resistor R23. The gates G of the eleventh transistor Q11 and the twelfth transistor Q12 are both connected between the source S of the eighth transistor Q8 and the drain D of the ninth transistor Q9. The source S of the eleventh transistor Q11 is connected to the drain D of the twelfth transistor Q12. The source S of the twelfth transistor Q12 is grounded. The drain D of the eleventh transistor Q11 is connected to the cathode of the second LED D2. The anode of the second LED D2 is connected to the power supply unit 10 by a resistor R24.

使用時,當負載發生故障致使所述第一電壓轉換器21有異常輸出時,此時所述第一電壓偵測電路41之所述第三電晶體Q3之基極B電壓降低。也即,所述第一電壓偵測電路41之輸入電壓降低。所述第三電晶體Q3截止,第一電晶體Q1之柵極G電壓升高,第一電晶體Q1截止,所述第一電壓轉換器21之輸入端211停止輸入,所述第一電壓轉換器21停止工作。同時,第七電晶體Q7、第八電晶體Q8及第九電晶體Q9均導通,所述第一發光二極體D1發光,從而發出警報。而由於所述第十一電晶體Q11與第十二電晶體Q12之柵極G均連接至所述第八電晶體Q8之源極S與第九電晶體Q9之漏極D之間,所述第九電晶體Q9之源極S接地,因此,所述第十一電晶 體Q11之柵極G與第十二電晶體Q12之柵極G得到一低電平,所述第十一電晶體Q11與第十二電晶體Q12均截止,所述第二發光二極體D2不發光。 In use, when the load fails to cause the first voltage converter 21 to have an abnormal output, the base B voltage of the third transistor Q3 of the first voltage detecting circuit 41 is lowered. That is, the input voltage of the first voltage detecting circuit 41 is lowered. The third transistor Q3 is turned off, the voltage of the gate G of the first transistor Q1 is increased, the first transistor Q1 is turned off, the input terminal 211 of the first voltage converter 21 stops inputting, and the first voltage is converted. The device 21 stops working. At the same time, the seventh transistor Q7, the eighth transistor Q8, and the ninth transistor Q9 are both turned on, and the first light-emitting diode D1 emits light, thereby issuing an alarm. And since the gates G of the eleventh transistor Q11 and the twelfth transistor Q12 are both connected between the source S of the eighth transistor Q8 and the drain D of the ninth transistor Q9, The source S of the ninth transistor Q9 is grounded, and therefore, the eleventh transistor The gate G of the body Q11 and the gate G of the twelfth transistor Q12 obtain a low level, and the eleventh transistor Q11 and the twelfth transistor Q12 are both turned off, and the second light emitting diode D2 Does not shine.

當負載發生故障致使所述第二電壓轉換器22有異常輸出時,此時所述第二電壓偵測電路42之所述第五電晶體Q5之基極B電壓降低,也即,所述第二電壓偵測電路42之輸入電壓降低。所述第五電晶體Q5截止,第二電晶體Q2之柵極G電壓升高,第二電晶體Q2截止。同時,第六電晶體Q6、第十電晶體Q10、第十一電晶體Q11及第十二電晶體Q12均導通,所述第二發光二極體D2發光,從而發出警報。而由於所述第八電晶體Q8與第九電晶體Q9之柵極G均連接至所述第十一電晶體Q11之源極S與第十二電晶體Q12之漏極D之間,所述第十二電晶體Q12之源極S接地,因此,所述第八電晶體Q8之柵極G與第九電晶體Q9之柵極G得到一低電平,所述第八電晶體Q8與第九電晶體Q9均截止,所述第一發光二極體D1不發光。 When the load is faulty, causing the second voltage converter 22 to have an abnormal output, the base B voltage of the fifth transistor Q5 of the second voltage detecting circuit 42 is lowered, that is, the first The input voltage of the two voltage detecting circuit 42 is lowered. The fifth transistor Q5 is turned off, the voltage of the gate G of the second transistor Q2 is increased, and the second transistor Q2 is turned off. At the same time, the sixth transistor Q6, the tenth transistor Q10, the eleventh transistor Q11, and the twelfth transistor Q12 are both turned on, and the second light-emitting diode D2 emits light, thereby issuing an alarm. And since the gates G of the eighth transistor Q8 and the ninth transistor Q9 are both connected between the source S of the eleventh transistor Q11 and the drain D of the twelfth transistor Q12, The source S of the twelfth transistor Q12 is grounded. Therefore, the gate G of the eighth transistor Q8 and the gate G of the ninth transistor Q9 get a low level, and the eighth transistor Q8 and the Nine transistors Q9 are all turned off, and the first light-emitting diode D1 does not emit light.

當所述第一電壓偵測電路偵測到第一電壓轉換器有故障發生時,所述第一開關電路切斷所述第一電壓轉換器,同時驅動第一報警電路發出相應之報警訊號,提醒人員注意第一電壓轉換器有故障。當所述第二電壓偵測電路偵測到第二電壓轉換器有故障發生時,所述第二開關電路切斷所述第二電壓轉換器,同時驅動第二報警電路發出相應之報警訊號,提醒人員注意第二電壓轉換器有故障。如此可以及時有效地查出故障之原因且避免了可能出現之各種事故。 When the first voltage detecting circuit detects that a fault occurs in the first voltage converter, the first switching circuit cuts off the first voltage converter, and simultaneously drives the first alarm circuit to issue a corresponding alarm signal. Remind the person that the first voltage converter is faulty. When the second voltage detecting circuit detects that a fault occurs in the second voltage converter, the second switching circuit cuts off the second voltage converter, and simultaneously drives the second alarm circuit to issue a corresponding alarm signal. Remind the person that the second voltage converter is faulty. In this way, the cause of the fault can be detected in a timely and effective manner and various accidents that may occur are avoided.

綜上所述,本發明確已符合發明專利之要件,遂依法提出專利申 請。惟,以上所述者僅為本發明之較佳實施方式,自不能以此限制本案之申請專利範圍。舉凡熟悉本案技藝之人士爰依本發明之精神所作之等效修飾或變化,皆應涵蓋於以下申請專利範圍內。 In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. please. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.

100‧‧‧電源保護電路 100‧‧‧Power protection circuit

10‧‧‧電源供應單元 10‧‧‧Power supply unit

21‧‧‧第一電壓轉換器 21‧‧‧First voltage converter

22‧‧‧第二電壓轉換器 22‧‧‧Second voltage converter

211、221‧‧‧輸入端 211, 221‧‧‧ input

212、222‧‧‧輸出端 212, 222‧‧‧ output

31‧‧‧第一開關電路 31‧‧‧First switch circuit

32‧‧‧第二開關電路 32‧‧‧Second switch circuit

Q1‧‧‧第一電晶體 Q1‧‧‧First transistor

Q2‧‧‧第二電晶體 Q2‧‧‧Second transistor

D‧‧‧漏極 D‧‧‧Drain

S‧‧‧源極 S‧‧‧ source

G‧‧‧柵極 G‧‧‧Gate

C1、C2‧‧‧延時電容 C1, C2‧‧‧ time delay capacitor

41‧‧‧第一電壓偵測電路 41‧‧‧First voltage detection circuit

42‧‧‧第二電壓偵測電路 42‧‧‧Second voltage detection circuit

Q3‧‧‧第三電晶體 Q3‧‧‧ Third transistor

Q4‧‧‧第四電晶體 Q4‧‧‧4th transistor

R1-R24‧‧‧電阻 R1-R24‧‧‧ resistance

B‧‧‧基極 B‧‧‧ base

C‧‧‧集電極 C‧‧‧ Collector

E‧‧‧發射極 E‧‧‧ emitter

Q5‧‧‧第五電晶體 Q5‧‧‧ fifth transistor

Q6‧‧‧第六電晶體 Q6‧‧‧ sixth transistor

51‧‧‧第一報警電路 51‧‧‧First alarm circuit

52‧‧‧第二報警電路 52‧‧‧Second alarm circuit

Q7‧‧‧第七電晶體 Q7‧‧‧ seventh transistor

Q8‧‧‧第八電晶體 Q8‧‧‧ eighth transistor

Q9‧‧‧第九電晶體 Q9‧‧‧Ninth transistor

D1‧‧‧第一發光二極體 D1‧‧‧First Light Emitting Diode

Q10‧‧‧第十電晶體 Q10‧‧‧10th transistor

Q11‧‧‧第十一電晶體 Q11‧‧‧Eleventh transistor

Q12‧‧‧第十二電晶體 Q12‧‧‧12th transistor

D2‧‧‧第二發光二極體 D2‧‧‧Second light-emitting diode

Claims (9)

一種電源保護電路,其包括一電源供應單元、一第一電壓轉換器、一第二電壓轉換器、一第一開關電路、一第二開關電路,所述第一開關電路連接在所述電源供應單元及所述第一電壓轉換器之間,所述第二開關電路連接在所述電源供應單元及所述第二電壓轉換器之間,所述電源供應單元用於為所述第一、第二電壓轉換器提供電壓源,其改進在於:所述電源保護電路進一步包括一第一電壓偵測電路、一第二電壓偵測電路及一第一報警電路及一第二報警電路,所述第一電壓偵測電路連接至所述第一電壓轉換器,所述第二電壓偵測電路連接至所述第二電壓轉換器,所述第一報警電路連接至所述第一電壓偵測電路,所述第二報警電路連接至所述第二電壓偵測電路,當所述第一電壓偵測電路之輸入電壓降低時,所述第一開關電路切斷所述第一電壓轉換器,同時所述電源供應單元驅動第一報警電路發出報警訊號,當所述第二電壓偵測電路之輸入電壓降低時,所述第二開關電路切斷所述第二電壓轉換器,同時所述電源供應單元驅動第二報警電路發出報警訊號。 A power protection circuit includes a power supply unit, a first voltage converter, a second voltage converter, a first switch circuit, and a second switch circuit, wherein the first switch circuit is connected to the power supply Between the unit and the first voltage converter, the second switch circuit is connected between the power supply unit and the second voltage converter, and the power supply unit is configured to be the first The second voltage converter provides a voltage source, and the improvement is that the power protection circuit further includes a first voltage detecting circuit, a second voltage detecting circuit, a first alarm circuit and a second alarm circuit, a voltage detecting circuit is connected to the first voltage converter, the second voltage detecting circuit is connected to the second voltage converter, and the first alarm circuit is connected to the first voltage detecting circuit. The second alarm circuit is connected to the second voltage detecting circuit, when the input voltage of the first voltage detecting circuit is lowered, the first switching circuit cuts off the first voltage converter, and the same The power supply unit drives the first alarm circuit to send an alarm signal, and when the input voltage of the second voltage detection circuit decreases, the second switch circuit cuts off the second voltage converter, and the power supply The unit drives the second alarm circuit to send an alarm signal. 如申請專利範圍第1項所述之電源保護電路,其中:所述第一開關電路包括一第一電晶體,所述第二開關電路包括一第二電晶體,當所述第一電壓偵測電路之輸入電壓降低時,所述第一電晶體切斷所述第一電壓轉換器,當所述第二電壓偵測電路之輸入電壓降低時,所述第二電晶體切斷所述第二電壓轉換器。 The power protection circuit of claim 1, wherein: the first switch circuit comprises a first transistor, and the second switch circuit comprises a second transistor, when the first voltage is detected. When the input voltage of the circuit decreases, the first transistor cuts off the first voltage converter, and when the input voltage of the second voltage detecting circuit decreases, the second transistor cuts off the second Voltage converter. 如申請專利範圍第2項所述之電源保護電路,其中:所述第一電壓轉換器之輸出端連接至一負載,所述第二電壓轉換器之輸出端連接至另一負載,所述第一電晶體與第二電晶體均為P-MOS電晶管,該第一電晶體之漏極連接至第一電壓轉換器之輸入端,所述第一電晶體之柵極連接所述第一電壓偵測電路,所述第一電晶體之源極連接至所述電源供應單元,所述第二電晶體之源極連接至所述電源供應單元,所述第二電晶體之漏極連接至所述第二電壓轉換器之輸入端,所述第二電晶體之柵極連接至所述第二電壓偵測電路。 The power protection circuit of claim 2, wherein: the output of the first voltage converter is connected to a load, and the output of the second voltage converter is connected to another load, the a transistor and a second transistor are both P-MOS transistors, a drain of the first transistor is connected to an input end of the first voltage converter, and a gate of the first transistor is connected to the first a voltage detecting circuit, a source of the first transistor is connected to the power supply unit, a source of the second transistor is connected to the power supply unit, and a drain of the second transistor is connected to An input end of the second voltage converter, a gate of the second transistor is connected to the second voltage detecting circuit. 如申請專利範圍第3項所述之電源保護電路,其中:所述第一電壓偵測電路包括一第三電晶體及一第四電晶體,所述第三電晶體及第四電晶體均為NPN型電晶體,所述第三電晶體之集電極藉由一電阻連接至所述第一電晶體之柵極,所述第三電晶體之發射極連接至地,所述第三電晶體之基極連接至所述第一電壓轉換器之輸出端,所述第四電晶體之集電極連接至所述電源供應單元,所述第四電晶體之發射極接地,所述第四電晶體之基極連接至所述電源供應單元,所述第三電晶體之集電極與第四電晶體之集電極之間相互連接。 The power protection circuit of claim 3, wherein: the first voltage detecting circuit comprises a third transistor and a fourth transistor, and the third transistor and the fourth transistor are both An NPN type transistor, a collector of the third transistor is connected to a gate of the first transistor by a resistor, an emitter of the third transistor is connected to a ground, and the third transistor is a base is connected to an output end of the first voltage converter, a collector of the fourth transistor is connected to the power supply unit, an emitter of the fourth transistor is grounded, and the fourth transistor is The base is connected to the power supply unit, and the collector of the third transistor and the collector of the fourth transistor are connected to each other. 如申請專利範圍第3項所述之電源保護電路,其中:所述第二電壓偵測電路包括一第五電晶體及一第六電晶體,所述第五電晶體及第六電晶體均為NPN型電晶體,所述第五電晶體之集電極藉由一電阻連接至所述第二電晶體之柵極,所述第五電晶體之發射極連接至地,所述第五電晶體之基極連接至所述第二電壓轉換器之輸出端,所述第六電晶體之集電極連接至所述電源供應單元,所 述第六電晶體之發射極接地,所述第六電晶體之基極連接至所述電源供應單元,所述第五電晶體之集電極與第六電晶體之集電極之間相互連接。 The power protection circuit of claim 3, wherein: the second voltage detecting circuit comprises a fifth transistor and a sixth transistor, and the fifth transistor and the sixth transistor are both An NPN type transistor, a collector of the fifth transistor is connected to a gate of the second transistor by a resistor, an emitter of the fifth transistor is connected to a ground, and the fifth transistor is a base is connected to an output end of the second voltage converter, and a collector of the sixth transistor is connected to the power supply unit The emitter of the sixth transistor is grounded, the base of the sixth transistor is connected to the power supply unit, and the collector of the fifth transistor and the collector of the sixth transistor are connected to each other. 如申請專利範圍第4項所述之電源保護電路,其中:所述第一報警電路包括一第七電晶體、一第八電晶體、一第九電晶體及一第一發光二極體,所述第七電晶體為一NPN型電晶體,第八電晶體與第九電晶體均為N-MOS電晶管,該第七電晶體之基極連接至第三電晶體之集電極,第七電晶體之集電極至所述電源供應單元,第七電晶體之發射極連接至所述第四電晶體之集電極,所述第八電晶體與第九電晶體之柵極均連接至第四電晶體之集電極,所述第八電晶體之源極連接至所述第九電晶體之漏極,所述第九電晶體之源極接地,所述第八電晶體之漏極連接第一發光二極體之陰極,所述第一發光二極體之陽極藉由一電阻連接至所述電源供應單元。 The power protection circuit of claim 4, wherein: the first alarm circuit comprises a seventh transistor, an eighth transistor, a ninth transistor, and a first LED, The seventh transistor is an NPN type transistor, and the eighth transistor and the ninth transistor are both N-MOS transistors, and the base of the seventh transistor is connected to the collector of the third transistor, and the seventh a collector of the transistor to the power supply unit, an emitter of the seventh transistor is connected to a collector of the fourth transistor, and a gate of the eighth transistor and the ninth transistor are connected to a fourth a collector of the transistor, a source of the eighth transistor is connected to a drain of the ninth transistor, a source of the ninth transistor is grounded, and a drain of the eighth transistor is connected to the first a cathode of the light emitting diode, wherein an anode of the first light emitting diode is connected to the power supply unit by a resistor. 如申請專利範圍第5項所述之電源保護電路,其中:所述第二報警電路包括一第十電晶體、一第十一電晶體、一第十二電晶體及一第二發光二極體,所述第十電晶體為一NPN型電晶體,第十一電晶體與第十二電晶體均為N-MOS電晶管,該第十電晶體之基極連接至第五電晶體之集電極,第十電晶體之集電極至所述電源供應單元,第十電晶體之發射極連接至所述第六電晶體之集電極,所述第十一電晶體與第十二電晶體之柵極均連接至所述第八電晶體之源極與第九電晶體之漏極之間,所述第十一電晶體之源極連接至所述第十二電晶體之漏極,所述第十二電晶體之源極接地,所述第十一電晶體之漏極連接至所述第二發光二極體之陰極,所 述第二發光二極體之陽極藉由一電阻連接至所述電源供應單元。 The power protection circuit of claim 5, wherein the second alarm circuit comprises a tenth transistor, an eleventh transistor, a twelfth transistor, and a second LED. The tenth transistor is an NPN type transistor, and the eleventh transistor and the twelfth transistor are both N-MOS transistors, and the base of the tenth transistor is connected to the fifth transistor. An electrode, a collector of the tenth transistor, to the power supply unit, an emitter of the tenth transistor is connected to a collector of the sixth transistor, and a gate of the eleventh transistor and the twelfth transistor a pole is connected between a source of the eighth transistor and a drain of the ninth transistor, and a source of the eleventh transistor is connected to a drain of the twelfth transistor, a source of twelve transistors is grounded, and a drain of the eleventh transistor is connected to a cathode of the second light emitting diode The anode of the second light emitting diode is connected to the power supply unit by a resistor. 如申請專利範圍第3項所述之電源保護電路,其中:所述第一電晶體藉由一延時電容接地。 The power protection circuit of claim 3, wherein the first transistor is grounded by a delay capacitor. 如申請專利範圍第3項所述之電源保護電路,其中:所述第二電晶體藉由一延時電容接地。 The power protection circuit of claim 3, wherein: the second transistor is grounded by a delay capacitor.
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Citations (3)

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US4663580A (en) * 1986-01-09 1987-05-05 Seiscor Technologies, Inc. Sealed lead-acid battery float charger and power supply
TW200807837A (en) * 2006-07-28 2008-02-01 Hon Hai Prec Ind Co Ltd Protecting apparatus for electronic device
TW200836443A (en) * 2006-09-21 2008-09-01 Intel Corp Method, apparatus, and system for power source failure prediction

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4663580A (en) * 1986-01-09 1987-05-05 Seiscor Technologies, Inc. Sealed lead-acid battery float charger and power supply
TW200807837A (en) * 2006-07-28 2008-02-01 Hon Hai Prec Ind Co Ltd Protecting apparatus for electronic device
TW200836443A (en) * 2006-09-21 2008-09-01 Intel Corp Method, apparatus, and system for power source failure prediction

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