TWI413229B - Electrostatic discharge structure - Google Patents

Electrostatic discharge structure Download PDF

Info

Publication number
TWI413229B
TWI413229B TW99140944A TW99140944A TWI413229B TW I413229 B TWI413229 B TW I413229B TW 99140944 A TW99140944 A TW 99140944A TW 99140944 A TW99140944 A TW 99140944A TW I413229 B TWI413229 B TW I413229B
Authority
TW
Taiwan
Prior art keywords
region
diffusion
electrostatic discharge
doped
substrate
Prior art date
Application number
TW99140944A
Other languages
Chinese (zh)
Other versions
TW201222767A (en
Inventor
Yeh Ning Jou
Chia Wei Hung
Hwa Chyi Chiou
Yeh Jen Huang
Shu Ling Chang
Original Assignee
Vanguard Int Semiconduct Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vanguard Int Semiconduct Corp filed Critical Vanguard Int Semiconduct Corp
Priority to TW99140944A priority Critical patent/TWI413229B/en
Publication of TW201222767A publication Critical patent/TW201222767A/en
Application granted granted Critical
Publication of TWI413229B publication Critical patent/TWI413229B/en

Links

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

An electrostatic discharge structure including a substrate, a first diffusion region, a first doped region, a second doped region, a third doped region, a fourth doped region and a first isolation region. The substrate includes a first conductive type. The first diffusion region is formed in the substrate and comprises a second conductive type. The first and the second doped regions are formed in the first diffusion region. The first doped region includes the first conductive type. The second doped region includes the second conductive type. The third doped region, the fourth doped region and the first isolation region are formed in the substrate. The third doped region includes the second conductive type. The fourth doped region includes the first conductive type. During releasing an ESD current, the second doped region does not connect to a first power line.

Description

靜電放電防護結構Electrostatic discharge protection structure

本發明係有關於一種防護結構,特別是有關於一種靜電放電(Electrostatic Discharge;ESD)防護結構。The present invention relates to a protective structure, and more particularly to an electrostatic discharge (ESD) protective structure.

因靜電放電所造成之元件損害對積體電路產品來說已經成為最主要的可靠度問題之一。尤其是隨著尺寸不斷地縮小至深次微米之程度,金氧半導體之閘極氧化層也越來越薄,積體電路更容易因靜電放電現象而遭受破壞。Component damage due to electrostatic discharge has become one of the most important reliability issues for integrated circuit products. In particular, as the size is continuously reduced to a depth of a micron, the gate oxide layer of the MOS semiconductor is also thinner and thinner, and the integrated circuit is more susceptible to damage due to the electrostatic discharge phenomenon.

在一般的工業標準中,積體電路產品之輸出入接腳(I/O pin)必需能夠通過2000伏特以上之人體模式靜電放電測試以及200伏特以上之機械模式靜電放電測試。因此,在積體電路產品中,靜電放電防護元件必需設置在所有輸出入銲墊(pad)附近,以保護內部之核心電路(core circuit)不受靜電放電電流之侵害。In the general industry standard, the input/output pins (I/O pins) of integrated circuit products must pass the human body mode electrostatic discharge test of 2000 volts or more and the mechanical mode electrostatic discharge test of 200 volts or more. Therefore, in the integrated circuit product, the ESD protection component must be placed near all the input and output pads to protect the internal core circuit from the electrostatic discharge current.

本發明提供一種靜電放電防護結構包括,一基底、一第一擴散區、一第一摻雜區、一第二摻雜區、一第三摻雜區、一第一隔離區以及一第四摻雜區。基底具有一第一導電型態。第一擴散區形成在基底之中,並具有一第二導電型態。第一摻雜區形成在第一擴散區之中,並具有第一導電型態。第二摻雜區形成在第一擴散區之中,具有第二導電型態。第三摻雜區形成在基底之中,並具有第二導電型態。第一隔離區形成在基底之中,覆蓋部分第一擴散區,並位於第二及第三摻雜區之間。第四摻雜區形成在基底之中,並具有第一導電型態。當第一摻雜區耦接到一第一電源線,第三及第四操雜區耦接到一第二電源線時,便可將來自第一電源線的一靜電放電電流釋放至第二電源線。在釋放靜電放電電流時,第二摻雜區並未電性連接第一電源線。The present invention provides an electrostatic discharge protection structure including a substrate, a first diffusion region, a first doped region, a second doped region, a third doped region, a first isolation region, and a fourth doped region. Miscellaneous area. The substrate has a first conductivity type. The first diffusion region is formed in the substrate and has a second conductivity type. The first doped region is formed in the first diffusion region and has a first conductivity type. The second doped region is formed in the first diffusion region and has a second conductivity type. The third doped region is formed in the substrate and has a second conductivity type. The first isolation region is formed in the substrate, covers a portion of the first diffusion region, and is located between the second and third doped regions. The fourth doped region is formed in the substrate and has a first conductivity type. When the first doping region is coupled to a first power line, and the third and fourth operating regions are coupled to a second power line, an electrostatic discharge current from the first power line can be released to the second power cable. When the electrostatic discharge current is released, the second doped region is not electrically connected to the first power line.

為讓本發明之特徵和優點能更明顯易懂,下文特舉出較佳實施例,並配合所附圖式,作詳細說明如下:In order to make the features and advantages of the present invention more comprehensible, the preferred embodiments are described below, and are described in detail with reference to the accompanying drawings.

第1A圖為本發明之靜電放電防護結構之一可能實施例。如圖所示,靜電放電防護結構100包括,基底101、擴散區111、摻雜區121~124以及隔離區131。基底101具有一第一導電型態。擴散區111形成在基底101之中,並具有一第二導電型態。在本實施例中,第一導電型態係為P型,而第二導電型態係為N型。在其它實施例中,第一導電型態係為N型,而第二導電型態係為P型。Fig. 1A is a possible embodiment of the electrostatic discharge protection structure of the present invention. As shown, the ESD protection structure 100 includes a substrate 101, a diffusion region 111, doped regions 121-124, and an isolation region 131. The substrate 101 has a first conductivity type. The diffusion region 111 is formed in the substrate 101 and has a second conductivity type. In this embodiment, the first conductivity type is a P type, and the second conductivity type is an N type. In other embodiments, the first conductivity type is N-type and the second conductivity type is P-type.

摻雜區121與122均形成在擴散區111之中。在本實施例中,摻雜區121具有第一導電型態,而摻雜區122具有第二導電型態。第1B圖為摻雜區121與122之俯視圖。摻雜區122以環狀方式,圍繞摻雜區121。Doped regions 121 and 122 are both formed in the diffusion region 111. In this embodiment, the doped region 121 has a first conductivity type and the doped region 122 has a second conductivity type. Figure 1B is a top plan view of doped regions 121 and 122. The doped region 122 surrounds the doped region 121 in an annular manner.

在第1A圖中,摻雜區123與124均形成在基底101之中。在本實施例中,摻雜區123具有第二導電型態,而摻雜區124具有第一導電型態。In FIG. 1A, doped regions 123 and 124 are both formed in the substrate 101. In the present embodiment, the doped region 123 has a second conductivity type, and the doped region 124 has a first conductivity type.

隔離區131形成在基底101之中,覆蓋部分擴散區111,並位於摻雜區122與123之間。隔離區131可為淺溝槽隔離(Shallow trench isolation)或是場氧化層(field oxide)。在本實施例中,靜電放電防護結構100更包括隔離區132~134。隔離區132設置在摻雜區123與124之間。隔離區133設置在摻雜區124的左側。隔離區134設置在摻雜區122的右側。The isolation region 131 is formed in the substrate 101, covers a portion of the diffusion region 111, and is located between the doping regions 122 and 123. The isolation region 131 may be a shallow trench isolation or a field oxide. In this embodiment, the electrostatic discharge protection structure 100 further includes isolation regions 132-134. The isolation region 132 is disposed between the doping regions 123 and 124. The isolation region 133 is disposed on the left side of the doping region 124. The isolation region 134 is disposed on the right side of the doping region 122.

在本實施例中,摻雜區121耦接到電源線VDD,操雜區123及124耦接到電源線VSS。當電源線VDD發生一靜電放電事件,並且電源線VSS接地時,來自電源線VDD的一靜電放電電流可經過摻雜區121、擴散區111、基底101、摻雜區123及124而釋放至地。在釋放靜電放電電流時,摻雜區122並未電性連接電源線VDD。In the present embodiment, the doping region 121 is coupled to the power supply line VDD, and the dummy regions 123 and 124 are coupled to the power supply line VSS. When an electrostatic discharge event occurs in the power line VDD and the power line VSS is grounded, an electrostatic discharge current from the power line VDD can be discharged to the ground through the doping region 121, the diffusion region 111, the substrate 101, and the doping regions 123 and 124. . When the electrostatic discharge current is released, the doping region 122 is not electrically connected to the power supply line VDD.

由於摻雜區122設置在摻雜區121及隔離區131之間,故可改變靜電放電電流的行進路徑,用以避免靜電放電電流直接地碰撞到隔離區131。另外,藉由控制摻雜區122的寬度D,便可調整靜電放電防護結構100的維持電壓(holding voltage)。在一可能實施例中,寬度D約在0.5μ~5μ之間。Since the doping region 122 is disposed between the doping region 121 and the isolation region 131, the traveling path of the electrostatic discharge current can be changed to prevent the electrostatic discharge current from directly colliding with the isolation region 131. In addition, by controlling the width D of the doping region 122, the holding voltage of the electrostatic discharge protection structure 100 can be adjusted. In a possible embodiment, the width D is between about 0.5 μ and 5 μ.

在本實施例中,摻雜區121左側的摻雜區122(以下簡稱左摻雜區122)同時接觸隔離區131及摻雜區121。在其它實施例中,左摻雜區122與隔離區131及摻雜區121之至少一者間具有一間隙。In the present embodiment, the doping region 122 on the left side of the doping region 121 (hereinafter referred to as the left doping region 122) simultaneously contacts the isolation region 131 and the doping region 121. In other embodiments, the left doped region 122 has a gap between at least one of the isolation region 131 and the doped region 121.

第2圖為本發明之靜電放電防護結構之另一可能實施例。第2圖相似第1A圖,差別在於第2圖多了井區212以及閘極241。由於第2圖的基底201、擴散區211、摻雜區221~224以及隔離區231~234與第1圖的基底101、擴散區111、摻雜區121~124以及隔離區131~134相似,故不再詳加說明。Figure 2 is another possible embodiment of the electrostatic discharge protection structure of the present invention. Figure 2 is similar to Figure 1A, with the difference that Figure 2 has more well 212 and gate 241. The substrate 201, the diffusion region 211, the doping regions 221 to 224, and the isolation regions 231 to 234 of FIG. 2 are similar to the substrate 101, the diffusion region 111, the doping regions 121 to 124, and the isolation regions 131 to 134 of FIG. Therefore, no further explanation is given.

如圖所示,井區212形成在基底201之中,並具有第二導電型態。井區212包含部分擴散區211及部分摻雜區222。摻雜區221形成在井區212之中。在本實施例中,井區212、擴散區211以及摻雜區222具有相同的導電型態。在一可能實施例中,摻雜區222具有重濃度的N摻雜物(N+),擴散區211係為一N型汲極漂移區(N-type drain drift;NDD),井區212係為一N型井區(NW)。As shown, the well region 212 is formed in the substrate 201 and has a second conductivity type. The well region 212 includes a partial diffusion region 211 and a partially doped region 222. Doped region 221 is formed in well region 212. In the present embodiment, well region 212, diffusion region 211, and doped region 222 have the same conductivity type. In a possible embodiment, the doped region 222 has a heavy concentration of N dopant (N+), the diffusion region 211 is an N-type drain drift (NDD), and the well region 212 is An N-type well area (NW).

閘極241形成在基底201之上,位於隔離區231與摻雜區223之間,並覆蓋部分隔離區231。閘極241與摻雜區221、223及224構成一雙擴散汲極金氧半場效電晶體(Double Diffused Drain MOSFET;DDMOSFET)。在本實施例中,摻雜區221係為DDMOSFET的汲極(drain)、摻雜區223係為DDMOSFET的源極(source)、摻雜區224係為DDMOSFET的基極(bulk)。The gate 241 is formed over the substrate 201 between the isolation region 231 and the doping region 223 and covers a portion of the isolation region 231. The gate 241 and the doped regions 221, 223, and 224 constitute a double diffused drain double MOSFET (DDMOSFET). In this embodiment, the doping region 221 is a drain of the DDMOSFET, the doping region 223 is a source of the DDMOSFET, and the doping region 224 is a bulk of the DDMOSFET.

此外,在釋放靜電放電電流時,閘極241係耦接電源線VSS,並且摻雜區222並未電性連接至電源線VDD。在一可能實施例中,摻雜區222為浮接(floating)狀態。In addition, when the electrostatic discharge current is released, the gate 241 is coupled to the power line VSS, and the doped region 222 is not electrically connected to the power line VDD. In a possible embodiment, the doped region 222 is in a floating state.

在本實施例中,摻雜區222與隔離區231間具有一間隙。藉由控制摻雜區222的寬度D,便可控制靜電放電防護結構200的維持電壓。In this embodiment, there is a gap between the doping region 222 and the isolation region 231. By controlling the width D of the doped region 222, the sustain voltage of the electrostatic discharge protection structure 200 can be controlled.

第3A圖為本發明之靜電放電防護結構之另一可能實施例。第3A圖相似第1A圖,不同之處在於,第3A圖多了擴散區312A~314A以及摻雜區325A。Fig. 3A is another possible embodiment of the electrostatic discharge protection structure of the present invention. Figure 3A is similar to Figure 1A, except that Figure 3A has more diffusion regions 312A-314A and doped regions 325A.

擴散區312A形成在擴散區313A之中,具有第一導電型態。在本實施例中,摻雜區323A、324A及隔離區332A均形成在擴散區312A之中。在一可能實施例中,擴散區312A的雜質濃度小於摻雜區324的雜質濃度。The diffusion region 312A is formed in the diffusion region 313A and has a first conductivity type. In the present embodiment, the doping regions 323A, 324A and the isolation regions 332A are both formed in the diffusion region 312A. In one possible embodiment, the impurity concentration of the diffusion region 312A is less than the impurity concentration of the doped region 324.

擴散區313A形成在基底301A之中,具有第二導電型態。在本實施例中,擴散區311A與312A形成在擴散區313A之中。在一可能實施例中,擴散區311A係為一N型汲極漂移區(NDD),而擴散區313A係為一高壓N型井區(HVNW)。The diffusion region 313A is formed in the substrate 301A and has a second conductivity type. In the present embodiment, the diffusion regions 311A and 312A are formed in the diffusion region 313A. In one possible embodiment, the diffusion region 311A is an N-type drain drift region (NDD) and the diffusion region 313A is a high voltage N-well region (HVNW).

擴散區314A形成在基底301A之中,並具有第一導電型態,摻雜區325A形成在擴散區314A之中,並具有第一導電型態,作為擴散區314A的金屬接觸點(contact)。在一可能實施例中,摻雜區325A係為一高壓P型井區(HVPW)。The diffusion region 314A is formed in the substrate 301A and has a first conductivity type, and the doping region 325A is formed in the diffusion region 314A and has a first conductivity type as a metal contact of the diffusion region 314A. In one possible embodiment, the doped region 325A is a high pressure P-type well region (HVPW).

在本實施例中,摻雜區323A、324A及325A耦接到電源線VSS,而摻雜區321A耦接到電源線VDD。摻雜區322A並未耦接到電源線VDD。藉由摻雜區322A,便可避免來自電源線VDD的靜電放電電流直接地碰撞到隔離區331A,進而增加靜電放電防護結構300A的維持電壓。In the present embodiment, the doping regions 323A, 324A, and 325A are coupled to the power supply line VSS, and the doping region 321A is coupled to the power supply line VDD. Doped region 322A is not coupled to power supply line VDD. By doping the region 322A, it is possible to prevent the electrostatic discharge current from the power supply line VDD from directly colliding with the isolation region 331A, thereby increasing the sustain voltage of the electrostatic discharge protection structure 300A.

第3B圖為本發明之靜電放電防護結構之另一可能實施例。第3B圖相似第3A圖,不同之處在於,第3B圖多了閘極341B。閘極341B形成在擴散區311B和312B之上,並覆蓋部分摻雜區323B及隔離區331B。Figure 3B is another possible embodiment of the electrostatic discharge protection structure of the present invention. Fig. 3B is similar to Fig. 3A except that the gate 341B is added to Fig. 3B. The gate 341B is formed over the diffusion regions 311B and 312B and covers the partially doped region 323B and the isolation region 331B.

在本實施例中,隔離區331B與摻雜區323B之間具有一間隙。另外,閘極341B、摻雜區321B、323B及324B構成一橫向擴散金屬氧化物半導體(Laterally Diffused Metal Oxide Semiconductor;LDMOS)電晶體。在釋放靜電放電電流時,閘極341B耦接電源線VSS,而摻雜區322B並未耦接到電源線VDD。In this embodiment, there is a gap between the isolation region 331B and the doping region 323B. In addition, the gate 341B and the doped regions 321B, 323B, and 324B constitute a laterally diffused metal oxide semiconductor (LDMOS) transistor. When the electrostatic discharge current is released, the gate 341B is coupled to the power line VSS, and the doped region 322B is not coupled to the power line VDD.

在本實施例中,擴散區311B及312B分別具有第二導電型態及第一導電型態。在一可能實施例中,擴散區311B係為HVNW,而擴散區312B係為HVPW。In this embodiment, the diffusion regions 311B and 312B have a second conductivity type and a first conductivity type, respectively. In one possible embodiment, the diffusion region 311B is HVNW and the diffusion region 312B is HVPW.

第4圖為本發明之靜電放電防護結構之另一可能實施例。第4圖相似第3B圖,不同之處在於,第4圖多了埋藏層451。在本實施例中,埋藏層(buried layer)451形成在基底401之中,並具有第二導電型態。擴散區411、412及415形成在埋藏層451之上。Figure 4 is another possible embodiment of the electrostatic discharge protection structure of the present invention. Figure 4 is similar to Figure 3B, except that Figure 4 has a buried layer 451. In the present embodiment, a buried layer 451 is formed in the substrate 401 and has a second conductivity type. Diffusion regions 411, 412, and 415 are formed over buried layer 451.

在一可能實施例中,埋藏層451係為一N型埋藏層。在本實施例中,擴散區411及415係為一高壓N型井區(HVNW),而擴散區412係為一高壓P型井區(HVPW)。In a possible embodiment, the buried layer 451 is an N-type buried layer. In the present embodiment, the diffusion regions 411 and 415 are a high pressure N-type well region (HVNW), and the diffusion region 412 is a high pressure P-type well region (HVPW).

在本實施例中,摻雜區421耦接到電源線VDD,摻雜區423、424及閘極441耦接到電源線VSS。由於摻雜區421與隔離區431之間具有摻雜區422,故可避免來自電源線VDD的靜電放電電流直接地碰撞到隔離區431,並可提高靜電放電防護結構400的維持電壓。In the present embodiment, the doping region 421 is coupled to the power line VDD, and the doping regions 423, 424 and the gate 441 are coupled to the power line VSS. Since the doping region 422 is provided between the doping region 421 and the isolation region 431, the electrostatic discharge current from the power supply line VDD can be prevented from directly colliding with the isolation region 431, and the sustain voltage of the electrostatic discharge protection structure 400 can be improved.

除非另作定義,在此所有詞彙(包含技術與科學詞彙)均屬本發明所屬技術領域中具有通常知識者之一般理解。此外,除非明白表示,詞彙於一般字典中之定義應解釋為與其相關技術領域之文章中意義一致,而不應解釋為理想狀態或過分正式之語態。Unless otherwise defined, all terms (including technical and scientific terms) are used in the ordinary meaning Moreover, unless expressly stated, the definition of a vocabulary in a general dictionary should be interpreted as consistent with the meaning of an article in its related art, and should not be interpreted as an ideal state or an overly formal voice.

雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100、200、300A、300B、400...靜電放電防護結構100, 200, 300A, 300B, 400. . . Electrostatic discharge protection structure

101、201、301A、301B、401...基底101, 201, 301A, 301B, 401. . . Base

111、211、311A~314A、311B、312B、411、412、415...擴散區111, 211, 311A~314A, 311B, 312B, 411, 412, 415. . . Diffusion zone

121~124、221~224、321A~325A、321B~324B、421~424...摻雜區121~124, 221~224, 321A~325A, 321B~324B, 421~424. . . Doped region

131~134、231~234、331A~335A、331B~334B、431~434...隔離區131~134, 231~234, 331A~335A, 331B~334B, 431~434. . . quarantine area

212...井區212. . . Well area

241、341B、441...閘極241, 341B, 441. . . Gate

451...埋藏層451. . . Buried layer

第1A圖為本發明之靜電放電防護結構之一可能實施例。Fig. 1A is a possible embodiment of the electrostatic discharge protection structure of the present invention.

第1B圖為本發明之靜電放電防護結構之部分俯視圖。Fig. 1B is a partial plan view showing the electrostatic discharge protection structure of the present invention.

第2、3A、3B及4圖為本發明之靜電放電防護結構之其它可能實施例。2, 3A, 3B and 4 are other possible embodiments of the electrostatic discharge protection structure of the present invention.

100...靜電放電防護結構100. . . Electrostatic discharge protection structure

101...基底101. . . Base

111...擴散區111. . . Diffusion zone

121~124...摻雜區121~124. . . Doped region

131~134...隔離區131~134. . . quarantine area

Claims (9)

一種靜電放電防護結構,包括:一基底,具有一第一導電型態;一第一擴散區,形成在該基底之中,並具有一第二導電型態;一第一摻雜區,形成在該第一擴散區之中,並具有該第一導電型態;一第二摻雜區,形成在該第一擴散區之中,具有該第二導電型態,其中該第二摻雜區圍繞該第一摻雜區,並直接接觸該第一摻雜區;一第三摻雜區,形成在該基底之中,並具有該第二導電型態;一第一隔離區,形成在該基底之中,覆蓋部分該第一擴散區,並位於該第二及第三摻雜區之間;以及一第四摻雜區,形成在該基底之中,並具有該第一導電型態;其中當該第一摻雜區耦接到一第一電源線,該第三及第四操雜區耦接到一第二電源線時,便可將來自該第一電源線的一靜電放電電流釋放至該第二電源線;其中在釋放該靜電放電電流時,該第二摻雜區並未電性連接該第一電源線。 An electrostatic discharge protection structure comprising: a substrate having a first conductivity type; a first diffusion region formed in the substrate and having a second conductivity type; a first doped region formed in Between the first diffusion region and having the first conductivity type; a second doped region formed in the first diffusion region, having the second conductivity type, wherein the second doping region surrounds The first doped region is in direct contact with the first doped region; a third doped region is formed in the substrate and has the second conductive type; a first isolation region is formed on the substrate Covering a portion of the first diffusion region between the second and third doped regions; and a fourth doped region formed in the substrate and having the first conductivity type; When the first doped region is coupled to a first power line, and the third and fourth operating regions are coupled to a second power line, an electrostatic discharge current from the first power line can be released. To the second power line; wherein the second doped region is not electrically discharged when the electrostatic discharge current is released Connected to the first power line. 如申請專利範圍第1項所述之靜電放電防護結構,更包括:一井區,形成在該基底之中,並具有該第二導電型態,該井區包含部分該第一擴散區及部分該第二摻雜區,該第 一摻雜區形成在該井區之中;以及一閘極,形成在基底之上,位於該第一隔離區與該第三摻雜區之間,並覆蓋部分該第一隔離區,該閘極與該第一、第三及第四摻雜區構成一雙擴散汲極金氧半場效電晶體(Double Diffused Drain MOSFET),在釋放該靜電放電電流時,該閘極耦接該第二電源線。 The electrostatic discharge protection structure of claim 1, further comprising: a well region formed in the substrate and having the second conductivity type, the well region including a portion of the first diffusion region and a portion The second doping region, the first a doped region is formed in the well region; and a gate is formed over the substrate between the first isolation region and the third doped region and covers a portion of the first isolation region, the gate The pole and the first, third and fourth doping regions form a double-diffused diode double-diffused Drain MOSFET, and the gate is coupled to the second power source when the electrostatic discharge current is released line. 如申請專利範圍第1項所述之靜電放電防護結構,更包括:一第二擴散區,形成在該基底之中,具有該第一導電型態,該第三及第四摻雜區形成在該第二擴散區之中;一第三擴散區,形成在該基底之中,具有該第二導電型態,該第一及第二擴散區形成在該第三擴散區之中。 The electrostatic discharge protection structure of claim 1, further comprising: a second diffusion region formed in the substrate, having the first conductivity type, wherein the third and fourth doped regions are formed Among the second diffusion regions, a third diffusion region is formed in the substrate and has the second conductivity type, and the first and second diffusion regions are formed in the third diffusion region. 如申請專利範圍第3項所述之靜電放電防護結構,其中該第一擴散區係為一N型汲極源移區(N-type drain drift),該第三擴散區係為一高壓N型井區(HVNW)。 The electrostatic discharge protection structure according to claim 3, wherein the first diffusion region is an N-type drain drift, and the third diffusion region is a high-pressure N-type. Well area (HVNW). 如申請專利範圍第1項所述之靜電放電防護結構,更包括:一第二擴散區,形成在該基底之中,具有該第一導電型態,該第三及第四摻雜區形成在該第二擴散區之中;以及一閘極,形成在該第一及第二擴散區之上,並覆蓋部分該第一及第二擴散區,該閘極、該第一、第三及第四摻雜區構成一橫向擴散金屬氧化物半導體(Laterally Diffused Metal Oxide Semiconductor;LDMOS)電晶體,在釋放該靜電放電電流時,該閘極耦接該第二電源線。 The electrostatic discharge protection structure of claim 1, further comprising: a second diffusion region formed in the substrate, having the first conductivity type, wherein the third and fourth doped regions are formed a second diffusion region; and a gate formed over the first and second diffusion regions and covering portions of the first and second diffusion regions, the gate, the first, third, and The four doped regions form a laterally diffused metal oxide semiconductor (LDMOS) transistor, and the gate is coupled to the second power line when the electrostatic discharge current is released. 如申請專利範圍第1項所述之靜電放電防護結構,更包括:一第二擴散區,形成在該基底之中,具有該第一導電型態,該第三及第四摻雜區形成在該第二擴散區之中;以及一埋藏層,形成在該基底之中,並具有該第二導電型態,該第一及第二擴散區形成在該埋藏層之上。 The electrostatic discharge protection structure of claim 1, further comprising: a second diffusion region formed in the substrate, having the first conductivity type, wherein the third and fourth doped regions are formed And a buried layer formed in the substrate and having the second conductivity type, the first and second diffusion regions being formed on the buried layer. 如申請專利範圍第6項所述之靜電放電防護結構,其中該第一擴散區係為一高壓N型井區(HVNW),該第二擴散區係為一高壓P型井區(HVPW)。 The electrostatic discharge protection structure according to claim 6, wherein the first diffusion zone is a high pressure N-type well zone (HVNW), and the second diffusion zone is a high pressure P-type well zone (HVPW). 如申請專利範圍第1項所述之靜電放電防護結構,其中該第二摻雜區接觸該第一摻雜區及該第一隔離區之至少一者。 The electrostatic discharge protection structure of claim 1, wherein the second doped region contacts at least one of the first doped region and the first isolated region. 如申請專利範圍第1項所述之靜電放電防護結構,其中該第二摻雜區與該第一隔離區之間具有一空隙。 The electrostatic discharge protection structure of claim 1, wherein the second doped region and the first isolation region have a gap therebetween.
TW99140944A 2010-11-26 2010-11-26 Electrostatic discharge structure TWI413229B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW99140944A TWI413229B (en) 2010-11-26 2010-11-26 Electrostatic discharge structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW99140944A TWI413229B (en) 2010-11-26 2010-11-26 Electrostatic discharge structure

Publications (2)

Publication Number Publication Date
TW201222767A TW201222767A (en) 2012-06-01
TWI413229B true TWI413229B (en) 2013-10-21

Family

ID=46725322

Family Applications (1)

Application Number Title Priority Date Filing Date
TW99140944A TWI413229B (en) 2010-11-26 2010-11-26 Electrostatic discharge structure

Country Status (1)

Country Link
TW (1) TWI413229B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW493265B (en) * 2001-08-16 2002-07-01 Winbond Electronics Corp ESD protection circuit with high trigger current
US20080054297A1 (en) * 2003-12-18 2008-03-06 Ming-Dou Ker Electrostatic discharge protection circuit using a double-triggered silicon controlling rectifier
US7838937B1 (en) * 2005-09-23 2010-11-23 Cypress Semiconductor Corporation Circuits providing ESD protection to high voltage laterally diffused metal oxide semiconductor (LDMOS) transistors

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW493265B (en) * 2001-08-16 2002-07-01 Winbond Electronics Corp ESD protection circuit with high trigger current
US20080054297A1 (en) * 2003-12-18 2008-03-06 Ming-Dou Ker Electrostatic discharge protection circuit using a double-triggered silicon controlling rectifier
US7838937B1 (en) * 2005-09-23 2010-11-23 Cypress Semiconductor Corporation Circuits providing ESD protection to high voltage laterally diffused metal oxide semiconductor (LDMOS) transistors

Also Published As

Publication number Publication date
TW201222767A (en) 2012-06-01

Similar Documents

Publication Publication Date Title
US7429774B2 (en) Electrostatic discharge (ESD) protection MOS device and ESD circuitry thereof
TWI393238B (en) Transistor-type protection device, semiconductor integrated circuit, and manufacturing method of the same
US8063444B2 (en) Lateral diffused metal oxide semiconductor (LDMOS) devices with electrostatic discharge (ESD) protection capability in integrated circuit
US8492834B2 (en) Electrostatic discharge protection device and applications thereof
US7838940B2 (en) Drain-extended field effect transistor
KR101975608B1 (en) Electrostatic discharge high voltage type transistor and electrostatic dscharge protection circuit thereof
US7709896B2 (en) ESD protection device and method
KR102361141B1 (en) Semiconductor Device for Electrostatic Discharge Protection
US20050179087A1 (en) LDMOS transistor with improved ESD protection
US20190109127A1 (en) Self-biased bidirectional esd protection circuit
US9219057B2 (en) Electrostatic discharge protection device and method for manufacturing the same
US20150129977A1 (en) Semiconductor electrostatic discharge protection apparatus
US20090050967A1 (en) Semiconductor device
US11222888B2 (en) Anti-static metal oxide semiconductor field effect transistor structure
KR101145786B1 (en) Electrostatic discharge protection device
KR100504203B1 (en) Protecting device of semiconductor device
TWI413229B (en) Electrostatic discharge structure
TWI613786B (en) Semiconductor device
US20100102379A1 (en) Lateral diffused metal oxide semiconductor device
TW201431070A (en) Transistor structure for electrostatic discharge protection
TWI538160B (en) Electrostatic discharge protection device and applications thereof
KR20110033788A (en) Semiconductor device
US8278715B2 (en) Electrostatic discharge protection device
TWI429058B (en) Electrostatic discharge protection device with silicon control rectifier
US9230954B1 (en) LDNMOS device for an ESD protection structure