TWI411111B - Thin-film transistor structure and manufacturing method of the same - Google Patents

Abstract

A thin film transistor structure includes a carrier substrate, a gate electrode layer, a gate dielectric layer, a first semiconductor layer, a second semiconductor layer and two semiconductor spacers. The gate electrode layer is formed on the surface of the carrier substrate. The gate dielectric layer overlays the carrier substrate and the gate electrode layer. The first semiconductor layer is formed on the gate dielectric layer and includes a channel region. The second semiconductor layer is formed on the first semiconductor layer and includes a source region and a drain region. A recess is formed between the source region and the drain region. There are two inner sidewalls where the recess adjoins the source region and the drain region. The two semiconductor spacers adjoins the two inner sidewalls and the surface of the channel region.

Description

Thin film transistor structure and manufacturing method thereof

The present invention relates to a thin film transistor structure and a method of fabricating the same, and more particularly to a thin film transistor structure capable of reducing a 汲 extreme electric field and a method of fabricating the same.

In recent years, polycrystalline germanium thin film transistors have higher carrier mobility than amorphous germanium thin film transistors, so they are applied to liquid crystal displays and circuits integrated on glass substrates to provide good performance, and have been applied to liquid crystals. Display, mobile phone panel, thin film solar cell, three-dimensional integrated circuit, as a switching element of pixels. However, due to the extremely high electric field of the crucible, strong leakage current and kink effect cause instability of the element, thus hindering the application of the polycrystalline silicon transistor to the high-performance circuit. The main mechanism of leakage current is that the strong electric field in the extremely depleted region induces the carrier to form a leakage current through defects in the grain boundary. Therefore, in order to reduce the strong leakage current, how to reduce the high electric field of the 汲 extreme is a technical bottleneck that is to be overcome.

In the current research, some scholars have proposed methods for improvement, such as offset, Lightly doped drain (LDD) (for example, US Patent No. 6,468,839 discloses LDD thin film transistor structure), gate coverage Structures such as light overlapped lightly doped drain (GOLDD) are used to alleviate the high electric field of the 汲 extreme, but some methods require additional ion-implantation conditions and doping. The energy agents are not well controlled, but have their limitations. Other methods need Additional masks are required, thus increasing overall cost.

In recent years, related research has also proposed a thin film transistor structure of Raised Source/Drain (RSD) to reduce the extremely high electric field of germanium, for example:

Kow Ming Chang et al. presented the paper "A Novel Low-Temperature Polysilicon Thin-Film Transistors With a Self-Aligned Gate and Raised Source/Drain Formed by the Damascene Process" (IEEE ELECTRON DEVICE LETTERS, VOL.28, NO. 9, SEPTEMBER 2007) discloses a thick source drain structure 10, as shown in Figure 1A. The thick source drain structure 10 includes a carrier 11, a source 12, a drain 13, a channel region 14, a gate dielectric layer 15, and a gate layer 16. The carrier 11 can be an oxide layer and the channel region 14 is composed of polysilicon. The formation of the thick source drain structure 10 requires chemical mechanical polishing (CMP) and ion implantation.

II-Suk Kang et al., 2008, presented "Novel Offset-Gated Bottom Gate Poly-Si TFTs With a Combination Structure of Ultrathin Channel and Raised Source/Drain" (IEEE ELECTRON DEVICE LETTERS, VOL.29, NO.3, MARCH In 2008), a thick gate drain structure 20 of a lower gate is disclosed. The thick source drain structure 20 includes a carrier 21, a source 22, a drain 23, a tantalum nitride layer 24, a gate dielectric layer 25, and a channel region. 26 and gate layer 27. The carrier 21 is glass and the channel region 26 is composed of polycrystalline germanium. The gate layer 27 of this paper is directly disposed on the carrier 21, which is slightly different from the conventional structure. Forming the thick source drain structure 20 requires back surface exposure and ion-implanting processes. The overall process is more complicated.

Even though academics or the industry have proposed thick-source bungee architectures to solve the problem of leakage current, these technologies require chemical mechanical polishing or additional ion implantation when making thick-source bungee structures, so the process is complicated and increases overall. The doubts spent.

The present invention provides a lower gate thin film transistor structure with a simple semiconductor edge liner process. The simulation results show that the gate thin film transistor structure under the semiconductor edge liner can effectively reduce the electric field of the 汲 extreme than the semiconductor lining. Furthermore, the structure with the semiconductor backing can effectively improve the impact dissociation, so the kink effect is improved. The semiconductor lining provides an effective way to expand the high electric field of the 汲 extreme, thereby improving the electrical properties of the component, and since the formed semiconductor lining is in the channel, the conduction current does not drop too much.

A thin film transistor structure according to an embodiment of the invention includes a carrier, a gate layer, a gate dielectric layer, a first semiconductor layer, a second semiconductor layer, and two semiconductor edge liners. A gate layer is formed on the surface of the carrier. A gate dielectric layer covers the carrier and the gate layer. A first semiconductor layer is formed on the surface of the gate dielectric layer and includes a channel region. a second semiconductor layer is formed on the first semiconductor layer, and includes a source region and a drain region. A recess is formed between the source region and the drain region, and the recess is adjacent to the source region and the drain region. Two inner side walls are formed. Two semiconductor backings respectively adjoin the two inner sidewalls and the surface of the channel region.

A method for fabricating a thin film transistor structure according to an embodiment of the present invention The method includes the steps of: providing a carrier; forming a gate layer over the carrier; forming a gate dielectric layer over the gate layer and the carrier; forming a first semiconductor layer on the gate Above the electrical layer, wherein the first semiconductor layer comprises a channel region; forming a second semiconductor layer over the first semiconductor layer; etching the second semiconductor layer to form a recess to expose the channel region, the two sides of the recess The two semiconductor layers are respectively a source region and a drain region, and the recesses form two inner sidewalls adjacent to the source region and the drain region; and two semiconductor edge liners are formed adjacent to the two inner sidewalls and the surface of the channel region.

The making and using of the present invention in the presently preferred embodiments are discussed in detail below. It should be understood, however, that the present invention provides many applicable inventive concepts which can be embodied in various specific embodiments. The specific embodiments of the present invention are merely illustrative of specific ways of making and using the invention and are not intended to limit the scope of the invention.

In order to reduce the high electric field of the crucible extreme, the present invention proposes a thin film transistor with a semiconductor backing without the need for additional ion implantation or chemical mechanical polishing steps. Compared with the conventional structure, the thin film transistor of the present invention lowers the high electric field of the 汲 extreme, and improves the kinking effect and reduces the leakage current.

2A to 2G illustrate a method of fabricating a thin film transistor structure according to an embodiment of the present invention. Referring to FIG. 2A, a substrate 31 is provided which may be a germanium substrate and a carrier 32 is formed on the substrate 31. The carrier 32 may be a ruthenium oxide layer, such as a buffer oxide, to simulate a glass substrate for a thin film transistor. In one embodiment, the thickness is about 4000 at 1050 ° C using a horizontal furnace tube. A buffer oxide layer of up to 5000 angstroms is used as a carrier plate 32 for subsequently forming a thin film transistor.

Referring to FIG. 2B, a gate layer 33 is then formed over the carrier 32. In one embodiment, the gate layer 33 is in-situ deposited with a doped polysilicon layer using a vertical furnace tube and the gate layer 33 is defined by photolithographic etching techniques. The so-called in-situ doped polysilicon technique is based on, for example, the formation of a polycrystalline germanium layer by chemical vapor deposition (CVD), with the addition of a dopant gas such as phosphine or diborane. Thereby, doped polysilicon is deposited directly without additional doping or implantation processes.

Referring to FIG. 2C, a gate dielectric layer 34 is sequentially deposited over the gate layer 33 and the carrier 32, and a first semiconductor layer 35 is formed over the gate dielectric layer 34. In one embodiment, a layer of tetraethoxy silane (TEOS) oxide is deposited as a gate dielectric layer 34 using a horizontal furnace tube. And an amorphous silicon layer was deposited and solid-state vapor phase crystallization (or tempering) was performed at 600 ° C for 24 hours to form polycrystalline germanium as the first semiconductor layer 35. The gate dielectric layer 34 and the portion of the first semiconductor layer 35 covering the gate layer 33 conform to the shape of the gate layer 33 to form a protruding structure 52. The first semiconductor layer 35 on the protruding structure 52 includes a channel region 36.

Referring to FIG. 2D, a second semiconductor layer 37 is formed over the first semiconductor layer 35. In one embodiment, a doped polysilicon layer is deposited as a second semiconductor layer 37 using a vertical furnace tube in-situ.

Referring to FIG. 2E, a recess 38 is formed by lithography and etching techniques, such as dry etching the second semiconductor layer 37 over the gate layer 33, thereby exposing the channel region 36. The second semiconductor layer 37 on both sides of the recess 38 is defined as a source region Field 41 and drain region 43. The recess 38 forms two inner side walls 39 adjacent to the source region 42 and the drain region 43.

Referring to FIG. 2F, a third semiconductor layer 40 is deposited over the second semiconductor layer 37 and the channel region 36. In one embodiment, the third semiconductor layer 40 is a polysilicon layer deposited in a horizontal furnace tube.

Referring to FIG. 2G, the third semiconductor layer 40 is etched, and the third semiconductor layer 40 in the recess 38 forms two semiconductor backings 41. Etching the third semiconductor layer 40 may completely remove the third semiconductor layer 40 on the second semiconductor layer 37 by dry etching anisotropic etching. Since the third semiconductor layer 40 in the central portion of the recess 38 is thin, it will be completely removed after etching to expose the channel region 36. The third semiconductor layer 40 adjacent the two inner sidewalls 39 in the opening 38 is thicker, so that the semiconductor backing 41 is formed after etching. An opening 50 is formed between the semiconductor backings 41 on the two sides which exposes the channel region 36. In this embodiment, the material of the semiconductor backing 41 is polysilicon. Further, a high dielectric constant material having a dielectric constant of 3.9 or more, such as hafnium oxide, tantalum nitride or hafnium oxide, can also be used as the material of the semiconductor backing 41.

Thus, the thin film transistor structure 30 of the embodiment of the present invention is formed. In terms of structural relationship, the thin film transistor structure 30 includes a carrier 32, a gate layer 33, a gate dielectric layer 34, a first semiconductor layer 35, The second semiconductor layer 37 and the two semiconductor backings 41. The gate layer 33 is formed on the surface of the carrier 32. The gate dielectric layer 34 covers the carrier 32 and the gate layer 33. The first semiconductor layer 35 is formed on the surface of the gate dielectric layer 34 and includes a channel region 36. The second semiconductor layer 37 is formed on the surface of the first semiconductor layer 35, and includes a source region 42 and a drain region 43. A recess 38 is formed between the source region 42 and the drain region 43. The recess 38 is formed. Two inner side walls 39 are formed adjacent to the source region 41 and the drain region 43. Two semiconductor backings 41 respectively adjoin the two inner sidewalls 39 and the surface of the channel region 36. An opening 50 is formed between the two semiconductor edge liners 41 to expose the channel region 36.

In particular, the semiconductor backing 41 includes a first connecting surface 61 and a second connecting surface 62, wherein the first connecting surface 61 abuts one end of the source region 42 or the drain region 43; the second connecting surface 62 is adjacent At least a portion of the channel region 36.

In one embodiment, in addition to the doped polysilicon, the gate layer 33 may also use tantalum carbide or tantalum.

In the present invention, the in-situ doping method is used to form the drain region 43 and the source region 42, which is less expensive than the ion implantation and is similar to the process of the amorphous germanium thin film transistor. And by using the height difference formed by the source region 42 and the drain region 43 and the channel 36, the structure of the polysilicon lining 41 is made, and the channel region 36 is thickened in the region near the drain region 43, and there is a flow of electrons. The effect of buffering mitigation is like adding an offset region with a higher resistance value, thus reducing the high electric field of the 汲 extreme.

A general offset structure, an LDD structure, or a GOLDD structure requires an additional mask. However, after the source and drain electrodes are defined, the process of depositing and etching is used to fabricate the polysilicon liner, without requiring additional A mask or a complicated process can reduce the high electric field of the crucible, and the effect of the undesirable effects of polysilicon, such as leakage current and kink effect, can be effectively improved.

In terms of the kink effect, a thin film transistor structure with a semiconductor edge liner can be found from the simulated impact dissociation pattern, which is more obvious than the semiconductor edge liner. The weakening is reduced. Collision by carrier, that is, impact dissociation, is one of the main factors affecting the kink effect. When the channel is near the bungee region, the carrier is affected by the high electric field in the depletion zone, accelerates the collision and dissociates, and has the semiconductor edge. The lining of the thin film transistor structure significantly reduces the electric field, thus improving the phenomenon of impact dissociation and improving the kink effect.

In terms of on-current, since the region where the semiconductor lining is formed is in the channel region, the on-current is not lowered due to the resistance value being too high, and the general offset structure or the LDD structure reduces the high electric field of the 汲 extreme, but also Let the on currents drop a lot because their resistance values are higher and affect the turn on current. Therefore, the semiconductor lining reduces the high electric field of the 汲 extreme and improves the leakage current without sacrificing the on current.

Figure 3 shows the relationship between the distance from the source and the electric field of the thin-film transistor structure, in which the influence of the size of the semiconductor backing without semiconductor backing and different thickness (width) on the electrical properties of the device is simulated. Obviously, there is no semiconductor edge. The thin film transistor structure has the largest electric field peak, that is, its electrical result is the worst. In contrast, having a thicker (200 nm) semiconductor lining has a smaller electric field peak, that is, it has a better anti-kink effect. This is because thicker semiconductor linings have greater resistance at the channel near the 汲 extreme and have a significant improvement in both electric field and shock dissociation.

4 shows the relationship between the drain-source voltage Vds of the thin film transistor structure and the drain-source current Ids, in which the influence of the size of the semiconductor edge liner without semiconductor edge liner and different thickness (width) on the electrical properties of the device is simulated. . As can be seen from FIG. 4, when the Vds is greater than about 7 V, the thin film transistor structure without the semiconductor edge liner has a semiconductor edge lining, and the Ids is significantly increased rapidly. That is, without semiconductor The edge-lined thin film transistor structure has a large leakage current. In addition, the thickness of the semiconductor lining of 100 nm is higher than that of the semiconductor lining of 200 nm. Therefore, a thin film transistor structure with a thick semiconductor edge can further reduce leakage current.

In summary, the thin film transistor structure with semiconductor edge liner of the present invention has the following characteristics: (1) the phenomenon of reducing the extremely high electric field of the germanium: the present invention has a polycrystalline germanium edged structure at the end of the crucible, thereby diffusing a strong electric field, and It is possible to reduce the extremely high electric field. (2) Reducing leakage current: The present invention improves the leakage current by the structure of the polysilicon crucible lining, which improves the resistance of the crucible extreme channel and lowers the high electric field. (3) Improving the kink effect: The present invention reduces the high electric field of the 汲 extreme by the structure of the polycrystalline lining, and also relieves the phenomenon of impact dissociation, thereby improving the kinking effect. (4) Maintaining the on-current: Since the high-resistance region formed by the polysilicon lining is in the channel, the structure will not have a large influence on the on-current, and thus the on-current is maintained.

In addition, the process of the invention is simple, no additional mask process is required, and only the deposition and re-etching is used to fabricate the semiconductor lining, thereby reducing the electric field of the 汲 extreme, and maintaining the conduction current without adding additional series series resistance.

The technical content and technical features of the invention have been disclosed as above, but those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should be construed as being limited by the scope of the appended claims

10‧‧‧Thick source bungee architecture

11‧‧‧ Carrier Board

12‧‧‧ source

13‧‧‧汲polar

14‧‧‧Channel area

15‧‧‧ gate dielectric layer

16‧‧ ‧ gate layer

20‧‧‧ Thick source bungee architecture

21‧‧‧ Carrier Board

22‧‧‧ source

23‧‧‧汲polar

24‧‧‧ layer of tantalum nitride

25‧‧‧ gate dielectric layer

26‧‧‧Channel area

27‧‧‧ gate layer

30‧‧‧Thin-film crystal structure

31‧‧‧Substrate

32‧‧‧ Carrier Board

33‧‧‧ gate layer

34‧‧‧ gate dielectric layer

35‧‧‧First semiconductor layer

36‧‧‧Channel area

37‧‧‧Second semiconductor layer

38‧‧‧ recess

40‧‧‧ third semiconductor layer

41‧‧‧Semiconductor lining

42‧‧‧ source area

43‧‧‧Bungee area

50‧‧‧ openings

52‧‧‧ protruding structure

61‧‧‧First connection surface

62‧‧‧second connection surface

1A and 1B show a conventional thin film transistor structure; FIGS. 2A to 2G show a method of fabricating a thin film transistor structure according to an embodiment of the present invention; and FIG. 3 shows an electric field curve of a thin film transistor according to an embodiment of the present invention; And Figure 4 is a graph showing the relationship between current and voltage of a thin film transistor according to an embodiment of the present invention.

30‧‧‧Thin-film crystal structure

31‧‧‧Substrate

32‧‧‧ Carrier Board

33‧‧‧ gate layer

34‧‧‧ gate dielectric layer

35‧‧‧First semiconductor layer

36‧‧‧Channel area

37‧‧‧Second semiconductor layer

41‧‧‧Semiconductor lining

42‧‧‧ source area

43‧‧‧Bungee area

50‧‧‧ openings

52‧‧‧ protruding structure

61‧‧‧First connection surface

62‧‧‧second connection surface

Claims (23)

A thin film transistor structure comprising: a carrier plate; a gate layer formed on the surface of the carrier; a gate dielectric layer covering the carrier and the gate layer; a first semiconductor layer formed on the substrate The surface of the gate dielectric layer includes a channel region; a second semiconductor layer is formed on the first semiconductor layer, and includes a source region and a drain region, and the source region and the drain region are formed. a recess forming a second inner sidewall adjacent to the source region and the drain region; and two semiconductor backings respectively adjoining the two inner sidewalls and the surface of the channel region. The thin film transistor structure of claim 1, wherein the two semiconductor edge liners form an opening exposing the channel region. The thin film transistor structure of claim 1, wherein the inner sidewall is aligned with a side of the gate layer. The thin film transistor structure of claim 1, wherein the portion of the gate dielectric layer covering the gate layer conforms to the shape of the gate layer to form a protruding structure. The thin film transistor structure of claim 1, wherein the portion of the first semiconductor layer on the gate layer conforms to the shape of the gate layer to form a convex structure. The thin film transistor structure of claim 5, wherein the semiconductor backing is on the protruding structure. The thin film transistor structure according to claim 1, wherein the gate layer comprises doped polysilicon, tantalum carbide or germanium telluride. The thin film transistor structure of claim 1, wherein the first semiconductor layer comprises polysilicon. The thin film transistor structure of claim 1, wherein the second semiconductor layer comprises doped polysilicon. The thin film transistor structure of claim 1, wherein the semiconductor liner comprises a polysilicon or a high dielectric constant material. The thin film transistor structure according to claim 10, wherein the high dielectric constant material has a dielectric constant of 3.9 or more and contains cerium oxide, cerium nitride or cerium oxide. The thin film transistor structure of claim 1, wherein the semiconductor edge comprises a first connection surface and a second connection surface, wherein: the first connection surface abuts one end of the source region or the drain region; The second connecting surface abuts at least a portion of the channel region. A method for fabricating a thin film transistor structure, comprising the steps of: providing a carrier; forming a gate layer over the carrier; forming a gate dielectric layer over the gate layer and the carrier; forming a first a semiconductor layer over the gate dielectric layer, wherein the first semiconductor layer comprises a channel region; forming a second semiconductor layer over the first semiconductor layer; etching the second semiconductor layer to form a recess to expose the channel a second semiconductor layer on both sides of the recess is a source region and a drain region, and a recess is formed adjacent to the source region and the drain region to form two inner sidewalls; and two semiconductor edge liners are formed adjacent to the two inner sidewalls And the surface of the channel area. The method of fabricating a thin film transistor structure according to claim 13, wherein the step of forming the two semiconductor linings comprises: depositing a third semiconductor layer over the second semiconductor layer and the channel region; etching the third semiconductor layer, The third semiconductor layer in the recess forms the two semiconductor backings. The method of fabricating a thin film transistor structure according to claim 14, wherein the etching the third semiconductor layer completely removes the third semiconductor layer above the second semiconductor layer. The method of fabricating a thin film transistor structure according to claim 13, wherein the gate layer is formed by a process of locally doping polysilicon. The method of fabricating a thin film transistor structure according to claim 13, wherein the step of providing a carrier comprises forming a ruthenium oxide layer on a substrate. The method of fabricating a thin film transistor structure according to claim 13, wherein the step of forming the first semiconductor layer over the gate dielectric layer comprises forming an amorphous germanium layer over the gate dielectric layer. The method for fabricating a thin film transistor structure according to claim 18, wherein after the amorphous germanium layer is formed over the gate dielectric layer, the step of tempering the amorphous germanium layer to form a polycrystalline germanium is further included. The method of fabricating a thin film transistor structure according to claim 13, wherein the second semiconductor layer is formed by a current doped polysilicon process. The method of fabricating a thin film transistor structure according to claim 13, wherein the third semiconductor layer is a polysilicon layer or a high dielectric constant material. The method for fabricating a thin film transistor structure according to claim 21, wherein the high dielectric constant material has a dielectric constant of 3.9 or more and contains cerium oxide, cerium nitride or cerium oxide. The method of fabricating a thin film transistor structure according to claim 13, wherein an opening is formed between the two semiconductor edge liners to expose the channel region.