TWI409928B - Universal chip-on-lead leadframe - Google Patents
Universal chip-on-lead leadframe Download PDFInfo
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- TWI409928B TWI409928B TW98139050A TW98139050A TWI409928B TW I409928 B TWI409928 B TW I409928B TW 98139050 A TW98139050 A TW 98139050A TW 98139050 A TW98139050 A TW 98139050A TW I409928 B TWI409928 B TW I409928B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/4809—Loop shape
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Abstract
Description
本發明係有關於半導體裝置之零部件,特別係有關於一種共用型引腳上晶片(Chip-On-Lead,COL)之導線架。The present invention relates to components of a semiconductor device, and more particularly to a lead frame for a chip-on-lead (COL).
在半導體封裝所使用晶片載體之演進中,導線架因具有低材料成本與高可靠度而被長期使用,對低輸入/輸出腳位的半導體產品而言,使用導線架之封裝構造仍具有成本效益。當晶片與導線架作電性連接時,由於導線架之引腳材質可為銅、鐵或其合金,而銲線之材質係為金,但銅與金的接合性不佳,因此通常會在導線架上欲進行打線之區域(例如引腳之接指部位)預先鍍上銀層或容易接合之金屬,俾在打線時,使銲線與引腳上銀層形成金屬鍵合結構,以使銲線能電性連接晶片之銲墊至導線架之引腳。依承載晶片的部位不同,導線架又可區分為使用晶片座之傳統導線架、晶片上引線(LOC)之導線架與引腳上晶片(COL)之導線架,其中,「晶片上引線」(LOC)與「引腳上晶片」(COL)的差異在於,「晶片上引線」(LOC)是使導線架之引腳貼附至晶片之主動面,「引腳上晶片」是使晶片之背面貼附至導線架之引腳。而傳統的「引腳上晶片」(COL)導線架有幾個缺點,以單側引腳承載晶片導致承載力較差,容易受到模流影響而晶片偏移。此外,在導線架設計上有針對晶片的專屬性,即共用性較差。In the evolution of wafer carriers used in semiconductor packages, leadframes have long been used due to their low material cost and high reliability. For semiconductor products with low input/output pins, the package construction using leadframes is still cost effective. . When the wafer is electrically connected to the lead frame, the lead material of the lead frame may be copper, iron or an alloy thereof, and the material of the bonding wire is gold, but the bonding property between copper and gold is not good, so usually The area on the lead frame where the wire is to be grounded (for example, the finger joint portion) is pre-plated with a silver layer or a metal that is easy to bond, and when the wire is wired, the wire is bonded to the silver layer on the lead to form a metal bond structure. The bonding wire can electrically connect the pad of the wafer to the pin of the lead frame. Depending on the location of the carrier chip, the lead frame can be further divided into a conventional lead frame using a wafer holder, a lead frame on a lead on a chip (LOC), and a lead frame on a lead-on-chip (COL), wherein "on-wafer leads" ( The difference between LOC) and "on-wafer chip" (COL) is that the "lead on the wafer" (LOC) is to attach the lead of the lead frame to the active side of the wafer, and the "on-wafer" is the back of the wafer. Attached to the lead of the lead frame. The conventional "on-chip" (COL) leadframe has several disadvantages. The carrier carrying the wafer on one side leads to poor bearing capacity and is susceptible to mold flow and wafer offset. In addition, there is a specificity for the wafer on the lead frame design, that is, the sharing is poor.
如第1A圖所示,為習知一種引腳上晶片(COL)之導線架100,係定義有一模封區110。該模封區110係為一模封形成之封膠體40之預定形成區域(如第1C圖所示)。該模封區110係具有相互平行之第一側邊111與第二側邊112,以供兩側引腳之導入。該模封區110內係包含有一相對較為接近該第一側邊111之打線接合區113。該導線架100係包含複數個設置在該第一側邊111之第一側引腳120以及複數個設置在該第二側邊112之第二側引腳130。該些引腳120、130係由同一導線架100所構成,皆為金屬材質,如銅、鐵或其合金,並在模封後之裁切操作可使引腳分離。其中,第一側引腳120與第二側引腳130依欲封裝晶片的類型不同而有不同長度,第二側引腳130係較長於第一側引腳120,以單側長引腳承載一第一晶片10(如第1B圖所示)。第二側引腳130係具有複數個在該模封區110內之短邊內引腳122,該些短邊內引腳122係延伸至該打線接合區113而形成有複數個中央收斂接指123。該些第二側引腳130係具有複數個在該模封區110內之長邊內引腳132,該些長邊內引腳132係延伸至該打線接合區113而形成有複數個側邊延伸接指134。As shown in FIG. 1A, a lead frame 100 for a pin-on-chip (COL) is defined as a die seal region 110. The molding region 110 is a predetermined formation region of the encapsulant 40 formed by a molding (as shown in FIG. 1C). The molding region 110 has a first side 111 and a second side 112 parallel to each other for introduction of the pins on both sides. The die seal region 110 includes a wire bonding region 113 relatively close to the first side edge 111. The lead frame 100 includes a plurality of first side pins 120 disposed on the first side 111 and a plurality of second side pins 130 disposed on the second side 112. The pins 120 and 130 are formed by the same lead frame 100, and are all made of a metal material such as copper, iron or an alloy thereof, and the cutting operation after the molding can separate the pins. The first side pin 120 and the second side pin 130 have different lengths depending on the type of the package to be packaged, and the second side pin 130 is longer than the first side pin 120 and is carried by the one-side long pin. A first wafer 10 (as shown in Figure 1B). The second side pin 130 has a plurality of short side inner pins 122 in the mold sealing area 110. The short side inner pins 122 extend to the wire bonding area 113 to form a plurality of central convergence fingers. 123. The second side pins 130 have a plurality of long-side inner leads 132 in the mold-sealing region 110. The long-side inner leads 132 extend to the wire bonding area 113 to form a plurality of sides. The extension finger 134 is extended.
如第1B與1C圖所示,第一晶片10之背面係黏設於該導線架100之第二側引腳130上,該第一晶片10之主動面係具有複數個第一銲墊11,該些銲墊11係為單邊排列並鄰近在該打線接合區113(對照第1A與1B圖)。如第1B與1C圖所示,該些短邊內引腳122係利用一第一絕緣膠帶150黏貼以固定,而該些長邊內引腳132係利用一第二絕緣膠帶160黏貼以固定。在該打線接合區113內之該些中央收斂接接指123與側邊延伸接指134之上表面係形成有一電鍍接合層140,以供複數個第一銲線31由該些第一銲墊11電性接合至在該些中央收斂接接指123與該些側邊延伸接指134上之電鍍接合層140。如第1A與1B圖所示,該些中央收斂接接指123與該些側邊延伸接指134是設計在該打線接合區113內並在該第一晶片10之外,以提供連接至該些第一銲墊11之最短打線距離。故,為了配合該第一晶片10之銲墊配置,該些第二側引腳130之長度應大於該些第一側引腳120,以單側引腳承載該第一晶片10。As shown in FIGS. 1B and 1C , the back surface of the first wafer 10 is adhered to the second side lead 130 of the lead frame 100 , and the active surface of the first wafer 10 has a plurality of first pads 11 . The pads 11 are arranged unilaterally adjacent to the wire bonding region 113 (cf. Figures 1A and 1B). As shown in FIGS. 1B and 1C, the short-side inner pins 122 are fixed by a first insulating tape 150, and the long-side inner leads 132 are adhered by a second insulating tape 160 for fixing. An electroplated bonding layer 140 is formed on the upper surface of the central converging contact fingers 123 and the side extending fingers 134 in the wire bonding region 113 for the plurality of first bonding wires 31 to be formed by the first bonding pads 11 is electrically bonded to the plated bonding layer 140 on the central convergence fingers 123 and the side extension fingers 134. As shown in FIGS. 1A and 1B, the central convergence fingers 123 and the side extension fingers 134 are designed in the wire bonding region 113 and outside the first wafer 10 to provide connection thereto. The shortest wire-bonding distance of the first pads 11. Therefore, in order to match the pad configuration of the first wafer 10, the second side pins 130 should be longer than the first side pins 120 to carry the first wafer 10 with a single-sided pin.
如第2A圖所示,為習知另一種引腳上晶片(COL)之導線架200,同樣地,該導線架200係定義有一模封區210,該模封區210係為封膠體40之預定形成區域(如第2C圖所示),可與前述的模封區110尺寸相同。該模封區210係具有相互平行之第一側邊211與第二側邊212。依專用的晶片類型之不同,該模封區210內係包含有一接近該第二側邊212之打線接合區214。該導線架200係包含複數個第一側引腳220以及複數個第二側引腳230。其中,第一側引腳220係較長於第二側引腳230,以單側長引腳承載一第二晶片20(如第2B圖所示)。As shown in FIG. 2A, there is another lead-on-chip (COL) lead frame 200. Similarly, the lead frame 200 defines a molding area 210, and the molding area 210 is a sealing body 40. The predetermined formation region (as shown in Fig. 2C) may be the same size as the aforementioned molding region 110. The molding area 210 has a first side 211 and a second side 212 that are parallel to each other. Depending on the type of wafer to be used, the mold region 210 includes a wire bond region 214 adjacent the second side 212. The lead frame 200 includes a plurality of first side pins 220 and a plurality of second side pins 230. The first side pin 220 is longer than the second side pin 230, and carries a second wafer 20 with a single long pin (as shown in FIG. 2B).
如第2B與2C圖所示,第二晶片20之背面係黏設於該導線架200之第一側引腳220上,該第二晶片20之主動面係具有複數個第二銲墊21,該些銲墊21係為單邊排列並鄰近在該打線接合區214(對照第2A與2B圖)。該些第一側引腳220係具有複數個在該模封區210內之長邊內引腳222,該些長邊內引腳222係延伸至該打線接合區214而形成為複數個中央延伸接指224。如第2C圖所示,該些長邊內引腳222係可利用一第二絕緣膠帶260黏貼以固定。該些第二側引腳230係具有複數個在該模封區210內之短邊內引腳232,該些短邊內引腳232係延伸至該打線接合區214而形成為複數個側邊收斂接指233。As shown in FIGS. 2B and 2C, the back surface of the second wafer 20 is adhered to the first side pin 220 of the lead frame 200, and the active surface of the second wafer 20 has a plurality of second pads 21, The pads 21 are arranged unilaterally adjacent to the wire bonding region 214 (cf. Figures 2A and 2B). The first side pins 220 have a plurality of long side pins 222 in the mold region 210. The long side pins 222 extend to the wire bonding region 214 to form a plurality of central extensions. Finger 224. As shown in FIG. 2C, the long-side inner leads 222 can be fixed by a second insulating tape 260. The second side pins 230 have a plurality of short side inner pins 232 in the mold sealing area 210. The short side inner pins 232 extend to the wire bonding area 214 to form a plurality of sides. Convergence refers to 233.
如第2A與2B圖所示,在該打線接合區214內之該些中央延伸接指224與側邊收斂接指233之上表面係形成有一電鍍接合層240,以供複數個第二銲線32由該些第二銲墊21電性接合至在該些中央延伸接指224與側邊收斂接指233上之電鍍接合層240。如第2A與2B圖所示,該些中央延伸接指224與該些側邊收斂接指233是設計在該打線接合區214內並在該第二晶片20之外,以提供連接至該些第二銲墊21之最短打線矩離。故,為了配合該第二晶片20之銲墊配置,該些第一側引腳220之長度係大於該些第二側引腳230,以單側引腳承載該第二晶片20。As shown in FIG. 2A and FIG. 2B, the central extension fingers 224 and the upper surface of the side convergence fingers 233 are formed with an electroplated bonding layer 240 in the wire bonding region 214 for a plurality of second bonding wires. The second bonding pads 21 are electrically bonded to the plating bonding layer 240 on the central extension fingers 224 and the side convergence fingers 233. As shown in FIGS. 2A and 2B, the central extension fingers 224 and the side convergence fingers 233 are designed in the wire bonding region 214 and outside the second wafer 20 to provide connections thereto. The shortest wire bonding moment of the second pad 21 is separated. Therefore, in order to match the pad configuration of the second wafer 20, the first side pins 220 are longer than the second side pins 230, and the second wafer 20 is carried by the one-sided pins.
同時比對第1B與2B圖,習知為了承載不同設計之晶片10、20,需設計兩側引腳長度不相同之導線架100、200來適應該些晶片10、20之可打線位置與晶片尺寸,由於打線接合區分佈在不同邊,故供應商需具備兩種電鍍模具與兩種光罩,以符合不同之導線架100、200,造成設備成本提高並且造成導線架之備料增加。At the same time, in comparison with the first and second embodiments, in order to carry the wafers 10 and 20 of different designs, it is necessary to design the lead frames 100 and 200 having different lead lengths on both sides to adapt to the wire position and the wafer of the wafers 10 and 20. Dimensions, because the wire bonding area is distributed on different sides, the supplier needs to have two kinds of plating molds and two kinds of masks to meet different lead frames 100 and 200, which causes the equipment cost to increase and the lead frame to be increased.
本發明之主要目的係在於提供一種共用型引腳上晶片之導線架,適用於兩種不同銲墊位置之晶片,電鍍模具與光罩只需一套,更可運用於多晶片堆疊。此外,不同側延伸之中央與側邊內引腳可供晶片背面之貼附,兩側引腳可共同承載晶片,以避免模封時晶片偏移。The main object of the present invention is to provide a lead frame for a chip on a common pin, which is suitable for wafers of two different pad positions, only one set of plating mold and mask, and can be applied to multi-wafer stacking. In addition, the central and side inner leads of the different side extensions are attached to the back side of the wafer, and the pins on both sides can collectively carry the wafer to avoid wafer offset during molding.
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種共用型引腳上晶片之導線架,係定義有一模封區,該模封區係具有相互平行之第一側邊與第二側邊,該模封區內係包含有一接近該第一側邊之第一打線接合區與一接近該第二側邊之第二打線接合區。該導線架主要包含複數個第一側引腳以及複數個第二側引腳。該些第一側引腳係具有複數個在該模封區之外且排列在該第一側邊之第一外引腳以及複數個在該模封區內之中央內引腳,其中該些中央內引腳係往該模封區之一中心線收斂,該些中央內引腳係穿過該第一打線接合區而形成為複數個中央收斂接指,並且該些中央內引腳之內端係延伸至該第二打線接合區而形成為複數個中央延伸接指。該些第二側引腳係具有複數個在該模封區之外且排列在該第二側邊之第二外引腳以及複數個在該模封區內且分散在該些中央內引腳兩邊之側邊內引腳,其中該些側邊內引腳係往該模封區之兩側邊收斂而不交錯在該些中央內引腳之間,該些側邊內引腳係穿過該第二打線接合區而形成為複數個側邊收斂接指,並且該些側邊內引腳更延伸至該第一打線接合區而形成為複數個側邊延伸接指。其中,該些中央收斂接指與該些側邊延伸接指係對齊為直線排列,該些中央延伸接指與該些側邊收斂接指係對齊為直線排列。The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The present invention discloses a lead frame for a chip on a shared pin, which defines a die seal region having first and second sides parallel to each other, and the die seal region includes a proximity a first wire bonding zone on the first side and a second wire bonding zone adjacent to the second side. The lead frame mainly includes a plurality of first side pins and a plurality of second side pins. The first side pins have a plurality of first outer leads outside the molding area and arranged on the first side, and a plurality of central inner pins in the molding area, wherein the The central inner pin is converged toward a center line of the mold sealing area, and the central inner lead is formed through the first wire bonding area to form a plurality of central convergence fingers, and the central inner pins are The end system extends to the second wire bonding zone to form a plurality of central extension fingers. The second side pins have a plurality of second outer leads outside the mold sealing region and arranged on the second side, and a plurality of pins in the mold sealing region and dispersed in the central pins The inner side pins of the two sides, wherein the inner side pins converge toward the two sides of the mold sealing area without interleaving between the central inner pins, and the inner side pins are passed through The second wire bonding region is formed as a plurality of side convergence fingers, and the side inner pins extend to the first wire bonding region to form a plurality of side extension fingers. The central convergence fingers are aligned with the side extension fingers in a straight line, and the central extension fingers are aligned with the side convergence fingers in a straight line.
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.
在前述的導線架中,該些中央收斂接指、該些側邊延伸接指、該些中央延伸接指係可與該些側邊收斂接指上皆形成有一電鍍接合層。In the above lead frame, the central convergence fingers, the side extension fingers, and the central extension fingers may form an electroplated bonding layer with the side convergence fingers.
在前述的導線架中,該電鍍接合層係可為銀層。In the aforementioned lead frame, the plating joint layer may be a silver layer.
在前述的導線架中,該些側邊內引腳係可穿過該第一打線接合區而使其內端形成為複數個模流平衡指。In the aforementioned lead frame, the side inner pins can pass through the first wire bonding zone such that the inner ends thereof are formed into a plurality of mold flow balance fingers.
在前述的導線架中,該些模流平衡指至該第一側邊之間隙距離係可相當於該些中央延伸接指至該第二側邊之間隙距離。In the foregoing lead frame, the gap distance of the mold flow balance fingers to the first side may correspond to the gap distance between the central extension fingers and the second side.
在前述的導線架中,可另包含一第一絕緣膠帶,係位於該第一側邊與該第一打線接合區之間,並貼附固定該些模流平衡指與該些中央內引腳。In the foregoing lead frame, a first insulating tape may be further disposed between the first side edge and the first wire bonding area, and the mold flow balance fingers and the central inner pins are attached and fixed. .
在前述的導線架中,可另包含一第二絕緣膠帶,係位於該第一打線接合區與該第二打線接合區之間,並貼附固定該些中央內引腳與該些側邊內引腳。In the lead frame, a second insulating tape may be further disposed between the first wire bonding zone and the second wire bonding zone, and the central pins are attached and fixed to the side edges. Pin.
在前述的導線架中,可另包含至少一獨立短引腳,係完全形成於該模封區內並被該第二絕緣膠帶貼附固定。In the foregoing lead frame, at least one independent short pin may be further included in the mold sealing area and attached by the second insulating tape.
在前述的導線架中,該些側邊內引腳在該第一打線接合區與該第二打線接合區之間係可為平面凹形曲折。In the lead frame of the foregoing, the side inner pins may have a planar concave meander between the first wire bonding zone and the second wire bonding zone.
在前述的導線架中,該些中央內引腳之至少一個中央內引腳係可具有一加寬中空部。In the aforementioned lead frame, at least one of the central inner leads of the central inner leads may have a widened hollow portion.
在前述的導線架中,該些側邊內引腳之至少一個側邊內引腳係可具有一加寬中空部。In the aforementioned lead frame, at least one of the side inner pins of the side inner pins may have a widened hollow portion.
由以上技術方案可以看出,本發明之共用型引腳上晶片之導線架,有以下優點與功效:It can be seen from the above technical solutions that the lead frame of the chip on the shared pin of the present invention has the following advantages and effects:
一、可藉由兩側引腳個別具有中央內引腳與側邊內引腳,每一內引腳具有在不同打線接合區之兩種接指作為其中之一技術手段,適用於兩種不同銲墊位置之晶片,電鍍模具與光罩只需一套,並可運用於多晶片堆疊。此外,不同側延伸之中央與側邊內引腳可供晶片背面之貼附,以共同承載晶片,進而避免模封時晶片偏移。1. Each of the two pins can have a central inner pin and a side inner pin, and each inner pin has two kinds of fingers in different wire bonding areas as one of the technical means, and is applicable to two different types. The wafer at the pad location, the plating mold and the mask are only one set and can be used for multi-wafer stacking. In addition, the central and side inner leads of the different side extensions can be attached to the back side of the wafer to collectively carry the wafer, thereby avoiding wafer offset during molding.
二、可藉兩側引腳個別具有中央內引腳與側邊內引腳,每一內引腳具有在不同打線接合區之兩種接指作為其中之一技術手段,使不同設計之晶片共用同一導線架,減少廠內導線架備料。Second, the two sides of the pin can have a central inner pin and a side inner pin, each inner pin has two kinds of fingers in different wire bonding areas as one of the technical means, so that different designs of the chip share The same lead frame reduces the preparation of the lead frame in the factory.
以下將配合所附圖示詳細說明本發明之實施例,然應注意的是,該些圖示均為簡化之示意圖,僅以示意方法來說明本發明之基本架構或實施方法,故僅顯示與本案有關之元件與組合關係,圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製,某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理,以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計,詳細之元件佈局可能更為複雜。The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.
依據本發明之一具體實施例,一種共用型引腳上晶片之導線架舉例說明於第3A至3C圖之俯視示意圖。該共用型引腳上晶片之導線架,其中「引腳上晶片」係為Chip-On-Lead的中文名稱,簡稱為COL,使晶片背面黏設於引腳上之封裝型態。該導線架300係定義有一模封區310,該模封區310係具有相互平行之第一側邊311與第二側邊312,該模封區310內係包含有一接近該第一側邊311之第一打線接合區313與一接近該第二側邊312之第二打線接合區314。請參閱第4A與5A圖所示,該導線架300係具有共用性,可供設置不同銲墊位置設計之一第一晶片10或/與一第二晶片20,其中該第一晶片10之銲墊配置係鄰近該第一打線接合區313,該第二晶片20之銲墊配置係鄰近該第二打線接合區314。該模封區310係供一封膠體40之形成(如第4B圖所示),通常該模封區310大於該些晶片10、20,以使該封膠體40能順利密封該些晶片10、20。在本實施例中,該第一晶片10可小於該第二晶片20。第一打線接合區313係為該導線架300提供用以電性連接至該第一晶片10之打線區域。第二打線接合區314係為該導線架300提供用以電性連接至該第二晶片20之打線區域。在本實施例中,如第3A圖所示,該些打線接合區313、314係為平行直線條排列,以符合不同晶片之銲墊配置。In accordance with an embodiment of the present invention, a lead frame for a wafer on a shared pin is illustrated in a top view of Figures 3A through 3C. The lead frame of the chip on the shared pin, wherein the "on-pin wafer" is the Chinese name of the Chip-On-Lead, referred to as COL, and the back side of the chip is adhered to the package type on the pin. The lead frame 300 defines a die seal area 310. The mold seal area 310 has a first side 311 and a second side 312 which are parallel to each other. The mold seal area 310 includes a first side 311 adjacent to the first side 311. The first wire bonding zone 313 and a second wire bonding zone 314 are adjacent to the second side edge 312. Referring to FIGS. 4A and 5A, the lead frame 300 has a commonality, and one of the first pads 10 or/and a second wafer 20 can be provided with different pad position designs, wherein the first wafer 10 is soldered. The pad configuration is adjacent to the first wire bonding region 313, and the pad configuration of the second wafer 20 is adjacent to the second wire bonding region 314. The molding area 310 is formed by forming a gel 40 (as shown in FIG. 4B ). Generally, the sealing area 310 is larger than the wafers 10 and 20 , so that the sealing body 40 can seal the wafers 10 smoothly. 20. In this embodiment, the first wafer 10 can be smaller than the second wafer 20. The first wire bonding area 313 is provided with the wire frame 300 for electrically connecting to the first wafer 10 . The second wire bonding area 314 is provided with the wire frame 300 for electrically connecting to the second wafer 20 . In the present embodiment, as shown in FIG. 3A, the wire bonding regions 313 and 314 are arranged in parallel straight lines to conform to the pad configuration of different wafers.
該導線架300主要包含複數個第一側引腳320以及複數個第二側引腳330。該些第一側引腳320以及該些第二側引腳330係為該導線架300之同一層的相同金屬材料,其材質可為銅、鐵或其合金。該些第一側引腳320係由該第一側邊311往該第二側邊312延伸。該些第二側引腳330係由該第二側邊312往該第一側邊311延伸。The lead frame 300 mainly includes a plurality of first side pins 320 and a plurality of second side pins 330. The first side pins 320 and the second side pins 330 are the same metal material of the same layer of the lead frame 300, and the material thereof may be copper, iron or an alloy thereof. The first side pins 320 extend from the first side 311 to the second side 312. The second side pins 330 extend from the second side 312 to the first side 311.
請參閱第3A與3B圖所示,該些第一側引腳320係具有複數個在該模封區310之外且排列在該第一側邊311之第一外引腳321以及複數個在該模封區310內之中央內引腳322,其中該些中央內引腳322係往該模封區310之一中心線315收斂,換言之,該些中央內引腳322之間隙小於該些第一外引腳321之間隙且趨向該中心線315集中。該些中央內引腳322係穿過該第一打線接合區313而形成為複數個中央收斂接指323,並且該些中央內引腳322之內端係延伸至該第二打線接合區314而形成為複數個中央延伸接指324。如第3A圖所示,該些中央收斂接指323係位在該第一打線接合區313內,該些中央延伸接指324係位在該第二打線接合區314內。該些中央延伸接指324係為該些第一側引腳320之懸空端。Referring to FIGS. 3A and 3B, the first side pins 320 have a plurality of first outer leads 321 outside the mold region 310 and arranged on the first side 311, and a plurality of The central inner lead 322 in the die seal area 310, wherein the central inner leads 322 converge toward a center line 315 of the mold sealing area 310. In other words, the gaps of the central inner leads 322 are smaller than the first A gap between the outer leads 321 and tends to concentrate on the centerline 315. The central inner pins 322 are formed through the first wire bonding regions 313 to form a plurality of central convergence fingers 323, and the inner ends of the central inner pins 322 extend to the second wire bonding regions 314. Formed as a plurality of central extension fingers 324. As shown in FIG. 3A, the central convergence fingers 323 are positioned within the first wire bonding zone 313, and the central extension fingers 324 are positioned within the second wire bonding zone 314. The central extension fingers 324 are the free ends of the first side pins 320.
請參閱第3A與3C圖所示,該些第二側引腳330係具有複數個在該模封區310之外且排列在該第二側邊312之第二外引腳331以及複數個在該模封區310內且分散在該些中央內引腳322兩邊之側邊內引腳332,換言之,該些側邊內引腳332之間隙小於該些第二外引腳331之間隙且往遠離該中心線315的方向匯集。其中該些側邊內引腳332係鄰靠該模封區310之兩無外引腳之側邊(即是在第一側邊311與第二側邊312之間的垂直側邊)收斂而不交錯在該些中央內引腳322之間,以確保與習知兩(多)種非共用型導線架之打線順序相吻合。並且,該些側邊內引腳332係穿過該第二打線接合區314而形成為複數個側邊收斂接指333,並且該些側邊內引腳332更延伸至該第一打線接合區313而形成為複數個側邊延伸接指334。其中,該些中央收斂接指323與該些側邊延伸接指334係對齊為直線排列而位在該第一打線接合區313內,該些中央延伸接指324與該些側邊收斂接指333係對齊為直線排列而位在該第二打線接合區314。換言之,該些第一側引腳320以及該些第二側引腳330皆為長引腳且非為個別引腳的交錯,該些第一側引腳320以及該些第二側引腳330之任一皆具有位在該第一打線接合區313與該第二打線接合區314之兩邊接指並且使不同側引腳的接指區分為中央與側邊,能以打線方式分別電性連接不同銲墊配置設計之晶片。Referring to FIGS. 3A and 3C, the second side pins 330 have a plurality of second outer leads 331 outside the mold region 310 and arranged on the second side 312, and a plurality of The die pad 310 is disposed on the side inner pins 332 of the two inner pins 322. In other words, the gap between the side inner pins 332 is smaller than the gap between the second outer pins 331. Away away from the direction of the centerline 315. The side inner pins 332 are adjacent to the sides of the two outer pins of the mold region 310 (ie, the vertical sides between the first side 311 and the second side 312). They are not interleaved between the central inner leads 322 to ensure alignment with the conventional two (multiple) non-shared leadframes. Moreover, the side inner pins 332 are formed through the second wire bonding region 314 to form a plurality of side convergence fingers 333, and the side inner pins 332 extend to the first wire bonding region. 313 is formed as a plurality of side extension fingers 334. The central convergence fingers 323 and the side extension fingers 334 are aligned in a straight line and are located in the first wire bonding area 313. The central extension fingers 324 and the side convergence fingers The 333 series alignment is arranged in a straight line and is located in the second wire bonding area 314. In other words, the first side pins 320 and the second side pins 330 are long pins and are not interleaved by individual pins, and the first side pins 320 and the second side pins 330 Any one of the first wire bonding area 313 and the second wire bonding area 314 are connected to each other and the fingers of the different side pins are divided into a center and a side, and can be electrically connected by wire bonding. Wafers with different pad configurations.
如第4B圖所示,在黏晶、打線與形成該封裝體40之後,可藉由去框步驟,用切腳機器將該些第一側引腳320與該些第二側引腳330(如第3A圖所示)由該導線架300之邊框切割分離,之後再進行該些第一外引腳321與該些第二外引腳331彎折的成形動作,作為對外電性傳遞。該些第一外引腳321與該些第二外引腳331係可彎折成海鷗腳(gull lead),或可彎折成其他形狀,如I形或J形。As shown in FIG. 4B, after the die bonding, wire bonding, and formation of the package body 40, the first side pins 320 and the second side pins 330 may be formed by a chipping machine by a frame removing step ( As shown in FIG. 3A, the frame of the lead frame 300 is cut and separated, and then the forming operation of bending the first outer leads 321 and the second outer leads 331 is performed as external electrical transmission. The first outer leads 321 and the second outer leads 331 can be bent into a gulla lead or can be bent into other shapes, such as an I shape or a J shape.
具體而言,如第3A圖所示,該些中央收斂接指323、該些中央延伸接指324、該些側邊收斂接指333與該些側邊延伸接指334上皆形成有一電鍍接合層340(如第3A圖中之斜線部分),以加強打線銲接之可靠性。通常該電鍍接合層340係可為銀層。Specifically, as shown in FIG. 3A, the central convergence fingers 323, the central extension fingers 324, the side convergence fingers 333, and the side extension fingers 334 are each formed with a plating joint. Layer 340 (as in the diagonal portion of Figure 3A) to enhance the reliability of wire bonding. Typically, the plated bonding layer 340 can be a silver layer.
再如第3A與3C圖所示,較佳地,該些側邊內引腳332係可穿過該第一打線接合區313而使其內端形成為複數個模流平衡指335,以達到以往單側長引腳承載晶片所不能及的模流平衡效果。該些模流平衡指335係為該些第二側引腳330之懸空內端。更具體地,如第6A與6B圖所示,該些模流平衡指335至該第一側邊311之間隙距離D1係可相當於該些中央延伸接指324至該第二側邊312之間隙距離D2,以使封膠體模封時模流平衡的功效更為明顯。以上所指的「相當」的間隙距離可容許之誤差(即D1減少D2的絕對值除以D1或D2的百分比)可在10%以下。Further, as shown in FIGS. 3A and 3C, preferably, the side inner pins 332 can pass through the first wire bonding region 313 such that the inner ends thereof are formed into a plurality of mold flow balance fingers 335. In the past, the single-sided long pin carrier chip can not match the mold flow balance effect. The mold flow balance fingers 335 are the suspended inner ends of the second side pins 330. More specifically, as shown in FIGS. 6A and 6B, the gap distance D1 of the mold flow balance fingers 335 to the first side edges 311 may correspond to the central extension fingers 324 to the second side edges 312. The gap distance D2 is more effective in making the mold flow balance when the sealant is molded. The allowable error of the "equal" gap distance referred to above (ie, the absolute value of D1 minus D2 divided by the percentage of D1 or D2) may be less than 10%.
具體而言,如第4A與4B圖所示,該導線架300可另包含一第一絕緣膠帶350,其係位於該第一側邊311與該第一打線接合區313(即設有該些中央收斂接指323與該些側邊延伸接指334的位置)之間,可貼附固定該些模流平衡指335與該些中央內引腳322。此外,該導線架可另包含一第二絕緣膠帶360,其係位於該第一打線接合區313與該第二打線接合區314(如第3A圖所示)之間,並貼附固定該些中央內引腳322與該些側邊內引腳332。該第一絕緣膠帶350與該第二絕緣膠帶360係為電性絕緣的黏著貼片,其材質可為聚亞醯胺(polyimide),例如Kapton膠帶。如第4B圖所示,該第一絕緣膠帶350與該第二絕緣膠帶360之任一係同時貼附固定於該兩側引腳320、330之下表面,以穩固兩側引腳,相較於習知絕緣膠帶只能黏貼單側引腳,更能避免模封時引腳產生位移或晃動。Specifically, as shown in FIGS. 4A and 4B, the lead frame 300 may further include a first insulating tape 350 disposed on the first side edge 311 and the first wire bonding area 313 (ie, provided) Between the central convergence fingers 323 and the positions of the side extension fingers 334, the mold flow balance fingers 335 and the central inner pins 322 can be attached and affixed. In addition, the lead frame may further include a second insulating tape 360 between the first wire bonding zone 313 and the second wire bonding zone 314 (as shown in FIG. 3A), and attach and fix the wires. The central inner pin 322 and the side inner pins 332. The first insulating tape 350 and the second insulating tape 360 are electrically insulated adhesive patches, and the material thereof may be polyimide, such as Kapton. tape. As shown in FIG. 4B, the first insulating tape 350 and the second insulating tape 360 are simultaneously attached and fixed on the lower surfaces of the two side pins 320 and 330 to stabilize the two sides of the pins. In the case of the conventional insulating tape, only one side of the pin can be adhered, and the pin can be displaced or shaken during the molding.
如第3A與4A圖所示,該導線架300可另包含至少一獨立短引腳370,其係完全形成於該模封區310內並被該第二絕緣膠帶360貼附固定。該獨立短引腳370係可為無電性傳遞功能之虛引腳(dummy lead),可供消除靜電。As shown in FIGS. 3A and 4A, the lead frame 300 may further include at least one independent short lead 370 which is completely formed in the mold sealing area 310 and is attached and fixed by the second insulating tape 360. The independent short pin 370 can be a dummy lead for the non-electrical transfer function to eliminate static electricity.
具體而言,再如第3A與3C圖所示,該些側邊內引腳332在該第一打線接合區313與該第二打線接合區314之間係可為平面凹形曲折,而往該些中央內引腳322之方向內縮,用以增加該些側邊內引腳332被模封結合力。較佳地,該些中央內引腳322之至少一個中央內引腳322係可具有一加寬中空部322A。該些側邊內引腳332之至少一個側邊內引腳332係可具有一加寬中空部332A。該些加寬中空部322A、332A係可設置在該第一打線接合區313,因引腳寬度增加可提供較佳的打線時支撐力,因封膠體填入其中空部達到較佳的鎖結力。Specifically, as shown in FIGS. 3A and 3C, the side inner pins 332 may be concave and concave between the first wire bonding region 313 and the second wire bonding region 314. The central inner pins 322 are retracted in the direction to increase the bonding force of the side inner pins 332. Preferably, at least one central inner lead 322 of the central inner leads 322 can have a widened hollow portion 322A. At least one of the side inner pins 332 of the side inner pins 332 may have a widened hollow portion 332A. The widened hollow portions 322A, 332A can be disposed in the first wire bonding region 313, and the pin width can be increased to provide better wire-supporting force, because the sealing body fills the hollow portion to achieve better locking. force.
請參閱第4A與5A圖所示,本發明之導線架300可供設置不同銲墊設置設計之晶片10、20,該些晶片10、20可具有不同側之銲墊配置與具有不同之晶片尺寸,以TSOP48 for DDR的封裝外型來說,可將該些第一側引腳320之第4、5、6、7、8、9、10、12、13、14、15、16、17、18與19支引腳拉往但未及至該第二側邊312,此設計較習知之導線架具有彈性與共用性,電鍍面積在左右兩邊(即第3A圖之該第一打線接合區313與該第二打線接合區314),故模具只須開一套並可同時鍍左右兩邊的打線接合區。結構上可用單晶片封裝或多晶片堆疊封裝。此外,不同側延伸之中央與側邊內引腳可供晶片背面之貼附,兩側引腳可共同承載晶片,以避免模封時晶片偏移的發生。Referring to Figures 4A and 5A, the lead frame 300 of the present invention can be used to provide wafers 10, 20 of different pad settings, the wafers 10, 20 having different side pad configurations and having different wafer sizes. In the package appearance of the TSOP48 for DDR, the 4th, 5th, 6th, 7th, 8th, 9th, 10th, 12th, 13th, 14, 15, 16, and 17 of the first side pins 320 may be The 18 and 19 pins are pulled to but not to the second side 312. This design has the flexibility and commonness of the conventional lead frame, and the plating area is on the left and right sides (ie, the first wire bonding area 313 of FIG. 3A and The second wire bonding zone 314), so the mold only needs to open one set and can simultaneously plate the wire bonding areas on the left and right sides. The structure can be packaged in a single chip package or a multi-wafer stack. In addition, the central and side inner leads of the different side extensions can be attached to the back side of the wafer, and the pins on both sides can share the wafer together to avoid wafer offset during molding.
如第4A與4B圖所示,該第一晶片10之主動面係具有複數個第一銲墊11,該些第一銲墊11係為單邊排列並鄰近在該第一打線接合區313(如第3A圖所示),故該第一晶片10可藉由複數個第一銲線31電性連接至該些中央收斂接指323與該些側邊延伸接指334。如第5A與5B圖所示,該第二晶片20之主動面係具有複數第二銲墊21,該些第二銲墊21係為單邊排列並鄰近在該第二打線接合區314(如第3A圖所示),故該第二晶片20可藉由複數個第二銲線32電性連接至該些中央延伸接指324與該些側邊收斂接指333。As shown in FIGS. 4A and 4B, the active surface of the first wafer 10 has a plurality of first pads 11 which are unilaterally arranged adjacent to the first bonding region 313 ( As shown in FIG. 3A, the first wafer 10 can be electrically connected to the central convergence fingers 323 and the side extension fingers 334 by a plurality of first bonding wires 31. As shown in FIGS. 5A and 5B, the active surface of the second wafer 20 has a plurality of second pads 21 which are arranged unilaterally adjacent to the second bonding region 314 (eg, As shown in FIG. 3A , the second wafer 20 can be electrically connected to the central extension fingers 324 and the side convergence fingers 333 by a plurality of second bonding wires 32 .
如第4B與5B圖所示,可利用模封(或稱轉移成形)方法形成該封裝體40以密封第一晶片10(或第二晶片20)、該些銲線31(或32)與該些中央內引腳322、側邊內引腳332,以使該些內部元件與外界隔離而免受外界衝擊或污染。該封裝體40係可為一種內含矽氧填充物的絕緣性熱固性樹脂,如環氧模封化合物(EMC,epoxy molding compound)。因此,該第一晶片10與該第二晶片20可共用同一種導線架,對供應商來說改變光罩與增加電鍍面積,無需增加設備費用,廠內也無備料問題,進而節省成本。在多晶片堆疊封裝中(圖中未繪出),該第一晶片10可預先設置在該導線架300上,並使其單側銲墊11打線至該第一打線接合區313,再堆疊該第二晶片20,並使其單側銲墊21打線至該第二打線接合區314,以完成不同類型的多晶片堆疊在該共用型引腳上晶片之導線架上。As shown in FIGS. 4B and 5B, the package body 40 may be formed by a molding (or transfer forming) method to seal the first wafer 10 (or the second wafer 20), the bonding wires 31 (or 32), and the The central inner pins 322 and the inner inner pins 332 are used to isolate the internal components from the outside world from external impact or contamination. The package 40 can be an insulating thermosetting resin containing a cerium oxide filler, such as an epoxy molding compound (EMC). Therefore, the first wafer 10 and the second wafer 20 can share the same lead frame, and the supplier can change the photomask and increase the plating area without increasing the equipment cost, and there is no material preparation problem in the factory, thereby saving cost. In the multi-wafer stack package (not shown), the first wafer 10 may be pre-disposed on the lead frame 300, and its single-sided pad 11 is wired to the first wire bonding region 313, and then stacked. The second wafer 20 is wired to the second bonding pad 314 to complete different types of multi-wafer stacking on the lead frame of the wafer on the common pin.
以上所述,僅是本發明的較佳實施例而已,並非對本發明作任何形式上的限制,雖然本發明已以較佳實施例揭露如上,然而並非用以限定本發明,任何熟悉本項技術者,在不脫離本發明之技術範圍內,所作的任何簡單修改、等效性變化與修飾,均仍屬於本發明的技術範圍內。The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.
D1...距離D1. . . distance
D2...距離D2. . . distance
10...第一晶片10. . . First wafer
11...第一銲墊11. . . First pad
20...第二晶片20. . . Second chip
21...第二銲墊twenty one. . . Second pad
31...第一銲線31. . . First wire bond
32...第二銲線32. . . Second wire
40...封膠體40. . . Sealant
100...導線架100. . . Lead frame
110...模封區110. . . Molded area
111...第一側邊111. . . First side
112...第二側邊112. . . Second side
113...打線接合區113. . . Wire junction
120...第一側引腳120. . . First side pin
122...短邊內引腳122. . . Short-edge pin
123...中央收斂接指123. . . Central convergence
130...第二側引腳130. . . Second side pin
132...長邊內引腳132. . . Long side pin
134...側邊延伸接指134. . . Side extension finger
140...電鍍接合層140. . . Plating joint
150...第一絕緣膠帶150. . . First insulating tape
160...第二絕緣膠帶160. . . Second insulating tape
200...導線架200. . . Lead frame
210...模封區210. . . Molded area
211...第一側邊211. . . First side
212...第二側邊212. . . Second side
214...打線接合區214. . . Wire junction
220...第一側引腳220. . . First side pin
222...長邊內引腳222. . . Long side pin
224...中央延伸接指224. . . Central extension finger
230...第二側引腳230. . . Second side pin
232...短邊內引腳232. . . Short-edge pin
233...側邊收斂接指233. . . Side convergence
240...電鍍接合層240. . . Plating joint
260...第二絕緣膠帶260. . . Second insulating tape
300...導線架300. . . Lead frame
310...模封區310. . . Molded area
311...第一側邊311. . . First side
312...第二側邊312. . . Second side
313...第一打線接合區313. . . First junction area
314...第二打線接合區314. . . Second wire joint
315...中心線315. . . Center line
320...第一側引腳320. . . First side pin
321...第一外引腳321. . . First outer pin
322...中央內引腳322. . . Central pin
322A...加寬中空部322A. . . Widening the hollow
323...中央收斂接指323. . . Central convergence
324...中央延伸接指324. . . Central extension finger
330...第二側引腳330. . . Second side pin
331...第二外引腳331. . . Second outer pin
332...側邊內引腳332. . . Side pin
332A...加寬中空部332A. . . Widening the hollow
333...側邊收斂接指333. . . Side convergence
334...側邊延伸接指334. . . Side extension finger
335...模流平衡指335. . . Mold flow balance
340...電鍍接合層340. . . Plating joint
350...第一絕緣膠帶350. . . First insulating tape
360...第二絕緣膠帶360. . . Second insulating tape
370...獨立短引腳370. . . Independent short pin
第1A至1C圖:為習知的一種導線架之俯視示意圖、導線架在設置第一晶片之後之俯視示意圖與截面示意圖。1A to 1C are schematic plan views and cross-sectional views of a lead frame of a conventional lead frame after the first wafer is disposed.
第2A至2C圖:為習知的另一種導線架之俯視示意圖、導線架在設置第二晶片之後之俯視示意圖與截面示意圖。2A to 2C are schematic top views of a conventional lead frame, and a schematic plan view and a cross-sectional view of the lead frame after the second wafer is disposed.
第3A至3C圖:依據本發明之一具體實施例的一種共用型引腳上晶片之導線架之俯視示意圖、第一側引腳之俯視圖與第二側引腳之俯視圖。3A-3C are top plan views of a lead frame of a common pin-on-chip, a top view of a first side pin, and a top view of a second side pin, in accordance with an embodiment of the present invention.
第4A與4B圖:依據本發明之一具體實施例的共用型引腳上晶片之導線架在設置第一晶片之後之俯視示意圖與截面示意圖。4A and 4B are schematic top and cross-sectional views of a lead frame of a wafer on a shared pin according to an embodiment of the present invention after the first wafer is disposed.
第5A與5B圖:依據本發明之一具體實施例的共用型引腳上晶片之導線架在設置第二晶片之後之俯視示意圖與截面示意圖。5A and 5B are schematic top and cross-sectional views of a lead frame of a wafer on a shared pin according to an embodiment of the present invention after a second wafer is disposed.
第6A與6B圖:依據本發明之一具體實施例的共用型引腳上晶片之導線架之第一側邊與第二側邊之局部放大俯視示意圖。6A and 6B are partially enlarged plan views showing a first side and a second side of a lead frame of a wafer on a shared pin according to an embodiment of the present invention.
300‧‧‧導線架300‧‧‧ lead frame
310‧‧‧模封區310‧‧‧Molding area
311‧‧‧第一側邊311‧‧‧ first side
312‧‧‧第二側邊312‧‧‧ second side
313‧‧‧第一打線接合區313‧‧‧First wire junction
314‧‧‧第二打線接合區314‧‧‧Second wire junction
315‧‧‧中心線315‧‧‧ center line
320‧‧‧第一側引腳320‧‧‧First side pin
321‧‧‧第一外引腳321‧‧‧First outer lead
322‧‧‧中央內引腳322‧‧‧Central pin
322A‧‧‧加寬中空部322A‧‧‧ widened hollow
323‧‧‧中央收斂接指323‧‧‧Central convergence finger
324‧‧‧中央延伸接指324‧‧‧Central extension finger
330‧‧‧第二側引腳330‧‧‧Second side pin
331‧‧‧第二外引腳331‧‧‧Second outer pin
332‧‧‧側邊內引腳332‧‧‧ Side pin
332A‧‧‧加寬中空部332A‧‧‧ widened hollow
333‧‧‧側邊收斂接指333‧‧‧Side convergence
334‧‧‧側邊延伸接指334‧‧‧Side extension finger
335‧‧‧模流平衡指335‧‧‧Moldflow balance
340‧‧‧電鍍接合層340‧‧‧Electroplating joint
370‧‧‧獨立短引腳370‧‧‧Independent short pin
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Citations (3)
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US6946721B2 (en) * | 2001-11-29 | 2005-09-20 | Infineon Technologies Ag | Leadframe of a conductive material and component with a leadframe of a conductive material |
TW200601534A (en) * | 2004-06-29 | 2006-01-01 | Advanced Semiconductor Eng | Leadframe for multi-chip package and method for manufacturing the same |
US7612436B1 (en) * | 2008-07-31 | 2009-11-03 | Micron Technology, Inc. | Packaged microelectronic devices with a lead frame |
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US6946721B2 (en) * | 2001-11-29 | 2005-09-20 | Infineon Technologies Ag | Leadframe of a conductive material and component with a leadframe of a conductive material |
TW200601534A (en) * | 2004-06-29 | 2006-01-01 | Advanced Semiconductor Eng | Leadframe for multi-chip package and method for manufacturing the same |
US7612436B1 (en) * | 2008-07-31 | 2009-11-03 | Micron Technology, Inc. | Packaged microelectronic devices with a lead frame |
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