TWI406072B - Pixel structure, active device array, display panel, and display apparatus - Google Patents
Pixel structure, active device array, display panel, and display apparatus Download PDFInfo
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本發明是有關於一種顯示面板,且特別是有關於一種顯示面板的畫素結構設計。 The present invention relates to a display panel, and more particularly to a pixel structure design of a display panel.
現今社會多媒體技術相當發達,多半受惠於半導體元件與顯示裝置的進步。就顯示器而言,具有高畫質、空間利用效率佳、低消耗功率、無輻射等優越特性之液晶顯示面板已逐漸成為市場之主流。一般而言,液晶顯示面板(LCD panel)主要是由一主動元件陣列基板、一彩色濾光基板與位於兩基板之間的液晶層所構成。 Today's social multimedia technology is quite developed, and most of them benefit from the advancement of semiconductor components and display devices. As far as the display is concerned, a liquid crystal display panel having superior characteristics such as high image quality, good space utilization efficiency, low power consumption, and no radiation has gradually become the mainstream of the market. Generally, a liquid crystal display panel (LCD panel) is mainly composed of an active device array substrate, a color filter substrate, and a liquid crystal layer between the two substrates.
圖1為習知一種主動元件陣列的上視圖。如圖1所示,主動元件陣列100包括多條掃描配線110、多條資料配線120、橫跨資料配線120的共用配線130、多個主動元件140以及多個畫素電極150。掃描配線110與資料配線120相交並定義出多個畫素區190。主動元件140與畫素電極150分別位於所對應的畫素區190內,其中主動元件140分別連接到所對應的掃描配線110與資料配線120,且同一畫素區190內的主動元件140以及畫素電極150彼此電性連接。由圖1所繪示的架構可知,習知此種主動元件陣列100的畫素結構重複排列,即,相鄰兩畫素區190內的相同元件相距一個畫素寬度。 1 is a top view of a conventional array of active components. As shown in FIG. 1, the active device array 100 includes a plurality of scan lines 110, a plurality of data lines 120, a common line 130 spanning the data lines 120, a plurality of active elements 140, and a plurality of pixel electrodes 150. The scan wiring 110 intersects the data wiring 120 and defines a plurality of pixel regions 190. The active element 140 and the pixel electrode 150 are respectively located in the corresponding pixel area 190, wherein the active element 140 is respectively connected to the corresponding scan line 110 and the data line 120, and the active element 140 and the picture in the same pixel area 190 The element electrodes 150 are electrically connected to each other. It can be seen from the architecture illustrated in FIG. 1 that the pixel structure of the active device array 100 is repeatedly arranged, that is, the same elements in the adjacent two pixel regions 190 are separated by one pixel width.
此外,為了克服非預期的漏光問題,習知會在彩色濾光基板或是主動元件陣列基板上製作黑矩陣,藉以遮蔽主 動元件陣列基板上可能會漏光的區域。 In addition, in order to overcome the unexpected light leakage problem, it is customary to make a black matrix on the color filter substrate or the active device array substrate, thereby shielding the main An area on the moving element array substrate where light may leak.
圖2為圖1之主動元件陣列基板沿A-A’線的剖面圖,且圖2更同時繪示了與該主動元件陣列基板對應的黑矩陣。如圖2所示,在製作液晶顯示面板的過程中,若黑矩陣180與畫素結構之間產生對位偏移(misalignment),將使得黑矩陣180與畫素結構之間產生位移S,而在每個畫素區內造成對應於此位移S的開口率損失。 2 is a cross-sectional view of the active device array substrate of FIG. 1 taken along line A-A', and FIG. 2 further illustrates a black matrix corresponding to the active device array substrate. As shown in FIG. 2, in the process of fabricating the liquid crystal display panel, if a misalignment occurs between the black matrix 180 and the pixel structure, a displacement S is generated between the black matrix 180 and the pixel structure. An aperture ratio loss corresponding to this displacement S is caused in each pixel region.
本發明關於一種畫素結構,其可減少顯示面板製作過程中因對位偏移造成的開口率損失,因而有助於提高製程良率。 The invention relates to a pixel structure, which can reduce the loss of aperture ratio caused by the alignment offset during the manufacturing process of the display panel, thereby contributing to the improvement of the process yield.
本發明另關於一種主動元件陣列基板,可有效避免在顯示面板製作過程中因對位偏移造成的開口率損失,因而有助於提高製程良率。 The invention further relates to an active device array substrate, which can effectively avoid the loss of aperture ratio caused by the alignment offset during the manufacturing process of the display panel, thereby contributing to the improvement of the process yield.
本發明更關於一種應用前述之主動元件陣列基板的顯示面板,其可有效避免因製程對位偏移造成的開口率損失,因而具有較佳的製程良率。 The invention further relates to a display panel using the foregoing active device array substrate, which can effectively avoid the loss of aperture ratio due to process alignment offset, and thus has better process yield.
本發明又關於一種應用前述之顯示面板的顯示裝置。 The present invention is further directed to a display device to which the aforementioned display panel is applied.
為具體描述本發明之內容,在此提出一種畫素結構,其位於一顯示面板的一畫素區內。此畫素結構包括一掃描配線、一第一資料配線、一第二資料配線、一共用配線、一第一主動元件、一第二主動元件、一第一畫素電極以及一第二畫素電極。第一資料配線以及第二資料配線分別位於畫素區的相對兩側,且第一資料配線以及第二資料配線 實質上相互平行,並分別與掃描配線相交。共用配線連接到一共用電壓源,且此共用配線實質上平行於第一資料配線以及第二資料配線,並位於第一資料配線與第二資料配線之間,以將畫素區分為一第一次畫素區以及一第二次畫素區,其中第一次畫素區位於第一資料配線與共用配線之間,而第二次畫素區位於第二資料配線與共用配線之間。第一主動元件位於第一次畫素區內,並且電性連接至掃描配線以及第一資料配線。第二主動元件位於第二次畫素區內,並且電性連接至掃描配線以及第二資料配線。第一畫素電極以及第二畫素電極分別位於第一次畫素區以及第二次畫素區內,並分別電性連接至第一主動元件與第二主動元件,其中第一畫素電極以及第二畫素電極分別與共用配線有部分重疊。 To specifically describe the contents of the present invention, a pixel structure is proposed herein that is located in a pixel region of a display panel. The pixel structure includes a scan line, a first data line, a second data line, a common line, a first active component, a second active component, a first pixel electrode, and a second pixel electrode. . The first data wiring and the second data wiring are respectively located on opposite sides of the pixel area, and the first data wiring and the second data wiring They are substantially parallel to each other and intersect with the scanning wiring. The common wiring is connected to a common voltage source, and the common wiring is substantially parallel to the first data wiring and the second data wiring, and is located between the first data wiring and the second data wiring to distinguish the pixels into a first The sub-pixel area and a second pixel area, wherein the first pixel area is located between the first data line and the shared line, and the second pixel area is located between the second data line and the shared line. The first active component is located in the first pixel region and is electrically connected to the scan wiring and the first data wiring. The second active component is located in the second pixel region and is electrically connected to the scan wiring and the second data wiring. The first pixel electrode and the second pixel electrode are respectively located in the first pixel region and the second pixel region, and are electrically connected to the first active device and the second active device, respectively, wherein the first pixel electrode And the second pixel electrodes partially overlap the common wiring.
在本發明之一實施例中,第一主動元件以及第二主動元件是以共用配線為中心軸而呈鏡像配置於共用配線的相對兩側。 In one embodiment of the present invention, the first active device and the second active device are mirror-arranged on opposite sides of the common wiring with the common wiring as a central axis.
在本發明之一實施例中,共用配線、第一資料配線以及第二資料配線位於同一膜層。 In an embodiment of the invention, the common wiring, the first data wiring, and the second data wiring are located on the same film layer.
在本發明之一實施例中,上述之畫素結構更包括一第一分支配線以及一第二分支配線,分別位於第一次畫素區以及第二次畫素區內,並且電性連接至共用配線。此外,第一分支配線以及第二分支配線分別繞行第一畫素電極以及第二畫素電極的邊緣,且第一分支配線以及第二分支配線分別與第一畫素電極以及第二畫素電極有部分重疊。 In an embodiment of the present invention, the pixel structure further includes a first branch wiring and a second branch wiring, respectively located in the first pixel region and the second pixel region, and electrically connected to Shared wiring. Further, the first branch wiring and the second branch wiring respectively bypass the edges of the first pixel electrode and the second pixel electrode, and the first branch wiring and the second branch wiring are respectively connected to the first pixel electrode and the second pixel The electrodes have partial overlap.
在本發明之一實施例中,第一分支配線以及第二分支配線是以共用配線為中心軸而呈鏡像配置於共用配線的相對兩側。 In one embodiment of the present invention, the first branch wiring and the second branch wiring are mirror-arranged on opposite sides of the common wiring with the common wiring as a central axis.
在本發明之一實施例中,第一分支配線或第二分支配線是由共用配線向外延伸所形成。 In an embodiment of the invention, the first branch wiring or the second branch wiring is formed by extending outward from the common wiring.
在本發明之一實施例中,第一主動元件或第二主動元件為一薄膜電晶體。 In an embodiment of the invention, the first active component or the second active component is a thin film transistor.
在此另提出一種主動元件陣列基板,主要包括一基板、多條掃描配線、多條成對的資料配線、多條共用配線、多個第一主動元件、多個第二主動元件、多個第一畫素電極以及多個第二畫素電極。掃描配線配置於基板上且實質上相互平行。成對的資料配線配置於該基板上,其中每一對資料配線包括實質上相互平行的一第一資料配線與一第二資料配線,且第一資料配線以及第二資料配線分別與掃描配線相交。基板上由每一對資料配線以及兩相鄰的掃描配線所圍成的區域被定義為一畫素區。共用配線配置於基板上並連接到一共用電壓源,且共用配線實質上相互平行並對應於成對的資料配線。每一共用配線位於所對應的第一資料配線與第二資料配線之間,以將每一畫素區分為一第一次畫素區以及一第二次畫素區,其中第一次畫素區位於第一資料配線與共用配線之間,而第二次畫素區位於第二資料配線與共用配線之間。第一主動元件配置於基板上並分別位於第一次畫素區內,且每一第一主動元件電性連接至所對應的掃描配線以及第一資料配線。第二主動元件 配置於基板上並分別位於第二次畫素區內,且每一第二主動元件電性連接至所對應的掃描配線以及第二資料配線。第一畫素電極分別位於第一次畫素區內,並電性連接至所對應的第一主動元件,其中每一第一畫素電極與所對應的共用配線有部分重疊。第二畫素電極分別位於第二次畫素區內,並電性連接至所對應的第二主動元件,其中每一第二畫素電極與所對應的共用配線有部分重疊。 An active device array substrate is further provided, which mainly includes a substrate, a plurality of scanning wires, a plurality of pairs of data wires, a plurality of shared wires, a plurality of first active components, a plurality of second active components, and a plurality of A pixel electrode and a plurality of second pixel electrodes. The scan lines are disposed on the substrate and are substantially parallel to each other. The pair of data wires are disposed on the substrate, wherein each pair of data wires includes a first data wire and a second data wire that are substantially parallel to each other, and the first data wire and the second data wire respectively intersect the scan wire . A region surrounded by each pair of data wirings and two adjacent scanning wirings on the substrate is defined as a pixel area. The common wiring is disposed on the substrate and connected to a common voltage source, and the common wirings are substantially parallel to each other and correspond to the pair of data wirings. Each of the shared wires is located between the corresponding first data line and the second data line to distinguish each pixel into a first pixel region and a second pixel region, wherein the first pixel is The area is located between the first data line and the shared line, and the second picture area is located between the second data line and the shared line. The first active components are disposed on the substrate and respectively located in the first pixel region, and each of the first active components is electrically connected to the corresponding scan wiring and the first data wiring. Second active component The second active device is electrically connected to the corresponding scan wiring and the second data wiring. The first pixel electrodes are respectively located in the first pixel region, and are electrically connected to the corresponding first active device, wherein each of the first pixel electrodes partially overlaps the corresponding common wiring. The second pixel electrodes are respectively located in the second pixel region, and are electrically connected to the corresponding second active device, wherein each of the second pixel electrodes partially overlaps the corresponding common wiring.
在本發明之一實施例中,每一畫素區內的第一主動元件以及第二主動元件是以所對應的共用配線為中心軸而呈鏡像配置於共用配線的相對兩側。 In an embodiment of the invention, the first active component and the second active component in each pixel region are mirror-imaged on opposite sides of the common wiring with the corresponding common wiring as a central axis.
在本發明之一實施例中,共用配線、第一資料配線以及第二資料配線位於同一膜層。 In an embodiment of the invention, the common wiring, the first data wiring, and the second data wiring are located on the same film layer.
在本發明之一實施例中,上述的主動元件陣列基板更包括多條第一分支配線以及多條第二分支配線。第一分支配線分別位於第一次畫素區內,並且分別電性連接至所對應的共用配線,其中每一第一分支配線繞行所對應的第一畫素電極的邊緣,且第一分支配線與第一畫素電極有部分重疊。此外,第二分支配線分別位於第二次畫素區內,並且分別電性連接至所對應的共用配線,其中每一第二分支配線繞行所對應的第二畫素電極的邊緣,且第二分支配線與第二畫素電極有部分重疊。 In an embodiment of the invention, the active device array substrate further includes a plurality of first branch wires and a plurality of second branch wires. The first branch wires are respectively located in the first pixel region, and are respectively electrically connected to the corresponding common wires, wherein each of the first branch wires bypasses the edge of the first pixel electrode corresponding to the row, and the first branch The wiring partially overlaps the first pixel electrode. In addition, the second branch wires are respectively located in the second pixel region, and are respectively electrically connected to the corresponding common wires, wherein each of the second branch wires bypasses the edge of the second pixel electrode corresponding to the row, and the The two branch wirings partially overlap the second pixel electrodes.
在本發明之一實施例中,每一畫素區內的第一分支配線以及第二分支配線是以所對應的共用配線為中心軸而呈鏡像配置於共用配線的相對兩側。 In one embodiment of the present invention, the first branch wiring and the second branch wiring in each pixel region are mirror-arranged on opposite sides of the common wiring with the corresponding common wiring as a central axis.
在本發明之一實施例中,每一第一分支配線或每一第二分支配線是由所對應的共用配線向外延伸所形成。 In an embodiment of the invention, each of the first branch wirings or each of the second branch wirings is formed by extending outwardly from the corresponding common wiring.
在本發明之一實施例中,每一第一主動元件或每一第二主動元件為一薄膜電晶體。 In an embodiment of the invention, each of the first active elements or each of the second active elements is a thin film transistor.
在此又提出一種顯示面板,主要包括前述之主動元件陣列基板、一對向基板以及一顯示介質層,其中顯示介質層配置於主動元件陣列基板與對向基板之間。 A display panel is further provided, which mainly includes the active device array substrate, the pair of substrates and a display medium layer, wherein the display medium layer is disposed between the active device array substrate and the opposite substrate.
在本發明之一實施例中,對向基板為一彩色濾光基板。 In an embodiment of the invention, the opposite substrate is a color filter substrate.
在本發明之一實施例中,顯示介質層為一液晶層。 In an embodiment of the invention, the display medium layer is a liquid crystal layer.
在此另提出一種顯示裝置,其採用前述之顯示面板並搭配一背光模組而成。背光模組配置於顯示面板旁,以提供一背光源至顯示面板。 A display device is also proposed, which adopts the foregoing display panel and is combined with a backlight module. The backlight module is disposed beside the display panel to provide a backlight to the display panel.
基於上述,本發明所提出的畫素結構在相鄰兩次畫素間形成與資料配線平行的共用配線。此共用配線可與其兩側相鄰畫素的畫素電極分別形成儲存電容,且可作為遮光層,避免兩相鄰次畫素之間的漏光。由於兩個次畫素共用一條共用配線,因此有助於增加畫素的開口率,同時也有助於降低製程中發生對位偏移時所造成的開口率損失。此外,作為遮光層的共用配線因為具有穩定的共用電壓,因此可以降低饋通電壓(Feed-Through Voltage)之變異,避免兩次畫素間的訊號干擾,從而減輕顯示面板的畫面閃爍(flicker)問題。 Based on the above, the pixel structure proposed by the present invention forms a common wiring parallel to the data wiring between adjacent pixels. The common wiring can form a storage capacitor respectively with the pixel electrodes of the adjacent pixels on both sides, and can be used as a light shielding layer to avoid light leakage between two adjacent sub-pixels. Since the two sub-pixels share one common wiring, it helps to increase the aperture ratio of the pixels, and also helps to reduce the aperture loss caused by the alignment offset in the process. In addition, since the common wiring as the light shielding layer has a stable common voltage, the variation of the feed-through voltage can be reduced, and signal interference between the two pixels can be avoided, thereby reducing the flicker of the display panel. problem.
為讓本發明之上述特徵和優點能更明顯易懂,下文特 舉實施例,並配合所附圖式作詳細說明如下。 In order to make the above features and advantages of the present invention more obvious, the following The embodiments are described in detail with reference to the accompanying drawings.
圖3為依據本發明之一實施例的一種主動元件陣列基板的線路佈局。本實施例的主動元件陣列基板可應用於各類型的顯示面板上,例如液晶顯示面板或有機電激發光顯示面板等,以驅動顯示介質,進而顯示畫面。如圖3所示的主動元件陣列基板300,本實施例係在一基板(未繪示)上形成多條掃描配線310、多條成對的資料配線320、多條共用配線330、多個第一主動元件342、多個第二主動元件344、多個第一畫素電極352以及多個第二畫素電極354。此處的基板例如是一玻璃基板或是一石英基板。掃描配線310相互平行,並且與成對的資料配線320相交,以定義出多個畫素區390。此外,共用配線330連接到一共用電壓源Vcom,且共用配線330實質上相互平行並對應於成對的資料配線320。 3 is a circuit layout of an active device array substrate in accordance with an embodiment of the present invention. The active device array substrate of this embodiment can be applied to various types of display panels, such as a liquid crystal display panel or an organic electroluminescent display panel, to drive a display medium to display a picture. The active device array substrate 300 shown in FIG. 3 is formed on a substrate (not shown) by forming a plurality of scan lines 310, a plurality of pairs of data lines 320, a plurality of common lines 330, and a plurality of An active component 342, a plurality of second active components 344, a plurality of first pixel electrodes 352, and a plurality of second pixel electrodes 354. The substrate here is, for example, a glass substrate or a quartz substrate. The scan lines 310 are parallel to each other and intersect the paired data lines 320 to define a plurality of pixel regions 390. Further, the common wiring 330 is connected to a common voltage source Vcom, and the common wirings 330 are substantially parallel to each other and correspond to the paired data wirings 320.
更詳細而言,每一對資料配線320包括實質上相互平行的一第一資料配線322與一第二資料配線324。並且,共用配線330位於所對應的第一資料配線322與第二資料配線324之間,以將每一畫素區390分為一第一次畫素區392以及一第二次畫素區394,其中第一次畫素區392位於第一資料配線322與共用配線330之間,而第二次畫素區394位於第二資料配線324與共用配線330之間。 In more detail, each pair of data wirings 320 includes a first data wiring 322 and a second data wiring 324 that are substantially parallel to each other. Moreover, the common wiring 330 is located between the corresponding first data line 322 and the second data line 324 to divide each pixel area 390 into a first pixel area 392 and a second pixel area 394. The first pixel area 392 is located between the first data line 322 and the common line 330, and the second pixel area 394 is located between the second data line 324 and the common line 330.
第一主動元件342與第二主動元件344分別位於第一次畫素區392與第二次畫素區394內。在本實施例中,第 一主動元件342與第二主動元件344例如分別是一薄膜電晶體。第一主動元件342電性連接至所對應的掃描配線310以及第一資料配線322,而第二主動元件344電性連接至所對應的掃描配線310以及第二資料配線324。此外,第一畫素電極352分別位於第一次畫素區392內,並電性連接至所對應的第一主動元件342,而第二畫素電極354分別位於第二次畫素區394內,並電性連接至所對應的第二主動元件344。另外,第一畫素電極352以及第二畫素電極354會分別與所對應的共用配線330有部分重疊,以形成儲存電容。 The first active component 342 and the second active component 344 are located in the first pixel region 392 and the second pixel region 394, respectively. In this embodiment, the first An active component 342 and a second active component 344 are, for example, a thin film transistor, respectively. The first active component 342 is electrically connected to the corresponding scan wiring 310 and the first data wiring 322 , and the second active component 344 is electrically connected to the corresponding scan wiring 310 and the second data wiring 324 . In addition, the first pixel electrodes 352 are respectively located in the first pixel region 392, and are electrically connected to the corresponding first active device 342, and the second pixel electrodes 354 are respectively located in the second pixel region 394. And electrically connected to the corresponding second active component 344. In addition, the first pixel electrode 352 and the second pixel electrode 354 partially overlap the corresponding common wiring 330 to form a storage capacitor.
為更詳細說明本發明之特點,圖4進一步繪示圖3之主動元件陣列基板中的畫素結構。如圖3與4所示,本實施例是將畫素區390分別兩個次畫素區392與394,並在該兩個次畫素區392與394內分別形成畫素結構。所述兩個次畫素結構分別包括掃描配線310、資料配線320、主動元件342、344以及畫素電極352、354,並且共用同一條共用配線330。共用配線330的材質可為不透光的金屬,其可作為遮光層,以避免兩相鄰次畫素區392、394之間的漏光。如此,將有助於增加畫素的開口率。 To further illustrate the features of the present invention, FIG. 4 further illustrates the pixel structure in the active device array substrate of FIG. As shown in FIGS. 3 and 4, in the present embodiment, the pixel region 390 has two sub-pixel regions 392 and 394, respectively, and a pixel structure is formed in the two sub-pixel regions 392 and 394, respectively. The two sub-pixel structures respectively include scan wiring 310, data wiring 320, active elements 342, 344, and pixel electrodes 352, 354, and share the same common wiring 330. The material of the common wiring 330 may be an opaque metal, which can serve as a light shielding layer to avoid light leakage between the two adjacent sub-pixel regions 392 and 394. In this way, it will help to increase the aperture ratio of the pixels.
在本實施例中,共用配線330較佳是與第一資料配線322以及第二資料配線324同時製作,即共用配線330、第一資料配線322以及第二資料配線324可位於同一膜層,例如是對同一個金屬層圖案化所形成者。 In this embodiment, the common wiring 330 is preferably formed simultaneously with the first data wiring 322 and the second data wiring 324, that is, the common wiring 330, the first data wiring 322, and the second data wiring 324 may be located on the same film layer, for example, It is formed by the patterning of the same metal layer.
此外,共用配線330會與其兩側的畫素電極352與354 分別形成儲存電容。並且,由於共用配線330具有穩定的共用電壓Vcom,因此可以有效降低饋通電壓之變異,避免兩畫素間的訊號干擾,從而減輕顯示面板的畫面閃爍問題。 In addition, the common wiring 330 will have pixel electrodes 352 and 354 on both sides thereof. The storage capacitors are formed separately. Moreover, since the common wiring 330 has a stable common voltage Vcom, the variation of the feedthrough voltage can be effectively reduced, and signal interference between the two pixels can be avoided, thereby reducing the flickering problem of the display panel.
在本實施例中,位於第一次畫素區392以及第二次畫素區394內的畫素結構是以共用配線330為中心軸而呈鏡像配置。更詳細而言,第一主動元件342以及第二主動元件344、第一資料配線322以及第二資料配線324都是位於共用配線330的相對兩側,並以共用配線330為中心軸而呈鏡像配置。 In the present embodiment, the pixel structure located in the first pixel region 392 and the second pixel region 394 is mirror-imaged with the common wiring 330 as a central axis. In more detail, the first active component 342 and the second active component 344, the first data wiring 322, and the second data wiring 324 are both located on opposite sides of the common wiring 330, and are mirrored with the common wiring 330 as a central axis. Configuration.
相較於圖1所繪示的習知的畫素結構,本實施例的第一次畫素區392以及第二次畫素區394係共用一條共用配線330,當在製程中發生對位偏移時,將有助於降低此對位偏移時所造成的開口率損失。更詳細而言,請參照圖5繪示的圖4之畫素結構沿B-B’線的剖面圖。在製作液晶顯示面板的過程中,若黑矩陣380與畫素結構之間產生對位偏移,將使得黑矩陣380與畫素結構之間產生位移S。然而,值得注意的是,由於本實施例是將兩個畫素結構整合在一起,共用同一條共用配線330做為遮光層,因此共用配線330上不需要形成黑矩陣。如此一來,對位偏移僅會對每兩個成對的畫素結構造成一個位移S所對應的開口率損失。換言之,與圖1所繪示的畫素結構將比,本實施例的畫素結構在面對相同的對位偏移時,所造成的開口率損失僅是習知的畫素結構的一半。 Compared with the conventional pixel structure shown in FIG. 1, the first pixel region 392 and the second pixel region 394 of the present embodiment share a common wiring 330, and a registration bias occurs in the process. When moving, it will help to reduce the loss of aperture ratio caused by this alignment offset. More specifically, please refer to FIG. 5 for a cross-sectional view of the pixel structure of FIG. 4 taken along line B-B'. In the process of fabricating the liquid crystal display panel, if a registration offset occurs between the black matrix 380 and the pixel structure, a displacement S is generated between the black matrix 380 and the pixel structure. However, it is worth noting that since the present embodiment is to integrate the two pixel structures together and share the same common wiring 330 as a light shielding layer, it is not necessary to form a black matrix on the common wiring 330. In this way, the alignment offset only causes an aperture ratio loss corresponding to a displacement S for every two pairs of pixel structures. In other words, compared with the pixel structure illustrated in FIG. 1, the pixel loss ratio of the pixel structure of the present embodiment is half of that of the conventional pixel structure when facing the same alignment offset.
另一方面,請再參考圖4。為了增加每一次畫素區內的儲存電容,本實施例更在每一共用配線330的兩側配置一第一分支配線332以及一第二分支配線334。第一分支配線332與第二分支配線334分別位於第一次畫素區392與第二次畫素區394內,並且電性連接至共用配線330。在本實施例中,第一分支配線332與第二分支配線334例如是由共用配線330向外延伸所形成。並且,第一分支配線332以及第二分支配線334是以所對應的共用配線330為中心軸而呈鏡像配置於共用配線330的相對兩側。 On the other hand, please refer to Figure 4 again. In order to increase the storage capacitance in each pixel region, a first branch wiring 332 and a second branch wiring 334 are disposed on both sides of each common wiring 330. The first branch wiring 332 and the second branch wiring 334 are respectively located in the first pixel region 392 and the second pixel region 394, and are electrically connected to the common wiring 330. In the present embodiment, the first branch wiring 332 and the second branch wiring 334 are formed, for example, by extending outward from the common wiring 330. Further, the first branch wiring 332 and the second branch wiring 334 are mirror-arranged on opposite sides of the common wiring 330 with the corresponding common wiring 330 as a central axis.
換言之,第一分支配線332、第二分支配線334以及共用配線330是位於同一膜層,例如是對同一個金屬層圖案化所形成者。此外,第一分支配線332繞行所對應的第一畫素電極392的邊緣,且第一分支配線332與第一畫素電極352有部分重疊,以形成儲存電容。第二分支配線334繞行所對應的第二畫素電極354的邊緣,且第二分支配線334與第二畫素電極354有部分重疊,以形成儲存電容。 In other words, the first branch wiring 332, the second branch wiring 334, and the common wiring 330 are located on the same film layer, for example, formed by patterning the same metal layer. Further, the first branch wiring 332 bypasses the edge of the corresponding first pixel electrode 392, and the first branch wiring 332 partially overlaps the first pixel electrode 352 to form a storage capacitor. The second branch wiring 334 bypasses the edge of the corresponding second pixel electrode 354, and the second branch wiring 334 partially overlaps with the second pixel electrode 354 to form a storage capacitor.
當然,本發明所揭露的畫素結構,其分支配線或其他元件的細部結構並非限於前述實施例所述。在可能的情況下,可依據實際所需的儲存電容或遮光效果,同時考量整體畫素結構的設計,來改變分支配線或其他元件的形狀。以下再列舉多個實施例來說明分支配線可能的變化。當然該些實施例僅是舉例之用,並非用以限定本發明。 Of course, the pixel structure disclosed in the present invention, the detailed structure of the branch wiring or other components is not limited to the foregoing embodiment. Where possible, the shape of the branch wiring or other components can be changed depending on the actual required storage capacitance or shading effect, while considering the design of the overall pixel structure. A number of embodiments are further enumerated below to illustrate possible variations in branch wiring. The embodiments are for illustrative purposes only and are not intended to limit the invention.
圖6-8分別繪示依據本發明之不同實施例的多種畫素結構。圖6-8的畫素結構明顯與前述實施例的畫素結構具 有不同形狀的分支配線。針對類似的元件,將採用相同的元件標號,而其他相同且未敘及的部份,可參照前述實施例,將不再進一步說明。在圖6-8中,第一分支配線332以及第二分支配線334分別是呈直線形、T形或L型,並分別呈鏡像配置在共用配線330的相對兩側。此外,隨著分支配線形狀的改變,如圖8所示的第一主動元件342與第二主動元件344的位置也可以移至共用配線330旁。 6-8 illustrate various pixel structures, respectively, in accordance with various embodiments of the present invention. The pixel structure of Figures 6-8 is significantly different from the pixel structure of the previous embodiment. There are branch wires of different shapes. For the similar elements, the same reference numerals will be used, and other identical and undisclosed parts may be referred to the foregoing embodiments and will not be further described. In FIGS. 6-8, the first branch wiring 332 and the second branch wiring 334 are respectively linear, T-shaped or L-shaped, and are respectively disposed on opposite sides of the common wiring 330 in a mirror image. Further, as the shape of the branch wiring changes, the positions of the first active element 342 and the second active element 344 as shown in FIG. 8 may also be moved to the side of the common wiring 330.
圖9為本發明之一實施例的一種顯示面板的示意圖。請參照圖9,本實施例的顯示面板900包括一主動元件陣列基板910、一對向基板920以及配置於主動元件陣列基板910以及對向基板920之間的顯示介質層930。此處的主動元件陣列基板910可以是本發明前述多個實施例所繪示的或是其他未繪示的主動元件陣列基板。對向基板920例如是具有黑矩陣980的一彩色濾光基板。當然,在可能的情況下,對向基板920也可以是僅具有共用電極的玻璃基板或石英基板,其上可製作黑矩陣,而對應的主動元件陣列基板910上則可能形成有彩色濾光層。在本實施例中,顯示介質層930例如是一液晶層,而顯示面板900為一液晶顯示面板。當然,在其他實施例中,顯示介質層930也可能是電激發光(electroluminescent)材料,則顯示面板900為電激發光顯示面板,其中電激發光材料例如是有機材料、無機材料或其組合。 FIG. 9 is a schematic diagram of a display panel according to an embodiment of the present invention. Referring to FIG. 9 , the display panel 900 of the present embodiment includes an active device array substrate 910 , a pair of substrates 920 , and a display medium layer 930 disposed between the active device array substrate 910 and the opposite substrate 920 . The active device array substrate 910 herein may be the active device array substrate shown in the foregoing various embodiments of the present invention or other not shown. The opposite substrate 920 is, for example, a color filter substrate having a black matrix 980. Of course, the opposite substrate 920 may be a glass substrate or a quartz substrate having only a common electrode, and a black matrix may be formed thereon, and a color filter layer may be formed on the corresponding active device array substrate 910. . In the embodiment, the display medium layer 930 is, for example, a liquid crystal layer, and the display panel 900 is a liquid crystal display panel. Of course, in other embodiments, the display medium layer 930 may also be an electroluminescent material, and the display panel 900 is an electroluminescent display panel, wherein the electroluminescent material is, for example, an organic material, an inorganic material, or a combination thereof.
應用上述之顯示面板,圖10更繪示依據本發明之一實施例的一種顯示裝置。以液晶顯示裝置為例,由於液晶 顯示面板1010無法自發光,因此液晶顯示面板1010旁會配置一背光模組1020。背光模組1020可提供背光源L至液晶顯示面板1010,以使液晶顯示面板1010顯示畫面。 Applying the above display panel, FIG. 10 further illustrates a display device according to an embodiment of the present invention. Taking a liquid crystal display device as an example, due to liquid crystal The display panel 1010 is not self-illuminating, so a backlight module 1020 is disposed next to the liquid crystal display panel 1010. The backlight module 1020 can provide the backlight L to the liquid crystal display panel 1010 to cause the liquid crystal display panel 1010 to display a picture.
綜上所述,本發明藉由上述畫素結構的設計,可以藉由共用配線來形成儲存電容並同時提供遮光層的效果。相鄰兩次畫素之間係共用一條共用配線,可大幅增加畫素的開口率,同時可降低製程中發生對位偏移時所造成的開口率損失,提升製程良率。此外,共用配線上具有穩定的共用電壓,可降低饋通電壓之變異,避免兩次畫素間的訊號干擾,從而減輕顯示面板的畫面閃爍問題,以提供較佳的顯示品質。 In summary, according to the design of the above pixel structure, the present invention can form a storage capacitor by sharing wiring and simultaneously provide an effect of a light shielding layer. A common wiring is shared between adjacent pixels, which can greatly increase the aperture ratio of the pixels, and at the same time reduce the aperture loss caused by the alignment offset in the process and improve the process yield. In addition, the shared wiring has a stable common voltage, which can reduce the variation of the feedthrough voltage and avoid signal interference between the two pixels, thereby reducing the flickering problem of the display panel to provide better display quality.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,故本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
100‧‧‧主動元件陣列 100‧‧‧Active component array
110‧‧‧掃描配線 110‧‧‧Scan wiring
120‧‧‧資料配線 120‧‧‧Data wiring
130‧‧‧共用配線 130‧‧‧Shared wiring
140‧‧‧主動元件 140‧‧‧Active components
150‧‧‧畫素電極 150‧‧‧pixel electrodes
180‧‧‧黑矩陣 180‧‧‧Black matrix
190‧‧‧畫素區 190‧‧‧Photo District
300‧‧‧主動元件陣列基板 300‧‧‧Active component array substrate
310‧‧‧掃描配線 310‧‧‧Scan wiring
320‧‧‧成對的資料配線 320‧‧‧ Paired data wiring
322‧‧‧第一資料配線 322‧‧‧First data wiring
324‧‧‧第二資料配線 324‧‧‧Second data wiring
330‧‧‧共用配線 330‧‧‧Shared wiring
332‧‧‧第一分支配線 332‧‧‧First branch wiring
334‧‧‧第二分支配線 334‧‧‧Second branch wiring
342‧‧‧第一主動元件 342‧‧‧First active component
344‧‧‧第二主動元件 344‧‧‧Second active component
352‧‧‧第一畫素電極 352‧‧‧ first pixel electrode
354‧‧‧第二畫素電極 354‧‧‧Second pixel electrode
380‧‧‧黑矩陣 380‧‧‧Black matrix
390‧‧‧畫素區 390‧‧‧Photo area
392‧‧‧第一次畫素區 392‧‧‧The first picture area
394‧‧‧第二次畫素區 394‧‧‧The second picture area
900‧‧‧顯示面板 900‧‧‧ display panel
910‧‧‧主動元件陣列基板 910‧‧‧Active component array substrate
920‧‧‧對向基板 920‧‧‧ opposite substrate
930‧‧‧顯示介質層 930‧‧‧ Display media layer
980‧‧‧黑矩陣 980‧‧‧Black matrix
1010‧‧‧液晶顯示面板 1010‧‧‧LCD panel
1020‧‧‧背光模組 1020‧‧‧Backlight module
A-A’、B-B’‧‧‧剖面線 A-A’, B-B’‧‧‧ hatching
L‧‧‧背光源 L‧‧‧Backlight
S‧‧‧位移 S‧‧‧ displacement
Vcom‧‧‧共用電壓源 Vcom‧‧‧shared voltage source
圖1為習知一種主動元件陣列的上視圖。 1 is a top view of a conventional array of active components.
圖2為圖1之主動元件陣列基板沿A-A’線的剖面圖。 Figure 2 is a cross-sectional view of the active device array substrate of Figure 1 taken along line A-A'.
圖3為依據本發明之一實施例的一種主動元件陣列基板的線路佈局。 3 is a circuit layout of an active device array substrate in accordance with an embodiment of the present invention.
圖4進一步繪示圖3之主動元件陣列基板中的畫素結構。 FIG. 4 further illustrates a pixel structure in the active device array substrate of FIG. 3.
圖5繪示圖4之畫素結構沿B-B’線的剖面圖。 Figure 5 is a cross-sectional view of the pixel structure of Figure 4 taken along line B-B'.
圖6-8分別繪示依據本發明之不同實施例的多種畫素 結構。 6-8 illustrate various pixels in accordance with various embodiments of the present invention, respectively. structure.
圖9為本發明之一實施例的一種顯示面板的示意圖。 FIG. 9 is a schematic diagram of a display panel according to an embodiment of the present invention.
圖10繪示依據本發明之一實施例的一種顯示裝置。 FIG. 10 illustrates a display device in accordance with an embodiment of the present invention.
300‧‧‧主動元件陣列基板 300‧‧‧Active component array substrate
310‧‧‧掃描配線 310‧‧‧Scan wiring
320‧‧‧成對的資料配線 320‧‧‧ Paired data wiring
322‧‧‧第一資料配線 322‧‧‧First data wiring
324‧‧‧第二資料配線 324‧‧‧Second data wiring
330‧‧‧共用配線 330‧‧‧Shared wiring
342‧‧‧第一主動元件 342‧‧‧First active component
344‧‧‧第二主動元件 344‧‧‧Second active component
352‧‧‧第一畫素電極 352‧‧‧ first pixel electrode
354‧‧‧第二畫素電極 354‧‧‧Second pixel electrode
390‧‧‧畫素區 390‧‧‧Photo area
392‧‧‧第一次畫素區 392‧‧‧The first picture area
394‧‧‧第二次畫素區 394‧‧‧The second picture area
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TW98110230A TWI406072B (en) | 2009-03-27 | 2009-03-27 | Pixel structure, active device array, display panel, and display apparatus |
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TWI406072B true TWI406072B (en) | 2013-08-21 |
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TW201215979A (en) * | 2010-10-15 | 2012-04-16 | Chunghwa Picture Tubes Ltd | Liquid crystal display |
KR102374537B1 (en) * | 2015-08-21 | 2022-03-15 | 삼성디스플레이 주식회사 | Display device |
TWI664474B (en) * | 2018-04-18 | 2019-07-01 | 友達光電股份有限公司 | Active component array substrate |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5408252A (en) * | 1991-10-05 | 1995-04-18 | Fujitsu Limited | Active matrix-type display device having a reduced number of data bus lines and generating no shift voltage |
TW200628948A (en) * | 2005-01-03 | 2006-08-16 | Samsung Electronics Co Ltd | Array substrate and display panel having the same |
CN101271904A (en) * | 2008-05-06 | 2008-09-24 | 友达光电股份有限公司 | Array substrate, LCD panel, optoelectronic device and its driving/production method |
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2009
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5408252A (en) * | 1991-10-05 | 1995-04-18 | Fujitsu Limited | Active matrix-type display device having a reduced number of data bus lines and generating no shift voltage |
TW200628948A (en) * | 2005-01-03 | 2006-08-16 | Samsung Electronics Co Ltd | Array substrate and display panel having the same |
CN101271904A (en) * | 2008-05-06 | 2008-09-24 | 友达光电股份有限公司 | Array substrate, LCD panel, optoelectronic device and its driving/production method |
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