TWI406072B - Pixel structure, active device array, display panel, and display apparatus - Google Patents

Abstract

A pixel structure provided with a common line formed between two adjacent sub-pixels and parallel to data lines of the same. The common line forms storage capacitors with pixel electrodes of the two adjacent sub-pixels and serves as a light-shielding layer for preventing light leakage. Since the two sub-pixels share the same common line, the aperture ratio of pixel can be improved, while the loss of aperture ratio cause by misalignment in manufacturing process can be reduced. Furthermore, the common line serving as the light-shielding layer carries a stable common voltage which reduces the variety of feed-through voltage and the interference of signal between the two sub-pixels, and therefore alleviates flicker of frames in display. An active device array, a display panel, and a display apparatus applying the pixel structure are also provided.

Description

Pixel structure, active device array substrate, display panel, and display device Set

The present invention relates to a display panel, and more particularly to a pixel structure design of a display panel.

Today's social multimedia technology is quite developed, and most of them benefit from the advancement of semiconductor components and display devices. As far as the display is concerned, a liquid crystal display panel having superior characteristics such as high image quality, good space utilization efficiency, low power consumption, and no radiation has gradually become the mainstream of the market. Generally, a liquid crystal display panel (LCD panel) is mainly composed of an active device array substrate, a color filter substrate, and a liquid crystal layer between the two substrates.

1 is a top view of a conventional array of active components. As shown in FIG. 1, the active device array 100 includes a plurality of scan lines 110, a plurality of data lines 120, a common line 130 spanning the data lines 120, a plurality of active elements 140, and a plurality of pixel electrodes 150. The scan wiring 110 intersects the data wiring 120 and defines a plurality of pixel regions 190. The active element 140 and the pixel electrode 150 are respectively located in the corresponding pixel area 190, wherein the active element 140 is respectively connected to the corresponding scan line 110 and the data line 120, and the active element 140 and the picture in the same pixel area 190 The element electrodes 150 are electrically connected to each other. It can be seen from the architecture illustrated in FIG. 1 that the pixel structure of the active device array 100 is repeatedly arranged, that is, the same elements in the adjacent two pixel regions 190 are separated by one pixel width.

In addition, in order to overcome the unexpected light leakage problem, it is customary to make a black matrix on the color filter substrate or the active device array substrate, thereby shielding the main An area on the moving element array substrate where light may leak.

2 is a cross-sectional view of the active device array substrate of FIG. 1 taken along line A-A', and FIG. 2 further illustrates a black matrix corresponding to the active device array substrate. As shown in FIG. 2, in the process of fabricating the liquid crystal display panel, if a misalignment occurs between the black matrix 180 and the pixel structure, a displacement S is generated between the black matrix 180 and the pixel structure. An aperture ratio loss corresponding to this displacement S is caused in each pixel region.

The invention relates to a pixel structure, which can reduce the loss of aperture ratio caused by the alignment offset during the manufacturing process of the display panel, thereby contributing to the improvement of the process yield.

The invention further relates to an active device array substrate, which can effectively avoid the loss of aperture ratio caused by the alignment offset during the manufacturing process of the display panel, thereby contributing to the improvement of the process yield.

The invention further relates to a display panel using the foregoing active device array substrate, which can effectively avoid the loss of aperture ratio due to process alignment offset, and thus has better process yield.

The present invention is further directed to a display device to which the aforementioned display panel is applied.

To specifically describe the contents of the present invention, a pixel structure is proposed herein that is located in a pixel region of a display panel. The pixel structure includes a scan line, a first data line, a second data line, a common line, a first active component, a second active component, a first pixel electrode, and a second pixel electrode. . The first data wiring and the second data wiring are respectively located on opposite sides of the pixel area, and the first data wiring and the second data wiring They are substantially parallel to each other and intersect with the scanning wiring. The common wiring is connected to a common voltage source, and the common wiring is substantially parallel to the first data wiring and the second data wiring, and is located between the first data wiring and the second data wiring to distinguish the pixels into a first The sub-pixel area and a second pixel area, wherein the first pixel area is located between the first data line and the shared line, and the second pixel area is located between the second data line and the shared line. The first active component is located in the first pixel region and is electrically connected to the scan wiring and the first data wiring. The second active component is located in the second pixel region and is electrically connected to the scan wiring and the second data wiring. The first pixel electrode and the second pixel electrode are respectively located in the first pixel region and the second pixel region, and are electrically connected to the first active device and the second active device, respectively, wherein the first pixel electrode And the second pixel electrodes partially overlap the common wiring.

In one embodiment of the present invention, the first active device and the second active device are mirror-arranged on opposite sides of the common wiring with the common wiring as a central axis.

In an embodiment of the invention, the common wiring, the first data wiring, and the second data wiring are located on the same film layer.

In an embodiment of the present invention, the pixel structure further includes a first branch wiring and a second branch wiring, respectively located in the first pixel region and the second pixel region, and electrically connected to Shared wiring. Further, the first branch wiring and the second branch wiring respectively bypass the edges of the first pixel electrode and the second pixel electrode, and the first branch wiring and the second branch wiring are respectively connected to the first pixel electrode and the second pixel The electrodes have partial overlap.

In one embodiment of the present invention, the first branch wiring and the second branch wiring are mirror-arranged on opposite sides of the common wiring with the common wiring as a central axis.

In an embodiment of the invention, the first branch wiring or the second branch wiring is formed by extending outward from the common wiring.

In an embodiment of the invention, the first active component or the second active component is a thin film transistor.

An active device array substrate is further provided, which mainly includes a substrate, a plurality of scanning wires, a plurality of pairs of data wires, a plurality of shared wires, a plurality of first active components, a plurality of second active components, and a plurality of A pixel electrode and a plurality of second pixel electrodes. The scan lines are disposed on the substrate and are substantially parallel to each other. The pair of data wires are disposed on the substrate, wherein each pair of data wires includes a first data wire and a second data wire that are substantially parallel to each other, and the first data wire and the second data wire respectively intersect the scan wire . A region surrounded by each pair of data wirings and two adjacent scanning wirings on the substrate is defined as a pixel area. The common wiring is disposed on the substrate and connected to a common voltage source, and the common wirings are substantially parallel to each other and correspond to the pair of data wirings. Each of the shared wires is located between the corresponding first data line and the second data line to distinguish each pixel into a first pixel region and a second pixel region, wherein the first pixel is The area is located between the first data line and the shared line, and the second picture area is located between the second data line and the shared line. The first active components are disposed on the substrate and respectively located in the first pixel region, and each of the first active components is electrically connected to the corresponding scan wiring and the first data wiring. Second active component The second active device is electrically connected to the corresponding scan wiring and the second data wiring. The first pixel electrodes are respectively located in the first pixel region, and are electrically connected to the corresponding first active device, wherein each of the first pixel electrodes partially overlaps the corresponding common wiring. The second pixel electrodes are respectively located in the second pixel region, and are electrically connected to the corresponding second active device, wherein each of the second pixel electrodes partially overlaps the corresponding common wiring.

In an embodiment of the invention, the first active component and the second active component in each pixel region are mirror-imaged on opposite sides of the common wiring with the corresponding common wiring as a central axis.

In an embodiment of the invention, the common wiring, the first data wiring, and the second data wiring are located on the same film layer.

In an embodiment of the invention, the active device array substrate further includes a plurality of first branch wires and a plurality of second branch wires. The first branch wires are respectively located in the first pixel region, and are respectively electrically connected to the corresponding common wires, wherein each of the first branch wires bypasses the edge of the first pixel electrode corresponding to the row, and the first branch The wiring partially overlaps the first pixel electrode. In addition, the second branch wires are respectively located in the second pixel region, and are respectively electrically connected to the corresponding common wires, wherein each of the second branch wires bypasses the edge of the second pixel electrode corresponding to the row, and the The two branch wirings partially overlap the second pixel electrodes.

In one embodiment of the present invention, the first branch wiring and the second branch wiring in each pixel region are mirror-arranged on opposite sides of the common wiring with the corresponding common wiring as a central axis.

In an embodiment of the invention, each of the first branch wirings or each of the second branch wirings is formed by extending outwardly from the corresponding common wiring.

In an embodiment of the invention, each of the first active elements or each of the second active elements is a thin film transistor.

A display panel is further provided, which mainly includes the active device array substrate, the pair of substrates and a display medium layer, wherein the display medium layer is disposed between the active device array substrate and the opposite substrate.

In an embodiment of the invention, the opposite substrate is a color filter substrate.

In an embodiment of the invention, the display medium layer is a liquid crystal layer.

A display device is also proposed, which adopts the foregoing display panel and is combined with a backlight module. The backlight module is disposed beside the display panel to provide a backlight to the display panel.

Based on the above, the pixel structure proposed by the present invention forms a common wiring parallel to the data wiring between adjacent pixels. The common wiring can form a storage capacitor respectively with the pixel electrodes of the adjacent pixels on both sides, and can be used as a light shielding layer to avoid light leakage between two adjacent sub-pixels. Since the two sub-pixels share one common wiring, it helps to increase the aperture ratio of the pixels, and also helps to reduce the aperture loss caused by the alignment offset in the process. In addition, since the common wiring as the light shielding layer has a stable common voltage, the variation of the feed-through voltage can be reduced, and signal interference between the two pixels can be avoided, thereby reducing the flicker of the display panel. problem.

In order to make the above features and advantages of the present invention more obvious, the following The embodiments are described in detail with reference to the accompanying drawings.

3 is a circuit layout of an active device array substrate in accordance with an embodiment of the present invention. The active device array substrate of this embodiment can be applied to various types of display panels, such as a liquid crystal display panel or an organic electroluminescent display panel, to drive a display medium to display a picture. The active device array substrate 300 shown in FIG. 3 is formed on a substrate (not shown) by forming a plurality of scan lines 310, a plurality of pairs of data lines 320, a plurality of common lines 330, and a plurality of An active component 342, a plurality of second active components 344, a plurality of first pixel electrodes 352, and a plurality of second pixel electrodes 354. The substrate here is, for example, a glass substrate or a quartz substrate. The scan lines 310 are parallel to each other and intersect the paired data lines 320 to define a plurality of pixel regions 390. Further, the common wiring 330 is connected to a common voltage source Vcom, and the common wirings 330 are substantially parallel to each other and correspond to the paired data wirings 320.

In more detail, each pair of data wirings 320 includes a first data wiring 322 and a second data wiring 324 that are substantially parallel to each other. Moreover, the common wiring 330 is located between the corresponding first data line 322 and the second data line 324 to divide each pixel area 390 into a first pixel area 392 and a second pixel area 394. The first pixel area 392 is located between the first data line 322 and the common line 330, and the second pixel area 394 is located between the second data line 324 and the common line 330.

The first active component 342 and the second active component 344 are located in the first pixel region 392 and the second pixel region 394, respectively. In this embodiment, the first An active component 342 and a second active component 344 are, for example, a thin film transistor, respectively. The first active component 342 is electrically connected to the corresponding scan wiring 310 and the first data wiring 322 , and the second active component 344 is electrically connected to the corresponding scan wiring 310 and the second data wiring 324 . In addition, the first pixel electrodes 352 are respectively located in the first pixel region 392, and are electrically connected to the corresponding first active device 342, and the second pixel electrodes 354 are respectively located in the second pixel region 394. And electrically connected to the corresponding second active component 344. In addition, the first pixel electrode 352 and the second pixel electrode 354 partially overlap the corresponding common wiring 330 to form a storage capacitor.

To further illustrate the features of the present invention, FIG. 4 further illustrates the pixel structure in the active device array substrate of FIG. As shown in FIGS. 3 and 4, in the present embodiment, the pixel region 390 has two sub-pixel regions 392 and 394, respectively, and a pixel structure is formed in the two sub-pixel regions 392 and 394, respectively. The two sub-pixel structures respectively include scan wiring 310, data wiring 320, active elements 342, 344, and pixel electrodes 352, 354, and share the same common wiring 330. The material of the common wiring 330 may be an opaque metal, which can serve as a light shielding layer to avoid light leakage between the two adjacent sub-pixel regions 392 and 394. In this way, it will help to increase the aperture ratio of the pixels.

In this embodiment, the common wiring 330 is preferably formed simultaneously with the first data wiring 322 and the second data wiring 324, that is, the common wiring 330, the first data wiring 322, and the second data wiring 324 may be located on the same film layer, for example, It is formed by the patterning of the same metal layer.

In addition, the common wiring 330 will have pixel electrodes 352 and 354 on both sides thereof. The storage capacitors are formed separately. Moreover, since the common wiring 330 has a stable common voltage Vcom, the variation of the feedthrough voltage can be effectively reduced, and signal interference between the two pixels can be avoided, thereby reducing the flickering problem of the display panel.

In the present embodiment, the pixel structure located in the first pixel region 392 and the second pixel region 394 is mirror-imaged with the common wiring 330 as a central axis. In more detail, the first active component 342 and the second active component 344, the first data wiring 322, and the second data wiring 324 are both located on opposite sides of the common wiring 330, and are mirrored with the common wiring 330 as a central axis. Configuration.

Compared with the conventional pixel structure shown in FIG. 1, the first pixel region 392 and the second pixel region 394 of the present embodiment share a common wiring 330, and a registration bias occurs in the process. When moving, it will help to reduce the loss of aperture ratio caused by this alignment offset. More specifically, please refer to FIG. 5 for a cross-sectional view of the pixel structure of FIG. 4 taken along line B-B'. In the process of fabricating the liquid crystal display panel, if a registration offset occurs between the black matrix 380 and the pixel structure, a displacement S is generated between the black matrix 380 and the pixel structure. However, it is worth noting that since the present embodiment is to integrate the two pixel structures together and share the same common wiring 330 as a light shielding layer, it is not necessary to form a black matrix on the common wiring 330. In this way, the alignment offset only causes an aperture ratio loss corresponding to a displacement S for every two pairs of pixel structures. In other words, compared with the pixel structure illustrated in FIG. 1, the pixel loss ratio of the pixel structure of the present embodiment is half of that of the conventional pixel structure when facing the same alignment offset.

On the other hand, please refer to Figure 4 again. In order to increase the storage capacitance in each pixel region, a first branch wiring 332 and a second branch wiring 334 are disposed on both sides of each common wiring 330. The first branch wiring 332 and the second branch wiring 334 are respectively located in the first pixel region 392 and the second pixel region 394, and are electrically connected to the common wiring 330. In the present embodiment, the first branch wiring 332 and the second branch wiring 334 are formed, for example, by extending outward from the common wiring 330. Further, the first branch wiring 332 and the second branch wiring 334 are mirror-arranged on opposite sides of the common wiring 330 with the corresponding common wiring 330 as a central axis.

In other words, the first branch wiring 332, the second branch wiring 334, and the common wiring 330 are located on the same film layer, for example, formed by patterning the same metal layer. Further, the first branch wiring 332 bypasses the edge of the corresponding first pixel electrode 392, and the first branch wiring 332 partially overlaps the first pixel electrode 352 to form a storage capacitor. The second branch wiring 334 bypasses the edge of the corresponding second pixel electrode 354, and the second branch wiring 334 partially overlaps with the second pixel electrode 354 to form a storage capacitor.

Of course, the pixel structure disclosed in the present invention, the detailed structure of the branch wiring or other components is not limited to the foregoing embodiment. Where possible, the shape of the branch wiring or other components can be changed depending on the actual required storage capacitance or shading effect, while considering the design of the overall pixel structure. A number of embodiments are further enumerated below to illustrate possible variations in branch wiring. The embodiments are for illustrative purposes only and are not intended to limit the invention.

6-8 illustrate various pixel structures, respectively, in accordance with various embodiments of the present invention. The pixel structure of Figures 6-8 is significantly different from the pixel structure of the previous embodiment. There are branch wires of different shapes. For the similar elements, the same reference numerals will be used, and other identical and undisclosed parts may be referred to the foregoing embodiments and will not be further described. In FIGS. 6-8, the first branch wiring 332 and the second branch wiring 334 are respectively linear, T-shaped or L-shaped, and are respectively disposed on opposite sides of the common wiring 330 in a mirror image. Further, as the shape of the branch wiring changes, the positions of the first active element 342 and the second active element 344 as shown in FIG. 8 may also be moved to the side of the common wiring 330.

FIG. 9 is a schematic diagram of a display panel according to an embodiment of the present invention. Referring to FIG. 9 , the display panel 900 of the present embodiment includes an active device array substrate 910 , a pair of substrates 920 , and a display medium layer 930 disposed between the active device array substrate 910 and the opposite substrate 920 . The active device array substrate 910 herein may be the active device array substrate shown in the foregoing various embodiments of the present invention or other not shown. The opposite substrate 920 is, for example, a color filter substrate having a black matrix 980. Of course, the opposite substrate 920 may be a glass substrate or a quartz substrate having only a common electrode, and a black matrix may be formed thereon, and a color filter layer may be formed on the corresponding active device array substrate 910. . In the embodiment, the display medium layer 930 is, for example, a liquid crystal layer, and the display panel 900 is a liquid crystal display panel. Of course, in other embodiments, the display medium layer 930 may also be an electroluminescent material, and the display panel 900 is an electroluminescent display panel, wherein the electroluminescent material is, for example, an organic material, an inorganic material, or a combination thereof.

Applying the above display panel, FIG. 10 further illustrates a display device according to an embodiment of the present invention. Taking a liquid crystal display device as an example, due to liquid crystal The display panel 1010 is not self-illuminating, so a backlight module 1020 is disposed next to the liquid crystal display panel 1010. The backlight module 1020 can provide the backlight L to the liquid crystal display panel 1010 to cause the liquid crystal display panel 1010 to display a picture.

In summary, according to the design of the above pixel structure, the present invention can form a storage capacitor by sharing wiring and simultaneously provide an effect of a light shielding layer. A common wiring is shared between adjacent pixels, which can greatly increase the aperture ratio of the pixels, and at the same time reduce the aperture loss caused by the alignment offset in the process and improve the process yield. In addition, the shared wiring has a stable common voltage, which can reduce the variation of the feedthrough voltage and avoid signal interference between the two pixels, thereby reducing the flickering problem of the display panel to provide better display quality.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Active component array

110‧‧‧Scan wiring

120‧‧‧Data wiring

130‧‧‧Shared wiring

140‧‧‧Active components

150‧‧‧pixel electrodes

180‧‧‧Black matrix

190‧‧‧Photo District

300‧‧‧Active component array substrate

310‧‧‧Scan wiring

320‧‧‧ Paired data wiring

322‧‧‧First data wiring

324‧‧‧Second data wiring

330‧‧‧Shared wiring

332‧‧‧First branch wiring

334‧‧‧Second branch wiring

342‧‧‧First active component

344‧‧‧Second active component

352‧‧‧ first pixel electrode

354‧‧‧Second pixel electrode

380‧‧‧Black matrix

390‧‧‧Photo area

392‧‧‧The first picture area

394‧‧‧The second picture area

900‧‧‧ display panel

910‧‧‧Active component array substrate

920‧‧‧ opposite substrate

930‧‧‧ Display media layer

980‧‧‧Black matrix

1010‧‧‧LCD panel

1020‧‧‧Backlight module

A-A’, B-B’‧‧‧ hatching

L‧‧‧Backlight

S‧‧‧ displacement

Vcom‧‧‧shared voltage source

1 is a top view of a conventional array of active components.

Figure 2 is a cross-sectional view of the active device array substrate of Figure 1 taken along line A-A'.

3 is a circuit layout of an active device array substrate in accordance with an embodiment of the present invention.

FIG. 4 further illustrates a pixel structure in the active device array substrate of FIG. 3.

Figure 5 is a cross-sectional view of the pixel structure of Figure 4 taken along line B-B'.

6-8 illustrate various pixels in accordance with various embodiments of the present invention, respectively. structure.

FIG. 9 is a schematic diagram of a display panel according to an embodiment of the present invention.

FIG. 10 illustrates a display device in accordance with an embodiment of the present invention.

300‧‧‧Active component array substrate

310‧‧‧Scan wiring

320‧‧‧ Paired data wiring

322‧‧‧First data wiring

324‧‧‧Second data wiring

330‧‧‧Shared wiring

342‧‧‧First active component

344‧‧‧Second active component

352‧‧‧ first pixel electrode

354‧‧‧Second pixel electrode

390‧‧‧Photo area

392‧‧‧The first picture area

394‧‧‧The second picture area

Claims (24)

A pixel structure is located in a pixel area of a display panel, the pixel structure includes: a scan line; a first data line and a second data line respectively located on opposite sides of the pixel area, The first data wiring and the second data wiring are substantially parallel to each other and respectively intersect the scanning wiring; a common wiring is connected to a common voltage source, the common wiring is substantially parallel to the first data wiring and the second Data wiring is located between the first data wiring and the second data wiring to distinguish the pixel into a first pixel region and a second pixel region, wherein the first pixel region Located between the first data line and the common line, and the second pixel area is located between the second data line and the common line, and the common line is parallel to the extending direction of the first data line a continuous pattern; a first active component, located in the first pixel region, and electrically connected to the scan wiring and the first data wiring; a second active component located in the second pixel region And electrically connected to the scan line and the second data line; and a first pixel electrode and a second pixel electrode respectively located in the first pixel region and the second pixel region And electrically connecting to the first active component and the second active component respectively, wherein the first pixel electrode and the second pixel electrode respectively partially overlap the common wiring. The pixel structure of claim 1, wherein the first active component and the second active component are centered on the common wiring The mirror images are disposed on opposite sides of the shared wiring. The pixel structure of claim 1, wherein the common wiring, the first data wiring, and the second data wiring are located on the same film layer. The pixel structure of claim 1, further comprising a first branch wiring and a second branch wiring, respectively located in the first pixel region and the second pixel region, and electrically Connecting to the common wiring, wherein the first branch wiring and the second branch wiring respectively bypass an edge of the first pixel electrode and the second pixel electrode, and the first branch wiring and the second branch wiring respectively Partially overlapping the first pixel electrode and the second pixel electrode. The pixel structure according to claim 4, wherein the first branch wiring and the second branch wiring are mirror-arranged on opposite sides of the common wiring with the common wiring as a central axis. The pixel structure of claim 4, wherein the first branch wiring or the second branch wiring is formed by extending the common wiring. The pixel structure of claim 1, wherein the first active component or the second active component is a thin film transistor. An active device array substrate includes: a substrate; a plurality of scanning wires disposed on the substrate, the scanning wires are substantially parallel to each other; and a plurality of pairs of data wires are disposed on the substrate, each pair of data The wiring includes a first data wiring and a second data wiring substantially parallel to each other, and the first data wiring and the second data wiring respectively intersect the scanning wiring, wherein the substrate is connected by each pair of data and two The area surrounded by the adjacent scan lines is defined as a pixel area; a plurality of common lines are disposed on the substrate and connected to a common voltage source, the common lines are substantially parallel to each other and correspond to the pixels For the data wiring, each common wiring is located between the corresponding first data wiring and the second data wiring to distinguish each pixel into a first pixel area and a second pixel area. The first pixel area is located between the first data line and the common line, and the second pixel area is located between the second data line and the common line, and the common line is parallel to The first data component is disposed in the continuous direction of the first data component; the plurality of first active components are disposed on the substrate and are respectively located in the first pixel regions, and each of the first active components is electrically connected to the correspond The scanning wiring and the first data wiring; the plurality of second active components are disposed on the substrate and respectively located in the second pixel regions, and each of the second active components is electrically connected to the corresponding scanning Wiring and the second data wiring; a plurality of first pixel electrodes respectively located in the first pixel regions and electrically connected to the corresponding first active component, wherein each first pixel electrode And partially corresponding to the shared wiring; and a plurality of second pixel electrodes respectively located in the second pixel regions and electrically connected to the corresponding second active component, wherein each The two pixel electrodes partially overlap the corresponding common wiring. The active device array substrate according to claim 8, wherein the first active component and the second active component in each pixel region are mirror-imaged with the corresponding common wiring as a central axis. The opposite sides of the shared wiring. The active device array substrate according to claim 8, wherein the common wiring, the first data wirings, and the second data wirings are located on the same film layer. The active device array substrate of claim 8, further comprising: a plurality of first branch wires respectively located in the first pixel regions and electrically connected to the corresponding common wires Each of the first branch wires bypasses an edge of the first pixel electrode corresponding to the row, and the first branch wire partially overlaps the first pixel electrode; and a plurality of second branch wires are respectively located at the edge The second pixel regions are electrically connected to the corresponding common wires, wherein each of the second branch wires bypasses an edge of the second pixel electrode corresponding to the row, and the second branch wire There is a partial overlap with the second pixel electrode. The active device array substrate according to claim 11, wherein the first branch wiring and the second branch wiring in each pixel region are mirror-imaged with the corresponding common wiring as a central axis. The opposite sides of the shared wiring. The active device array substrate according to claim 11, wherein each of the first branch wires or each of the second branch wires is formed by extending the corresponding common wires. The active device array substrate according to claim 8, wherein each of the first active devices or each of the second active devices is a thin film transistor. A display panel includes: an active device array substrate, comprising: a substrate; a plurality of scanning wires disposed on the substrate, the scan wires are substantially parallel to each other; and a plurality of pairs of data wires are disposed on the substrate Each pair of data wires includes a first data wire and a second data wire that are substantially parallel to each other, and the first data wire and the second data wire respectively intersect the scan wire, wherein the substrate is each The area surrounded by the data wiring and the two adjacent scanning lines is defined as a pixel area; a plurality of common lines are disposed on the substrate and connected to a common voltage source, the common lines are substantially parallel to each other and Corresponding to the pair of data wires, each of the common wires is located between the corresponding first data wires and the second data wires to distinguish each pixel into a first pixel region and a first pixel a second pixel area, wherein the first pixel area is located between the first data line and the common line, and the second pixel area is located between the second data line and the shared line , And the common wiring extending in a direction parallel to the first data line is a continuous pattern; a first plurality of active elements disposed on the substrate and are located Each of the first active elements is electrically connected to the corresponding scan line and the first data line; a plurality of second active elements are disposed on the substrate and are respectively located In the second pixel region, each of the second active components is electrically connected to the corresponding scan wiring and the second data wiring; and the plurality of first pixel electrodes are respectively located in the first pixel regions. And electrically connected to the corresponding first active component, wherein each first pixel electrode partially overlaps the corresponding common wiring; and the plurality of second pixel electrodes are respectively located in the second painting And electrically connected to the corresponding second active component, wherein each of the second pixel electrodes partially overlaps the corresponding common wiring; a pair of substrates; and a display dielectric layer disposed on Between the active device array substrate and the opposite substrate. The display panel of claim 15, wherein the first active component and the second active component in each pixel region are mirrored and disposed in the common with the corresponding common wiring as a central axis. The opposite sides of the wiring. The display panel of claim 15, wherein the common wiring, the first data wirings, and the second data wirings are located on the same film layer. The display panel of claim 15, wherein the active device array substrate further comprises: a plurality of first branch wires respectively located in the first pixel regions; And electrically connected to the corresponding common wires, wherein each of the first branch wires bypasses an edge of the first pixel electrode corresponding to the row, and the first branch wire has a portion with the first pixel electrode And a plurality of second branch wires respectively located in the second pixel regions and electrically connected to the corresponding common wires, wherein each of the second branch wires is adjacent to the row The edge of the two pixel electrodes, and the second branch wiring partially overlaps the second pixel electrode. The display panel of claim 18, wherein the first branch wiring and the second branch wiring in each pixel region are mirrored and disposed in the common with the corresponding common wiring as a central axis. The opposite sides of the wiring. The display panel of claim 18, wherein each of the first branch wires or each of the second branch wires is formed by extending the corresponding common wires. The display panel of claim 15, wherein each of the first active elements or each of the second active elements is a thin film transistor. The display panel of claim 15, wherein the opposite substrate is a color filter substrate. The display panel of claim 15, wherein the display medium layer is a liquid crystal layer. A display device comprising: the display panel of claim 15; and a backlight module disposed adjacent to the display panel to provide a backlight to the display panel.