TWI404014B - Display panel and driving circuit thereof - Google Patents

Abstract

The present invention provides a driving circuit, including a plurality of gate lines, a plurality of first data lines, a plurality of second data lines, a plurality of first sub-pixels, a plurality of second sub-pixels, a plurality of third sub-pixels and a plurality of fourth sub-pixels. The first sub-pixels, the second sub-pixels, the third sub-pixels and the fourth sub-pixels are arranged in matrix. Each second sub-pixel is respectively electrically connected to each first sub-pixel, and each first sub-pixel is electrically connected to the corresponding first data line. Each fourth sub-pixel is respectively electrically connected to each third sub-pixel, and each third sub-pixel is electrically connected to the corresponding second data line.

Description

Display panel and its driving circuit

The invention relates to a display panel and a driving circuit thereof, in particular to a driving circuit composed of two sets of half source driver (HSD) circuits and a display panel using the same.

The current liquid crystal displays can be mainly divided into three categories: transmissive liquid crystal displays, reflective liquid crystal displays, and semi-transmissive liquid crystal displays. A penetrating liquid crystal display requires a backlight module and has problems such as excessive power consumption and unclear display when the ambient light is too strong. The reflective liquid crystal display replaces the transparent electrode layer with a reflective electrode layer, and does not require a backlight module, but does not function in a dark environment. The transflective liquid crystal display has both a transmissive area and a reflective area to avoid the disadvantages of full penetration or total reflection.

The conventional transflective liquid crystal display panel can be further divided into a single liquid crystal gap type and a dual liquid crystal gap type (dual cell gap). The reflective area of the single liquid crystal gap type transflective liquid crystal display panel has the same liquid crystal gap as the transmissive area. However, since the optical path difference between the ambient light of the reflective area and the backlight of the transmissive area is different, the reflective area is caused by The gamma curve of the penetrating zone is different, and the best optical effect of the reflection mode and the penetrating mode cannot be achieved. In order to solve the difference in the gamma curve between the reflective region and the transmissive region caused by the difference in optical path difference, a double liquid crystal gap type transflective liquid crystal display panel has been developed. Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a conventional trans-liquid crystal display panel with a double liquid crystal gap type. As shown in FIG. 1, the conventional transflective liquid crystal display device 10 includes an array substrate 20, a color filter substrate 30, and a liquid crystal molecular layer 40 disposed between the array substrate 20 and the color filter substrate 30. The array substrate 20 and the color filter substrate 30 define a plurality of pixel regions 22, and each of the pixel regions 22 includes a reflective region 27 and a penetrating region 28. In order to clearly show the structure of each pixel region 22, only one pixel region 22 is shown in Fig. 1 as an illustration. The array substrate 20 of each pixel region 22 includes a first substrate 24, a protective layer 26 and a pixel electrode 32. The protective layer 26 is disposed between the liquid crystal molecular layer 40 and the first substrate 24, and the pixel electrode 32 is provided. It is provided between the protective layer 26 and the liquid crystal molecule layer 20. Further, the pixel electrode 32 provided in the transmissive region 28 is a transparent electrode 32a, and the pixel electrode 32 provided in the reflective region 27 is a reflective electrode 32b. The color filter substrate 30 of each pixel region 22 includes a second substrate 34, a color filter 36, a bump 38, and a common electrode 42. The color filter 30 is disposed on the liquid crystal molecular layer 20. The common electrode 42 is disposed between the color filter 30 and the liquid crystal molecule layer 20 between the second substrate 34 and the second substrate 34. The bump 38 is disposed between the common electrode 42 of the reflective region 27 and the color filter 38 to reduce the thickness of the liquid crystal molecular layer 40 of the reflective region 27, that is, to reduce the liquid crystal gap of the reflective region 27, so that the double liquid crystal gap type The liquid crystal gap of the reflective region 27 of the transflective liquid crystal display panel is about half of the liquid crystal gap of the transmissive region 28, whereby the ambient light of the reflective region 27 and the backlight of the transmissive region 28 have the same optical path difference. In this case, the reflective region 27 and the penetrating region 28 can have a gamma curve.

However, since the double liquid crystal gap type transflective liquid crystal display panel must use an additional process to set the bumps in the reflective area to adjust the liquid crystal gap, the process complexity is increased, thereby causing a problem of increased production cost.

One of the objectives of the present invention is to provide a display panel and a driving circuit thereof, the driving circuit is composed of two sets of half-source driving circuits to respectively drive the sub-pixels of the transmissive area and the reflective area, thereby solving the conventional technology. The above question.

To achieve the above objective, the present invention provides a driving circuit including a plurality of gate lines, a plurality of first data lines, a plurality of second data lines, a plurality of first pixels, and a plurality of second pixels. , a plurality of third pixels and a plurality of fourth pixels. Wherein the second (m+1)th data line is disposed between the first (m+1)th data line and the (m+2)th first data line, and the (m+2)th A data line is disposed between the second (m+1)th data line and the (m+2)th second data line. The first pixel is set between the two adjacent (2n+1) gate lines and the (2n+2) gate lines and the two adjacent (m+1) second data. Between the line and the first (m+2) first data line, and between the two adjacent (2n+2) gate lines and the (2n+3) gate lines and the two adjacent (m+1) between the first data line and the (m+1)th second data line. The second pixel is respectively disposed between two adjacent (2n+1) gate lines and the (2n+2) gate lines and two adjacent (m+1) first data. Between the line and the (m+1)th second data line, and between the two adjacent (2n+2) gate lines and the (2n+3)th gate line and the two adjacent (m+2) between the first data line and the (m+1)th second data line. Each of the second pixels is electrically connected to each of the first pixels. The third pixel is respectively set between the two adjacent (2n+1) gate lines and the (2n+2) gate lines and the two adjacent (m+1) first data. Between the line and the (m+1)th second data line, and between the two adjacent (2n+2) gate lines and the (2n+3)th gate line and the two adjacent (m+2) between the first data line and the (m+1)th second data line. The fourth pixel is set between the two adjacent (2n+1) gate lines and the (2n+2) gate lines and the two adjacent (m+1) second data. Between the line and the first (m+2) first data line, and between the two adjacent (2n+2) gate lines and the (2n+3) gate lines and the two adjacent (m+1) between the first data line and the (m+1)th second data line. Each of the fourth pixels is electrically connected to each of the third pixels, and the first pixel, the second pixel, the third pixel, and the fourth pixel are arranged in a matrix manner. Wherein, the (2n+1)th gate line is electrically connected to the second pixel and the fourth pixel between the (2n+1)th gate line and the (2n+2)th gate line The (2n+2)th gate line is electrically connected to the first pixel and the third pixel between the (2n+1)th gate line and the (2n+2)th gate line, And electrically connecting the second pixel and the fourth pixel between the (2n+2) gate line and the (2n+3) gate line; the (2n+3) gate line The first pixel and the third pixel between the (2n+2) gate line and the (2n+3) gate line; the (m+1)th first data line electrical property Connecting the first pixel between the (m+1)th first data line and the (m+1)th second data line; the (m+1)th second data line electrical connection is located at Between the (m+1) first data line and the (m+1) second data line, and the (m+1) second data line and the (m+2) first data line The third pixel between the first pixel; the (m+2)th first data line is electrically connected between the (m+2)th first data line and the (m+1)th second data line The first pixel, and m and n are integers greater than or equal to zero.

To achieve the above object, the present invention further provides a display panel including a substrate, the above driving circuit, a color filter substrate, and a liquid crystal layer. The driving circuit is disposed on the substrate, and the liquid crystal layer is disposed between the substrate and the color filter substrate.

The invention connects the sub-pixel of the penetrating region and the sub-pixel of the reflection region to different data lines respectively, so that the voltage value of the sub-pixel received by the sub-pixel in the reflection region can be compared with the sub-pixel of the penetrating region. The received high-level voltage values are different, so that the sub-pixels of the penetration region show that the gamma curve can match the gamma curve displayed by the sub-pixels of the reflection region to avoid the penetration region and the reflection. The gamma curves caused by the same liquid crystal gap are different.

The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .

Referring to FIG. 2 and FIG. 3, FIG. 2 is a cross-sectional view showing a display panel according to a first embodiment of the present invention, and FIG. 3 is a schematic diagram showing a driving circuit of the display panel according to the first embodiment of the present invention. As shown in FIG. 2, the display panel 100 includes a substrate 102, a color filter substrate 104, a liquid crystal layer 106, and a driving circuit 108. The substrate 102 is disposed opposite to the color filter substrate 104, and the liquid crystal layer 106 is disposed between the substrate 102 and the color filter substrate 104, and the driving circuit 108 is disposed between the substrate 102 and the liquid crystal layer 106. In the embodiment, the display panel 100 is a single liquid crystal gap type transflective liquid crystal display panel, and has only a single cell gap d, and the display panel defines a plurality of transmissive regions T and a plurality of reflections. District R. As shown in FIG. 3, the driving circuit 108 includes a plurality of gate lines GL ₁ - GL _x , a plurality of first data lines DL _{1 -} DL _y , a plurality of second data lines RL _{1 -} RL _y , and a plurality of first a secondary pixel P ₁ , a plurality of second pixels P ₂ , a plurality of third pixels P _{3 ,} and a plurality of fourth pixels P ₄ , wherein the first pixel P ₁ , the second pixel P ₂ , the third pixel P ₃ and the fourth pixel P ₄ are arranged in a matrix manner, and x and y are positive integers greater than or equal to 1. Moreover, each of the first pixel P ₁ and each of the second pixels P ₂ are located in each of the penetration regions T, and each of the third pixel P ₃ and each of the fourth pixels P ₄ are respectively located in each reflection. Within area R. Further, the gate line GL ₁ -GL _x and the first data line DL ₁ -DL _y and the second data line RL ₁ -RL _y substantially perpendicular to each other, and the first data line DL ₁ -DL _y and the second data line RL ₁ -RL _y are substantially parallel to each other.

Wherein, the (m+1)th second data line RL _(m+1) is set in the (m+1)th first data line DL _(m+1) and the (m+2)th first data line Between DL _(m+2) , and the (m+2)th first data line DL _(m+2) is set in the (m+1)th second data line RL _(m+1) and the (m) +2 ₎ Between the second data line RL _(m+2) . Each of the first pixels P _{1 is} respectively disposed between two adjacent (2n+1)th gate lines GL _(2n+1) and (2n+2)th gate lines GL _(2n+2) And two adjacent (m+1)th second data lines RL _(m+1) and (m+2) first data lines DL _(m+2) , and two adjacent ones ( 2n+2) between the gate line GL _(2n+2) and the (2n+3)th gate line GL _(2n+3) and the two adjacent (m+1)th first data lines DL _(m+1) and the (m+1)th second data line RL _(m+1) . Each of the second pixels P _{2 is} respectively disposed between two adjacent (2n+1) gate lines GL _(2n+1) and (2n+2) gate lines GL _(2n+2) And two adjacent (m+1)th first data lines DL _(m+1) and (m+1) second data lines RL _(m+1) , and two adjacent ones ( 2n+2) between the gate line GL _(2n+2) and the (2n+3)th gate line GL _(2n+3) and the two adjacent (m+2)th first data lines DL _(m+2) and the (m+1)th second data line RL _(m+1) . The first pixel P ₁ and the second pixel P ₂ located between the two adjacent gate lines GL ₁ -GL _x and the two adjacent first data lines DL ₁ -DL _y are electrically connected to each other. Each of the third pixels P _{3 is} respectively disposed between two adjacent (2n+1) gate lines GL _(2n+1) and (2n+2) gate lines GL _(2n+2) And two adjacent (m+1)th first data lines DL _(m+1) and (m+1) second data lines RL _(m+1) , and two adjacent ones ( 2n+2) between the gate line GL _(2n+2) and the (2n+3)th gate line GL _(2n+3) and the two adjacent (m+2)th first data lines DL _(m+2) and the (m+1)th second data line RL _(m+1) . Each fourth pixel P _{4 is} respectively disposed between two adjacent (2n+1) gate lines GL _(2n+1) and (2n+2) gate lines GL _(2n+2) And two adjacent (m+1)th second data lines RL _(m+1) and (m+2) first data lines DL _(m+2) , and two adjacent ones ( 2n+2) between the gate line GL _(2n+2) and the (2n+3)th gate line GL _(2n+3) and the two adjacent (m+1)th first data lines DL _(m+1) and the (m+1)th second data line RL _(m+1) . The third pixel P ₃ and the fourth pixel P ₄ located between the two adjacent gate lines GL ₁ -GL _x and the two adjacent second data lines RL ₁ -RL _y are electrically connected to each other.

Further, the (2n+1)th gate line GL _{(2n+1) is} electrically connected to the (2n+1)th gate line GL _(2n+1) and the (2n+2)th gate line GL. The second pixel P ₂ and the fourth pixel P ₄ between _(2n+2) . The (2n+2)th gate line GL _{(2n+2) is} electrically connected to the (2n+1)th gate line GL _(2n+1) and the (2n+2)th gate line GL _{(2n) +2)} The first pixel P ₁ and the third pixel P ₃ , and the electrical connection is located at the (2n+2)th gate line GL _(2n+2) and the (2n+3) gate The second pixel P ₂ and the fourth pixel P ₄ between the polar lines GL _(2n+3) . The (2n+3)th gate line GL _{(2n+3) is} electrically connected to the (2n+2)th gate line GL _(2n+2) and the (2n+3)th gate line GL _{(2n+) 3)} The first pixel P ₁ and the third pixel P ₃ . And the (m+1)th first data line DL _{(m+1) is} electrically connected to the (m+1)th first data line DL _(m+1) and the (m+1)th second The first pixel P ₁ between the data lines RL _(m+1) . The (m+1)th second data line RL _{(m+1) is} electrically connected to the (m+1)th first data line DL _(m+1) and the (m+1)th second data line Between DL _(m+1) , and between the (m+1)th second data line RL _(m+1) and the (m+2)th first data line DL _(m+2) Three pixels P ₃ . The (m+2)th first data line DL _{(m+2) is} electrically connected at the (m+2)th first data line DL _(m+2) and the (m+1)th second data line The first pixel P ₁ between DL _(m+1) , and m and n are integers greater than or equal to zero. It can be seen that the second pixel P _{2 is} electrically connected to the first pixel P ₁ , and the first pixel P ₁ is electrically connected to the corresponding first data line (DL ₁ , DL ₂ , DL ₃ ... or DL _y ), so the display data signal for displaying the screen of the penetration area T can be transmitted to each of the first data lines (DL ₁ , DL ₂ , DL ₃ ... or DL _y ) to The first pixel P ₁ and the second pixel P ₂ . Similarly, the fourth pixel P ₄ is electrically connected to the third pixel P ₃ , and the third pixel P ₃ is electrically connected to the corresponding second data line (RL ₁ , RL ₂ , RL ₃ ... or RL _y ), so that the display data signal for displaying the screen of the reflection area R can be transmitted to the second data line (RL ₁ , RL ₂ , RL ₃ ... or RL _y ) The third pixel P ₃ and the fourth pixel P ₄ .

In this embodiment, each of the first pixels P ₁ is located in the (4n+2)th row (2m+2) row and the (4n+4)th column (2m+1) row, and each second. sub-pixel P ₂ are respectively located on lines (4n + 1) column (2m + 1) and the second line (4n + 3) column (2m + 2) line, each third sub-pixel lines were located at P ₃ (4n+2) column (2m+1) row and (4n+4) column (2m+2) row, and each fourth pixel P ₄ system is located in the (4n+1)th column ( 2m+2) rows and (4n+1) rows (2m+1) rows. And, the first pixel P ₁ , the second pixel P ₂ , the third pixel P ₃ and the fourth pixel P ₄ located in the (3m+1)th row may be red sub-pixels, located at The first pixel P ₁ , the second pixel P ₂ , the third pixel P ₃ and the fourth pixel P _{4 of} the (3m+2)th line may be green sub-pixels and located at the The first pixel P ₁ , the second pixel P ₂ , the third pixel P ₃ and the fourth pixel P _{4 of the} 3m+3) line may be blue sub-pixels, but are not limited thereto. The positions of the red sub-pixels, green sub-pixels or blue sub-pixels of the present invention may also be interchanged with each other.

In addition, each of the first pixels P ₁ includes a first switching element SW ₁ and a first pixel electrode PE ₁ , and each of the first pixel electrodes PE _{1 is} electrically connected to each of the first switching elements SW ₁ . pole. Each of the second pixels P ₂ includes a second switching element SW ₂ and a second pixel electrode PE ₂ , and each of the second pixel electrodes PE _{2 is} electrically connected to the drain of each of the second switching elements SW ₁ . The first pixel electrode PE ₁ and the second pixel electrode PE ₂ of the embodiment are composed of a transparent conductive layer, such as indium tin oxide (ITO) or indium zinc oxide (IZO), etc., so as to be located in the penetration region T. The first pixel P ₁ and the second pixel P ₂ can use a backlight to display the picture. Each of the third pixels P ₃ includes a third switching element SW ₃ and a third pixel electrode PE ₃ , and each of the third pixel electrodes PE _{3 is} electrically connected to the drain of each of the third switching elements SW ₃ . Each fourth pixel P ₄ includes a fourth switching element SW ₄ and a fourth pixel electrode PE ₄ , and each fourth pixel electrode PE _{4 is} electrically connected to the drain of each fourth switching element SW ₄ . The third pixel electrode PE ₃ and the fourth pixel electrode PE ₄ of the present embodiment are composed of a conductive layer having high reflectivity, for example, metal or the like, so that the third pixel P ₃ located in the reflective region R And the fourth pixel P ₄ can use an ambient light source to display the picture. Moreover, the source of each of the second switching elements SW ₂ between the two adjacent gate lines GL ₁ -GL _x and the two adjacent first data lines DL ₁ -DL _y is adjacent to each of the first switching elements SW ₁ The poles are electrically connected to each other, and the source and each of the fourth switching elements SW ₄ between the two adjacent gate lines GL ₁ -GL _x and the two adjacent second data lines DL ₁ -DL _y The drains of the third switching element SW ₃ are electrically connected to each other such that the first pixel P ₁ and the second pixel P ₂ located in different rows can share the same first data line (DL ₁ , DL ₂ , DL ₃ ... or DL _y ), and the third pixel P ₃ and the fourth pixel P ₄ located in different rows may share the same second data line (RL ₁ , RL ₂ , RL ₃ .. Or RL _y ). The gates of the second switching element SW ₂ and the fourth switching element SW ₄ in the (4n+1)th column are electrically connected to the (2n+1)th gate line GL _(2n+1) at the 4n+3) the gates of the second switching element SW ₂ and the fourth switching element SW _{4 and} the gates of the first switching element SW ₁ and the third switching element SW ₃ in the (4n+2)th column Connected to the (2n+2)th gate line GL _(2n+2) , the gates of the first switching element SW ₁ and the third switching element SW ₃ in the (4n+4)th column are electrically connected to The (2n+3)th gate line GL _(2n+3) .

In addition, the driving circuit 108 further includes a gate driving circuit 110, a first data driving circuit 112 and a second data driving circuit 114, wherein the gate driving circuit 110 is electrically connected to each of the gate lines GL ₁ -GL _x , The first data driving circuit 112 is electrically connected to each of the first data lines (DL ₁ , DL ₂ , DL ₃ ... or DL _y ), and the second data driving circuit 114 is electrically connected to each of the second data lines ( RL ₁ , RL ₂ , RL ₃ ... or RL _y ). It should be noted that the present invention connects the first pixel P ₁ and the second pixel P _{2 of the} penetrating region and the third pixel P ₃ and the second pixel P _{4 of the} reflection region to the phase respectively. Corresponding first data lines (DL ₁ , DL ₂ , DL ₃ ... or DL _y ) and second data lines (RL ₁ , RL ₂ , RL ₃ ... or RL _y ), and driven by the first data The circuit 112 is electrically connected to all of the first data lines DL ₁ -DL _y , and the second data driving circuit 114 is used to electrically pass all the second data lines RL ₁ -RL _y , so that the first pixel P _{1 of the} penetration region is The second pixel P ₂ can independently receive the display data signal of the penetration region transmitted from the first data driving circuit 112, and the third pixel P ₃ and the fourth pixel P _{4 of the} reflection region can be independently received. The display data signal of the reflection area transmitted from the second data driving circuit 114.

It is worth mentioning that the first data driving circuit and the second data driving circuit respectively provide different display data signals to the first pixel and the second pixel of the penetrating region and the third pixel of the reflection region and The fourth pixel, so the voltage value of the high level provided by the second data driving circuit can be different from the high level voltage value provided by the first data driving circuit. Moreover, by correcting the voltage value of the high level provided by the second data driving circuit, the first pixel and the second pixel of the penetrating region can be displayed as a gamma curve and a reflection region. The third pixel matches the gamma curve shown by the fourth pixel. Therefore, even if the display panel of the embodiment is a single liquid crystal gap display panel, that is, the liquid crystal gap of the penetration region is the same as the liquid crystal gap of the reflection region, the display panel of the present invention can avoid the penetration region and the reflection region. The gamma curves caused by the same liquid crystal gap are different.

In order to clearly explain the operation principle of the display panel, the following description will be described by taking the first pixel and the second pixel of the penetration region driven by the first data driving circuit as an example. Please refer to Figures 4 and 5. FIG. 4 is a timing chart showing the display data signal transmitted to the gate line and the first data line when the red area of the display panel is displayed in the first embodiment of the present invention, and FIG. 5 is the first embodiment of the present invention. A schematic diagram of a drive circuit for a penetration region of an embodiment. In order to clearly explain the display condition of the sub-pixels, the driving circuit of FIG. 5 only shows four gate lines GL ₁ - GL ₄ , three first data lines DL _{1 -} DL ₃ , and eight first-order pixels. P ₁ and 8 second pixels P ₂ , but actually the number of gate lines of the driving circuit, the number of first data lines, and the number of first pixels and second pixels are not Limited. As shown in FIGS. 4 and 5, the drive circuit of the penetration region constitutes a first half source driver (HSD) circuit 108a, and each gate line (GL ₁ , GL ₂ , GL ₃ Or GL ₄ ) sequentially input the gate signal with a waveform of 1011, where 1 is a high level and 0 is a low level, and each level continues for the same time interval. First, in a first time interval T _1, the article 1 and the gate line GL ₁ Article 2 gate lines GL are both high-level gate signal of the transmission _2, the rest of the gate line GL _3, GL ₄ Suo the display data transfer signal level was low, and therefore is electrically connected to the first section ₁ of the gate line GL ₂ and a second switching element SW is electrically connected to the second section of the gate line GL of the first switching element SW _{2 1} and the second switching element SW ₂ will be turned on. At the same time, the display data signal transmitted by the first data line DL _{2 of} the second strip is a high level, and the display data signal transmitted by the first data line DL ₁ of the first strip and the first data line DL _{3 of} the third strip is a low level. Therefore, the display data signal transmitted by the first data line DL ₂ of the second line can be stored in the first pixel P ₁ of the second row and the second column, and the second pixel P ₂ of the first row and the first column. . Then, in the second time interval T ₂ , the gate signal transmitted by the second gate line GL ₂ is converted to a low level, so that the first switching element SW ₁ and the third column of the second column are turned off. Two switching elements SW ₃ . Moreover, the signal transmitted by the first first data line DL ₁ is converted to a high level. Then, in the third time interval T ₃ , the gate signals transmitted by the second gate line GL ₂ and the third gate line GL _{3 are} converted to a high level, and the first gate line GL _{1 is} converted into Since the low level is low, the first switching element SW ₁ and the fourth row and third column of the third row, the fourth row, the fourth row and the second column, and the second switching element SW _{2 of} the third row and the fifth column are turned on. At the same time, the display data signal transmitted by the first data line DL ₂ of the second item is converted to a high level, so the display data signal is stored in the first pixel P ₁ and the fourth line 3 of the third row and the fourth column. The second pixel of the column is P ₂ . Then, in the fourth time interval T ₄ , the signal of the third gate line GL ₃ is converted to a low level, so that the first switching element SW ₁ of the third row and the fourth column is turned off. At the same time, the signal of the first data line DL ₂ of the second strip is converted to a low level, so that the display data signal of the first pixel P ₁ stored in the second row and the second column is transmitted through the first switching element SW ₁ that is turned on. The second data line DL ₂ is removed to the second data line, and the display data signal in the first pixel P ₁ of the second row and the second column is removed. At the same time, the signal of the first data line DL ₃ of the _third line will be converted to a high level, so that the first pixel P ₁ of the fourth column of the fourth row is stored in the display data signal. Then, in the fifth time interval T ₅ , the second gate line GL _{2 is} converted to a low level, and the gate signal transmitted by the third gate line GL ₃ and the fourth gate line GL ₄ is converted into high level, while the second section first data line DL of the display data signals transmitted at a high level, thus the display data signals into the first column 6, line 2 of the first row pixels P ₁ and the first and _second The second pixel of the 5th column is P ₂ . Next, in the sixth time interval T _6, the strip gate line GL 4 ₄ converts the signal to a low level, and the 2nd first data line DL signal is converted to a low level of _2, the article 1 The signal of the first data line DL ₁ is converted to the high level, so the display data signal of the first pixel P ₁ stored in the third row and the fourth column is transmitted to the second strip through the first switching element SW ₁ that is turned on. a data line DL _2, and 4 of the first row of the third pixel P ₁ in the first display data signals is removed, and a P ₁ into the display pixels in the first row of 4 1 Information signal. By analogy, the gate signals of 1011 are sequentially input to each gate line (GL ₁ , GL ₂ , GL ₃ , GL ₄ ... or GL _x ), and a time interval display is input every three time intervals. Data signal to the (3m+1)th first data line DL _(3m+1) and the (3m+3) first data line DL _(3m+3) , and input a time interval every other time interval The data signal is displayed to the (3m+2)th first data line DL _(3m+2) , and the red sub-pixels located in the penetration area of the (3m+1)th line can be displayed. It should be noted that the present invention stores the display data signal in the second pixel P ₂ of red and the first pixel P ₁ of non-red at the first time interval T ₁ , and after two time intervals. The display data signal stored in the non-red first pixel P ₁ is removed in the fourth time interval T ₄ . Therefore, the display data signal stored to the non-red first pixel P ₁ when storing the display data signal to the second pixel P ₂ in red may also be electrically connected to the low level after two time intervals. And was removed.

Please refer to FIG. 6 and FIG. 7 . FIG. 6 is a timing diagram of the display data signal transmitted to the gate line and the first data line when the green area of the display panel is displayed in the first embodiment of the present invention. FIG. 7 is a timing chart showing the display data signal transmitted to the gate line and the first data line when the blue screen is displayed in the penetration area of the display panel according to the first embodiment of the present invention. As shown in Figure 6, when displaying a green screen, the display of the data signal to the (3m+2) first data is displayed every three time intervals compared to the display data signal provided by the red screen. Line DL _(3m+1) and (3m+3) first data line DL _(3m+3) , and input a time interval display data signal to every (3m+1) first every other time interval The data line DL _(3m+1) , the green sub-pixel located in the penetration area of the (3m+2)th line can be displayed. In other words, the display data signal input to the (3m+1)th first data line DL _(3m+1) in FIG. 4 is changed to the first (3m+3) first data line DL _{(3m+3). )} , the display data signal input to the (3m+2)th first data line DL _(3m+2) in Fig. 4 is changed to the first (3m+1) first data line DL _{(3m+1) )} , the display data signal input to the (3m+3)th first data line DL _(3m+3) in Fig. 4 is changed to the first (3m+2) first data line DL _{(3m+2) )} to display a green picture. As shown in Fig. 7, the display data signal input to the (3m+1)th first data line DL _(3m+1) in Fig. 4 is changed to the first (3m+2) first data line. DL _(3m+2) , the display data signal input to the (3m+2)th first data line DL _(3m+2) in Fig. 4 is changed to the first (3m+3) first data line. DL _(3m+3) , the display data signal input to the (3m+3)th first data line DL _(3m+3) in Fig. 4 is changed to the first (3m+1) first data line. DL _{(3m+1) will} give a blue picture.

Please refer to FIG. 8. FIG. 8 is a schematic diagram showing a driving circuit of a reflective region according to the first embodiment of the present invention. As shown in Fig. 8, the driving circuit of the reflective region constitutes a second half-source driving circuit 108b, and the driving circuit of the reflective region is approximately the same as the driving circuit of the penetrating region. The difference between the two is that the position of the third pixel P ₃ and the fourth pixel P _{4 is different from} the position of the first pixel P ₁ and the second pixel P ₂ , and therefore is located in the third row. The third pixel P ₃ of the two columns has a similar connection circuit to the first pixel P ₁ located in the second row of the second column, but displays a different color. Therefore, the display data signals of the third pixel P ₃ and the fourth pixel P ₄ supplied to the reflection area must be adjusted. When the red screen is displayed, the second data driving circuit supplies the display data signal input to the (3m+1)th first data line DL _(3m+1) in FIG. 4 to the third (3m+2) second. The data line RL _(3m+2) provides the display data signal input to the (3m+2)th first data line DL _{(3m+2) in} the fourth picture to the (3m+3) second data line. RL _(3m+3) , providing the display data signal input to the (3m+3)th first data line DL _(3m+3) in FIG. 4 to the (3m+1)th second data line RL _{( 3m+1)} . When the green screen is displayed, the second data driving circuit supplies the display data signal input to the (3m+1)th first data line DL _(3m+1) in FIG. 4 to the (3m+1)th second. The data line RL _(3m+1) supplies the display data signal input to the (3m+2)th first data line DL _{(3m+2) in} the fourth picture to the (3m+2) second data line. RL _(3m+2) , providing the display data signal input to the (3m+3)th first data line DL _(3m+3) in FIG. 4 to the (3m+3)th second data line RL _{( 3m+3)} . When the blue screen is displayed, the second data driving circuit supplies the display data signal input to the (3m+1)th first data line DL _(3m+1) in FIG. 4 to the (3m+3)th The second data line RL _(3m+3) provides the display data signal input to the (3m+2) first data line DL _{(3m+2) in} the fourth picture to the (3m+1) second data. Line RL _(3m+1) , providing the display data signal input to the (3m+3)th first data line DL _(3m+3) in FIG. 4 to the (3m+2)th first data line DL _(3m+2) .

Referring to FIG. 9 and FIG. 10, FIG. 9 is a schematic diagram showing a driving circuit of a display panel according to a second embodiment of the present invention, and FIG. 10 is a schematic diagram showing a display screen of a display panel according to a second embodiment of the present invention. As shown in FIG. 9, the first pixel P ₁ of the driving circuit 200 of the present embodiment is located at the (2n+1)th column (4m+4), respectively, compared to the display panel of the first embodiment. Row and (2n+2)th row (4m+1) row, each second pixel P ₂ system is located in the (2n+1)th column (4m+1) row and the (2n+2)th column In the (4m+4)th row, each of the third pixel P ₃ systems is located in the (4n+2)th row and the (2n+2)th row (4m+3)th row of the (2n+1)th column, respectively, and Each of the fourth pixel P ₄ systems is located at the (4m+3)th row and the (2n+2)th row (4m+2)th row of the (2n+1)th column. The second pixel P ₂ and the fourth pixel P ₄ located in the (2n+1)th column are electrically connected to the (2n+1)th gate line GL _(2n+1) at the (2n+) 2) the second pixel P ₂ and the fourth pixel P ₄ in the column and the first pixel P ₁ and the third pixel P ₃ in the (2n+1)th column are electrically connected to the first pixel (2n+2) gate line GL _(2n+2) , and the first pixel P ₁ and the third pixel system P ₃ in the (2n+2)th column are electrically connected to the second (2n+) 3) Strip gate line GL _(2n+3) . In this embodiment, the first pixel P ₁ and the second pixel P ₂ of the penetrating region are disposed in the same column as the third pixel P ₃ and the fourth pixel P ₄ of the reflective region, so that The through zone and the reflective zone are alternately arranged in the same column. Therefore, as shown in FIG. 10, the display panel 202 of the present embodiment, the first data driving circuit 112 may be displayed in a first viewing angle data transmission, the reception time of the first signal and the second pixels P ₁ The sub-pixel P ₂ displays a first view picture 204, and the second data driving circuit 114 can be used to transmit a second view display data so that the third pixel P ₃ and the fourth pixel P of the received signal are received. ₄ shows a second perspective screen 206. Moreover, the display panel 202 is provided with an optical element having a birefringence in the front direction, so that the first viewing angle screen 204 is emitted toward an angle, and the second viewing angle screen 206 is emitted toward another angle, thereby causing the display panel 202 to be viewed at different angles. The viewer can watch different display screens.

In addition, in addition to displaying a two-dimensional picture, the display panel of the present invention can also be applied to display a three-dimensional picture. Please refer to FIG. 11 and refer to FIG. 3 together. FIG. 11 is a schematic diagram showing a three-dimensional display of the display panel of the present invention. As shown in FIG. 3 and FIG. 11, an image 300 is divided into a first display material 302 having a sharpness value and a second display material 304 having a contrast value. first data transfer may be used to display the data of the first transmissive region 302 to a driving circuit of the pixel and the second sub-pixel P ₁ P _2, and the second data driving circuit may be used to transmit the second data 304 to the reflective display The third pixel of the region is P ₃ and the fourth pixel P ₄ . Thus, with the first pixel and the second sub-pixel P ₁ P ₂ of the image shows a sharp image 300 using the third pixel value, and the fourth sub-pixel P ₃ P ₄ the contrast of the display image 300, whereby the first A display material 302 and a second display material 304 form a three-dimensional picture material 306, so that the display panel displays a three-dimensional picture.

Please refer to FIG. 12, and please refer to FIG. 3 together. FIG. 12 is a schematic diagram showing another three-dimensional display of the display panel of the present invention. As shown in FIG. 3 and FIG. 12, an image 350 is divided into a first pattern data 352 having a first brightness and a second pattern data 354 having a second brightness, and the first data driving circuit is available. To transmit the first pattern data to the first pixel P ₁ and the second pixel P _{2 of the} penetrating region, the second data driving circuit can be used to transmit the second pattern data to the third pixel P _{3 of the} reflective region. And the fourth pixel P ₄ , and the present invention uses the first brightness to be smaller than the second brightness to present the first pattern data 352 behind the second pattern data 354 , thereby presenting the first pattern data 352 having different depth of field. And the second pattern data 354, thereby displaying a three-dimensional picture.

In summary, the present invention utilizes two sets of half-source driving circuits to independently provide different display data signals to the sub-pixels of the transmissive area and the reflective area, so that the sub-pixels of the reflective area receive the high-level voltage. The value may be different from the high level voltage value received by the sub-pixel of the penetrating region, whereby the sub-pixel of the penetrating region shows that the gamma curve can show the gamma curve with the sub-pixel of the reflecting region. Matching to avoid different gamma curves caused by the same liquid crystal gap between the penetrating zone and the reflecting zone. Moreover, since the two sets of half-source driving circuits can independently provide different display data signals to the sub-pixels of the transmissive area and the reflective area, the driving circuit of the present invention can be applied to a display displaying a dual-view picture and displaying a three-dimensional picture. The display or the three-dimensional display that needs to display the left eye and right eye signals respectively.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10. . . Semi-transparent liquid crystal display device

20. . . Array substrate

twenty two. . . Graphic area

twenty four. . . First substrate

26. . . The protective layer

27. . . Reflection zone

28. . . Penetration zone

30. . . Color filter substrate

32. . . Pixel electrode

32a. . . Transparent electrode

32b. . . Reflective electrode

34. . . Second substrate

36. . . Color filter

38. . . Bump

40. . . Liquid crystal layer

42. . . Common electrode

100. . . Display panel

102. . . Substrate

104. . . Color filter substrate

106. . . Liquid crystal layer

108. . . Drive circuit

110. . . Gate drive circuit

112. . . First data driving circuit

114. . . Second data driving circuit

GL ₁ -GL _x . . . Gate line

DL ₁ -DL _y . . . First data line

RL ₁ -RL _y . . . Second data line

P ₁ . . . First pixel

P ₂ . . . Second pixel

P ₃ . . . Third pixel

P ₄ . . . Fourth pixel

SW ₁ . . . First switching element

SW ₂ . . . Second switching element

SW ₃ . . . Third switching element

SW ₄ . . . Fourth switching element

PE ₁ . . . First pixel electrode

PE ₂ . . . Second pixel electrode

PE ₃ . . . Third pixel electrode

PE ₄ . . . Fourth pixel electrode

T ₁ . . . First time interval

T ₂ . . . Second time interval

T ₃ . . . Third time interval

T ₄ . . . Fourth time interval

T ₅ . . . Fifth time interval

T ₆ . . . Sixth time interval

d. . . Liquid crystal gap

200. . . Drive circuit

202. . . Display panel

204. . . First perspective

206. . . Second perspective picture

300. . . image

302. . . First display data

304. . . Second display data

306. . . 3D image data

350. . . image

352. . . First pattern data

354. . . Second pattern data

FIG. 1 is a schematic view showing a conventional trans-liquid crystal display panel of a double liquid crystal gap type.

FIG. 2 is a cross-sectional view showing the display panel of the first embodiment of the present invention.

FIG. 3 is a schematic diagram showing a driving circuit of the display panel according to the first embodiment of the present invention.

FIG. 4 is a timing diagram showing the display data signal transmitted to the gate line and the first data line when the red area of the display panel is displayed in the first embodiment of the present invention.

FIG. 5 is a schematic diagram showing a driving circuit of a penetration region according to the first embodiment of the present invention.

FIG. 6 is a schematic view showing a driving circuit of a reflective region according to the first embodiment of the present invention.

FIG. 7 is a timing chart showing the display data signal transmitted to the gate line and the first data line when the green area of the display panel is displayed in the first embodiment of the present invention.

FIG. 8 is a timing chart showing the display data signal transmitted to the gate line and the first data line when the blue area of the display panel is displayed in the penetrating area of the first embodiment of the present invention.

FIG. 9 is a schematic diagram showing a driving circuit of a display panel according to a second embodiment of the present invention.

FIG. 10 is a schematic diagram showing a display screen of a display panel according to a second embodiment of the present invention.

Figure 11 is a schematic view showing the display panel of the present invention displaying a three-dimensional picture.

Figure 12 is a schematic view showing the display panel of the present invention displaying another three-dimensional picture.

108. . . Drive circuit

110. . . Gate drive circuit

112. . . First data driving circuit

114. . . Second data driving circuit

GL ₁ -GL _x . . . Gate line

DL ₁ -DL _y . . . First data line

RL ₁ -RL _y . . . Second data line

P ₁ . . . First pixel

P ₂ . . . Second pixel

P ₃ . . . Third pixel

P ₄ . . . Fourth pixel

SW ₁ . . . First switching element

SW ₂ . . . Second switching element

SW ₃ . . . Third switching element

SW ₄ . . . Fourth switching element

PE ₁ . . . First pixel electrode

PE ₂ . . . Second pixel electrode

PE ₃ . . . Third pixel electrode

PE ₄ . . . Fourth pixel electrode

Claims (13)

A driving circuit comprising: a plurality of gate lines; a plurality of first data lines; and a plurality of second data lines, wherein the (m+1)th second data line is set in the (m+1)th first data Between the line and the first (m+2)th data line, and the (m+2)th first data line is set in the (m+1)th second data line and the (m+2)th Between the two data lines; a plurality of first pixels are respectively disposed between two adjacent (2n+1) gate lines and the (2n+2) gate lines and two adjacent pixels (m+1) between the second data line and the (m+2)th first data line, and the two adjacent (2n+2) gate lines and the (2n+3)th gate Between the lines and the two adjacent (m+1) first data lines and the (m+1) second data lines; the plurality of second pixels are respectively set in two adjacent (2n+1) gate line and (2n+2) gate line and two adjacent (m+1) first data lines and (m+1) second data lines Between the two adjacent (2n+2) gate lines and the (2n+3) gate lines and the two adjacent (m+2) first data lines and the m+1) between the second data lines, wherein each of the second pixels is separately Sexually connected to each of the first pixels; a plurality of third pixels are respectively disposed between two adjacent (2n+1) gate lines and (2n+2) gate lines Between the adjacent (m+1)th first data line and the (m+1)th second data line, and the two adjacent (2n+2) gate lines and the second (2n+ 3) between the gate lines and between the two adjacent (m+2) first data lines and the (m+1) second data lines; and a plurality of fourth pixels, respectively Between the two adjacent (2n+1) gate lines and the (2n+2)th gate line and the two adjacent (m+1)th second data lines and the (m+2) Between the first data lines, and between the two adjacent (2n+2) gate lines and the (2n+3) gate lines and the two adjacent (m+1)th Between a data line and the (m+1)th second data line, wherein each of the fourth pixels is electrically connected to each of the third pixels, and the first pixels, the first pixels, the first pixels The second pixel, the third pixel and the fourth pixel are arranged in a matrix manner; wherein the (2n+1)th gate line electrical connection is located at the (2n+1)th gate The number between the polar line and the (2n+2) gate line The second pixel and the fourth pixel; the (2n+2) gate line is electrically connected between the (2n+1)th gate line and the (2n+2)th gate line The first pixels and the third pixels, and the second pixels electrically connected between the (2n+2)th gate line and the (2n+3)th gate line And the fourth pixel; the (2n+3)th gate line is electrically connected between the (2n+2)th gate line and the (2n+3)th gate line for the first time The pixel and the third pixel; the (m+1)th first data line is electrically connected to the first (m+1)th data line and the (m+1)th second data line The first pixel of the first (m+1)th second data line is electrically connected between the (m+1)th first data line and the (m+1)th second data line And the third pixel between the second (m+1)th data line and the (m+2)th first data line; the (m+2)th first data line electrical property The first pixels are located between the first (m+2)th data line and the (m+1)th second data line, and m and n are integers greater than or equal to zero. The driving circuit according to claim 1, wherein each of the first pixel systems is located in the (4n+2)th row and the (4n+4)th column (2m+1)th row of the (4n+2)th column. Each of the second pixel systems is located in the (4n+1)th row (2m+1) row and the (4n+3)th column (2m+2) row, respectively, and each of the third pixel systems is respectively Located in the (4m+1)th row of the (4n+2)th column and the (2m+2)th row of the (4n+4)th column, and each of the fourth pixel regions is located in the (4n+1)th column The (2m+2) row and the (4n+3)th column (2m+1) row. The driving circuit of claim 2, wherein the second pixels located in the (4n+1)th column and the fourth pixels are electrically connected to the (2n+1)th gate line, The second pixel in the (4n+3)th column and the fourth pixel and the first pixel in the (4n+2)th column and the third pixel system Electrically connected to the (2n+2)th gate line, and the first pixels in the (4n+4)th column are electrically connected to the third pixel system to the second (2n+3) ) The gate line. The driving circuit according to claim 1, wherein each of the first pixel systems is located in the (4n+1)th row and the (2n+2)th column (4m+1) row in the (2n+1)th column. Each of the second pixel systems is located in the (2n+1)th row (4m+1) row and the (2n+2)th column (4m+4) row, respectively, and each of the third pixel systems is respectively Located in the (4m+2)th row of the (2n+1)th column and the (4m+3)th row of the (2n+2)th column, and each of the fourth pixel regions is located in the (2n+1)th column The (4m+3) row and the (2n+2)th column (4m+2) row. The driving circuit of claim 4, wherein the second pixels located in the (2n+1)th column and the fourth pixels are electrically connected to the (2n+1)th gate line, The second pixel in the (2n+2)th column and the fourth pixel and the first pixel in the (2n+1)th column and the third pixel system Electrically connected to the (2n+2)th gate line, and the first pixels in the (2n+2)th column are electrically connected to the third pixel system to the second (2n+3) ) The gate line. The driving circuit of claim 1, wherein each of the first pixels includes a first switching element and a first pixel electrode, and each of the second pixels includes a second switching element and a second picture Each of the third pixels includes a third switching element and a third pixel electrode, and each of the fourth pixels includes a fourth switching element and a fourth pixel electrode. The driving circuit of claim 6, wherein each of the first pixel electrodes is electrically connected to a drain of each of the first switching elements, and each of the second pixel electrodes is electrically connected to each of the second switching elements. Each of the third pixel electrodes is electrically connected to the drains of the third switching elements, and each of the fourth pixel electrodes is electrically connected to the drains of the fourth switching elements. The driving circuit of claim 6, wherein a source of each of the second switching elements is electrically connected to a drain of each of the first switching elements, and a source of each of the fourth switching elements is electrically connected to The drain of each of the third switching elements. The driving circuit of claim 1, further comprising a first data driving circuit and a second data driving circuit, wherein the first data driving circuit is electrically connected to the first data lines, and the second data driving The circuit is electrically connected to the second data lines. The driving circuit of claim 9, wherein the first data driving circuit is configured to transmit a first viewing angle display data, and the second data driving circuit is configured to transmit a second viewing angle display material. The driving circuit of claim 9, wherein the first data driving circuit is configured to transmit a first display data having a sharpness value, and the second data driving circuit is configured to transmit a comparison value. a second display material of the (contrast value), wherein the first display material and the second display material form a three-dimensional picture material. The driving circuit of claim 9, wherein the first data driving circuit is configured to transmit a first pattern data having a first brightness, and the second data driving circuit is configured to transmit a second color having a second brightness Pattern data, and the first brightness is less than the second brightness. A display panel comprising: a substrate; the driving circuit according to claim 1 is disposed on the substrate; a color filter substrate; and a liquid crystal layer disposed between the substrate and the color filter substrate .