TW201142783A - Display panel and driving circuit thereof - Google Patents

Display panel and driving circuit thereof Download PDF

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TW201142783A
TW201142783A TW99116629A TW99116629A TW201142783A TW 201142783 A TW201142783 A TW 201142783A TW 99116629 A TW99116629 A TW 99116629A TW 99116629 A TW99116629 A TW 99116629A TW 201142783 A TW201142783 A TW 201142783A
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Taiwan
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data
line
pixel
driving circuit
gate
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TW99116629A
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Chinese (zh)
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TWI404014B (en
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Ke-Chih Chang
Kuo-Yu Huang
Ze-Yu Yen
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Au Optronics Corp
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Abstract

The present invention provides a driving circuit, including a plurality of gate lines, a plurality of first data lines, a plurality of second data lines, a plurality of first sub-pixels, a plurality of second sub-pixels, a plurality of third sub-pixels and a plurality of fourth sub-pixels. The first sub-pixels, the second sub-pixels, the third sub-pixels and the fourth sub-pixels are arranged in matrix. Each second sub-pixel is respectively electrically connected to each first sub-pixel, and each first sub-pixel is electrically connected to the corresponding first data line. Each fourth sub-pixel is respectively electrically connected to each third sub-pixel, and each third sub-pixel is electrically connected to the corresponding second data line.

Description

201142783 六、發明說明: 【發明所屬之技術領域】 本發明係關於一種顯示面板及其驅動電路,尤指一種由兩組半源 極驅動(half source driver,HSD)電路所組成之驅動電路與應用此驅 動電路之顯示面板。 【先前技術】 目前的液晶顯示器主要可分為三類:穿透式液晶顯示器、反射式 液晶顯示器、半穿反式液晶顯示器。穿透式液晶顯示器需要一背光 模組,且具有耗電量過大及環境光太強時顯示不清等問題。反射式 液晶顯示器以反射電極層取代透明電極層,不需背光模組,但在黑 暗環境下無法作用。半穿反式液晶顯示H同時具有紐區及反射 區’可避免全穿透式或全反射式之缺點。 習知半穿反式液晶顯示面板可進一步區分成單液晶間隙型 (_e ceU gap)與雙液晶間隙型(dual cell gap)。單液晶間隙型半穿反 式液晶顯示面板之反射區與穿透區具有相_液晶間隙,然而由於 ㈣區的魏光與穿賴的背光源兩者絲差不同,因此造成反射 區與穿透區的伽瑪曲線(Gammacurve)不同,而無法兼顧反射模式與 穿透模式的最佳光學絲。為了解決因絲差的不同所造成之反射 區域與穿透區域的伽瑪曲射同,因而發展出雙液晶間隙型半穿反 式液晶顯示面板。請參考第1圖,第1圖繪示了習知雙液晶間隙型 201142783 ^不裝置^含有—陣列基板2〇、-彩色遽光片基板3G與一液 日〆刀子層40设置於陣列基板2〇與彩色遽光片基板 30之間。陣列基 板2〇與彩色滤光片基板3〇定義有複數個晝素區22,且各書素區22 均包含有-反射區27與一穿透區28。為了清楚表示出各晝素區22 t结構’第1圖中僅綠示一個晝素區22作為說明。各書素區22之 陣列基板况包含有一第—基板%、一保護層%以及一晝素電極 • 32 ’其中保㈣26設於液晶分子層4()與第—基板%之間,且畫素 電極32設於保護層26與液晶分子層%之間。並且,設於穿透區 28之畫素f極32係為—翻電極瓜,而設於反舰π之畫素電 極32係為-反射電極32b。各畫素區22之彩色遽光片基板邓包含 有-第二基板34、-彩色遽光片36、—凸塊卿以及一共通 電極42,彩色光片30設於液晶分子層烈與第二基板%之間, 且共通電極42設於彩色遽光片3〇與液晶分子層2〇之間。凸塊% 馨係設於反射區27之共通電極42與彩色滤光片%之間,以縮小反射 區27之液晶分子層40之厚度,亦即降低反射區27之液晶間隙,使 雙液晶間隙型半穿反式液晶顯示面板之反射區27的液晶間隙約為 穿透區28的液晶間隙的一半’藉此使反射區27的環境光與穿透區 28的背光源的光程差相同,在此狀況下可使反射區27與穿透區 具有一致的伽瑪曲線。 然而,由於雙液晶間隙型半穿反式液晶顯示面板必翻用額外 製程於反㈣設置凸塊來調整液,因此增加製程複雜度,進 201142783 而造成生產成本提高的問題。 【發明内容】 本發月之目的之一在於提供一種顯示面板及其驅動電路,驅動電 ⑽由兩組半_驅動電_域,时職動穿賴與反射區之 次晝素,進而解決習知技術之上述問題。 為達上述之目的’本發明提供-獅動電路,其包純數條開極 線、複數條第1料線、複數條第二資料線、複數個第-次畫素、 複數個第二次晝素、複數個第三次畫素以及複數個第四次晝素。其 中^第(m+1)條第二資料線設於第(m+丨)條第—資料線與第㈣)條第 -身料線之間’且第(m+2)條第-資料線設於第(m+1)條第二資料線 與第(m+2)條第二資料線之間^第—次晝素分別設於兩相鄰之第 (2n+l)條閘極線與第(2n+2)條閘極線之間與兩相_之第_骑第二 貝料線與第(m+2)條第-資料線之間,以及兩相鄰之第(2n+2)條間極 線與第(2n+3)條閘極線之間與兩相鄰之第(m+1)條第一資料線與第 (m+1)條第二資料線之間。第二次晝素分別設於兩相鄰之第(2n+l) 條閘極線與第(2n+2)條閘極線之間與兩相鄰之第(m+丨)條第一資料 線與第(m+1)條第二資料線之間,以及兩相鄰之第(2n+2)條閘極線與 第(2n+3)條閘極線之間與兩相鄰之第(m+2)條第一資料線與第(m+1) 條第二資料線之間。各第二次晝素分別電性連接至各第一次晝素。 第三次晝素分別設於兩相鄰之第(2n+l)條閘極線與第(2n+2)條閘極 線之間與兩相鄰之第(m+1)條第一資料線與第(m+1)條第二資料線之 201142783 - 間’以及兩相鄰之第(2n+2)條閘極線與第(2n+3)條閘極線之間與兩相 鄰之第(m+2)條第一資料線與第(m+1)條第二資料線之間。第四次晝 素分別設於兩相鄰之第(2n+l)條閘極線與第(2n+2)條閘極線之間與 兩相鄰之第(m+1)條第二資料線與第(m+2)條第一資料線之間,以及 兩相鄰之第(2n+2)條閘極線與第pn+3)條閘極線之間與兩相鄰之第 (m+1)條第一資料線與第(m+1)條第二資料線之間。各第四次晝素分 別電性連接至各第三次晝素,且第一次晝素、第二次晝素、第三次 φ 畫素與第四次晝素呈矩陣方式排列。其中,第(2n+l)條閘極線電 性連接位於第(2n+l)條閘極線與第(2n+2)條閘極線間之第二次晝 素與第四次晝素;第(2n+2)條閘極線電性連接位於第(2n+1)條 閘極線與第(2n+2)條閘極線間之第一次晝素與第三次晝素,以及電 性連接位於第(2n+2)條閘極線與第(2n+3)閘極線間之第二次晝素與 第四次晝素;第(2n+3)條·線電性連接位於第(2n+2)條閘極線 :、第(2n+3)閘極線間之第—次晝素與第三次晝素;第(㈣)條第一資 籲料線電性連接位於第(m+·第一·線與第(m+i)條第二資料線之 1之第-人晝素,第(m+l)條第二資料線電性連接位於第(_)條第 一資料線與第(m+1)條第二資料線之間,與位於第(m+1)條第二資料 Ί、第(m+2)條第-資料線之間之第三次晝素;第條第一資料 線電性連接位於第(m+2)條第一資料線與第條第二資料線之間 之第一次畫素,而出與!!為大於等於〇的整數。 為達上述之目的,本發明另提供—種顯示面板,其包括一基板、 上迷驅動電路、-彩色遽光片基板以及—液晶層。驅動電路設於基 201142783 板上且液阳層设於基板與彩色遽光片基板之間。 本發明將穿透區之次晝素與反射區之次畫素分別連接至不同資 料線,使反射區之次晝素所接收到高準位的電壓值可與穿透區之次 畫素所接收到之高準位值抑,#此紐區之次晝素所顯示出 伽瑪曲線可與反㈣之次晝素賴示出㈣崎相隨,以避免因 穿透區與反射區具有相同液晶間隙所造成伽瑪曲線不同。 【實施方式】 為使熟習本發明所屬技術領域之一般技藝者能更進一步了解本 發明,下文特列舉本發明之較佳實施例,並配合所附圖式,詳細說 明本發明的構成内容及所欲達成之功效。 請參考第2圖與第3圖,第2圖繪示了本發明第一實施例之顯示 面板的剖面示意圖,第3圖繪示了本發明第一實施例之顯示面板的 驅動電路示意圖。如第2圖所示,顯示面板1〇〇包括一基板1〇2、 一彩色濾光片基板104、一液晶層106以及一驅動電路1〇8。基板 102與彩色遽光片基板1〇4相對設置’且液晶層1〇6設於基板1〇2 與彩色濾光片基板104之間,而驅動電路1〇8設於基板1〇2與液晶 層106之間。於本實施例中,顯示面板10〇係為單液晶間隙型半穿 反式液晶顯示面板,而僅具有單一液晶間隙(cell gap)d,並且顯示面 板定義有複數個穿透區T與複數個反射區R。如第3圖所示,驅動 電路108包括複數條閘極線GLrGLx、複數條第一資料線DLrDLy、 201142783 複數條第二資料線、複數個第—次晝素Ρι、複數個第二次 晝素P2、複數個第三次晝素&以及複數個第四次畫素匕,其中第 -次晝素?】、第:次晝素P2、第三次畫素&與第四次晝素&係呈 矩陣方式排列’且X與y為大於等於!的正整數。並且,各第一次 畫素P,與各第二次晝素!>2分職於各穿透區了内,而各第三次晝 素P3與各第四次晝素1>4分別位於各反射區尺内。此外,間極線旦 GLrGLx與第-資料線DLi_DLy以及第二資料線叫叫大體上互 相垂直’且第-資料、線DLrDLy與第二資料線叫叫大體上互 平行。 其中,第(m+1)條第二資料線虹㈣)設於第㈣)條第一資料線 DL(m+1)與第(m+2)條第一資料線DL(m+2)之間,且第(m+2)條第一資料 線DL(m+2)設於第(m+1)條第二資料線虹(_)與第(m+2)條第二資料 線虹(m+2)之間。各第一次晝素p丨分別設於兩相鄰之第(2州则極 線GL(2n+1〉與第(2n+2)條閘極線GW2)之間與兩相鄰之第㈣则 二資料線RL㈣)與第㈣)條第一資料線DL㈣)之間,以及兩相鄰 之第㈣)條間極線沉㈣與第(2n+3)條閘極 鄰之第㈣)條第-資料線DL㈣)與第㈣)條第二資料線虹㈣ 之間。各第二次晝素P2分別設於兩相鄰之第(2州则極線^丨) 與第(2n+2)條閘極線GL(2n+2)之間與兩相鄰之第㈣)條第一資料線 DL㈣與第㈣)條第二資料線虹㈣)之間,以及兩相鄰之第㈣) 條閘極線GL(2n+2)與第(2n+3__ GL㈣之财兩相鄰之第 ㈣2)條第-資料線DL㈣與第㈣)條第二資料線虹㈣之間* 201142783 於兩相鄰閘極線GLrGLx與兩相鄰第一資料線DLrDLy之間的第一 次晝素P!與第二次晝素P2係彼此電性連接。各第三次畫素込分別 設於兩相鄰之第(2n+l)條閘極線GL(2n+1}與第(2n+2)條閘極線GL(2n+2) 之間與兩相鄰之第(m+1)條第一資料線DL(m+i}與第(m+1)條第二資幻 料線RL(m+1}之間,以及兩相鄰之第(2n+2)條閘極線证㈣)與第如+3) 條閘極線GL(2n+3)之間與兩相鄰之第(m+2)條第一資料線DL_)與第 (m+1)條第二資料、線RL(m+1)之間。各第四次晝素?4分別設於兩相鄰 之第(2n+l)條閘極線GL(2n+1}與第(2n+2)條閘極'線沉㈣之間與兩相 鄰之第(m+1)條第二資料線虹―)與第(m+2)條第一資料線dl_) 之間’以及兩相鄰之第(2n+2)條閘極線证㈣與第(Μ3)條間極線 gl(2„+3)之間與兩相鄰之第(m+丨)條第一資料線DL_)與第扣+丨)條 第二資料線虹㈣叫之間。位於兩相鄰閘極線GLi_GLx與兩相鄰第二 資料線RL i - RLy之間的第三次晝素p3與第四次畫素係彼此電性連 接。 並且,第(2n+l)條閘極線GL(2n+1》電性連接位於第(2n+1)條 閘極線GL(2n+1>與第(2計2)條閘極線沉㈣間之第二次畫素&與第 四次晝素P4。第(2n+2)條閘極線(}1^211+2)電性連接位於第(2n+1) 條閘極線GL^與第(211+2)條閘極線(^+2)間之第一次畫素&與 第三次畫素込,以及電性連接位於第(2n+2)條閘極線沉^)與第 (2n+3)閘極線GL(2„+3)間之第二次畫素P2與第四次晝素p4。第(2n+3 ) 條閘極線電性連接位於第(2n+2)條閘極線GL_)與第(2n+3) 閘極線GL(2„+3)間之第一次畫素P丨與第三次晝素p3。並且,第(m+i) 201142783 '條第一貝料線DL(m+1)電性連接位於第(m+l)條第一資料線DL(_)與 第(m+1)條第二資料線虹(_)之間之第一次晝素&。第扣+ i)條第二 資料線RL(m+1)電性連接位於第(m+1)條第一資料線DL(m+i)與第(酬) 條第二資料線DL(m+i)之間,與位於第(m+i)條第二資料、線虹㈣)與 第(m+2)條第-資料'線沉㈣之間之第三次晝素。帛(m+2)條第一 資料線DL(m+2)電性連接位於第(m+2)條第一資料線DL(m+2)與第(m+i) 條第一:貝料線DL(m+1)之間之第一次晝素& ’而爪與n為大於等於〇 •的整數。由此可知,第二次晝素Ρ2電性連接至第一次晝素?丨,且第 一次晝素卩!係電性連接至相對應之第一資料線(%、%、% 或DLy),因此用於顯示穿透區τ之晝面的顯示資料訊號可藉由各第 一資料線狐、DL2、DL3.·.或DLy)傳遞至第一次晝素Pl與第二次 畫素P2。同理,第四次晝素A係電性連接至第三次晝素p3,且第 三次畫素P3係電性連接至相對應之第二資料線(RLi、虹2、虹〗.或 RLy),因此用於顯示反射區R之晝面的顯示資料訊號可藉由各第二 資料線(RLl、虹2、肛3…或RLy)傳遞至第三次畫素p3與第四次畫 •素 P4。 於本實施例中’各第一次畫素P,係分別位於第(4n+2)列第(2m+2) 行與第(4n+4)列第(2m+l)行,各第二次畫素!>2係分別位於第(4n+1) 列第(2m+l)行與第(4n+3)列第(2m+2)行,各第三次晝素p3係分別位 於第(4n+2)列第(2m+1)行與第(4n+4)列第(2m+2)行,且各第四次晝素 P4係分別位於第(4n+l)列第(2m+2)行與第(4n+3)列第(2m+l)行。並 • 且,位於第(3m+1)行之第一次畫素卩丨、第二次晝素p2、第三次晝素 11 201142783 P3與第四次晝素P4可為紅色次晝素’位於第(3m+2)行之第_次晝素 Pi、第一次晝素P2、第二次晝素P3與第四次晝素Pa可為綠色次書' 素’且位於第(3m+3)行之第一次畫素h、第二次畫素p2、第三次查 素匕與第四次晝素P4可為藍色次晝素,但不限於此,本發明之紅 色次畫素、綠色次晝素或藍色次畫素之位置亦可彼此互換。 另外,各第一次晝素卩1 電極P& ’且各第一畫素電極PEl電性連接至各第一開關元件s^i' 之没極。各第二次畫素P2包括一第二開關元件SW2與一第二晝素電 極PE2 ’且各第二畫素雜鸣電性連接至各第二開關元件撕丨之 汲極。本實施例之第-晝素電極PEl與第二晝素電極吗係由透明 導電層所構成,例如:氧化銦錫(IT〇)或氧化鋼辞(IZ〇)等,使位於 穿透區T内之第-次畫素Ρι與第二次畫素&可顧—背光源來顯 不畫面。各第二次畫素p3包括一第三開關元件⑽與一第三竺素電 極玛,且各第三晝素電極PE3電性連接至各第三開關元件^之 沒極。各第四次畫找包括—第四_元件%與—細畫錢極 PE4,且各第四畫素電極鸣雜連接至各第四開關元件抓之汲 ==素:極PE3與第四畫素電_係由具有高 幻如.金屬等,使位於反射區R内之第三 人二、P3與第四次畫素?4可_—環境光源來顯示晝面。並且, 第」:鄰r^GLrGLx與兩相鄰第,線〇叫之間的各 源極與各第一開關元件%之沒極係彼此電 在一起,且位於兩相鄰閘極線GLrGLX與兩相鄰第二資料線 12 201142783 DLrDLy之間的各第四開關元件gw*之源極與各第三開關元件^^3 之汲極彼此電性連接在一起,使位於不同行的第一次晝素Pi與第二 次晝素P2可以共用同一條第一資料線(DLi、DL2、DL3或DLy), 且位於不同行的第三次畫素&與第四次畫素h可以共用同一^第 一為料線(RL!、RL2、RL3…或RLy)。而位於第(4η+ι)列之第二開關 元件sw#第四開關元件SW4之閘極電性連接至第(2η+ι)條問極線 GL^+o ’位於第(4η+3)列之第二開關元件撕2與第四開關元件sw々 鲁之閘極以及位於第(如十2)列之第一開關元件sw丨與第三開關元件 SW3之閘極係電性連接至第(2_條閘極線沉㈣,位於第0㈣ 列之第一開關元件SW1與第三開關元件SW3之閘極係電性連接至 第(2n+3)條閘極線GL(2n+3)。 此外,驅動電路1〇8另包括一閘極驅動電路11〇、一第一資料驅 動電路112與一第三資料驅動電路114,其巾閘極驅動電路11〇電 性連接至各閘極線GLrGLx,且第一資料驅動電路112電性連接至 參各第-資料線(DL,、DL2、DL3.··或DLy),而第二資料驅動電路m 電性連接至各第二資料線(RLr^)。值得注意的是, 本發明將穿透區之第一次畫素P!與第二次畫素p2以及反射區之第 二次晝素P3與第二次畫素P4分別連接至相對應之第一資料線 (DL!、DL2、DL3…或DLy)與第二資料線(RLl、rl2、虹3或, 並利用第一資料驅動電路112電性連接所有第一資料線DLi_DLy, 以及利用第二資料驅動電路114電性所有第二資料線,因 • 此穿透區之第一次畫素卩!與第二次晝素匕可獨立接收從第一資料 13 201142783201142783 VI. Description of the Invention: [Technical Field] The present invention relates to a display panel and a driving circuit thereof, and more particularly to a driving circuit and application comprising two sets of half source driver (HSD) circuits The display panel of this drive circuit. [Prior Art] Current liquid crystal displays can be mainly classified into three types: transmissive liquid crystal displays, reflective liquid crystal displays, and transflective liquid crystal displays. A transmissive liquid crystal display requires a backlight module and has problems such as excessive power consumption and unclear display when the ambient light is too strong. The reflective liquid crystal display replaces the transparent electrode layer with a reflective electrode layer, and does not require a backlight module, but does not function in a dark environment. The trans-transparent liquid crystal display H has both a button and a reflective area to avoid the disadvantages of full penetration or total reflection. The conventional transflective liquid crystal display panel can be further divided into a single liquid crystal gap type (_e ceU gap) and a dual liquid crystal gap type (dual cell gap). The reflection area and the penetration area of the single liquid crystal gap type transflective liquid crystal display panel have a phase-liquid crystal gap. However, since the difference between the Weiguang and the backlight of the (four) area is different, the reflection area and the penetration are caused. The gamma curve of the zone is different, and the best optical fiber cannot be combined with the reflection mode and the penetration mode. In order to solve the gamma curvature of the reflection region and the penetration region caused by the difference in the filament difference, a double liquid crystal gap type transflective liquid crystal display panel has been developed. Please refer to FIG. 1 . FIG. 1 illustrates a conventional dual liquid crystal gap type 201142783. The device does not include an array substrate 2 , a color light plate substrate 3G and a liquid coring knife layer 40 are disposed on the array substrate 2 . Between the crucible and the color slab substrate 30. The array substrate 2 and the color filter substrate 3 are defined with a plurality of halogen regions 22, and each of the pixel regions 22 includes a reflection region 27 and a penetration region 28. In order to clearly show the structure of each of the halogen regions 22 t, only one pixel region 22 is shown green in the first drawing. The array substrate condition of each of the pixel regions 22 includes a first substrate %, a protective layer %, and a halogen electrode • 32 ' wherein the (four) 26 is disposed between the liquid crystal molecular layer 4 () and the first substrate %, and the pixel The electrode 32 is provided between the protective layer 26 and the liquid crystal molecule layer %. Further, the pixel f-pole 32 provided in the penetrating region 28 is a flip-electrode, and the pixel electrode 32 provided in the anti-ship π is a-reflecting electrode 32b. The color light-emitting substrate of each pixel region 22 includes a second substrate 34, a color light-emitting sheet 36, a bump and a common electrode 42, and the color light sheet 30 is disposed on the liquid crystal layer and the second layer. Between the substrates %, and the common electrode 42 is provided between the color light-emitting sheet 3 and the liquid crystal molecule layer 2A. The bump % is disposed between the common electrode 42 of the reflective region 27 and the color filter % to reduce the thickness of the liquid crystal molecular layer 40 of the reflective region 27, that is, to reduce the liquid crystal gap of the reflective region 27, so that the double liquid crystal gap The liquid crystal gap of the reflective region 27 of the transflective liquid crystal display panel is about half of the liquid crystal gap of the transmissive region 28, thereby making the ambient light of the reflective region 27 and the optical path difference of the backlight of the transmissive region 28 the same, In this case, the reflection region 27 and the penetration region can be made to have a gamma curve. However, since the double liquid crystal gap type transflective liquid crystal display panel must use an additional process to adjust the liquid in the reverse (four) setting bumps, the process complexity is increased, and the production cost is increased by entering 201142783. SUMMARY OF THE INVENTION One of the purposes of the present month is to provide a display panel and a driving circuit thereof. The driving power (10) is composed of two sets of half-drive electric fields, and the secondary elements of the time-shifting and reflecting areas are further solved. Know the above problems of technology. In order to achieve the above purpose, the present invention provides a lion circuit comprising a plurality of open lines, a plurality of first lines, a plurality of second lines, a plurality of first-order pixels, and a plurality of second times. Alizarin, a plurality of third pixels, and a plurality of fourth pixels. Wherein the second (m+1)th data line of ^(m+1) is located between the first (m+丨)-data line and the fourth (fourth)-th body-line and the (m+2)th-data line Located between the second (m+1)th data line and the (m+2)th second data line, the first and second elements are respectively located at two adjacent (2n+l) gate lines. Between the (2n+2) gate line and the two phases _ the first _ riding second and the (m + 2) first - data line, and the two adjacent (2n + 2) Between the inter-strip pole line and the (2n+3)-th gate line and between the two adjacent (m+1)th first data lines and the (m+1)th second data line. The second element is set between the two adjacent (2n+l) gate lines and the (2n+2) gate lines and the two adjacent (m+丨) first data lines. Between the (m+1)th second data line and the two adjacent (2n+2) gate lines and the (2n+3)th gate lines and the two adjacent ones ( m+2) between the first data line and the (m+1) second data line. Each of the second halogens is electrically connected to each of the first halogens. The third element is set between the two adjacent (2n+l) gate lines and the (2n+2) gate lines and the two adjacent (m+1) first data. Between the line and the (m+1) second data line 201142783 - between the two adjacent (2n + 2) gate lines and the (2n + 3) gate lines and two adjacent Between the (m+2)th first data line and the (m+1)th second data line. The fourth element is set between the two adjacent (2n+l) gate lines and the (2n+2) gate lines and the two adjacent (m+1) second data. Between the line and the (m+2)th first data line, and between the two adjacent (2n+2) gate lines and the pn+3) gate lines and the two adjacent ones ( m+1) between the first data line and the (m+1)th second data line. Each fourth element is electrically connected to each third element, and the first element, the second element, the third piece of φ pixel and the fourth element are arranged in a matrix. Wherein, the (2n+l) gate line is electrically connected to the second and fourth halogens between the (2n+1)th gate line and the (2n+2)th gate line The (2n+2) gate line is electrically connected to the first and third halogens between the (2n+1)th gate line and the (2n+2)th gate line. And electrically connecting the second and fourth halogens between the (2n+2)th gate line and the (2n+3)th gate line; the (2n+3) strip line property Connected to the (2n+2) gate line: the (2n+3) gate line between the first and second elements and the third element; ((4)) Connecting the first-human element in the (m+·first line and the (m+i)th second data line, the (m+l)th second data line is electrically connected (_) Between the first data line and the (m+1) second data line, and the third between the (m+1) second data 第 and the (m+2) first data line The second pixel is electrically connected to the first pixel between the first (m+2)th data line and the second data line, and the !! is greater than or equal to 〇 Integer. To achieve the above The invention further provides a display panel comprising a substrate, an upper driving circuit, a color light-emitting substrate and a liquid crystal layer, wherein the driving circuit is disposed on the base 201142783 and the liquid-yang layer is disposed on the substrate and the color light Between the substrate and the substrate. The present invention connects the secondary elements of the penetrating region and the sub-pixels of the reflective region to different data lines, so that the voltage value of the secondary region of the reflective region receives the high level and the penetrating region. The high-level value received by the second pixel is suppressed. #The second element of the nucleus shows that the gamma curve can be matched with the inverse (four). The gamma curve is different from the reflection area having the same liquid crystal gap. [Embodiment] In order to make the present invention more familiar to those skilled in the art to which the present invention pertains, the preferred embodiments of the present invention are exemplified below. The present invention will be described in detail with reference to FIG. 2 and FIG. 3, and FIG. 2 is a cross-sectional view showing the display panel of the first embodiment of the present invention. The figure shows the first invention A schematic diagram of a driving circuit of a display panel of an embodiment. As shown in FIG. 2, the display panel 1A includes a substrate 1 〇 2, a color filter substrate 104, a liquid crystal layer 106, and a driving circuit 1 〇 8. 102 is disposed opposite to the color slab substrate 1 ' 4 and the liquid crystal layer 1 〇 6 is disposed between the substrate 1 〇 2 and the color filter substrate 104, and the driving circuit 1 〇 8 is disposed on the substrate 1 〇 2 and the liquid crystal layer In the present embodiment, the display panel 10 is a single liquid crystal gap type transflective liquid crystal display panel, and has only a single cell gap d, and the display panel defines a plurality of penetrating regions. T and a plurality of reflection regions R. As shown in Fig. 3, the driving circuit 108 includes a plurality of gate lines GLrGLx, a plurality of first data lines DLrDLy, 201142783, a plurality of second data lines, and a plurality of first-order 昼素Ρ , a plurality of second halogen P2, a plurality of third halogens & and a plurality of fourth pixels, wherein the first-times? 】, the first: the second pixel P2, the third pixel & and the fourth time the prime & is arranged in a matrix manner 'and X and y are greater than or equal! Positive integer. Further, each of the first pixel P, and each of the second pixels!>2 are divided into the respective penetration regions, and each of the third pixel P3 and each of the fourth pixels 1 > 4 respectively Located in each reflective area. In addition, the inter-polar line GLrGLx is substantially perpendicular to the first data line DLi_DLy and the second data line, and the first data, the line DLrDLy and the second data line are called substantially parallel to each other. Wherein, the (m+1)th second data line rainbow (4)) is set in the first (4)th data line DL(m+1) and the (m+2)th first data line DL(m+2) And the (m+2)th first data line DL(m+2) is set in the (m+1)th second data line rainbow (_) and the (m+2)th second data line Between rainbows (m+2). Each of the first prime p丨 is set between two adjacent (the second state is the line GL (2n+1> and the (2n+2) gate line GW2) and the two adjacent (four) Then between the second data line RL(4)) and the (4)) first data line DL(4)), and between the two adjacent (4)) poles (4) and (2n+3) gates (4) The first - data line DL (four)) and the fourth (4)) data line between the rainbow (four). Each of the second halogen P2 is respectively disposed between two adjacent (the second state is the polar line ^丨) and the second (2n + 2) gate line GL (2n + 2) and the two adjacent (four) ) between the first data line DL (4) and the (4)) second data line rainbow (4)), and the two adjacent (4)) gate lines GL (2n + 2) and the second (2n + 3__ GL (four) of the two Adjacent to (4) 2) - data line DL (4) and (4)) second data line rainbow (4) * 201142783 between the two adjacent gate lines GLrGLx and the two adjacent first data lines DLrDLy for the first time The halogen P! and the second halogen P2 are electrically connected to each other. Each of the third pixels is respectively disposed between two adjacent (2n+l) gate lines GL(2n+1} and (2n+2) gate lines GL(2n+2). The two adjacent (m+1)th first data lines DL(m+i} and the (m+1)th second imaginary line RL(m+1}, and two adjacent (2n+2) gate line certificate (4)) and the same as the +3) gate line GL (2n+3) and the two adjacent (m+2) first data line DL_) and (m+1) between the second data and the line RL(m+1). The fourth time? 4 is respectively set between two adjacent (2n+l) gate lines GL(2n+1} and (2n+2) gates' line sinks (four) and two adjacent (m+1) ) between the second data line rainbow --) and the (m+2) first data line dl_) and between the two adjacent (2n+2) gate lines (4) and (3) Between the polar line gl (2 „ + 3) and the two adjacent (m + 丨) first data line DL_) and the first buckle + 丨) second data line rainbow (four) called. The third pixel p3 and the fourth pixel between the polar line GLi_GLx and the two adjacent second data lines RL i - RLy are electrically connected to each other. And, the (2n+1)th gate line GL ( 2n+1" electrically connected to the second pixel & and the fourth time between the (2n+1)th gate line GL (2n+1> and the (2 count 2) gate line sink (4) Alizarin P4. The (2n+2) gate line (}1^211+2) is electrically connected to the (2n+1) gate line GL^ and the (211+2) gate line ( ^+2) The first pixel & and the third pixel, and the electrical connection are located at the (2n+2) gate line sinking ^) and the (2n+3) gate line GL The second pixel P2 between (2„+3) and the fourth pixel p4. (2n+3) gate line The first connection between the (2n+2)th gate line GL_) and the (2n+3)th gate line GL(2„+3) is the first pixel P丨 and the third pixel p3. , (m+i) 201142783 'The first batting line DL(m+1) is electrically connected at the (m+l)th first data line DL(_) and the (m+1)th second The first data element between the data line rainbow (_) and the first data line RL(m+1) is electrically connected to the first data line DL (m+1) m+i) and the second data line DL(m+i) of the (remuneration), and the second data, the line (4) and the (m+2) of the (m+i) The third parameter between the data line (4). 帛(m+2) The first data line DL(m+2) is electrically connected at the (m+2)th first data line DL(m+ 2) and the first (m+i) first: the first element of the batting line DL (m+1) & 'and the claw and n are integers greater than or equal to 〇•. It can be seen that The secondary halogen Ρ 2 is electrically connected to the first 昼 丨 丨, and the first 昼 卩 卩 is electrically connected to the corresponding first data line (%, %, % or DLy), and thus is used for The display data signal showing the area of the penetration area τ can be obtained by the first data line fox, DL2, DL 3.·. or DLy) is transmitted to the first halogen Pl and the second pixel P2. Similarly, the fourth halogen A is electrically connected to the third halogen p3, and the third pixel The P3 system is electrically connected to the corresponding second data line (RLi, Rainbow 2, Rainbow, or RLy), so the display data signal for displaying the back surface of the reflective area R can be obtained by each second data line (RLl) , Rainbow 2, Anal 3... or RLy) is passed to the third pixel p3 and the fourth painting P4. In the present embodiment, each of the first pixels P is located in the (2n+2)th row and the (4n+4)th column (2m+1) row in the (4n+2)th column, and each second. The second pixel is located in the (4n+1)th column (2m+l) row and the (4n+3)th column (2m+2) row, and each third pixel element p3 system is located. In the (4n+1)th column (2m+1) row and the (4n+4)th column (2m+2) row, and each fourth pixel Alimentin P4 system is located in the (4n+l)th column ( 2m+2) rows and (4n+3) columns (2m+l) rows. And •, the first pixel in the (3m+1) row, the second pixel p2, the third pixel 11 201142783 P3 and the fourth halogen P4 can be red secondary The first 昼 昼 Pi Pi, the first 昼 P P2, the second 昼 P P3, and the fourth 昼 Pa Pa can be the green sub-study and located at the (3m+) 3) The first pixel h, the second pixel p2, the third pixel, and the fourth pixel P4 may be blue secondary halogen, but are not limited thereto, and the red secondary painting of the present invention The positions of the prime, green secondary or blue sub-pixels can also be interchanged. In addition, each of the first pixel electrodes P& and each of the first pixel electrodes PE1 is electrically connected to the second pole of each of the first switching elements s^i'. Each of the second pixels P2 includes a second switching element SW2 and a second halogen electrode PE2' and each of the second pixel noises is electrically connected to the drain of each of the second switching elements. The first halogen electrode PE1 and the second halogen electrode of the embodiment are composed of a transparent conductive layer, for example, indium tin oxide (IT〇) or oxidized steel (IZ〇), etc., so as to be located in the penetration region T The first-time pixel Ρι and the second pixel & can be considered - the backlight to display the picture. Each of the second pixels p3 includes a third switching element (10) and a third halogen element, and each of the third element electrodes PE3 is electrically connected to the third switching element. Each of the fourth paintings includes - the fourth_component % and the fine-grained money pole PE4, and each fourth pixel electrode is connected to each of the fourth switching elements. 汲 == prime: pole PE3 and fourth painting Is it a third person, a P3, and a fourth pixel located in the reflection zone R? 4 can be _- ambient light source to display the surface. And, the first: the adjacent r^GLrGLx and the two adjacent first, the source between the line squeak and the first switching element% of the non-polar system are electrically connected to each other, and located at two adjacent gate lines GLrGLX and The source of each of the fourth switching elements gw* between the two adjacent second data lines 12 201142783 DLrDLy and the anodes of the third switching elements ^3 are electrically connected to each other, so that the first time in different rows The alizarin Pi and the second alizarin P2 may share the same first data line (DLi, DL2, DL3 or DLy), and the third pixel & located in different rows may share the same same as the fourth pixel h ^The first is the feed line (RL!, RL2, RL3... or RLy). The gate of the second switching element sw# of the fourth (4n+ι) column is electrically connected to the (2n+ι)th line GL^+o ' at the (4n+3) The second switching element tearing 2 and the fourth switching element sw々 and the gate of the first switching element sw丨 and the third switching element SW3 in the (eg, twelfth) column are electrically connected to the first (2_ gate line sinking (4), the gates of the first switching element SW1 and the third switching element SW3 in the 0th (fourth) column are electrically connected to the (2n+3)th gate line GL(2n+3) In addition, the driving circuit 1 8 further includes a gate driving circuit 11 , a first data driving circuit 112 and a third data driving circuit 114 , and the pad gate driving circuit 11 is electrically connected to each gate line. GLrGLx, and the first data driving circuit 112 is electrically connected to each of the first data lines (DL, DL2, DL3, . . . or DLy), and the second data driving circuit m is electrically connected to each of the second data lines ( RLr^). It is worth noting that the present invention connects the first pixel P! of the penetrating region with the second pixel p2 and the second pixel P3 and the second pixel P4 of the reflection region, respectively. Corresponding a data line (DL!, DL2, DL3, ... or DLy) and a second data line (RL1, rl2, rainbow 3 or, and electrically connected to all of the first data lines DLi_DLy by the first data driving circuit 112, and using the second The data driving circuit 114 electrically treats all the second data lines, because the first pixel of the penetrating zone is 卩! and the second pixel can be independently received from the first data 13 201142783

所傳送的穿親之顯讀料訊號,而反射區之第三次 二「晝素Ρ4可獨立接收從第二資料驅動電路114所傳 达的反射區之顯示資料訊號。 y θ由於帛貞料购電路與第二資料鶴電路可分別提 二=資料訊號至穿透區之第-次畫素與第二次晝素以及反 一人畫素與第四次晝素’因此第二資料驅動電路提供之高 >的電壓值可與第一資料驅動電路提供之高準位電壓值不同。並 t藉由修正第二資料驅動電路提供之高準位的電廢值,可使穿透 區之第-人畫素與第二次畫素所顯示出伽瑪曲線(Gamma curve)與 反射區之第—次畫素與第四次晝素所顯示出伽瑪曲線相匹配。因 此,即使本實施例之_面板係為單—液晶間隙之顯示面板,亦即 穿透區之液晶_:與反射區之液晶_侧,本發明之顯示面板仍 可避免因穿透區與反射區具有綱液晶_所造成伽瑪曲線不同。The transmitted reading signal of the wearing pass, and the third time of the reflective area 2 "the 昼 Ρ 4 can independently receive the display data signal of the reflective area conveyed from the second data driving circuit 114. y θ due to the data Buying the circuit and the second data crane circuit can separately provide the second data signal to the first-order pixel and the second pixel of the penetrating region and the inverse one-dimensional pixel and the fourth pixel. Therefore, the second data driving circuit provides The voltage value of the height > can be different from the high level voltage value provided by the first data driving circuit, and can be made by modifying the electrical waste value of the high level provided by the second data driving circuit. - The human pixel and the second pixel show that the gamma curve matches the gamma pixel of the reflection region and the gamma curve displayed by the fourth pixel. Therefore, even this embodiment The panel is a single-liquid crystal gap display panel, that is, the liquid crystal _: of the penetrating region and the liquid crystal_ side of the reflective region, and the display panel of the present invention can still avoid the liquid crystal due to the penetrating region and the reflecting region. Causes the gamma curve to be different.

為了清楚說示面板的運作原理,町描述以彻第—資料驅 動電路驅動穿透(1之第—次畫素與第二次晝素為例來做說明。請參 考第4圖與第5圖。第4麟示了本發明第—實關於顯示面板的 穿透區顯7Γ紅色晝㈣傳送至閘極軸第-資料線之齡資料訊號 時序圖’第5圖繪示了本發明第—實施例之穿透區的驅動電路示意 圖。為凊楚㈣次畫素之顯示狀況,第5圖之驅動電路僅繪示出4 條閘極線GLrGL4、3條第一資料線DLi_DL3、8個第一次晝素& 與8個第二次畫素P2 ’但實際上驅動電路之閘極_數、第一資料 14 201142783 * 線個數以及第一次晝素與第二次晝素的個數並不以此為限。如第4 圖與第5圖所示,穿透區之驅動電路係構成一第一半源極驅動(half source driver,HSD)電路 l〇8a,且各閘極線(GL!、GL2、GL3 或 GL4) 依序輸入波形為1011之閘極訊號,其中1為高準位,且〇為低準位, 各準位所持續的時間間隔彼此相同。首先,於第一時間間隔T1中, 第1條閘極線GL!與第2條閘極線GL2所傳遞之閘極訊號皆為高準 位’其餘閘極線GL3、GL4所傳遞之顯示資料訊號則為低準位,因 φ 此電性連接至第1條閘極線第二開關元件SW2與電性連接至 第2條閘極線GL2之第一開關元件SW〗與第二開關元件SW2會被 開啟。同時,第2條第一資料線Dl2傳送之顯示資料訊號為高準位, 而第1條第一資料線DLl與第3條第一資料線DL3傳送之顯示資料 訊號為低準位,因此第2條第一資料線DL2所傳送之顯示資料訊號 可儲存於第2行第2列之第一次晝素卩]以及第1行第丨列之第二次 畫素P2中。接著,於第二時間間隔丁2中,第2條閘極線gl2所傳 •送之閘極訊號轉換為低準位,因此關閉了第2列之第—開關元件 SW!與第3列之第二開關元件sw3。並且,第1條第—資料線叫 所傳送之況號轉換為高準位。然後,於第三時間間隔丁3中,第2條 閘極線GL2與第3條閘極線gl3傳遞之閘極訊號轉換為高準位,且 第1條閘極線GL!轉換為低準位,因此第3行第4列與第4行第2 列之第一開關元件SWi以及第4行第3列與第3行第5列之第二開 關元件SW2會被開啟。同時,第2條第一資料線DL2所傳遞之顯示 資料讯號轉換為高準位,因此顯示資料訊號會儲存於第3行第4列 之第一次晝素卩丨以及第4行第3列之第二次畫素&中。接著,於 15 201142783 第四時間間5¾ TV中,帛3條閘板線%之訊號轉換為低準位,因此 關閉了第3行第4列之第—開關元件SWi。同時,帛2條第—資料 線DL2之訊號轉換為低準位,使得儲存於第2行第2列之第—次書 素Pi的顯示資料訊號透過開啟之第一開關元件SWi傳遞至第2條第 一資料線DL2,而將第2行第2列之第一次畫素p1中之顯示資料訊 5虎移除。同時,第3條第-資料線DL3之訊號會轉換至高準位,使 第4打第2列之第一次晝素Ρι存入顯示資料訊號。然後,於第五時 間間隔τ5中’第2條閘極線%轉換為低準位,且第3條間極線 GL3與第4條閘極線ο。傳遞之閘極訊號轉換為高準位,而第2條 第一賣料線DL2所傳遞之顯示資料訊號為高準位,因此顯示資料訊 號存入第2行第6列之第一次晝素P!與第1行第5列之第二次晝素 p2中。接著’於第六時間間隔丁6中,第4條閘極線%之訊號轉換 為低準位’並且第2條第—倾線%之訊號倾換為低準位,而 第1條第一資料線DLl之訊號轉換至高準位,因此儲存於第3行第 4列之第-人畫素的顯示資料訊號會透過開啟之第一開關元件 SW,傳遞至第2條第—資料線%,而將第3行第4列之第一次畫 素Pl中的顯示資料訊號移除,並且於第1行第4列之第-次畫素忠 Pl中存入顯示資料訊號。以此類推,於各閘極線(GLl、GL2、^、 GL—或 GLX)依序輸人咖之閘極訊號,且每隔三個時間間隔輸入 一個時間間隔之顯示資料訊號至第伽+1)條第-資料線DL(㈣與 第(3m 3)條帛資料線沉口㈣y,而每隔一個時間間隔輸入一個時 間間隔之顯示資料訊號至第(3m+2)條第—資料線沉㈣,位於第 (3m+l)行之穿透區的紅色次畫素可被顯示出。值得注意的是,本發 16 201142783 明於第-時間間隔1時儲存顯 與非紅色之第-次書朴中1 =㈣於紅色之第二次晝素?2 ρ τ 辦__之第四時間間 mzttr色之第一次畫奸的顯示資料訊號移除。因 i第γγρ色之第二次畫素P2中時儲存至非紅色 至低準::被移:姻虎亦可於兩辦 •面=考透第「6晶圖與第7圖’第6崎示了本發明第一實施例於顯系 =區顯示綠色畫面時傳送至問極線與第一資料線之顯示資 顧=序圖’第7圖繪示了本發明第一實施例於顯示面板的第透 二二色旦面時傳运至閘極線與第—資料線之顯示資料訊號時序 顧-綠ώ 6騎7^,她錢示紅色畫輯提供之顯示資料訊號, 表色旦面時,每隔三個時間間隔輸入一個時間間隔之顯示資料 «至第(3阶2)條第一資料線沉㈣與第伽+3)條第一資料線 DL㈣)’ *每隔—辦_隔輸人—個_間隔之顯示資料訊號至 條第一資料線沉(㈣,位於第(3m+2)行之穿透區的綠色 :欠畫素可被顯示出。換言之,將第4圖中輸入至第(3111+1)條第一資 料線DL(3m+1)之顯示資料訊號改為輸入至第(3m+3)條第一資料線 ’將第4 U中輸入至第(Μ,條第一資料線DL_)之顯示 資料訊號改為輸入至第(如+1)條第-資料線DL^,將第4圖中 輸入至第(3m+3)條第一資料線〇1伽+3)之顯示資料訊號改為輸入至 第(3m+2)條第—資料、線DL(3m+2)即可呈現出 綠色晝面。如第7圖所 不將第4圖中輸入至第伽+丨)條第一資料線DL伽之顯示資料 17 201142783 =改為輸獨(3m+獅—嶋DW),物圖中輸入 第(3m+2)條第一資料線沉㈣之顯示資料訊號改為輸入至第 Ll 3)條第一資料線DL(3m+3),將第4圖中輸入至第伽+3)條第-貝料線DL—之顯示資料訊號改為輸入至第伽+1條第一資料線 DL(3m+u即可呈現出藍色晝面。 ,请參考第8圖,第8圖繪示了本發明第一實施例之反射區的驅動 電路不意圖。如第8圖所示,反射區之驅動電路 極驅動電路嶋,並且反·之驅動電路係財透區之驅動電路約 略相同。兩者之差異在於,第三次畫素&與第时晝素&之位置 係與第一次畫素ρι與第二次畫素P2之位置不同,因此位於第3行 第2列之第三次畫素p3雖與位於第2列第2行之第—次畫素&具 有相^之連接電路,但卻顯示不同之顏色1以,提供至反射區之 第--人晝素卩3與第四次晝素&之顯示資料訊麵加關整。於顯 示^色晝面時’第二資料驅動電路將第4圖中輸人至第(3m叫條第 一資料線DL(3m+1}之顯示資料訊號提供至第(3m+2)條第二資料線 虹㈣’將第4圖中輸入至第(3m+2)條第一資料線DL㈣之顯示 資料訊號提供至第(3价3)條第工資料線虹㈣,將第4圖中輸入至 第(3m+3)條第-資料線DL(3m+3)之顯示資料訊號提供至第(加+^條 第二資料線Rl^ma。於顯示綠色畫面時,第二資料驅動電路將第4 圖中輸入至第(3m+l)條第一資料線沉師)之顯示資料訊號提供至 第(3m+l)條第二資料、線叫㈣,將第4 中輸人至第(如十2)條第一 資料線DL(3m+2)之顯示資料訊號提供至第(3m+2)條第二資料線 18 201142783 RL⑽幻,將第4圖中輸入至第(3m+;3)條第一資料線沉㈣)之顧示 資料訊號提供至第(3m+3)條第二資料、線虹㈣。於顯示藍色晝面 時,第二資料驅動電路將第4圖中輸入至第(3m+1)條第一資料線 之顯示資料訊號提供至第(3m+3)條第二資料線,將 第4圖中輸入至第(3m+2)條第-資料線DL(3m+2)之顯*資料訊號提 供至第(3m+l)條第二資料線壯伽叫,將第4圖中輸入至第(如+3) 條第一資料線DL(3m+3)之顯示資料訊號提供至第(3m+2)條第一資料 線 DL(3m+2) 〇 請參考第9圖與第10圖,第9圖繪示了本發明第二實施例顯示 面板之驅動電路示意圖,第1〇圖繪示了本發明第二實施例之顯示面 板的顯示晝面示意圖。如第9圖所示,相較於第一實施例之顯示面 板’本實施例之驅動電路200的各第一次畫素?1係分別位於第(2η+ι) 列第(4m+4)行與第(2n+2)列第(4m+l)行,各第二次畫素匕係分別位 於第(2n+l)列第(4m+l)行與第(2n+2)列第(4m+4)行,各第三次畫素 &係分別位於第(2n+l)列第(4m+2)行與第(2n+2)列第(4m+3)行,且各 第四次畫素P4係分別位於第(2n+1)列第(4m+3)行與第(2n+2)列第 (4m+2)行。位於第(2n+1)列之第二次畫素P2與第四次晝素p4電性連 接至第(2n+l)條閘極線GL(2n+1),位於第(2n+2)列之第二次晝素P2與 第四次畫素P4以及位於第(2n+l)列之第一次畫素?丨與第三次畫素 P3係電性連接至第(2n+2)條閘極線GL(2n+2),且位於第(2n+2)列之第 一次畫素P!與第三次畫素係P3電性連接至第(2ii+3)條閘極線 GL(2n+3)。本實施例係將穿透區之第一次晝素P,與第二次晝素p2與 201142783 反射區之第三次晝素Pa與第四次晝素P4設於同—列,使穿透區與 反射區交替設於同一列。因此,如第10圖所示,於本實施例之顯示 面板202中,第一資料驅動電路112可用以傳送一第一視角顯示資 料,使接收到訊號之第一次畫素?!與第二次晝素p2顯示出一第一 視角晝面204 ’且第二資料驅動電路114可用以傳送一第二視角顯 示資料,使接收到訊號之第三次晝素&與第四次晝素p4顯示出一 第一視角晝面206。並且,顯示面板2〇2之前方係設置一具有雙折 射率之光學元件,使第一視角晝面204朝一角度射出,而第二視角 晝面206朝另一角度射出’藉此使得位於不同角度觀看顯示面板2〇2 的觀看者可以觀看到不同之顯示晝面。 另外’除了顯不二維畫面之外’本發明之顯示面板亦可應用於顯 不二維晝面。請參考第U圖,並請一併參考第3 _,第u圖繪示 了本發明之顯示面板顯示一種三維晝面之示意圖。如第3圖與第Η 圖所示,將一影像300區分為一具有一銳利值(shaipnessvalue)之第 一顯示資料302與-具有-對比值(c〇_tvalue)之第二顯示資料 304’^第-資料驅動電路可用以傳送第一顯示資料3〇2至穿透區之 第-人畫素Pi與第一次晝素Pz,且第二資料驅動電路可用以傳送第 ,顯示資料304至反射區之第三次畫奸與第四次晝素p4。因此, J用第_欠晝素Pl與第二次晝素^顯示影像之銳利值以及利 用第―人晝素卩3與第四次晝素p4顯示影像·之對比度,藉此第 〜顯不資料302與第二顯示資料304構成一三維畫面資料306,使 _示面板顯示出一三維畫面。 201142783 °月參考第12圖’並請一併參考第3圖,第12圖繪示了本發明之 顯不面板顯示另一種三維畫面之示意圖。如第3圖與第12圖所示, 將一影像350區分為一具有一第一亮度之第一圖案資料352與一具 有一第二亮度之第二圖案資料354,而第一資料驅動電路可用以傳 送第圖案資料至穿透區之第一次晝素Ρι與第二次畫素P2’第二資 料驅動電路可用以傳送第二圖案資料至反射區之第三次畫素!>3與 • 第四次晝素匕,並且本發明利用第一亮度小於第二亮度來呈現第一 圖案資料352係位於第二圖案資料354的後方,藉此呈現出具有不 同景深之第一圖案資料352與第二圖案資料354,進而顯示出三維 畫面。 V、上所述’本發明利用兩組半源極驅動電路分別獨立提供不同之 ’’、、員不貝料訊號至穿透區與反射區之次晝素,使反射區之次晝素所接 魯收到高準位的電壓值可與穿透區之次晝素所接收到之高準位電壓值 不同,藉此穿透區之次晝素所顯示出伽瑪曲線可與反射區之次畫素 所顯不出伽瑪曲線相匹配,以避免因穿透區與反射區具有相同液晶 間隙所造成伽瑪曲線不同。並且,由於兩組半源極驅動電路可分= 獨立提供不同之顯示資料訊號至穿透區與反射區之次晝素,本發明 =驅動電路更可應用至顯示雙視肖畫面之顯示^、顯示三維書面之 ‘”、員示器或需分別顯示左眼與右眼訊號之三維立體顯示器。 卩上所述僅為本發明之較佳實施例,凡依本發㈣請專利範圍 201142783 所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖繪示了習知雙液晶間隙型之半穿反式液晶顯示面 圖。 第2圖繪示了本發明第—實施例之顯示面板的剖面示意圖。 第3 _示了本發明第—實施例之顯示面板的购電路示音圖。 第4圖繪示了本發明第一實施例於顯示面板的穿透區顯示:色畫面 時傳送至間極線與第—資料線之顯示資料峨時序圖。 · 第5圖繪tf 了本發明第—實施例之穿透區的驅動電路示意圖。 第6圖繪不了本發明第—實施例之反祕的驅動電路示意圖。 第7圖綠不了本發明第一實施例於顯示面板的穿透區顯示綠色晝面 時傳送至問極線與第—資料線之顯示資料訊號時序圖。 第8圖缘示了本發明第—實施例於顯示面板的穿透區顯示藍色晝面 日,达至閘極線與第—#料線之顯减料訊號時序圖。 第9圖、θ不了本發明第二實施例顯示面板之驅動電路示音圖。 鲁 第1〇畴示了本發明第二實施例之顯示面板的顯示書的意圖。 第U崎示了本發明之顯示面_示-種三維晝面之示音圖。 第12崎示了本發明之顯示面板顯示另,三維晝面之示音、圖。 【主要元件符號說明】 陣列基板 第一基板 半穿反液晶顯示裝置20 畫素區 % 22 22 201142783 26 保護層 27 28 穿透區 30 32 晝素電極 32a 32b 反射電極 34 36 彩色遽光片 38 40 液晶層 42 100 顯示面板 102 104 • 彩色?慮光片基板 106 108 驅動電路 110 112 第一資料驅動電路 114 GL,-GLX 閘極線 DLr RLpRLy 第二資料線 Pi p2 第二次晝素 p3 p4 第四次晝素 SW, sw2 第二開關元件 sw2 ® sw4 第四開關元件 PE, pe2 第二畫素電極 pe3 pe4 第四晝素電極 Ti T2 第二時間間隔 T3 T4 第四時間間隔 T5 T6 第六時間間隔 d 200 驅動電路 202 反射區 彩色濾光片基板 透明電極 第二基板 凸塊 共通電極 基板 液晶層 閘極驅動電路 第二資料驅動電路 第一資料線 第一次晝素 第三次晝素 第一開關元件 第三開關元件 第一畫素電極 第三晝素電極 第一時間間隔 第三時間間隔 第五時間間隔 液晶間隙 顯示面板 23 201142783 204 300 304 350 354 第一視角晝面 206 第二視角畫面 影像 302 第一顯示資料 第二顯示資料 306 三維晝面資料 影像 352 第一圖案資料 第二圖案資料In order to clearly explain the operation principle of the display panel, the town description is described by the example of the data-driven circuit drive penetration (1st - the second pixel and the second pixel). Please refer to Figure 4 and Figure 5. The fourth embodiment of the present invention shows the first embodiment of the present invention. The fifth embodiment of the present invention shows the penetration of the display panel. The red line is transmitted to the gate axis. For example, the driving circuit of the penetrating zone is shown in Fig. 5. The driving circuit of Fig. 5 only shows four gate lines GLrGL4, three first data lines DLi_DL3, and eight first Subsequences & with 8 second pixels P2 'but actually drive the gate _ number, first data 14 201142783 * number of lines and the number of first and second morpheme It is not limited to this. As shown in Fig. 4 and Fig. 5, the driving circuit of the penetrating region constitutes a first half source driver (HSD) circuit l8a, and each gate line (GL!, GL2, GL3 or GL4) Input the gate signal of waveform 1011 in sequence, where 1 is high level and 〇 is low level, each level The successive time intervals are the same as each other. First, in the first time interval T1, the gate signals transmitted by the first gate line GL! and the second gate line GL2 are both high level 'the remaining gate lines GL3 The display data signal transmitted by the GL4 is a low level, because the φ is electrically connected to the first gate line second switching element SW2 and the first switching element SW electrically connected to the second gate line GL2. The second switching element SW2 is turned on. At the same time, the display data signal transmitted by the second first data line D12 is at a high level, and the first first data line DL1 and the third first data line DL3 are transmitted. The display data signal is at a low level. Therefore, the display data signal transmitted by the first data line DL2 of the second line can be stored in the first pixel of the second row and the second column] and the first row of the first row. In the second pixel P2, then, in the second time interval D2, the gate signal transmitted and transmitted by the second gate line gl2 is converted to a low level, thus closing the first switch element of the second column SW! and the second switching element sw3 of the third column. Moreover, the first item-data line is called the transmitted condition number to be converted to a high level. In the third time interval D3, the gate signal transmitted by the second gate line GL2 and the third gate line gl3 is converted to a high level, and the first gate line GL! is converted to a low level. Therefore, the first switching element SWi of the third row, the fourth column, the fourth row, and the second column, and the second switching element SW2 of the fourth row, the third column, and the third row and the fifth column are turned on. Meanwhile, the second column The display data signal transmitted by the first data line DL2 is converted to a high level, so the display data signal will be stored in the first row of the third row and the fourth column and the second row and the third column. In the picture, &, in the fifth time, the signal of the 3 gate lines is converted to the low level, so the switch element SWi of the third row and the fourth column is turned off. At the same time, the signal of the second data line DL2 is converted to a low level, so that the display data signal of the first-order pixel Pi stored in the second row and the second column is transmitted to the second through the first switching element SWi that is turned on. The first data line DL2 is removed, and the display data 5 in the first pixel p1 of the second row and the second column is removed. At the same time, the signal of the third item-data line DL3 will be converted to a high level, so that the first time of the fourth column and the second column will be stored in the display data signal. Then, in the fifth time interval τ5, the second gate line % is converted to the low level, and the third inter-pole line GL3 and the fourth gate line ο. The transmitted gate signal is converted to a high level, and the display data signal transmitted by the first line DL2 of the second item is a high level, so the data signal is displayed in the first line of the second row and the sixth column. P! is in the second pixel p2 of the first row and the fifth column. Then, in the sixth time interval, the signal of the fourth gate line % is converted to the low level and the signal of the second line - the tilt line is switched to the low level, and the first one is the first The signal of the data line DL1 is converted to a high level, so the display data signal of the first human pixel stored in the third row and the fourth column is transmitted to the second data line % through the first switching element SW that is turned on. The display data signal in the first pixel P1 of the third row and the fourth column is removed, and the display data signal is stored in the first-time pixel P1 of the first row and the fourth column. By analogy, each gate line (GLl, GL2, ^, GL- or GLX) sequentially inputs the gate signal of the coffee, and enters a time interval display data signal to the third plus every three time intervals. 1) The strip-data line DL ((4) and the (3m 3) strip data line sinks (4) y, and every other time interval enters a time interval display data signal to the (3m+2) first-data line Shen (4), the red sub-pixel in the penetrating zone of the (3m+l) row can be displayed. It is worth noting that the present invention 16 201142783 shows that the first and the time interval 1 store the non-red one - The second book Puzhong 1 = (four) in the second red color of the red? 2 ρ τ __ the fourth time between the mzttr color of the first painting of the display of the information signal removed. Because i is the second γγρ color When the secondary pixel P2 is stored in the non-red to low-level:: is moved: the marriage tiger can also be in the two sides • face = test the "6 crystal picture and the seventh picture" 6th shows the first implementation of the invention For example, when the display of the green screen is displayed on the green screen, the display information is transmitted to the question line and the first data line. FIG. 7 is a diagram showing the first embodiment of the present invention. When the color surface is transmitted to the gate line and the data line of the first - data line, the timing of the information signal Gu-Green ώ 6 rides 7^, her money shows the display information signal provided by the red picture series, every three times when the color surface is Input time interval display data «to (3rd order 2) first data line sink (4) and gamma +3) first data line DL (four)) '* every other - do not separate people - _ Interval display data signal to the first data line sink ((4), green in the penetration area of the (3m+2) line: under-pixel can be displayed. In other words, enter the picture in Figure 4 ( 3111+1) The first data line DL (3m+1) display data signal is changed to input to the (3m+3) first data line 'Enter the 4 U to the first (Μ, first data) The display data signal of the line DL_) is changed to the first (for example +1)-data line DL^, and the fourth picture is input to the first (3m+3) first data line 〇1 gamma +3) The display data signal is changed to input to the (3m+2)th item-data, line DL(3m+2), and the green surface can be displayed. If it is not shown in Figure 7, the picture is input to the gamma + 丨) The first data line DL gamma display data 17 201142783 = change Lose the original (3m + lion - 嶋 DW), enter the first (3m + 2) first data line sink (4) display data signal in the object map to input to the first Ll 3) first data line DL (3m + 3) Change the display data signal input to the gamma +3) strip-bee line DL- in the fourth picture to the first data line DL of the gamma +1 (3m+u can be blue) Please refer to FIG. 8. FIG. 8 is a schematic diagram showing the driving circuit of the reflective region of the first embodiment of the present invention. As shown in FIG. 8, the driving circuit of the reflective region drives the circuit, and The driving circuit of the driving circuit is about the same as the driving circuit of the rich area. The difference between the two is that the position of the third pixel & and the time pixel & is different from the position of the first pixel ρι and the second pixel P2, so it is located in the third row and the second column. The third pixel p3 has a connection circuit with the first pixel and the second pixel in the second row of the second column, but displays a different color 1 to provide the first human pixel to the reflection region.卩3 and the fourth 昼素 & display information and face adjustment. When displaying the color surface, the second data driving circuit will input the image data from the first data line DL (3m+1} to the third (3m+2) 2. The data line rainbow (4) 'provides the display data signal input to the (3m+2)th first data line DL (4) in the fourth picture to the (3) 3th work data line rainbow (4), which will be shown in Figure 4 The display data signal input to the (3m+3)th-th data line DL(3m+3) is supplied to the second (plus +^ second data line Rl^ma. When the green screen is displayed, the second data driving circuit The display information signal input to the (3m+l) first data line in the fourth picture is provided to the second (3m+l) second data, the line is called (4), and the fourth is input to the first (For example, 10) The display data signal of the first data line DL (3m+2) is provided to the (3m+2) second data line 18 201142783 RL (10) illusion, and input to the third picture (3m+; 3 The first data line Shen (4)) provides the information signal to the (3m+3) second data, line rainbow (4). When the blue surface is displayed, the second data driving circuit will be input in Figure 4. To the (3m+1) first data line display information signal is provided to (3m+3) second data line, providing the data signal input to the (3m+2)th-data line DL(3m+2) in the fourth picture to the (3m+l) The second data line Zhuangjia, the display data signal input to the first (eg, +3) first data line DL (3m+3) in FIG. 4 is provided to the (3m+2) first data line DL ( 3m+2) Please refer to FIG. 9 and FIG. 10, FIG. 9 is a schematic diagram showing a driving circuit of a display panel according to a second embodiment of the present invention, and FIG. 1 is a view showing a display panel according to a second embodiment of the present invention. As shown in FIG. 9, the first pixel 1 of the driving circuit 200 of the present embodiment is located in the (2η+ι) column, respectively, compared to the display panel of the first embodiment. The (4m+4)th row and the (2n+2)th column (4m+l) row, and the second pixel pixel system is located in the (2n+l)th column (4m+l) row and the first ( 2n+2) column (4m+4) rows, each third pixel & system is located in the (2n+l)th column (4m+2) row and the (2n+2)th column (4m+ 3) Row, and each fourth pixel P4 is located in the (2n+1)th row (4m+3) row and the (2n+2)th column (4m+2) row, respectively. 1) The second pixel P2 and the fourth time The p4 is electrically connected to the (2n+l)th gate line GL(2n+1), the second pixel P2 and the fourth pixel P4 in the (2n+2)th column, and the second (2n) +l) The first pixel of the column? The third pixel is electrically connected to the (2n+2) gate line GL(2n+2) and is located in the (2n+2)th column. The first pixel P! is electrically connected to the third pixel system P3 to the (2ii+3)th gate line GL(2n+3). In this embodiment, the first halogen P of the penetrating zone is set in the same column as the third halogen P and the fourth halogen P4 of the 201142783 reflection zone, so that the penetrating The area and the reflection area are alternately arranged in the same column. Therefore, as shown in FIG. 10, in the display panel 202 of the embodiment, the first data driving circuit 112 can be used to transmit a first viewing angle display material so that the first pixel of the received signal is received. And the second pixel p2 displays a first viewing angle 204' and the second data driving circuit 114 can be used to transmit a second viewing angle display data, so that the third pixel receiving the signal and the fourth The secondary pixel p4 shows a first viewing angle pupil 206. Moreover, the display panel 2〇2 is provided with an optical element having a birefringence, such that the first viewing angle 204 is emitted at an angle, and the second viewing angle 206 is emitted toward another angle, thereby making the angles at different angles A viewer viewing the display panel 2〇2 can view different display faces. Further, the display panel of the present invention can be applied to display a two-dimensional facet in addition to the display of a two-dimensional picture. Please refer to FIG. U, and please refer to FIG. 3 together. FIG. 9 is a schematic diagram showing a three-dimensional facet of the display panel of the present invention. As shown in FIG. 3 and FIG. 3, an image 300 is divided into a first display material 302 having a sharpness value and a second display material 304 having a contrast value (c〇_tvalue). ^ The first data driving circuit can be used to transmit the first display data 3〇2 to the first-pixel pixel Pi of the penetrating region and the first pixel Pz, and the second data driving circuit can be used to transmit the first, display data 304 to The third time in the reflection zone was painted with the fourth bite p4. Therefore, J uses the first _ 昼 昼 P P P and the second 昼 ^ ^ to display the sharpness of the image and the use of the first human 卩 卩 与 3 and the fourth 昼 p p4 to display the contrast of the image, thereby The data 302 and the second display material 304 form a three-dimensional picture material 306, so that the display panel displays a three-dimensional picture. 201142783 ° month refers to FIG. 12' and please refer to FIG. 3 together. FIG. 12 is a schematic diagram showing another three-dimensional display of the display panel of the present invention. As shown in FIG. 3 and FIG. 12, an image 350 is divided into a first pattern data 352 having a first brightness and a second pattern data 354 having a second brightness, and the first data driving circuit is available. The second pixel driving circuit for transmitting the first pattern data to the penetrating region and the second pixel P2' second data driving circuit can be used to transmit the second pattern data to the third pixel of the reflection region! >3 and • a fourth time, and the present invention uses the first brightness to be less than the second brightness to present the first pattern data 352 behind the second pattern data 354, thereby presenting the first pattern data 352 having different depth of fields. The second pattern data 354 further displays a three-dimensional picture. V, the above description 'The invention utilizes two sets of half-source driving circuits to independently provide different '', 员 贝 料 至 至 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到The voltage value of the high level received by the Lu is different from the high level voltage received by the secondary element of the penetrating region, so that the gamma curve of the penetrating region can be compared with the reflecting region. The sub-pixels do not show a gamma curve matching to avoid the gamma curve caused by the same liquid crystal gap between the penetrating region and the reflecting region. Moreover, since the two sets of half-source driving circuits can separately provide different display data signals to the secondary elements of the transmissive area and the reflective area, the present invention=the driving circuit can be further applied to display the display of the dual-view mode. Display a three-dimensional written '', a pointer or a three-dimensional display that needs to display the left and right eye signals respectively. The above description is only a preferred embodiment of the present invention, and the patent scope 201142783 is made according to the present invention. The equal change and modification should be within the scope of the present invention. [Simplified description of the drawing] Fig. 1 is a view showing a half-transflective liquid crystal display surface of a conventional double liquid crystal gap type. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3 shows a circuit diagram of a display panel of a display panel according to a first embodiment of the present invention. FIG. 4 is a view showing a first embodiment of the present invention for wearing on a display panel. The transmissive area display: the display data transmitted to the interpolar line and the first data line in the color picture, and the timing chart. Fig. 5 is a schematic diagram showing the driving circuit of the penetration area of the first embodiment of the present invention. The first embodiment of the present invention Schematic diagram of the anti-secret driving circuit. Figure 7 is a green timing diagram of the display data signal transmitted to the interrogating line and the first data line when the green area of the display panel is displayed in the transparent area of the display panel. It is to be noted that the first embodiment of the present invention displays a blue kneading day in the penetration area of the display panel, and reaches a timing chart of the display signal of the gate line and the ## material line. FIG. 9 and θ are not invented by the present invention. The second embodiment shows a display circuit diagram of the driving circuit of the panel. The first aspect of the present invention shows the intention of the display of the display panel of the second embodiment of the present invention. The display surface of the present invention shows the display surface of the present invention. The display of the display panel of the present invention is shown in Fig. 12, and the display panel of the present invention displays the sound and the figure of the three-dimensional surface. [Description of main components] The first substrate of the array substrate is transflected by the liquid crystal display device 20 % 22 22 201142783 26 Protective layer 27 28 Transmissive area 30 32 Alizarin electrode 32a 32b Reflecting electrode 34 36 Color fluorescent sheet 38 40 Liquid crystal layer 42 100 Display panel 102 104 • Color? Light-sensitive sheet substrate 106 108 Driving circuit 110 112 First data Drive circuit 114 GL, -GLX gate line DLr RLpRLy second data line Pi p2 second pixel p3 p4 fourth pixel SW, sw2 second switching element sw2 ® sw4 fourth switching element PE, pe2 second picture Prime electrode pe3 pe4 fourth halogen electrode Ti T2 second time interval T3 T4 fourth time interval T5 T6 sixth time interval d 200 drive circuit 202 reflective region color filter substrate transparent electrode second substrate bump common electrode substrate liquid crystal Layer gate drive circuit second data drive circuit first data line first passivation third passivation first switching element third switching element first pixel electrode third halogen electrode first time interval third time interval The fifth time interval liquid crystal gap display panel 23 201142783 204 300 304 350 354 the first viewing angle pupil 206 the second viewing angle image 302 the first display data the second display data 306 the three-dimensional facial data image 352 the first pattern data the second pattern data

24twenty four

Claims (1)

201142783 七、申請專利範圍: I —種驅動電路,包括: 複數條閘極線; 複數條第一資料線; 贿條第二資料線’其”(m+1)條第二資料線設於第(糾)條第 -資料線鮮(m+2)條第__ t料線之間,且第(m+2)條第一資 料線設於第(m+l)條第二資料線與第(m+2)條第二資料線之 間; 、' 複數個第一次晝素,分別設於兩相鄰之第(2n+1)條閘極線與第 (2n+2)條閘極線之間與兩相鄰之第(m+1)條第二資料線與第 (m+2)條第一資料線之間,以及兩相鄰之第(2n+2)條閘極線 與第(2n+3)條閘極線之間與兩相鄰之第(m+丨)條第一資料線 與第(m+1)條第二資料線之間; 複數個第二次晝素,分別設於兩相鄰之第(2n+1)條閘極線與第 (2n+2)條閘極線之間與兩相鄰之第(m+丨)條第一資料線與第 (m+1)條第二資料線之間,以及兩相鄰之第(2n+2)條閘極線 與第(2n+3)條閘極線之間與兩相鄰之第(m+2)條第一資料線 與第(m+1)條第二資料線之間,其中各該第二次晝素分別電 性連接至各該第一次晝素; 複數個第三次晝素,分別設於兩相鄰之第(2n+l)條閘極線與第 (2n+2)條閘極線之間與兩相鄰之第(m+1)條第一資料線與第 (m+1)條第二資料線之間,以及兩相鄰之第(2n+2)條閘極線 25 201142783 與第(2n+3)條閘極線之間與兩相鄰之第(m+2)條第一資料線 與第(m+1)條第二資料線之間;以及 複數個第四次畫素,分別設於兩相鄰之第(2n+1)條閘極線與第 (2n+2)條閘極線之間與兩相鄰之第(m+1)條第二資料線與第 (m+2)條第一資料線之間,以及兩相鄰之第(2n+2)條閘極線 與第(2n+3)條閘極線之間與兩相鄰之第(m+1)條第一資料線 與第_)條第二資料線之間,射各該第四次畫素分別電 性連接至各該第三次畫素,且該等第—次畫素、該等第二次 畫素、該等第三次畫素與該等第四次畫素呈矩陣方式排列,· 其中,第(2n+l)條閘極線電性連接位於第(2η+ι)條間極線 與第(2n+2)制極賴之料第二次畫素與該等第 四次畫素; ' 第(2n+2)條閘極線電性連接位於第(2㈣)條閘極線 與別2n+2)條線間之料第-次晝素與該等第 二次畫素,以及紐連接倾第(211+2)制極線201142783 VII. Patent application scope: I—a kind of driving circuit, including: a plurality of gate lines; a plurality of first data lines; a bribe second data line 'its' (m+1) second data line is set at (correction) Article - data line fresh (m + 2) Article __ t between the material lines, and the (m + 2) first data line is set in the (m + l) second data line and Between the (m+2)th second data lines; , 'a plurality of first morpheme, respectively located at two adjacent (2n+1) gate lines and (2n+2) gates Between the two lines (m+1) second data line and the (m+2) first data line, and two adjacent (2n+2) gate lines Between the (2n+3)th gate line and the two adjacent (m+丨) first data lines and the (m+1)th second data line; the plurality of second 昼, respectively, between two adjacent (2n+1) gate lines and the (2n+2) gate lines and two adjacent (m+丨) first data lines and (m) +1) between the second data lines, and between the two adjacent (2n+2) gate lines and the (2n+3)th gate lines and the two adjacent (m+2) First data line and (m+1) Between the second data lines, each of the second halogens is electrically connected to each of the first halogens; and the plurality of third halogens are respectively disposed at two adjacent (2n+l) strips Between the gate line and the (2n+2)th gate line and between two adjacent (m+1)th first data lines and (m+1)th second data lines, and two phases The first (2n+2) gate line 25 201142783 and the (2n+3) gate line and the two adjacent (m+2) first data lines and the (m+1)th Between the second data lines; and a plurality of fourth pixels, respectively, between two adjacent (2n+1) gate lines and the (2n+2) gate lines and two phases Between the (m+1)th second data line and the (m+2)th first data line, and the two adjacent (2n+2) gate lines and the second (2n+3) Between the gate lines and between the two adjacent (m+1) first data lines and the _) second data lines, each of the fourth pixels is electrically connected to each of the first Three pixels, and the first-order pixels, the second pixels, the third pixels, and the fourth pixels are arranged in a matrix manner, wherein, (2n+ l) The gate connection is electrically connected between the (2η+ι) strip and the (2n+2) system, and the second pixel and the fourth pixel; '第(2n +2) The gate line is electrically connected between the (2(4)) gate line and the other 2n+2) line, the first-order element and the second pixel, and the new connection 211+2) system line (⑽)_線間之料第二:欠畫雜稱第四次晝 素; 一 第(:3)軸_電,_位於細糊極_第 =3)閘極,_之該等第—次晝素與該等第三次晝 第—資料線紐連接位於第(m+1)條第-資料 第㈣條第二資料線電性連接位於到;^素 線與第(_)條第二資料線之間之該等第一: 資料 26 201142783 、線與第(m+i)條第二資料線之間,與位於第(m+i)條 第二資料線與第(m+2)條第一資料線之間之該等第 三次晝素; 第(m+2)條第一資料線電性連接位於第(_)條第一資料 線與第(m+1)條第二資料線之間之該等第一次晝 素’而m與η為大於等於〇的整數。 籲2_如請求項】所述之驅動電路,其中各該第一次畫素係分別位於第 (如+2)列第(2m+2)行與第(如+句列第伽+1)行,各該第二次畫素 係分別位於第(4n+l)列第(2m+1)行與第(4n+3)列第(2m+2)行各 該第三次晝素係分別位於第(如+2)列第伽叫行與第(々η.1)列第 (2m+2)行’且各該第四次畫素係分別位於第(411+1)列第伽+2)行 與第(4n+3)列第(2m+l)行。 3. 如請求項2所述之驅動電路,其中位於第(4n+1)列之該等第二次 • 畫素與該等第四次晝素電性連接至第(2n+l)條閘極線,位於第 (4n+3)列之該等第二次畫素與該等第四次畫素以及位於第(4n+2) 列之該等第一次晝素與該等第三次晝素係電性連接至第(2n+2)條 閘極線,且位於第(4n+4)列之該等第一次晝素與該等第三次畫素 係電性連接至第(2n+3)條閘極線。 27 1 如請求項1所述之驅動電路,其中各該第一次晝素係分別位於第 (2n+l)列第(4m+4)行與第(2n+2)列第(4m+l)行,各該第二次晝素 201142783 係分別位於第(2n+1)列第(4m+l)行與第(2n+2)列第(4m+4)行,各 該第三次晝素係分別位於第(2n+1)列第(4m+2)行與第(2n+2)列第 (4m+3)行,且各該第四次畫素係分別位於第(2n+1)列第(4m+3)行 與第(2n+2)列第(4m+2)行。 5.如明求項4所述之驅動電路,其中位於第(2n+1)列之該等第二次 畫素與該等第四次畫素電性連接至第(2n+1)條閘極線,位於第 你+2)列之該雜二:欠晝素與該衫四次畫素以及錄第(2_ 歹!之該等帛·人晝雜該等第三:欠晝雜電性連接至第(㈣)條 閘極線’且位於第(2n+2)列之轉第—次畫素與該等第三次晝素 係電性連接至第(2n+3)條閘極線。 6.如請求項1所述之驅動電路,其中各該第—次晝素包括 關兀件與-第-晝素電極,各該第二次 _ 與一第二畫素電極,各該第三次佥去w 第-開關讀 三畫素電極,且各該第四次晝^括I —第三關元件與一第 素電極。 紅括-第四開關元件與-第四畫 如請求項6所述之驅動電路,其中各 — 各該第-開關it叙祕,各該帛 ^、電極f性連接至 之汲極 二開關元件找極,各該第三畫====連接至各該第 元且各該第四畫素電極電性連接至各該第== 28 201142783 8·如請求項6所述之驅動電路,其中各該第二開關元件之源極分別 電性連接至各該第一開關元件之汲極,且各該第四開關元件之源 極分別電性連接至各該第三開關元件之汲極。 9·如π求項1所述之驅動電路,另包括一第一資料驅動電路與一第 — >料驅動電路,且該第一資料驅動電路電性連接至該等第一資 料線,而該第二資料驅動電路電性連接至該等第二資料線。 〇·如明求項9所述之驅動電路,其中該第一資料驅動電路用以傳 送—第一視角顯示資料,且該第二資料驅動電路用以傳送一第二 視角顯示資料。 Π.如請求項9所述之驅動電路,其中該第一資料驅動電路用以傳 适一具有一銳利值(sharpnessvalue)之第一顯示資料,且該第二資 料驅動電路用以傳送一具有一對比值(contrast value)之第二顯示 資料’而該第一顯示資料與該第二顯示資料構成一三維晝面資 料。 *1 •如請求項9所述之驅動電路,其中該第一資料驅動電路用以傳 送—具有一第一亮度之第一圖案資料,該第二資料驅動電路用以 傳送一具有一第二亮度之第二圖案資料,且該第一亮度小於該第 ~免度〇 29 201142783 13. —種顯示面板,包括: 一基板; 如請求項1所述之驅動電路,設於該基板上; 一彩色濾光片基板;以及 一液晶層,設於該基板與該彩色濾光片基板之間。 、圖式.((10)) _ line material second: under the drawing miscellaneous fourth 昼 ;; one (: 3) axis _ electricity, _ located in the fine paste _ _ 3) gate, _ the same - The connection between the secondary sputum and the third 昼-data line is located at the (m+1)th-data (2) second data line electrical connection is located; the ^ line and the (_) The first between the two data lines: Data 26 201142783, between the line and the (m+i) second data line, and the second (m+i) data line and the (m+2) The third element of the first data line; the first (m+2) first data line is electrically connected to the first (_)th data line and the (m+1)th The first primes between the two data lines and m and η are integers greater than or equal to 〇. The driving circuit described in claim 2, wherein each of the first pixel systems is located at the (2m+2)th row and the first (eg, + sentence column +1) of the (eg, +2) column respectively. In the row, each of the second pixel systems is located in the (4n+1)th row (2m+1) row and the (4n+3)th column (2m+2) row, respectively. Located in the (e.g., +2) column, the gamma row and the (々η.1) column (2m+2) row, and each of the fourth pixel systems is located at the (411+1)th column gamma + 2) Line and (4n+3) column (2m+l). 3. The driving circuit of claim 2, wherein the second pixel in the (4n+1)th column is electrically connected to the fourth pixel to the (2n+l) gate a polar line, the second pixel in the (4n+3)th column and the fourth pixel and the first pixel in the (4n+2)th column and the third time The halogen element is electrically connected to the (2n+2)th gate line, and the first halogen elements in the (4n+4)th column are electrically connected to the third pixel element to the first 2n+3) gate line. 27 1 The driving circuit according to claim 1, wherein each of the first sub-systems is located in the (2n+l)th column (4m+4) row and the (2n+2)th column (4m+l) The second time, each of the second prime 201142783 is located in the (2n+1)th row (4m+l) row and the (2n+2)th column (4m+4) row, respectively, each of the third times The prime system is located at the (4m+2)th and (2n+2)th (4m+3)th rows of the (2n+1)th column, and each of the fourth pixel systems is located at the (2n+1) ) The (4m+3)th row and the (2n+2)th row (4m+2) row. 5. The driving circuit of claim 4, wherein the second pixels located in the (2n+1)th column and the fourth pixels are electrically connected to the (2n+1)th gate The polar line, located in the second +2) column of the second: 昼 昼 与 and the shirt four times and the recording of the second (2 歹 之 之 之 昼 昼 昼 昼 昼 昼 第三 第三 第三 第三 第三 第三 第三 第三 第三Connected to the ((4)) gate line ' and the second pixel in the (2n+2)th column is electrically connected to the third (2n+3) gate line 6. The driving circuit according to claim 1, wherein each of the first and second elements includes a contact element and a - dysprosium electrode, each of the second time _ and a second pixel electrode, each of the Three times to remove the first switch to read the three pixel electrodes, and each of the fourth times includes I - the third off element and a first element electrode. Red - fourth switch element and - fourth picture such as request The driving circuit of the above, wherein each of the first switches is secreted, and each of the electrodes is electrically connected to the draining diodes of the two switching elements, and each of the third paintings ==== is connected to each The first element and each of the fourth pixel electrodes are electrically connected to each of the first == 28 2011 The driving circuit of claim 6, wherein the source of each of the second switching elements is electrically connected to the drains of the first switching elements, and the sources of the fourth switching elements are respectively electrically connected. The driving circuit is connected to each of the third switching elements. The driving circuit of the first aspect, further comprising a first data driving circuit and a first -> material driving circuit, and the first data driving The circuit is electrically connected to the first data lines, and the second data driving circuit is electrically connected to the second data lines. The driving circuit of claim 9, wherein the first data driving circuit For transmitting - the first view display data, and the second data driving circuit is configured to transmit a second view display data. The drive circuit of claim 9, wherein the first data drive circuit is used for transmitting a first display data having a sharpness value, and the second data driving circuit is configured to transmit a second display data having a contrast value and the first display data and the second display Data composition one three The driving circuit of claim 9, wherein the first data driving circuit is configured to transmit a first pattern data having a first brightness, and the second data driving circuit is configured to transmit a second pattern data of the second brightness, and the first brightness is less than the first degree of freedom 〇29 201142783. The display panel comprises: a substrate; the driving circuit according to claim 1 is disposed on the substrate a color filter substrate; and a liquid crystal layer disposed between the substrate and the color filter substrate. 3030
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