TWI399758B - Word line decoder circuit - Google Patents

Description

Word line decoder circuit

The present invention relates to a memory device, and more particularly to a decoder circuit for a memory device.

The memory device has a plurality of memory cells. When a plurality of materials are stored in the memory (or read), the memory device must receive a word line selection signal of each data to store the plurality of data according to the word line selection signals to correspond to Memory unit (or read this multiple data from the corresponding memory unit). Thus, in the memory device, the word line driver circuit is applied to generate these word line select signals.

Please refer to FIG. 1. FIG. 1 is a circuit diagram of a conventional word line decoder circuit 10 provided by Intel Corporation. The conventional word line decoder circuit 10 includes a controllable pull-down circuit 11, eight local decoders 12_1~12_8, a PMOS transistor P4, and eight word line clusters. 13_1~13_8. Each of the word line clusters 13_1~13_8 includes sixteen column drivers 14_1~14_16. Each of these area decoders 12_1~12_8 includes an NMOS transistor N1 and two PMOS transistors P1, P2. The controllable pull-down circuit 11 includes two NMOS transistors N2 and N3. Each of the column drivers 14_1~14_16 includes a PMOS transistor P3 and two NMOS transistors N4, N5. In the sector 10 of the conventional word line decoder circuit, the connection relationship of all components is shown in FIG. 1 and will not be described herein.

Please refer to FIG. 2. FIG. 2 is a circuit diagram of the conventional word line decoder circuit 10 provided by Intel Corporation when the word line WL<1> is selected. At this time, when the conventional word line decoder circuit 10 is selected, the segment selection signals BLKSEL and BLKSELHB are VCC and 0, respectively. The word line WL<1> is selected such that the area pre-decode signal PREA<1> and the column driver selection signal PRERN<1> are VCC and 0, respectively. The other area pre-decode signals PREA<2>~PREA<7> are 0. The other column driver selection signals PRERN<2>~PRERN<16> are VPX. The pre-decode signal PREB<1> and the bias signal AWLH are 0 respectively. When operating in the READ mode, the power supplies VPIXH and VPXH are VPX and the power supply VNX is zero.

The PMOS transistor P4 is turned on and the node VPXX is VPX. The PMOS transistor P1 of the area decoder 12_1 and the NMOS transistor N1 of the area decoder 12_1 are turned on, and the NMOS transistors N2, N3 of the pull-down circuit 11 can be controlled to be on. Thus, the reset signal VGRST<1> is 0. Thus, the PMOS transistor P2 of the region decoder 12_1 is turned on, and the NMOS transistors N5 of the column drivers 14_1 to 14_16 in the word line cluster 13_1 are turned off. Node VX<1> is VPX. The column driver selection signal PRERN<1> is 0. In the word line cluster 13_1, the PMOS transistor P3 of the column driver 14_1 is turned on, and the NMOS transistor N4 of the column driver 14_1 is turned off. Therefore, the word line WL<1> is VPX. In contrast, the other column driver selection signals PRERN<2>~PRERN<16> are VPX. In the word line cluster 13_1, the PMOS transistors P3 of the column drivers 14_2 to 14_16 are turned off, and the NMOS transistors N4 of the column drivers 14_2 to 14-16 are turned on. Therefore, the word line WL<2>~WL<16> is 0.

The PMOS transistors P1 of the area decoders 12_2 to 12_8 are turned on, and the NMOS transistors N1 of the area decoders 12_2 to 12_8 are turned off. Therefore, the reset signals VGRST<2>~VGRST<8> are VPX, and the PMOS transistors P2 of the area decoders 12_2~12_8 are turned off. Node VX<8> is high impedance. In the word line clusters 13_2 to 13_8, the NMOS transistors N5 of the column drivers 14_1 to 14_16 are turned on. The column driver selection signal PRERN<1> is 0. Thus, in the word line clusters 13_2 to 13_8, the PMOS transistor P3 of the column driver 14_1 is turned off, and the NMOS transistor N4 of the column driver 14_1 is turned off. Therefore, the word line WL<1> is 0. In contrast, the other column driver selection signals PRERN<2>~PRERN<16> are VPX. In the word line clusters 13_2 to 13_7, the PMOS transistors P3 of the column drivers 14_2 to 14_16 are turned off, and the NMOS transistors N4 of the column drivers 14_2 to 14_16 are turned on. Therefore, the word line WL<2>~WL<16> is 0.

The size of each PMOS transistor P1 is a design issue. Taking FIG. 2 as an example, when the PMOS transistor P1 is small in size, the reset signal VGRST<1> can be quickly pulled down to 0, and the node VX<1> can be quickly pulled up to VPX, and the NMOS transistor N5 in the word line cluster 13_1 can be turned off quickly. Therefore, the selected word line WL<1> can also be quickly pulled up to the VPX. However, the reset signal VGRST<2>~VGRST<8> will be slowly pulled up to VPX, and the NMOS transistor N5 in the word line cluster 13_2~13_8 will be slowly turned on. Therefore, the unselected word lines WL<17>~WL<128> will also slowly pull down to zero.

In contrast, when the PMOS transistor P1 is large in size, the reset signals VGRST<2>~VGRST<8> can be quickly pulled up to the VPX, and the NMOS transistors N5 in the word line clusters 13_2~13_8 can be quickly turned on. Therefore, the unselected word lines WL<17>~WL<128> can be quickly pulled down to zero. However, the reset signal VGRST<1> will slowly pull down to 0, and the NMOS transistor N5 in the word line cluster 13_1 will slowly turn off. If the reset signal VGRST<1> is too large, the NMOS transistor N5 of the column driver 14_1 in the word line cluster 13_1 may be turned on. Therefore, the selected word line WL<1> will slowly pull up to the VPX, or even not reach the VPX.

In summary, the size of the PMOS transistor P1 must fall within an appropriate range to avoid slow reading speeds of selected and unselected word lines.

Further, taking FIG. 2 as an example, all of the PMOS transistor P3 and the NMOS transistor N4 are charged to the VPX except for the PMOS transistor P3 and the NMOS transistor N4 of the column driver 14_1 in the word line cluster 13_1. The NMOS transistor N4 of the word line cluster 13_2~13_8 is also charged to the VPX. In reality, the voltage VPX is generated by an internal pump circuit. The power efficiency of the internal pump circuit is approximately 20% to 30%, so there is a large amount of power wasted and a long settling time is required to set the VPX. Therefore, a problem occurs in the reading speed of the selected word line.

As a result, conventional word line decoder circuits can cause problems in the read speed of selected or unselected word lines, and there is a problem of a large amount of power consumption.

The present invention provides a word line decoder circuit that has lower power consumption and higher operating speed.

The invention provides a word line decoder circuit, the word line decoder circuit comprising a controllable power supply, at least one area predecoder, at least one local pre-decoder, at least one A word line cluster and at least one controllable pull down circuit. The controllable power supply is controlled by an inverted sector select signal to provide a first voltage to the at least one regional predecoder. The regional predecoder includes a first PMOS transistor, a second PMOS transistor, an NMOS transistor, a second NMOS transistor, and a third NMOS transistor. The gate of the first PMOS transistor is coupled to a bias voltage, and the source thereof is coupled to a second voltage. The gate of the second PMOS transistor is coupled to the drain of the first PMOS transistor, and the source thereof is coupled to the controllable power supply. The gate of the first NMOS transistor is coupled to an area pre-decode signal, and the drain of the first NMOS transistor is coupled to the drain of the first PMOS transistor. The gate of the second NMOS transistor is coupled to the region pre-decode signal. The gate of the third NMOS transistor is coupled to the gate of the second PMOS transistor, and the drain thereof is coupled to a reset signal, and the source thereof is coupled to the drain of the second NMOS transistor. The word line cluster includes at least one column of drivers, and the column driver includes a third PMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor. The gate of the third PMOS transistor is coupled to a column of driver pull-up signals, the source of which is connected to the drain of the second PMOS transistor, and the drain of the third PMOS transistor is coupled to a word line. The gate of the fourth PMOS transistor is coupled to a column of driver pull-down signals, the drain of the fourth PMOS transistor is coupled to the drain of the third PMOS transistor, and the source thereof is coupled to a third voltage. The gate of the fifth NMOS transistor is coupled to the source of the third NMOS transistor, the drain of the fifth NMOS transistor is coupled to the drain of the third PMOS transistor, and the source thereof is coupled to the third voltage. The controllable pull-down circuit is coupled to the sources of the first and second NMOS transistors of the regional pre-decoder, and is controlled by a pre-decode signal and a segment selection signal, and the second and the second of the pull-down area pre-decoder The source of the three NMOS transistors is to the third voltage.

Based on the above, the word line decoder circuit of the present invention divides the column driver selection signal into a column driver pull-down signal and a column driver pull-up signal to control the NMOS transistor and the PMOS transistor of the corresponding column driver, and controls the NMOS transistor. The voltage that causes the unselected word line to discharge to zero is VCC, not VPX. Therefore, power consumption can be reduced. Therefore, the power consumption of the word line decoder circuit of the present invention can be reduced. In addition, in the word line decoder circuit, the selected word line can be quickly charged to VCC, and the unselected word line can also be quickly discharged to zero. Therefore, the operation speed of the word line decoder circuit of the present invention can be improved.

The above described features and advantages of the present invention will be more apparent from the following description.

Please refer to FIG. 3. FIG. 3 is a circuit diagram of a word line decoder 20 according to an embodiment of the present invention. The word line decoder circuit 20 includes a controllable power supply 21, eight regional pre-decoders 22_1~22_8, eight word line clusters 23_1~23_8, and a controllable pull-down circuit 24. Among them, each of the word line clusters 23_1~23_8 has sixteen column drivers 25_1~25_16.

The controllable power supply 21 is controlled by a reverse sector select signal SECSELHN to provide a first voltage VPXH to eight regional pre-decoders 22_1~22_8. In the present embodiment, the controllable power supply 21 includes a PMOS transistor P04. The gate of the PMOS transistor P04 is coupled to the reverse sector select signal SECSELHN, the source of which is coupled to the first voltage VPXH, and the drain of which is coupled to the eight regional pre-decoders 22_1 22 22_8. In addition, the implementation of the above controllable power supply 21 is not intended to limit the present invention. The area pre-decoders 22_1~22_8 are controlled by the area pre-decode signals PREA<1:8> to select the word line clusters 23_1~23_8, respectively.

The i ^{th th} region predecoder (in the present embodiment, i is, for example, an integer from 1 to 8) includes two PMOS transistors P01, P02 and three NMOS transistors N01, N02, N03. The gate of the PMOS transistor P01 is coupled to a bias voltage VGBIAS, and the source thereof is coupled to a second voltage VPIXH. The gate of the PMOS transistor P02 is coupled to the drain of the PMOS transistor P01, and the source thereof is coupled to the controllable power supply 21. In addition, the drain of the PMOS transistor P02 is coupled to the word line cluster 23_i. When the PMOS transistor P02 is turned on, the first voltage VPXH is supplied to the column drivers 25_1 to 25_16 of the word line cluster 23_i.

The gate of the NMOS transistor N01 is coupled to a region pre-decode signal PREA<i>, and its drain is coupled to the drain of the PMOS transistor P01. The gate of the NMOS transistor N02 is coupled to the region pre-decode signal PREA<i>. The sources of the NMOS transistors N01, N02 are coupled to the controllable pull-down circuit 24. When the controllable pull-down circuit 24 is enabled, the sources of the NMOS transistors N01, N02 are pulled down. The gate of the NMOS transistor N03 is coupled to the gate of the PMOS transistor P02, the drain of the NMOS transistor N02 is coupled to a reset signal VRSTX, and the source thereof is coupled to the drain of the NMOS transistor N02 and the word line cluster 23_i. Column drivers 25_1~25_16. When the NMOS transistor N03 is turned on, the reset signal VRSTX assists the pull-down word line WL<16*i: 16*(i-1)+1>.

The controllable pull-down circuit 24 is controlled by a pre-decode signal PREB<1> and a sector selection signal SECSEL, the source of the NMOS transistors N01, N02 of the pull-down area pre-decoder 22_i to a third voltage VNX. In the present embodiment, the controllable pull-down circuit 24 includes two NMOS transistors N06, N07. The drain of the NMOS transistor N06 is coupled to the sources of the NMOS transistors N01 and N02, and the gate thereof is coupled to the pre-decode signal PREB<1>. The drain of the NMOS transistor N07 is coupled to the source of the NMOS transistor N06, the gate of which is coupled to the segment select signal SECSEL, and the source of which is coupled to the third voltage VNX. Moreover, the implementation of the controllable pull down circuit 24 described above is not intended to limit the invention.

The column driver 25_j of the word line cluster 22_i (j is, for example, an integer from 1 to 16) includes a PMOS transistor P03 and two NMOS transistors N04, N05. The gate of the PMOS transistor P03 is coupled to a column of the driver pull-up signal PU<j>, the source thereof is coupled to the drain of the PMOS transistor P02, and the drain thereof is coupled to the word line WL<16*(i- 1) +j>. The gate of the NMOS transistor N04 is coupled to a column of the driver pull-down signal PD<j>, the drain of the NMOS transistor N04 is coupled to the drain of the PMOS transistor P03, and the source thereof is coupled to the third voltage VNX. The gate of the NMOS transistor N05 is coupled to the source of the NMOS transistor N03, the drain of the NMOS transistor N05 is coupled to the drain of the PMOS transistor P03, and the source thereof is coupled to the third voltage VNX.

Please refer to FIG. 4. FIG. 4 is a circuit diagram of the word line decoder 20 when the word line WL<1> is selected according to an embodiment of the present invention. When the word line WL<1> is selected, the reverse sector select signal SECSELHN and the sector select signal SECSEL are 0 and VCC, respectively, and the pre-decode signal PREB<1> is VCC. The area pre-decode signal PREA<1> is asserted at VCC, and the other area pre-decode signals PREA<8:2> are 0. Further, the bias voltage VGBIAS is VBIAS, the first voltage VPXH and the second voltage VPIXH are VPX, the third voltage VNX is 0, and the reset signal VRSTX is VCC. Since only the word line WL<1> is selected, and the other word lines WL<16:2> are not selected, the column driver pull-down signal PU<1> is 0, and the other column drivers pull up the signal PU<2> ~PU<16> is VPX. In addition, the column driver pull-down signal PD<1> is 0, and the other column driver pull-up signals PU<2>~PU<16> are VCC.

The PMOS transistor P04 is turned on and its source is extremely VPX. The NMOS transistors N06 and N07 are turned on. In the case of the area predecoder 22_1, the PMOS transistor P01 and the NMOS transistors N01, N02 are turned on. Therefore, in the area predecoder 22_1, a current flows from the source of the PMOS transistor P01 to the source of the NMOS transistor N01, and the other current flows from the drain of the NMOS transistor N02 to the source. The NMOS transistor N02 sinks the charge of the gate of the NMOS transistor N05 of the word line cluster 23_1 to assist in speeding up the cut-off of the NMOS transistor N05. The PMOS transistor P02 of the area predecoder 22_1 is turned on, and its 汲 is extremely VPX. In the column driver 25_1 of the word line cluster 23_1, the PMOS transistor P03 is turned on, and the NMOS transistors N04, N05 are turned off. Therefore, the word line WL<1> is VPX. In the word line cluster 23_1, in addition to the column driver 25_1, the NMOS transistors N04 of the column drivers 25_2 to 25_16 are turned on, the PMOS transistor P03 is turned off, and the NMOS transistor N05 is turned off. Therefore, the word line WL<16:2> is 0.

In the area predecoder 22_8, the PMOS transistor P01 and the NMOS transistor N03 are turned on. Therefore, in the area predecoder 22_8, a current flows from the source of the PMOS transistor P01 to the source of the NMOS transistor N03. The NMOS transistor N03 can assist in speeding up the opening of the NMOS transistor N05. In the area predecoder 22_8, the PMOS transistor P02 and the NMOS transistors N01, N02 are turned off. Therefore, the PMOS of the PMOS transistor P02 of the area predecoder 22_8 is extremely high impedance. The NMOS transistor N05 of the column driver 25_1 of the word line cluster 23_8 is turned on. Since the NMOS transistor N05 is turned on, the word line WL<113> is 0. In the word line cluster 23_8, in addition to the column driver 25_1, the NMOS transistors N04 and N05 of the column drivers 25_2 to 25_16 are turned on. Therefore, the word line WL<128:114> is 0.

Correspondingly, in the area predecoder 22_1, the NMOS transistor N02 is substantially a voltage drop VDS of the gate voltage of the PMOS transistor P02 (that is, the voltage drop VDS of the PMOS transistor P02 gate voltage approaches 0). ). The gate voltage of the NMOS transistor N02 of the area predecoder 22_1 can be used as a control signal for turning off the NMOS transistor N05 of the word line cluster 23_1. Even if the size of the PMOS transistor P01 channel of the area predecoder 22_1 is large, the risk of turning on the NMOS transistor N05 of the column driver 25_1 of the word line cluster 23_1 can be lowered. That is to say, the selected word line WL<1> can reach VPX, and the speed of reaching VPX is also fast. On the other hand, in the case of the area predecoder 22_8, the source of the NMOS transistor N03 is extremely VCC. If the channel size of the PMOS transistor P01 of the regional predecoder 22_8 is large, the voltage of the source of the NMOS transistor N03 can be quickly charged to VCC, and the unselected word line WL<128:113> can be quickly discharged. To 0.

In the word line decoder circuit 20, the voltage of the NMOS transistor N03 of the area pre-decoders 22_2 to 22_8 is charged to VCC instead of VPX. In addition, the column driver is selected by the column driver pull-up signal and the column driver pull-down signal to control the corresponding PMOS transistor and NMOS transistor, so that the power of the VPX pump pump drops. As such, the word line decoder circuit 20 consumes less power than conventional word line decoder circuits.

Please refer to FIG. 5. FIG. 5 is a circuit diagram of a word line decoder 30 according to an embodiment of the present invention. In this embodiment, the word line decoder circuit 30 includes a controllable power supply 31, sixteen regional pre-decoders 32_1~32_16, sixteen word line clusters 33_1~33_16, and two controllable pull-down circuits 34_1~34. -2. Among them, each of the word line clusters 33_1~33_16 has sixteen column drivers 35_1~35_16. The difference between FIG. 3 and FIG. 5 is that the area pre-decoders 32_9~32_16 are added, and the controllable pull-down circuit 34_2 controlled by the pre-decode signal PREB<2> is added. However, this embodiment is not intended to limit the present invention. The number of regional pre-decoders, the number of controllable pull-down circuits, the number of word line clusters, and the number of column drivers can all be adjusted to meet the needs of different applications.

Please refer to FIG. 6. FIG. 6 is a circuit diagram of the word line decoder 30 when the pre-decode signal PREB<1> is changed from VCC to 0, and the pre-decode signal PREB<2> is changed from 0 to VCC according to an embodiment of the present invention. When the pre-decode signal PREB<1> is changed from VCC to 0, the solid current paths indicated by the solid lines in the area pre-decoder 32_1 and the word line cluster 33_1 are changed to the current paths indicated by the broken lines ( Dotted current paths). The gate of the PMOS transistor P02 of the area predecoder 32_1 changes from 0 to VPX, and its drain changes from VPX to high impedance. The source of the NMOS transistor N03 of the area predecoder 32_1 is changed from 0 to VCC, so the word line WL<1> is changed from VPX to 0. When the pre-decode signal PREB<2> is changed from 0 to VCC, the physical current path of the region pre-decoder 32_9 and the word line cluster 33_9 is changed to a point current path. The PMOS transistor P02 gate of the regional predecoder 32_16 is changed from VPX to 0, and its drain is changed from high impedance to VPX. The source of the NMOS transistor N03 of the area predecoder 32_1 is changed from VCC to 0, so the word line WL<129> is changed from 0 to VPX.

Correspondingly, the word line decoder circuit of the embodiment divides the column driver selection signal into a column driver pull-down signal and a column driver pull-up signal to control the NMOS transistor and the PMOS transistor of the corresponding column driver. In addition, the voltage that controls the NMOS transistor to discharge the unselected word line to zero is VCC, not VPX. Therefore, power consumption can be reduced. In addition, in the word line decoder circuit, the selected word line can be quickly charged to VCC, and the unselected word line can also be quickly discharged to zero.

In summary, the power consumption of the word line decoder circuit of the present invention can be reduced compared to the conventional word line decoder circuit, and the operation speed of the word line decoder circuit can also be improved.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10, 20, 30. . . Word line decoder circuit

11, 24, 34_1~34_2. . . Controllable pull-down circuit

12_1~12_8. . . Area decoder

13_1~13_8, 23_1~23_8, 33_1~33_16. . . Word line cluster

14_1~14_16, 25_1~25_16, 35_1~35_16. . . Column driver

21, 31. . . Controllable power supply

22_1~22_8, 32_1~32_16. . . Regional predecoder

AWLH. . . Bias signal

BLKSEL, BLKSELHB. . . Section selection signal

N1~N5, N01~N07. . . NMOS transistor

P1~P4, P01~P03. . . PMOS transistor

PD<1>~PD<16>. . . Column driver pulldown

PREA<1>~PREA<8>. . . Area pre-decode signal

PREB<1>~PREB<2>. . . Pre-decoded signal

PRERN<1>~PRERN<16>. . . Column driver selection signal

PU<1>~PU<16>. . . Column driver pull signal

SECSEL. . . Section selection signal

SECSELHN. . . Reverse segment selection signal

VCC, VNX, VPIXH, VPX, VPXH. . . Voltage

VPXX, VX<1>~VX<8>. . . node

VGBIAS. . . bias

VDS. . . Voltage drop

VGRST<1>~VGRST<8>, VRSTX. . . Reset signal

WL<1>~WL<256>. . . Word line

1 is a circuit diagram of a conventional word line decoder circuit 10 provided by Intel Corporation.

2 is a circuit diagram of a conventional word line decoder circuit 10 provided by Intel Corporation when word line WL<1> is selected.

3 is a circuit diagram of a word line decoder 20 in accordance with an embodiment of the present invention.

4 is a circuit diagram of the word line decoder 20 when the word line WL<1> is selected, according to an embodiment of the present invention.

FIG. 5 is a circuit diagram of a word line decoder 30 in accordance with an embodiment of the present invention.

FIG. 6 is a circuit diagram of the word line decoder 30 when the pre-decode signal PREB<1> is changed from VCC to 0 and the pre-decode signal PREB<2> is changed from 0 to VCC according to an embodiment of the present invention.

20. . . Word line decoder circuit

twenty one. . . Controllable power supply

22_1~22_8. . . Regional predecoder

23_1~23_8, 33_1~33_16. . . Word line cluster

twenty four. . . Controllable pull-down circuit

25_1~25_16. . . Column driver

N01~N07. . . NMOS transistor

P01~P03. . . PMOS transistor

PD<1>~PD<16>. . . Column driver pulldown

PREA<1>~PREA<8>. . . Area pre-decode signal

PREB<1>~PREB<2>. . . Pre-decoded signal

PU<1>~PU<16>. . . Column driver pull signal

VNX, VPIXH, VPXH. . . Voltage

VGBIAS. . . bias

WL<1>~WL<128>. . . Word line

Claims (9)

A word line decoder circuit comprising: a controllable power supply, controlled by a reverse sector selection signal to provide a first voltage to at least one regional predecoder; the regional predecoder comprising: a first PMOS transistor having a gate coupled to a bias and a source coupled to a second voltage; a second PMOS transistor having a gate coupled to the drain of the first PMOS transistor And a source coupled to the controllable power supply; a first NMOS transistor having a gate coupled to an area pre-decode signal and a drain coupled to the drain of the first PMOS transistor a second NMOS transistor having a gate coupled to the pre-decode signal of the region; and a third NMOS transistor having a gate coupled to the gate of the second PMOS transistor, the drain of which is coupled to a reset signal, and a source thereof is coupled to the drain of the second NMOS transistor; at least one word line cluster includes at least one column driver, and the column driver includes: a third PMOS transistor, the gate coupling Connected to a column of driver pull-up signals, the source of which is coupled to the drain of the second PMOS transistor, and The pole is coupled to a word line; the fourth NMOS transistor has a gate coupled to the column of the driver pull-down signal, the drain is coupled to the drain of the third PMOS transistor, and the source is coupled to the a third voltage; and a fifth NMOS transistor having a gate coupled to the source of the third NMOS transistor, a drain coupled to the drain of the third PMOS transistor, and a source coupled Up to the third voltage; and at least one controllable pull-down circuit coupled to the source of the first and second NMOS transistors of the area predecoder, and controlled by a pre-decode signal and a segment selection Signaling, the second and the third NMOS transistors of the region predecoder are pulled to the third voltage. The word line decoder circuit of claim 1, wherein the controllable power supply comprises a fourth PMOS transistor, wherein a gate of the fourth PMOS transistor is coupled to the reverse segment selection The signal of the fourth PMOS transistor is coupled to the first voltage, and the drain of the fourth PMOS transistor is coupled to the source of the second PMOS transistor. The word line decoder circuit of claim 1, wherein the controllable pull-down circuit comprises: a sixth NMOS transistor, the drain of which is coupled to the source of the first and second NMOS transistors a gate coupled to the pre-decode signal; and a seventh NMOS transistor having a drain connected to the source of the sixth NMOS transistor, the gate coupled to the segment select signal, and The source is coupled to the third voltage. The word line decoder circuit of claim 1, wherein when the first PMOS transistor is turned on, the area pre-decode signal and the pre-decode signal are VCC, the sector selection signal and the reverse region. The segment selection signals are VCC and 0 respectively, the first and second voltages are VPX, the third voltage is 0, and the column driver pull-up signal and the column driver pull-down signal are 0, and the word line is VPX. The NMOS of the second PMOS transistor is substantially VPX, and the source of the third NMOS transistor is a voltage drop VDS of the gate voltage of the second PMOS transistor, wherein VDS is the drain of the first NMOS transistor The voltage difference of the source. The word line decoder circuit of claim 4, wherein the first and the second NMOS transistors are turned on, the third NMOS transistor is turned off, and the second PMOS transistor is turned on. The word line decoder circuit according to claim 1, wherein when the first PMOS transistor is turned on, the area pre-decode signal is 0, the pre-decode signal is VCC, and the sector selects a signal and the counter The selection signals for the segments are VCC and 0 respectively, the first and second voltages are VPX, the third voltage is 0, and the column driver pull-up signal and the column driver pull-down signal are 0, and the word line is The PMOS of the second PMOS transistor is extremely high impedance, and the source of the third NMOS transistor is extremely VCC. The word line decoder circuit of claim 6, wherein the first and the second NMOS transistors are turned off, the third NMOS transistors are turned on, and the second PMOS transistors are turned off. The word line decoder circuit according to claim 1, wherein when the first PMOS transistor is turned on, the area pre-decode signal is VCC, the pre-decode signal is 0, and the segment selection signal and the inverse The selection signals for the segments are VCC and 0 respectively, the first and second voltages are VPX, the third voltage is 0, and the column driver pull-up signal and the column driver pull-down signal are 0, and the word line is 0, the 汲 of the second PMOS transistor is extremely high impedance, and the source of the third NMOS transistor is extremely VCC. The word line decoder circuit of claim 8, wherein the first, the second and the third NMOS transistors are on, and the second PMOS transistor is off.